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   1 /*
   2  *   ALSA driver for Intel ICH (i8x0) chipsets
   3  *
   4  *      Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
   5  *
   6  *
   7  *   This code also contains alpha support for SiS 735 chipsets provided
   8  *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
   9  *   for SiS735, so the code is not fully functional.
  10  *
  11  *
  12  *   This program is free software; you can redistribute it and/or modify
  13  *   it under the terms of the GNU General Public License as published by
  14  *   the Free Software Foundation; either version 2 of the License, or
  15  *   (at your option) any later version.
  16  *
  17  *   This program is distributed in the hope that it will be useful,
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *   GNU General Public License for more details.
  21  *
  22  *   You should have received a copy of the GNU General Public License
  23  *   along with this program; if not, write to the Free Software
  24  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25
  26  *
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/moduleparam.h>
  37 #include <sound/core.h>
  38 #include <sound/pcm.h>
  39 #include <sound/ac97_codec.h>
  40 #include <sound/info.h>
  41 #include <sound/initval.h>
  42 /* for 440MX workaround */
  43 #include <asm/pgtable.h>
  44 #include <asm/cacheflush.h>
  45
  46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  48 MODULE_LICENSE("GPL");
  49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  50                 "{Intel,82901AB-ICH0},"
  51                 "{Intel,82801BA-ICH2},"
  52                 "{Intel,82801CA-ICH3},"
  53                 "{Intel,82801DB-ICH4},"
  54                 "{Intel,ICH5},"
  55                 "{Intel,ICH6},"
  56                 "{Intel,ICH7},"
  57                 "{Intel,6300ESB},"
  58                 "{Intel,ESB2},"
  59                 "{Intel,MX440},"
  60                 "{SiS,SI7012},"
  61                 "{NVidia,nForce Audio},"
  62                 "{NVidia,nForce2 Audio},"
  63                 "{AMD,AMD768},"
  64                 "{AMD,AMD8111},"
  65                 "{ALI,M5455}}");
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable this card */
  70 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0};
  71 static char *ac97_quirk[SNDRV_CARDS];
  72 static int buggy_irq[SNDRV_CARDS];
  73 static int xbox[SNDRV_CARDS];
  74
  75 #ifdef SUPPORT_MIDI
  76 static int mpu_port[SNDRV_CARDS]; /* disabled */
  77 #endif
  78
  79 module_param_array(index, int, NULL, 0444);
  80 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  81 module_param_array(id, charp, NULL, 0444);
  82 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  83 module_param_array(enable, bool, NULL, 0444);
  84 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard.");
  85 module_param_array(ac97_clock, int, NULL, 0444);
  86 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
  87 module_param_array(ac97_quirk, charp, NULL, 0444);
  88 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  89 module_param_array(buggy_irq, bool, NULL, 0444);
  90 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  91 module_param_array(xbox, bool, NULL, 0444);
  92 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  93
  94 /*
  95  *  Direct registers
  96  */
  97 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  98
  99 #define ICHREG(x) ICH_REG_##x
 100
 101 #define DEFINE_REGSET(name,base) \
 102 enum { \
 103         ICH_REG_##name##_BDBAR  = base + 0x0,   /* dword - buffer descriptor list base address */ \
 104         ICH_REG_##name##_CIV    = base + 0x04,  /* byte - current index value */ \
 105         ICH_REG_##name##_LVI    = base + 0x05,  /* byte - last valid index */ \
 106         ICH_REG_##name##_SR     = base + 0x06,  /* byte - status register */ \
 107         ICH_REG_##name##_PICB   = base + 0x08,  /* word - position in current buffer */ \
 108         ICH_REG_##name##_PIV    = base + 0x0a,  /* byte - prefetched index value */ \
 109         ICH_REG_##name##_CR     = base + 0x0b,  /* byte - control register */ \
 110 };
 111
 112 /* busmaster blocks */
 113 DEFINE_REGSET(OFF, 0);          /* offset */
 114 DEFINE_REGSET(PI, 0x00);        /* PCM in */
 115 DEFINE_REGSET(PO, 0x10);        /* PCM out */
 116 DEFINE_REGSET(MC, 0x20);        /* Mic in */
 117
 118 /* ICH4 busmaster blocks */
 119 DEFINE_REGSET(MC2, 0x40);       /* Mic in 2 */
 120 DEFINE_REGSET(PI2, 0x50);       /* PCM in 2 */
 121 DEFINE_REGSET(SP, 0x60);        /* SPDIF out */
 122
 123 /* values for each busmaster block */
 124
 125 /* LVI */
 126 #define ICH_REG_LVI_MASK                0x1f
 127
 128 /* SR */
 129 #define ICH_FIFOE                       0x10    /* FIFO error */
 130 #define ICH_BCIS                        0x08    /* buffer completion interrupt status */
 131 #define ICH_LVBCI                       0x04    /* last valid buffer completion interrupt */
 132 #define ICH_CELV                        0x02    /* current equals last valid */
 133 #define ICH_DCH                         0x01    /* DMA controller halted */
 134
 135 /* PIV */
 136 #define ICH_REG_PIV_MASK                0x1f    /* mask */
 137
 138 /* CR */
 139 #define ICH_IOCE                        0x10    /* interrupt on completion enable */
 140 #define ICH_FEIE                        0x08    /* fifo error interrupt enable */
 141 #define ICH_LVBIE                       0x04    /* last valid buffer interrupt enable */
 142 #define ICH_RESETREGS                   0x02    /* reset busmaster registers */
 143 #define ICH_STARTBM                     0x01    /* start busmaster operation */
 144
 145
 146 /* global block */
 147 #define ICH_REG_GLOB_CNT                0x2c    /* dword - global control */
 148 #define   ICH_PCM_SPDIF_MASK    0xc0000000      /* s/pdif pcm slot mask (ICH4) */
 149 #define   ICH_PCM_SPDIF_NONE    0x00000000      /* reserved - undefined */
 150 #define   ICH_PCM_SPDIF_78      0x40000000      /* s/pdif pcm on slots 7&8 */
 151 #define   ICH_PCM_SPDIF_69      0x80000000      /* s/pdif pcm on slots 6&9 */
 152 #define   ICH_PCM_SPDIF_1011    0xc0000000      /* s/pdif pcm on slots 10&11 */
 153 #define   ICH_PCM_20BIT         0x00400000      /* 20-bit samples (ICH4) */
 154 #define   ICH_PCM_246_MASK      0x00300000      /* 6 channels (not all chips) */
 155 #define   ICH_PCM_6             0x00200000      /* 6 channels (not all chips) */
 156 #define   ICH_PCM_4             0x00100000      /* 4 channels (not all chips) */
 157 #define   ICH_PCM_2             0x00000000      /* 2 channels (stereo) */
 158 #define   ICH_SIS_PCM_246_MASK  0x000000c0      /* 6 channels (SIS7012) */
 159 #define   ICH_SIS_PCM_6         0x00000080      /* 6 channels (SIS7012) */
 160 #define   ICH_SIS_PCM_4         0x00000040      /* 4 channels (SIS7012) */
 161 #define   ICH_SIS_PCM_2         0x00000000      /* 2 channels (SIS7012) */
 162 #define   ICH_TRIE              0x00000040      /* tertiary resume interrupt enable */
 163 #define   ICH_SRIE              0x00000020      /* secondary resume interrupt enable */
 164 #define   ICH_PRIE              0x00000010      /* primary resume interrupt enable */
 165 #define   ICH_ACLINK            0x00000008      /* AClink shut off */
 166 #define   ICH_AC97WARM          0x00000004      /* AC'97 warm reset */
 167 #define   ICH_AC97COLD          0x00000002      /* AC'97 cold reset */
 168 #define   ICH_GIE               0x00000001      /* GPI interrupt enable */
 169 #define ICH_REG_GLOB_STA                0x30    /* dword - global status */
 170 #define   ICH_TRI               0x20000000      /* ICH4: tertiary (AC_SDIN2) resume interrupt */
 171 #define   ICH_TCR               0x10000000      /* ICH4: tertiary (AC_SDIN2) codec ready */
 172 #define   ICH_BCS               0x08000000      /* ICH4: bit clock stopped */
 173 #define   ICH_SPINT             0x04000000      /* ICH4: S/PDIF interrupt */
 174 #define   ICH_P2INT             0x02000000      /* ICH4: PCM2-In interrupt */
 175 #define   ICH_M2INT             0x01000000      /* ICH4: Mic2-In interrupt */
 176 #define   ICH_SAMPLE_CAP        0x00c00000      /* ICH4: sample capability bits (RO) */
 177 #define   ICH_SAMPLE_16_20      0x00400000      /* ICH4: 16- and 20-bit samples */
 178 #define   ICH_MULTICHAN_CAP     0x00300000      /* ICH4: multi-channel capability bits (RO) */
 179 #define   ICH_MD3               0x00020000      /* modem power down semaphore */
 180 #define   ICH_AD3               0x00010000      /* audio power down semaphore */
 181 #define   ICH_RCS               0x00008000      /* read completion status */
 182 #define   ICH_BIT3              0x00004000      /* bit 3 slot 12 */
 183 #define   ICH_BIT2              0x00002000      /* bit 2 slot 12 */
 184 #define   ICH_BIT1              0x00001000      /* bit 1 slot 12 */
 185 #define   ICH_SRI               0x00000800      /* secondary (AC_SDIN1) resume interrupt */
 186 #define   ICH_PRI               0x00000400      /* primary (AC_SDIN0) resume interrupt */
 187 #define   ICH_SCR               0x00000200      /* secondary (AC_SDIN1) codec ready */
 188 #define   ICH_PCR               0x00000100      /* primary (AC_SDIN0) codec ready */
 189 #define   ICH_MCINT             0x00000080      /* MIC capture interrupt */
 190 #define   ICH_POINT             0x00000040      /* playback interrupt */
 191 #define   ICH_PIINT             0x00000020      /* capture interrupt */
 192 #define   ICH_NVSPINT           0x00000010      /* nforce spdif interrupt */
 193 #define   ICH_MOINT             0x00000004      /* modem playback interrupt */
 194 #define   ICH_MIINT             0x00000002      /* modem capture interrupt */
 195 #define   ICH_GSCI              0x00000001      /* GPI status change interrupt */
 196 #define ICH_REG_ACC_SEMA                0x34    /* byte - codec write semaphore */
 197 #define   ICH_CAS               0x01            /* codec access semaphore */
 198 #define ICH_REG_SDM             0x80
 199 #define   ICH_DI2L_MASK         0x000000c0      /* PCM In 2, Mic In 2 data in line */
 200 #define   ICH_DI2L_SHIFT        6
 201 #define   ICH_DI1L_MASK         0x00000030      /* PCM In 1, Mic In 1 data in line */
 202 #define   ICH_DI1L_SHIFT        4
 203 #define   ICH_SE                0x00000008      /* steer enable */
 204 #define   ICH_LDI_MASK          0x00000003      /* last codec read data input */
 205
 206 #define ICH_MAX_FRAGS           32              /* max hw frags */
 207
 208
 209 /*
 210  * registers for Ali5455
 211  */
 212
 213 /* ALi 5455 busmaster blocks */
 214 DEFINE_REGSET(AL_PI, 0x40);     /* ALi PCM in */
 215 DEFINE_REGSET(AL_PO, 0x50);     /* Ali PCM out */
 216 DEFINE_REGSET(AL_MC, 0x60);     /* Ali Mic in */
 217 DEFINE_REGSET(AL_CDC_SPO, 0x70);        /* Ali Codec SPDIF out */
 218 DEFINE_REGSET(AL_CENTER, 0x80);         /* Ali center out */
 219 DEFINE_REGSET(AL_LFE, 0x90);            /* Ali center out */
 220 DEFINE_REGSET(AL_CLR_SPI, 0xa0);        /* Ali Controller SPDIF in */
 221 DEFINE_REGSET(AL_CLR_SPO, 0xb0);        /* Ali Controller SPDIF out */
 222 DEFINE_REGSET(AL_I2S, 0xc0);    /* Ali I2S in */
 223 DEFINE_REGSET(AL_PI2, 0xd0);    /* Ali PCM2 in */
 224 DEFINE_REGSET(AL_MC2, 0xe0);    /* Ali Mic2 in */
 225
 226 enum {
 227         ICH_REG_ALI_SCR = 0x00,         /* System Control Register */
 228         ICH_REG_ALI_SSR = 0x04,         /* System Status Register  */
 229         ICH_REG_ALI_DMACR = 0x08,       /* DMA Control Register    */
 230         ICH_REG_ALI_FIFOCR1 = 0x0c,     /* FIFO Control Register 1  */
 231         ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
 232         ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
 233         ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt  Status Register */
 234         ICH_REG_ALI_FIFOCR2 = 0x1c,     /* FIFO Control Register 2   */
 235         ICH_REG_ALI_CPR = 0x20,         /* Command Port Register     */
 236         ICH_REG_ALI_CPR_ADDR = 0x22,    /* ac97 addr write */
 237         ICH_REG_ALI_SPR = 0x24,         /* Status Port Register      */
 238         ICH_REG_ALI_SPR_ADDR = 0x26,    /* ac97 addr read */
 239         ICH_REG_ALI_FIFOCR3 = 0x2c,     /* FIFO Control Register 3  */
 240         ICH_REG_ALI_TTSR = 0x30,        /* Transmit Tag Slot Register */
 241         ICH_REG_ALI_RTSR = 0x34,        /* Receive Tag Slot  Register */
 242         ICH_REG_ALI_CSPSR = 0x38,       /* Command/Status Port Status Register */
 243         ICH_REG_ALI_CAS = 0x3c,         /* Codec Write Semaphore Register */
 244         ICH_REG_ALI_HWVOL = 0xf0,       /* hardware volume control/status */
 245         ICH_REG_ALI_I2SCR = 0xf4,       /* I2S control/status */
 246         ICH_REG_ALI_SPDIFCSR = 0xf8,    /* spdif channel status register  */
 247         ICH_REG_ALI_SPDIFICS = 0xfc,    /* spdif interface control/status  */
 248 };
 249
 250 #define ALI_CAS_SEM_BUSY        0x80000000
 251 #define ALI_CPR_ADDR_SECONDARY  0x100
 252 #define ALI_CPR_ADDR_READ       0x80
 253 #define ALI_CSPSR_CODEC_READY   0x08
 254 #define ALI_CSPSR_READ_OK       0x02
 255 #define ALI_CSPSR_WRITE_OK      0x01
 256
 257 /* interrupts for the whole chip by interrupt status register finish */
 258
 259 #define ALI_INT_MICIN2          (1<<26)
 260 #define ALI_INT_PCMIN2          (1<<25)
 261 #define ALI_INT_I2SIN           (1<<24)
 262 #define ALI_INT_SPDIFOUT        (1<<23) /* controller spdif out INTERRUPT */
 263 #define ALI_INT_SPDIFIN         (1<<22)
 264 #define ALI_INT_LFEOUT          (1<<21)
 265 #define ALI_INT_CENTEROUT       (1<<20)
 266 #define ALI_INT_CODECSPDIFOUT   (1<<19)
 267 #define ALI_INT_MICIN           (1<<18)
 268 #define ALI_INT_PCMOUT          (1<<17)
 269 #define ALI_INT_PCMIN           (1<<16)
 270 #define ALI_INT_CPRAIS          (1<<7)  /* command port available */
 271 #define ALI_INT_SPRAIS          (1<<5)  /* status port available */
 272 #define ALI_INT_GPIO            (1<<1)
 273 #define ALI_INT_MASK            (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
 274
 275 #define ICH_ALI_SC_RESET        (1<<31) /* master reset */
 276 #define ICH_ALI_SC_AC97_DBL     (1<<30)
 277 #define ICH_ALI_SC_CODEC_SPDF   (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
 278 #define ICH_ALI_SC_IN_BITS      (3<<18)
 279 #define ICH_ALI_SC_OUT_BITS     (3<<16)
 280 #define ICH_ALI_SC_6CH_CFG      (3<<14)
 281 #define ICH_ALI_SC_PCM_4        (1<<8)
 282 #define ICH_ALI_SC_PCM_6        (2<<8)
 283 #define ICH_ALI_SC_PCM_246_MASK (3<<8)
 284
 285 #define ICH_ALI_SS_SEC_ID       (3<<5)
 286 #define ICH_ALI_SS_PRI_ID       (3<<3)
 287
 288 #define ICH_ALI_IF_AC97SP       (1<<21)
 289 #define ICH_ALI_IF_MC           (1<<20)
 290 #define ICH_ALI_IF_PI           (1<<19)
 291 #define ICH_ALI_IF_MC2          (1<<18)
 292 #define ICH_ALI_IF_PI2          (1<<17)
 293 #define ICH_ALI_IF_LINE_SRC     (1<<15) /* 0/1 = slot 3/6 */
 294 #define ICH_ALI_IF_MIC_SRC      (1<<14) /* 0/1 = slot 3/6 */
 295 #define ICH_ALI_IF_SPDF_SRC     (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
 296 #define ICH_ALI_IF_AC97_OUT     (3<<8)  /* 00 = PCM, 10 = spdif-in, 11 = i2s */
 297 #define ICH_ALI_IF_PO_SPDF      (1<<3)
 298 #define ICH_ALI_IF_PO           (1<<1)
 299
 300 /*
 301  *
 302  */
 303
 304 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR };
 305 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR };
 306 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT };
 307
 308 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data)
 309
 310 typedef struct {
 311         unsigned int ichd;                      /* ich device number */
 312         unsigned long reg_offset;               /* offset to bmaddr */
 313         u32 *bdbar;                             /* CPU address (32bit) */
 314         unsigned int bdbar_addr;                /* PCI bus address (32bit) */
 315         snd_pcm_substream_t *substream;
 316         unsigned int physbuf;                   /* physical address (32bit) */
 317         unsigned int size;
 318         unsigned int fragsize;
 319         unsigned int fragsize1;
 320         unsigned int position;
 321         unsigned int pos_shift;
 322         int frags;
 323         int lvi;
 324         int lvi_frag;
 325         int civ;
 326         int ack;
 327         int ack_reload;
 328         unsigned int ack_bit;
 329         unsigned int roff_sr;
 330         unsigned int roff_picb;
 331         unsigned int int_sta_mask;              /* interrupt status mask */
 332         unsigned int ali_slot;                  /* ALI DMA slot */
 333         struct ac97_pcm *pcm;
 334         int pcm_open_flag;
 335         unsigned int page_attr_changed: 1;
 336         unsigned int suspended: 1;
 337 } ichdev_t;
 338
 339 typedef struct _snd_intel8x0 intel8x0_t;
 340
 341 struct _snd_intel8x0 {
 342         unsigned int device_type;
 343
 344         int irq;
 345
 346         unsigned int mmio;
 347         unsigned long addr;
 348         void __iomem *remap_addr;
 349         unsigned int bm_mmio;
 350         unsigned long bmaddr;
 351         void __iomem *remap_bmaddr;
 352
 353         struct pci_dev *pci;
 354         snd_card_t *card;
 355
 356         int pcm_devs;
 357         snd_pcm_t *pcm[6];
 358         ichdev_t ichd[6];
 359
 360         unsigned multi4: 1,
 361                  multi6: 1,
 362                  dra: 1,
 363                  smp20bit: 1;
 364         unsigned in_ac97_init: 1,
 365                  in_sdin_init: 1;
 366         unsigned in_measurement: 1;     /* during ac97 clock measurement */
 367         unsigned fix_nocache: 1;        /* workaround for 440MX */
 368         unsigned buggy_irq: 1;          /* workaround for buggy mobos */
 369         unsigned xbox: 1;               /* workaround for Xbox AC'97 detection */
 370
 371         int spdif_idx;  /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
 372         unsigned int sdm_saved; /* SDM reg value */
 373
 374         ac97_bus_t *ac97_bus;
 375         ac97_t *ac97[3];
 376         unsigned int ac97_sdin[3];
 377
 378         spinlock_t reg_lock;
 379
 380         u32 bdbars_count;
 381         struct snd_dma_buffer bdbars;
 382         u32 int_sta_reg;                /* interrupt status register */
 383         u32 int_sta_mask;               /* interrupt status mask */
 384 };
 385
 386 static struct pci_device_id snd_intel8x0_ids[] = {
 387         { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */
 388         { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */
 389         { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */
 390         { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */
 391         { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */
 392         { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */
 393         { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */
 394         { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */
 395         { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */
 396         { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */
 397         { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */
 398         { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },   /* SI7012 */
 399         { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE */
 400         { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* MCP04 */
 401         { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE2 */
 402         { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK804 */
 403         { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8 */
 404         { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* NFORCE3 */
 405         { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE },        /* CK8S */
 406         { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */
 407         { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */
 408         { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
 409         { 0, }
 410 };
 411
 412 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
 413
 414 /*
 415  *  Lowlevel I/O - busmaster
 416  */
 417
 418 static u8 igetbyte(intel8x0_t *chip, u32 offset)
 419 {
 420         if (chip->bm_mmio)
 421                 return readb(chip->remap_bmaddr + offset);
 422         else
 423                 return inb(chip->bmaddr + offset);
 424 }
 425
 426 static u16 igetword(intel8x0_t *chip, u32 offset)
 427 {
 428         if (chip->bm_mmio)
 429                 return readw(chip->remap_bmaddr + offset);
 430         else
 431                 return inw(chip->bmaddr + offset);
 432 }
 433
 434 static u32 igetdword(intel8x0_t *chip, u32 offset)
 435 {
 436         if (chip->bm_mmio)
 437                 return readl(chip->remap_bmaddr + offset);
 438         else
 439                 return inl(chip->bmaddr + offset);
 440 }
 441
 442 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val)
 443 {
 444         if (chip->bm_mmio)
 445                 writeb(val, chip->remap_bmaddr + offset);
 446         else
 447                 outb(val, chip->bmaddr + offset);
 448 }
 449
 450 static void iputword(intel8x0_t *chip, u32 offset, u16 val)
 451 {
 452         if (chip->bm_mmio)
 453                 writew(val, chip->remap_bmaddr + offset);
 454         else
 455                 outw(val, chip->bmaddr + offset);
 456 }
 457
 458 static void iputdword(intel8x0_t *chip, u32 offset, u32 val)
 459 {
 460         if (chip->bm_mmio)
 461                 writel(val, chip->remap_bmaddr + offset);
 462         else
 463                 outl(val, chip->bmaddr + offset);
 464 }
 465
 466 /*
 467  *  Lowlevel I/O - AC'97 registers
 468  */
 469
 470 static u16 iagetword(intel8x0_t *chip, u32 offset)
 471 {
 472         if (chip->mmio)
 473                 return readw(chip->remap_addr + offset);
 474         else
 475                 return inw(chip->addr + offset);
 476 }
 477
 478 static void iaputword(intel8x0_t *chip, u32 offset, u16 val)
 479 {
 480         if (chip->mmio)
 481                 writew(val, chip->remap_addr + offset);
 482         else
 483                 outw(val, chip->addr + offset);
 484 }
 485
 486 /*
 487  *  Basic I/O
 488  */
 489
 490 /*
 491  * access to AC97 codec via normal i/o (for ICH and SIS7012)
 492  */
 493
 494 /* return the GLOB_STA bit for the corresponding codec */
 495 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec)
 496 {
 497         static unsigned int codec_bit[3] = {
 498                 ICH_PCR, ICH_SCR, ICH_TCR
 499         };
 500         snd_assert(codec < 3, return ICH_PCR);
 501         if (chip->device_type == DEVICE_INTEL_ICH4)
 502                 codec = chip->ac97_sdin[codec];
 503         return codec_bit[codec];
 504 }
 505
 506 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec)
 507 {
 508         int time;
 509
 510         if (codec > 2)
 511                 return -EIO;
 512         if (chip->in_sdin_init) {
 513                 /* we don't know the ready bit assignment at the moment */
 514                 /* so we check any */
 515                 codec = ICH_PCR | ICH_SCR | ICH_TCR;
 516         } else {
 517                 codec = get_ich_codec_bit(chip, codec);
 518         }
 519
 520         /* codec ready ? */
 521         if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
 522                 return -EIO;
 523
 524         /* Anyone holding a semaphore for 1 msec should be shot... */
 525         time = 100;
 526         do {
 527                 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
 528                         return 0;
 529                 udelay(10);
 530         } while (time--);
 531
 532         /* access to some forbidden (non existant) ac97 registers will not
 533          * reset the semaphore. So even if you don't get the semaphore, still
 534          * continue the access. We don't need the semaphore anyway. */
 535         snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
 536                         igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
 537         iagetword(chip, 0);     /* clear semaphore flag */
 538         /* I don't care about the semaphore */
 539         return -EBUSY;
 540 }
 541
 542 static void snd_intel8x0_codec_write(ac97_t *ac97,
 543                                      unsigned short reg,
 544                                      unsigned short val)
 545 {
 546         intel8x0_t *chip = ac97->private_data;
 547
 548         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 549                 if (! chip->in_ac97_init)
 550                         snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 551         }
 552         iaputword(chip, reg + ac97->num * 0x80, val);
 553 }
 554
 555 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97,
 556                                               unsigned short reg)
 557 {
 558         intel8x0_t *chip = ac97->private_data;
 559         unsigned short res;
 560         unsigned int tmp;
 561
 562         if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
 563                 if (! chip->in_ac97_init)
 564                         snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
 565                 res = 0xffff;
 566         } else {
 567                 res = iagetword(chip, reg + ac97->num * 0x80);
 568                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 569                         /* reset RCS and preserve other R/WC bits */
 570                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 571                         if (! chip->in_ac97_init)
 572                                 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
 573                         res = 0xffff;
 574                 }
 575         }
 576         return res;
 577 }
 578
 579 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec)
 580 {
 581         unsigned int tmp;
 582
 583         if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
 584                 iagetword(chip, codec * 0x80);
 585                 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
 586                         /* reset RCS and preserve other R/WC bits */
 587                         iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
 588                 }
 589         }
 590 }
 591
 592 /*
 593  * access to AC97 for Ali5455
 594  */
 595 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask)
 596 {
 597         int count = 0;
 598         for (count = 0; count < 0x7f; count++) {
 599                 int val = igetbyte(chip, ICHREG(ALI_CSPSR));
 600                 if (val & mask)
 601                         return 0;
 602         }
 603         snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
 604         return -EBUSY;
 605 }
 606
 607 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip)
 608 {
 609         int time = 100;
 610         while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
 611                 udelay(1);
 612         if (! time)
 613                 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
 614         return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
 615 }
 616
 617 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg)
 618 {
 619         intel8x0_t *chip = ac97->private_data;
 620         unsigned short data = 0xffff;
 621
 622         if (snd_intel8x0_ali_codec_semaphore(chip))
 623                 goto __err;
 624         reg |= ALI_CPR_ADDR_READ;
 625         if (ac97->num)
 626                 reg |= ALI_CPR_ADDR_SECONDARY;
 627         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 628         if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
 629                 goto __err;
 630         data = igetword(chip, ICHREG(ALI_SPR));
 631  __err:
 632         return data;
 633 }
 634
 635 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val)
 636 {
 637         intel8x0_t *chip = ac97->private_data;
 638
 639         if (snd_intel8x0_ali_codec_semaphore(chip))
 640                 return;
 641         iputword(chip, ICHREG(ALI_CPR), val);
 642         if (ac97->num)
 643                 reg |= ALI_CPR_ADDR_SECONDARY;
 644         iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
 645         snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
 646 }
 647
 648
 649 /*
 650  * DMA I/O
 651  */
 652 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev)
 653 {
 654         int idx;
 655         u32 *bdbar = ichdev->bdbar;
 656         unsigned long port = ichdev->reg_offset;
 657
 658         iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
 659         if (ichdev->size == ichdev->fragsize) {
 660                 ichdev->ack_reload = ichdev->ack = 2;
 661                 ichdev->fragsize1 = ichdev->fragsize >> 1;
 662                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
 663                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
 664                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 665                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 666                         bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
 667                         bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 668                                                      ichdev->fragsize1 >> ichdev->pos_shift);
 669                 }
 670                 ichdev->frags = 2;
 671         } else {
 672                 ichdev->ack_reload = ichdev->ack = 1;
 673                 ichdev->fragsize1 = ichdev->fragsize;
 674                 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
 675                         bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
 676                         bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
 677                                                      ichdev->fragsize >> ichdev->pos_shift);
 678                         // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
 679                 }
 680                 ichdev->frags = ichdev->size / ichdev->fragsize;
 681         }
 682         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
 683         ichdev->civ = 0;
 684         iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
 685         ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
 686         ichdev->position = 0;
 687 #if 0
 688         printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
 689                         ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
 690 #endif
 691         /* clear interrupts */
 692         iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
 693 }
 694
 695 #ifdef __i386__
 696 /*
 697  * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 698  * which aborts PCI busmaster for audio transfer.  A workaround is to set
 699  * the pages as non-cached.  For details, see the errata in
 700  *      http://www.intel.com/design/chipsets/specupdt/245051.htm
 701  */
 702 static void fill_nocache(void *buf, int size, int nocache)
 703 {
 704         size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 705         change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL);
 706         global_flush_tlb();
 707 }
 708 #else
 709 #define fill_nocache(buf,size,nocache)
 710 #endif
 711
 712 /*
 713  *  Interrupt handler
 714  */
 715
 716 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev)
 717 {
 718         unsigned long port = ichdev->reg_offset;
 719         int status, civ, i, step;
 720         int ack = 0;
 721
 722         spin_lock(&chip->reg_lock);
 723         status = igetbyte(chip, port + ichdev->roff_sr);
 724         civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
 725         if (!(status & ICH_BCIS)) {
 726                 step = 0;
 727         } else if (civ == ichdev->civ) {
 728                 // snd_printd("civ same %d\n", civ);
 729                 step = 1;
 730                 ichdev->civ++;
 731                 ichdev->civ &= ICH_REG_LVI_MASK;
 732         } else {
 733                 step = civ - ichdev->civ;
 734                 if (step < 0)
 735                         step += ICH_REG_LVI_MASK + 1;
 736                 // if (step != 1)
 737                 //      snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
 738                 ichdev->civ = civ;
 739         }
 740
 741         ichdev->position += step * ichdev->fragsize1;
 742         if (! chip->in_measurement)
 743                 ichdev->position %= ichdev->size;
 744         ichdev->lvi += step;
 745         ichdev->lvi &= ICH_REG_LVI_MASK;
 746         iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
 747         for (i = 0; i < step; i++) {
 748                 ichdev->lvi_frag++;
 749                 ichdev->lvi_frag %= ichdev->frags;
 750                 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
 751         // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR));
 752                 if (--ichdev->ack == 0) {
 753                         ichdev->ack = ichdev->ack_reload;
 754                         ack = 1;
 755                 }
 756         }
 757         spin_unlock(&chip->reg_lock);
 758         if (ack && ichdev->substream) {
 759                 snd_pcm_period_elapsed(ichdev->substream);
 760         }
 761         iputbyte(chip, port + ichdev->roff_sr,
 762                  status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
 763 }
 764
 765 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 766 {
 767         intel8x0_t *chip = dev_id;
 768         ichdev_t *ichdev;
 769         unsigned int status;
 770         unsigned int i;
 771
 772         status = igetdword(chip, chip->int_sta_reg);
 773         if (status == 0xffffffff)       /* we are not yet resumed */
 774                 return IRQ_NONE;
 775
 776         if ((status & chip->int_sta_mask) == 0) {
 777                 if (status) {
 778                         /* ack */
 779                         iputdword(chip, chip->int_sta_reg, status);
 780                         if (! chip->buggy_irq)
 781                                 status = 0;
 782                 }
 783                 return IRQ_RETVAL(status);
 784         }
 785
 786         for (i = 0; i < chip->bdbars_count; i++) {
 787                 ichdev = &chip->ichd[i];
 788                 if (status & ichdev->int_sta_mask)
 789                         snd_intel8x0_update(chip, ichdev);
 790         }
 791
 792         /* ack them */
 793         iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
 794
 795         return IRQ_HANDLED;
 796 }
 797
 798 /*
 799  *  PCM part
 800  */
 801
 802 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
 803 {
 804         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 805         ichdev_t *ichdev = get_ichdev(substream);
 806         unsigned char val = 0;
 807         unsigned long port = ichdev->reg_offset;
 808
 809         switch (cmd) {
 810         case SNDRV_PCM_TRIGGER_RESUME:
 811                 ichdev->suspended = 0;
 812                 /* fallthru */
 813         case SNDRV_PCM_TRIGGER_START:
 814                 val = ICH_IOCE | ICH_STARTBM;
 815                 break;
 816         case SNDRV_PCM_TRIGGER_SUSPEND:
 817                 ichdev->suspended = 1;
 818                 /* fallthru */
 819         case SNDRV_PCM_TRIGGER_STOP:
 820                 val = 0;
 821                 break;
 822         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 823                 val = ICH_IOCE;
 824                 break;
 825         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 826                 val = ICH_IOCE | ICH_STARTBM;
 827                 break;
 828         default:
 829                 return -EINVAL;
 830         }
 831         iputbyte(chip, port + ICH_REG_OFF_CR, val);
 832         if (cmd == SNDRV_PCM_TRIGGER_STOP) {
 833                 /* wait until DMA stopped */
 834                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
 835                 /* reset whole DMA things */
 836                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 837         }
 838         return 0;
 839 }
 840
 841 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd)
 842 {
 843         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 844         ichdev_t *ichdev = get_ichdev(substream);
 845         unsigned long port = ichdev->reg_offset;
 846         static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) };
 847         unsigned int val, fifo;
 848
 849         val = igetdword(chip, ICHREG(ALI_DMACR));
 850         switch (cmd) {
 851         case SNDRV_PCM_TRIGGER_RESUME:
 852                 ichdev->suspended = 0;
 853                 /* fallthru */
 854         case SNDRV_PCM_TRIGGER_START:
 855         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 856                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 857                         /* clear FIFO for synchronization of channels */
 858                         fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
 859                         fifo &= ~(0xff << (ichdev->ali_slot % 4));
 860                         fifo |= 0x83 << (ichdev->ali_slot % 4);
 861                         iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
 862                 }
 863                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
 864                 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
 865                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */
 866                 break;
 867         case SNDRV_PCM_TRIGGER_SUSPEND:
 868                 ichdev->suspended = 1;
 869                 /* fallthru */
 870         case SNDRV_PCM_TRIGGER_STOP:
 871         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 872                 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */
 873                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
 874                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
 875                         ;
 876                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 877                         break;
 878                 /* reset whole DMA things */
 879                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
 880                 /* clear interrupts */
 881                 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
 882                 iputdword(chip, ICHREG(ALI_INTERRUPTSR),
 883                           igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
 884                 break;
 885         default:
 886                 return -EINVAL;
 887         }
 888         return 0;
 889 }
 890
 891 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream,
 892                                   snd_pcm_hw_params_t * hw_params)
 893 {
 894         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 895         ichdev_t *ichdev = get_ichdev(substream);
 896         snd_pcm_runtime_t *runtime = substream->runtime;
 897         int dbl = params_rate(hw_params) > 48000;
 898         int err;
 899
 900         if (chip->fix_nocache && ichdev->page_attr_changed) {
 901                 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
 902                 ichdev->page_attr_changed = 0;
 903         }
 904         err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 905         if (err < 0)
 906                 return err;
 907         if (chip->fix_nocache) {
 908                 if (runtime->dma_area && ! ichdev->page_attr_changed) {
 909                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
 910                         ichdev->page_attr_changed = 1;
 911                 }
 912         }
 913         if (ichdev->pcm_open_flag) {
 914                 snd_ac97_pcm_close(ichdev->pcm);
 915                 ichdev->pcm_open_flag = 0;
 916         }
 917         err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
 918                                 params_channels(hw_params),
 919                                 ichdev->pcm->r[dbl].slots);
 920         if (err >= 0) {
 921                 ichdev->pcm_open_flag = 1;
 922                 /* Force SPDIF setting */
 923                 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
 924                         snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params));
 925         }
 926         return err;
 927 }
 928
 929 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream)
 930 {
 931         intel8x0_t *chip = snd_pcm_substream_chip(substream);
 932         ichdev_t *ichdev = get_ichdev(substream);
 933
 934         if (ichdev->pcm_open_flag) {
 935                 snd_ac97_pcm_close(ichdev->pcm);
 936                 ichdev->pcm_open_flag = 0;
 937         }
 938         if (chip->fix_nocache && ichdev->page_attr_changed) {
 939                 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
 940                 ichdev->page_attr_changed = 0;
 941         }
 942         return snd_pcm_lib_free_pages(substream);
 943 }
 944
 945 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip,
 946                                        snd_pcm_runtime_t *runtime)
 947 {
 948         unsigned int cnt;
 949         int dbl = runtime->rate > 48000;
 950
 951         spin_lock_irq(&chip->reg_lock);
 952         switch (chip->device_type) {
 953         case DEVICE_ALI:
 954                 cnt = igetdword(chip, ICHREG(ALI_SCR));
 955                 cnt &= ~ICH_ALI_SC_PCM_246_MASK;
 956                 if (runtime->channels == 4 || dbl)
 957                         cnt |= ICH_ALI_SC_PCM_4;
 958                 else if (runtime->channels == 6)
 959                         cnt |= ICH_ALI_SC_PCM_6;
 960                 iputdword(chip, ICHREG(ALI_SCR), cnt);
 961                 break;
 962         case DEVICE_SIS:
 963                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 964                 cnt &= ~ICH_SIS_PCM_246_MASK;
 965                 if (runtime->channels == 4 || dbl)
 966                         cnt |= ICH_SIS_PCM_4;
 967                 else if (runtime->channels == 6)
 968                         cnt |= ICH_SIS_PCM_6;
 969                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 970                 break;
 971         default:
 972                 cnt = igetdword(chip, ICHREG(GLOB_CNT));
 973                 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
 974                 if (runtime->channels == 4 || dbl)
 975                         cnt |= ICH_PCM_4;
 976                 else if (runtime->channels == 6)
 977                         cnt |= ICH_PCM_6;
 978                 if (chip->device_type == DEVICE_NFORCE) {
 979                         /* reset to 2ch once to keep the 6 channel data in alignment,
 980                          * to start from Front Left always
 981                          */
 982                         if (cnt & ICH_PCM_246_MASK) {
 983                                 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
 984                                 spin_unlock_irq(&chip->reg_lock);
 985                                 msleep(50); /* grrr... */
 986                                 spin_lock_irq(&chip->reg_lock);
 987                         }
 988                 } else if (chip->device_type == DEVICE_INTEL_ICH4) {
 989                         if (runtime->sample_bits > 16)
 990                                 cnt |= ICH_PCM_20BIT;
 991                 }
 992                 iputdword(chip, ICHREG(GLOB_CNT), cnt);
 993                 break;
 994         }
 995         spin_unlock_irq(&chip->reg_lock);
 996 }
 997
 998 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream)
 999 {
1000         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1001         snd_pcm_runtime_t *runtime = substream->runtime;
1002         ichdev_t *ichdev = get_ichdev(substream);
1003
1004         ichdev->physbuf = runtime->dma_addr;
1005         ichdev->size = snd_pcm_lib_buffer_bytes(substream);
1006         ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
1007         if (ichdev->ichd == ICHD_PCMOUT) {
1008                 snd_intel8x0_setup_pcm_out(chip, runtime);
1009                 if (chip->device_type == DEVICE_INTEL_ICH4)
1010                         ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
1011         }
1012         snd_intel8x0_setup_periods(chip, ichdev);
1013         return 0;
1014 }
1015
1016 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream)
1017 {
1018         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1019         ichdev_t *ichdev = get_ichdev(substream);
1020         size_t ptr1, ptr;
1021         int civ, timeout = 100;
1022         unsigned int position;
1023
1024         spin_lock(&chip->reg_lock);
1025         do {
1026                 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
1027                 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
1028                 position = ichdev->position;
1029                 if (ptr1 == 0) {
1030                         udelay(10);
1031                         continue;
1032                 }
1033                 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
1034                     ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
1035                         break;
1036         } while (timeout--);
1037         ptr1 <<= ichdev->pos_shift;
1038         ptr = ichdev->fragsize1 - ptr1;
1039         ptr += position;
1040         spin_unlock(&chip->reg_lock);
1041         if (ptr >= ichdev->size)
1042                 return 0;
1043         return bytes_to_frames(substream->runtime, ptr);
1044 }
1045
1046 static snd_pcm_hardware_t snd_intel8x0_stream =
1047 {
1048         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1049                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1050                                  SNDRV_PCM_INFO_MMAP_VALID |
1051                                  SNDRV_PCM_INFO_PAUSE |
1052                                  SNDRV_PCM_INFO_RESUME),
1053         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1054         .rates =                SNDRV_PCM_RATE_48000,
1055         .rate_min =             48000,
1056         .rate_max =             48000,
1057         .channels_min =         2,
1058         .channels_max =         2,
1059         .buffer_bytes_max =     128 * 1024,
1060         .period_bytes_min =     32,
1061         .period_bytes_max =     128 * 1024,
1062         .periods_min =          1,
1063         .periods_max =          1024,
1064         .fifo_size =            0,
1065 };
1066
1067 static unsigned int channels4[] = {
1068         2, 4,
1069 };
1070
1071 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = {
1072         .count = ARRAY_SIZE(channels4),
1073         .list = channels4,
1074         .mask = 0,
1075 };
1076
1077 static unsigned int channels6[] = {
1078         2, 4, 6,
1079 };
1080
1081 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = {
1082         .count = ARRAY_SIZE(channels6),
1083         .list = channels6,
1084         .mask = 0,
1085 };
1086
1087 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev)
1088 {
1089         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1090         snd_pcm_runtime_t *runtime = substream->runtime;
1091         int err;
1092
1093         ichdev->substream = substream;
1094         runtime->hw = snd_intel8x0_stream;
1095         runtime->hw.rates = ichdev->pcm->rates;
1096         snd_pcm_limit_hw_rates(runtime);
1097         if (chip->device_type == DEVICE_SIS) {
1098                 runtime->hw.buffer_bytes_max = 64*1024;
1099                 runtime->hw.period_bytes_max = 64*1024;
1100         }
1101         if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
1102                 return err;
1103         runtime->private_data = ichdev;
1104         return 0;
1105 }
1106
1107 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream)
1108 {
1109         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1110         snd_pcm_runtime_t *runtime = substream->runtime;
1111         int err;
1112
1113         err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
1114         if (err < 0)
1115                 return err;
1116
1117         if (chip->multi6) {
1118                 runtime->hw.channels_max = 6;
1119                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6);
1120         } else if (chip->multi4) {
1121                 runtime->hw.channels_max = 4;
1122                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4);
1123         }
1124         if (chip->dra) {
1125                 snd_ac97_pcm_double_rate_rules(runtime);
1126         }
1127         if (chip->smp20bit) {
1128                 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1129                 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
1130         }
1131         return 0;
1132 }
1133
1134 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream)
1135 {
1136         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1137
1138         chip->ichd[ICHD_PCMOUT].substream = NULL;
1139         return 0;
1140 }
1141
1142 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream)
1143 {
1144         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1145
1146         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
1147 }
1148
1149 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream)
1150 {
1151         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1152
1153         chip->ichd[ICHD_PCMIN].substream = NULL;
1154         return 0;
1155 }
1156
1157 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream)
1158 {
1159         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1160
1161         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
1162 }
1163
1164 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream)
1165 {
1166         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1167
1168         chip->ichd[ICHD_MIC].substream = NULL;
1169         return 0;
1170 }
1171
1172 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream)
1173 {
1174         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1175
1176         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
1177 }
1178
1179 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream)
1180 {
1181         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1182
1183         chip->ichd[ICHD_MIC2].substream = NULL;
1184         return 0;
1185 }
1186
1187 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream)
1188 {
1189         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1190
1191         return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
1192 }
1193
1194 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream)
1195 {
1196         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1197
1198         chip->ichd[ICHD_PCM2IN].substream = NULL;
1199         return 0;
1200 }
1201
1202 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream)
1203 {
1204         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1205         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1206
1207         return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
1208 }
1209
1210 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream)
1211 {
1212         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1213         int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
1214
1215         chip->ichd[idx].substream = NULL;
1216         return 0;
1217 }
1218
1219 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream)
1220 {
1221         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1222         unsigned int val;
1223
1224         spin_lock_irq(&chip->reg_lock);
1225         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1226         val |= ICH_ALI_IF_AC97SP;
1227         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1228         /* also needs to set ALI_SC_CODEC_SPDF correctly */
1229         spin_unlock_irq(&chip->reg_lock);
1230
1231         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
1232 }
1233
1234 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream)
1235 {
1236         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1237         unsigned int val;
1238
1239         chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
1240         spin_lock_irq(&chip->reg_lock);
1241         val = igetdword(chip, ICHREG(ALI_INTERFACECR));
1242         val &= ~ICH_ALI_IF_AC97SP;
1243         iputdword(chip, ICHREG(ALI_INTERFACECR), val);
1244         spin_unlock_irq(&chip->reg_lock);
1245
1246         return 0;
1247 }
1248
1249 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream)
1250 {
1251         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1252
1253         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
1254 }
1255
1256 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream)
1257 {
1258         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1259
1260         chip->ichd[ALID_SPDIFIN].substream = NULL;
1261         return 0;
1262 }
1263
1264 #if 0 // NYI
1265 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream)
1266 {
1267         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1268
1269         return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
1270 }
1271
1272 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream)
1273 {
1274         intel8x0_t *chip = snd_pcm_substream_chip(substream);
1275
1276         chip->ichd[ALID_SPDIFOUT].substream = NULL;
1277         return 0;
1278 }
1279 #endif
1280
1281 static snd_pcm_ops_t snd_intel8x0_playback_ops = {
1282         .open =         snd_intel8x0_playback_open,
1283         .close =        snd_intel8x0_playback_close,
1284         .ioctl =        snd_pcm_lib_ioctl,
1285         .hw_params =    snd_intel8x0_hw_params,
1286         .hw_free =      snd_intel8x0_hw_free,
1287         .prepare =      snd_intel8x0_pcm_prepare,
1288         .trigger =      snd_intel8x0_pcm_trigger,
1289         .pointer =      snd_intel8x0_pcm_pointer,
1290 };
1291
1292 static snd_pcm_ops_t snd_intel8x0_capture_ops = {
1293         .open =         snd_intel8x0_capture_open,
1294         .close =        snd_intel8x0_capture_close,
1295         .ioctl =        snd_pcm_lib_ioctl,
1296         .hw_params =    snd_intel8x0_hw_params,
1297         .hw_free =      snd_intel8x0_hw_free,
1298         .prepare =      snd_intel8x0_pcm_prepare,
1299         .trigger =      snd_intel8x0_pcm_trigger,
1300         .pointer =      snd_intel8x0_pcm_pointer,
1301 };
1302
1303 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = {
1304         .open =         snd_intel8x0_mic_open,
1305         .close =        snd_intel8x0_mic_close,
1306         .ioctl =        snd_pcm_lib_ioctl,
1307         .hw_params =    snd_intel8x0_hw_params,
1308         .hw_free =      snd_intel8x0_hw_free,
1309         .prepare =      snd_intel8x0_pcm_prepare,
1310         .trigger =      snd_intel8x0_pcm_trigger,
1311         .pointer =      snd_intel8x0_pcm_pointer,
1312 };
1313
1314 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = {
1315         .open =         snd_intel8x0_mic2_open,
1316         .close =        snd_intel8x0_mic2_close,
1317         .ioctl =        snd_pcm_lib_ioctl,
1318         .hw_params =    snd_intel8x0_hw_params,
1319         .hw_free =      snd_intel8x0_hw_free,
1320         .prepare =      snd_intel8x0_pcm_prepare,
1321         .trigger =      snd_intel8x0_pcm_trigger,
1322         .pointer =      snd_intel8x0_pcm_pointer,
1323 };
1324
1325 static snd_pcm_ops_t snd_intel8x0_capture2_ops = {
1326         .open =         snd_intel8x0_capture2_open,
1327         .close =        snd_intel8x0_capture2_close,
1328         .ioctl =        snd_pcm_lib_ioctl,
1329         .hw_params =    snd_intel8x0_hw_params,
1330         .hw_free =      snd_intel8x0_hw_free,
1331         .prepare =      snd_intel8x0_pcm_prepare,
1332         .trigger =      snd_intel8x0_pcm_trigger,
1333         .pointer =      snd_intel8x0_pcm_pointer,
1334 };
1335
1336 static snd_pcm_ops_t snd_intel8x0_spdif_ops = {
1337         .open =         snd_intel8x0_spdif_open,
1338         .close =        snd_intel8x0_spdif_close,
1339         .ioctl =        snd_pcm_lib_ioctl,
1340         .hw_params =    snd_intel8x0_hw_params,
1341         .hw_free =      snd_intel8x0_hw_free,
1342         .prepare =      snd_intel8x0_pcm_prepare,
1343         .trigger =      snd_intel8x0_pcm_trigger,
1344         .pointer =      snd_intel8x0_pcm_pointer,
1345 };
1346
1347 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = {
1348         .open =         snd_intel8x0_playback_open,
1349         .close =        snd_intel8x0_playback_close,
1350         .ioctl =        snd_pcm_lib_ioctl,
1351         .hw_params =    snd_intel8x0_hw_params,
1352         .hw_free =      snd_intel8x0_hw_free,
1353         .prepare =      snd_intel8x0_pcm_prepare,
1354         .trigger =      snd_intel8x0_ali_trigger,
1355         .pointer =      snd_intel8x0_pcm_pointer,
1356 };
1357
1358 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = {
1359         .open =         snd_intel8x0_capture_open,
1360         .close =        snd_intel8x0_capture_close,
1361         .ioctl =        snd_pcm_lib_ioctl,
1362         .hw_params =    snd_intel8x0_hw_params,
1363         .hw_free =      snd_intel8x0_hw_free,
1364         .prepare =      snd_intel8x0_pcm_prepare,
1365         .trigger =      snd_intel8x0_ali_trigger,
1366         .pointer =      snd_intel8x0_pcm_pointer,
1367 };
1368
1369 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = {
1370         .open =         snd_intel8x0_mic_open,
1371         .close =        snd_intel8x0_mic_close,
1372         .ioctl =        snd_pcm_lib_ioctl,
1373         .hw_params =    snd_intel8x0_hw_params,
1374         .hw_free =      snd_intel8x0_hw_free,
1375         .prepare =      snd_intel8x0_pcm_prepare,
1376         .trigger =      snd_intel8x0_ali_trigger,
1377         .pointer =      snd_intel8x0_pcm_pointer,
1378 };
1379
1380 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = {
1381         .open =         snd_intel8x0_ali_ac97spdifout_open,
1382         .close =        snd_intel8x0_ali_ac97spdifout_close,
1383         .ioctl =        snd_pcm_lib_ioctl,
1384         .hw_params =    snd_intel8x0_hw_params,
1385         .hw_free =      snd_intel8x0_hw_free,
1386         .prepare =      snd_intel8x0_pcm_prepare,
1387         .trigger =      snd_intel8x0_ali_trigger,
1388         .pointer =      snd_intel8x0_pcm_pointer,
1389 };
1390
1391 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = {
1392         .open =         snd_intel8x0_ali_spdifin_open,
1393         .close =        snd_intel8x0_ali_spdifin_close,
1394         .ioctl =        snd_pcm_lib_ioctl,
1395         .hw_params =    snd_intel8x0_hw_params,
1396         .hw_free =      snd_intel8x0_hw_free,
1397         .prepare =      snd_intel8x0_pcm_prepare,
1398         .trigger =      snd_intel8x0_pcm_trigger,
1399         .pointer =      snd_intel8x0_pcm_pointer,
1400 };
1401
1402 #if 0 // NYI
1403 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = {
1404         .open =         snd_intel8x0_ali_spdifout_open,
1405         .close =        snd_intel8x0_ali_spdifout_close,
1406         .ioctl =        snd_pcm_lib_ioctl,
1407         .hw_params =    snd_intel8x0_hw_params,
1408         .hw_free =      snd_intel8x0_hw_free,
1409         .prepare =      snd_intel8x0_pcm_prepare,
1410         .trigger =      snd_intel8x0_pcm_trigger,
1411         .pointer =      snd_intel8x0_pcm_pointer,
1412 };
1413 #endif // NYI
1414
1415 struct ich_pcm_table {
1416         char *suffix;
1417         snd_pcm_ops_t *playback_ops;
1418         snd_pcm_ops_t *capture_ops;
1419         size_t prealloc_size;
1420         size_t prealloc_max_size;
1421         int ac97_idx;
1422 };
1423
1424 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec)
1425 {
1426         snd_pcm_t *pcm;
1427         int err;
1428         char name[32];
1429
1430         if (rec->suffix)
1431                 sprintf(name, "Intel ICH - %s", rec->suffix);
1432         else
1433                 strcpy(name, "Intel ICH");
1434         err = snd_pcm_new(chip->card, name, device,
1435                           rec->playback_ops ? 1 : 0,
1436                           rec->capture_ops ? 1 : 0, &pcm);
1437         if (err < 0)
1438                 return err;
1439
1440         if (rec->playback_ops)
1441                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
1442         if (rec->capture_ops)
1443                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
1444
1445         pcm->private_data = chip;
1446         pcm->info_flags = 0;
1447         if (rec->suffix)
1448                 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
1449         else
1450                 strcpy(pcm->name, chip->card->shortname);
1451         chip->pcm[device] = pcm;
1452
1453         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1454                                               rec->prealloc_size, rec->prealloc_max_size);
1455
1456         return 0;
1457 }
1458
1459 static struct ich_pcm_table intel_pcms[] __devinitdata = {
1460         {
1461                 .playback_ops = &snd_intel8x0_playback_ops,
1462                 .capture_ops = &snd_intel8x0_capture_ops,
1463                 .prealloc_size = 64 * 1024,
1464                 .prealloc_max_size = 128 * 1024,
1465         },
1466         {
1467                 .suffix = "MIC ADC",
1468                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1469                 .prealloc_size = 0,
1470                 .prealloc_max_size = 128 * 1024,
1471                 .ac97_idx = ICHD_MIC,
1472         },
1473         {
1474                 .suffix = "MIC2 ADC",
1475                 .capture_ops = &snd_intel8x0_capture_mic2_ops,
1476                 .prealloc_size = 0,
1477                 .prealloc_max_size = 128 * 1024,
1478                 .ac97_idx = ICHD_MIC2,
1479         },
1480         {
1481                 .suffix = "ADC2",
1482                 .capture_ops = &snd_intel8x0_capture2_ops,
1483                 .prealloc_size = 0,
1484                 .prealloc_max_size = 128 * 1024,
1485                 .ac97_idx = ICHD_PCM2IN,
1486         },
1487         {
1488                 .suffix = "IEC958",
1489                 .playback_ops = &snd_intel8x0_spdif_ops,
1490                 .prealloc_size = 64 * 1024,
1491                 .prealloc_max_size = 128 * 1024,
1492                 .ac97_idx = ICHD_SPBAR,
1493         },
1494 };
1495
1496 static struct ich_pcm_table nforce_pcms[] __devinitdata = {
1497         {
1498                 .playback_ops = &snd_intel8x0_playback_ops,
1499                 .capture_ops = &snd_intel8x0_capture_ops,
1500                 .prealloc_size = 64 * 1024,
1501                 .prealloc_max_size = 128 * 1024,
1502         },
1503         {
1504                 .suffix = "MIC ADC",
1505                 .capture_ops = &snd_intel8x0_capture_mic_ops,
1506                 .prealloc_size = 0,
1507                 .prealloc_max_size = 128 * 1024,
1508                 .ac97_idx = NVD_MIC,
1509         },
1510         {
1511                 .suffix = "IEC958",
1512                 .playback_ops = &snd_intel8x0_spdif_ops,
1513                 .prealloc_size = 64 * 1024,
1514                 .prealloc_max_size = 128 * 1024,
1515                 .ac97_idx = NVD_SPBAR,
1516         },
1517 };
1518
1519 static struct ich_pcm_table ali_pcms[] __devinitdata = {
1520         {
1521                 .playback_ops = &snd_intel8x0_ali_playback_ops,
1522                 .capture_ops = &snd_intel8x0_ali_capture_ops,
1523                 .prealloc_size = 64 * 1024,
1524                 .prealloc_max_size = 128 * 1024,
1525         },
1526         {
1527                 .suffix = "MIC ADC",
1528                 .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
1529                 .prealloc_size = 0,
1530                 .prealloc_max_size = 128 * 1024,
1531                 .ac97_idx = ALID_MIC,
1532         },
1533         {
1534                 .suffix = "IEC958",
1535                 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
1536                 .capture_ops = &snd_intel8x0_ali_spdifin_ops,
1537                 .prealloc_size = 64 * 1024,
1538                 .prealloc_max_size = 128 * 1024,
1539                 .ac97_idx = ALID_AC97SPDIFOUT,
1540         },
1541 #if 0 // NYI
1542         {
1543                 .suffix = "HW IEC958",
1544                 .playback_ops = &snd_intel8x0_ali_spdifout_ops,
1545                 .prealloc_size = 64 * 1024,
1546                 .prealloc_max_size = 128 * 1024,
1547         },
1548 #endif
1549 };
1550
1551 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip)
1552 {
1553         int i, tblsize, device, err;
1554         struct ich_pcm_table *tbl, *rec;
1555
1556         switch (chip->device_type) {
1557         case DEVICE_INTEL_ICH4:
1558                 tbl = intel_pcms;
1559                 tblsize = ARRAY_SIZE(intel_pcms);
1560                 break;
1561         case DEVICE_NFORCE:
1562                 tbl = nforce_pcms;
1563                 tblsize = ARRAY_SIZE(nforce_pcms);
1564                 break;
1565         case DEVICE_ALI:
1566                 tbl = ali_pcms;
1567                 tblsize = ARRAY_SIZE(ali_pcms);
1568                 break;
1569         default:
1570                 tbl = intel_pcms;
1571                 tblsize = 2;
1572                 break;
1573         }
1574
1575         device = 0;
1576         for (i = 0; i < tblsize; i++) {
1577                 rec = tbl + i;
1578                 if (i > 0 && rec->ac97_idx) {
1579                         /* activate PCM only when associated AC'97 codec */
1580                         if (! chip->ichd[rec->ac97_idx].pcm)
1581                                 continue;
1582                 }
1583                 err = snd_intel8x0_pcm1(chip, device, rec);
1584                 if (err < 0)
1585                         return err;
1586                 device++;
1587         }
1588
1589         chip->pcm_devs = device;
1590         return 0;
1591 }
1592
1593
1594 /*
1595  *  Mixer part
1596  */
1597
1598 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus)
1599 {
1600         intel8x0_t *chip = bus->private_data;
1601         chip->ac97_bus = NULL;
1602 }
1603
1604 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97)
1605 {
1606         intel8x0_t *chip = ac97->private_data;
1607         chip->ac97[ac97->num] = NULL;
1608 }
1609
1610 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
1611         /* front PCM */
1612         {
1613                 .exclusive = 1,
1614                 .r = {  {
1615                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1616                                          (1 << AC97_SLOT_PCM_RIGHT) |
1617                                          (1 << AC97_SLOT_PCM_CENTER) |
1618                                          (1 << AC97_SLOT_PCM_SLEFT) |
1619                                          (1 << AC97_SLOT_PCM_SRIGHT) |
1620                                          (1 << AC97_SLOT_LFE)
1621                         },
1622                         {
1623                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1624                                          (1 << AC97_SLOT_PCM_RIGHT) |
1625                                          (1 << AC97_SLOT_PCM_LEFT_0) |
1626                                          (1 << AC97_SLOT_PCM_RIGHT_0)
1627                         }
1628                 }
1629         },
1630         /* PCM IN #1 */
1631         {
1632                 .stream = 1,
1633                 .exclusive = 1,
1634                 .r = {  {
1635                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1636                                          (1 << AC97_SLOT_PCM_RIGHT)
1637                         }
1638                 }
1639         },
1640         /* MIC IN #1 */
1641         {
1642                 .stream = 1,
1643                 .exclusive = 1,
1644                 .r = {  {
1645                                 .slots = (1 << AC97_SLOT_MIC)
1646                         }
1647                 }
1648         },
1649         /* S/PDIF PCM */
1650         {
1651                 .exclusive = 1,
1652                 .spdif = 1,
1653                 .r = {  {
1654                                 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
1655                                          (1 << AC97_SLOT_SPDIF_RIGHT2)
1656                         }
1657                 }
1658         },
1659         /* PCM IN #2 */
1660         {
1661                 .stream = 1,
1662                 .exclusive = 1,
1663                 .r = {  {
1664                                 .slots = (1 << AC97_SLOT_PCM_LEFT) |
1665                                          (1 << AC97_SLOT_PCM_RIGHT)
1666                         }
1667                 }
1668         },
1669         /* MIC IN #2 */
1670         {
1671                 .stream = 1,
1672                 .exclusive = 1,
1673                 .r = {  {
1674                                 .slots = (1 << AC97_SLOT_MIC)
1675                         }
1676                 }
1677         },
1678 };
1679
1680 static struct ac97_quirk ac97_quirks[] __devinitdata = {
1681         {
1682                 .subvendor = 0x0e11,
1683                 .subdevice = 0x008a,
1684                 .name = "Compaq Evo W4000",     /* AD1885 */
1685                 .type = AC97_TUNE_HP_ONLY
1686         },
1687         {
1688                 .subvendor = 0x0e11,
1689                 .subdevice = 0x00b8,
1690                 .name = "Compaq Evo D510C",
1691                 .type = AC97_TUNE_HP_ONLY
1692         },
1693         {
1694                 .subvendor = 0x0e11,
1695                 .subdevice = 0x0860,
1696                 .name = "HP/Compaq nx7010",
1697                 .type = AC97_TUNE_MUTE_LED
1698         },
1699         {
1700                 .subvendor = 0x1014,
1701                 .subdevice = 0x1f00,
1702                 .name = "MS-9128",
1703                 .type = AC97_TUNE_ALC_JACK
1704         },
1705         {
1706                 .subvendor = 0x1014,
1707                 .subdevice = 0x0267,
1708                 .name = "IBM NetVista A30p",    /* AD1981B */
1709                 .type = AC97_TUNE_HP_ONLY
1710         },
1711         {
1712                 .subvendor = 0x1028,
1713                 .subdevice = 0x00d8,
1714                 .name = "Dell Precision 530",   /* AD1885 */
1715                 .type = AC97_TUNE_HP_ONLY
1716         },
1717         {
1718                 .subvendor = 0x1028,
1719                 .subdevice = 0x010d,
1720                 .name = "Dell", /* which model?  AD1885 */
1721                 .type = AC97_TUNE_HP_ONLY
1722         },
1723         {
1724                 .subvendor = 0x1028,
1725                 .subdevice = 0x0126,
1726                 .name = "Dell Optiplex GX260",  /* AD1981A */
1727                 .type = AC97_TUNE_HP_ONLY
1728         },
1729         {
1730                 .subvendor = 0x1028,
1731                 .subdevice = 0x012c,
1732                 .name = "Dell Precision 650",   /* AD1981A */
1733                 .type = AC97_TUNE_HP_ONLY
1734         },
1735         {
1736                 .subvendor = 0x1028,
1737                 .subdevice = 0x012d,
1738                 .name = "Dell Precision 450",   /* AD1981B*/
1739                 .type = AC97_TUNE_HP_ONLY
1740         },
1741         {
1742                 .subvendor = 0x1028,
1743                 .subdevice = 0x0147,
1744                 .name = "Dell", /* which model?  AD1981B*/
1745                 .type = AC97_TUNE_HP_ONLY
1746         },
1747         {
1748                 .subvendor = 0x1028,
1749                 .subdevice = 0x0163,
1750                 .name = "Dell Unknown", /* STAC9750/51 */
1751                 .type = AC97_TUNE_HP_ONLY
1752         },
1753         {
1754                 .subvendor = 0x103c,
1755                 .subdevice = 0x006d,
1756                 .name = "HP zv5000",
1757                 .type = AC97_TUNE_MUTE_LED      /*AD1981B*/
1758         },
1759         {       /* FIXME: which codec? */
1760                 .subvendor = 0x103c,
1761                 .subdevice = 0x00c3,
1762                 .name = "HP xw6000",
1763                 .type = AC97_TUNE_HP_ONLY
1764         },
1765         {
1766                 .subvendor = 0x103c,
1767                 .subdevice = 0x088c,
1768                 .name = "HP nc8000",
1769                 .type = AC97_TUNE_MUTE_LED
1770         },
1771         {
1772                 .subvendor = 0x103c,
1773                 .subdevice = 0x0890,
1774                 .name = "HP nc6000",
1775                 .type = AC97_TUNE_MUTE_LED
1776         },
1777         {
1778                 .subvendor = 0x103c,
1779                 .subdevice = 0x0934,
1780                 .name = "HP nx8220",
1781                 .type = AC97_TUNE_MUTE_LED
1782         },
1783         {
1784                 .subvendor = 0x103c,
1785                 .subdevice = 0x099c,
1786                 .name = "HP nx6110",    /* AD1981B */
1787                 .type = AC97_TUNE_HP_ONLY
1788         },
1789         {
1790                 .subvendor = 0x103c,
1791                 .subdevice = 0x129d,
1792                 .name = "HP xw8000",
1793                 .type = AC97_TUNE_HP_ONLY
1794         },
1795         {
1796                 .subvendor = 0x103c,
1797                 .subdevice = 0x12f1,
1798                 .name = "HP xw8200",    /* AD1981B*/
1799                 .type = AC97_TUNE_HP_ONLY
1800         },
1801         {
1802                 .subvendor = 0x103c,
1803                 .subdevice = 0x12f2,
1804                 .name = "HP xw6200",
1805                 .type = AC97_TUNE_HP_ONLY
1806         },
1807         {
1808                 .subvendor = 0x103c,
1809                 .subdevice = 0x3008,
1810                 .name = "HP xw4200",    /* AD1981B*/
1811                 .type = AC97_TUNE_HP_ONLY
1812         },
1813         {
1814                 .subvendor = 0x104d,
1815                 .subdevice = 0x8197,
1816                 .name = "Sony S1XP",
1817                 .type = AC97_TUNE_INV_EAPD
1818         },
1819         {
1820                 .subvendor = 0x1043,
1821                 .subdevice = 0x80f3,
1822                 .name = "ASUS ICH5/AD1985",
1823                 .type = AC97_TUNE_AD_SHARING
1824         },
1825         {
1826                 .subvendor = 0x10cf,
1827                 .subdevice = 0x11c3,
1828                 .name = "Fujitsu-Siemens E4010",
1829                 .type = AC97_TUNE_HP_ONLY
1830         },
1831         {
1832                 .subvendor = 0x10cf,
1833                 .subdevice = 0x1225,
1834                 .name = "Fujitsu-Siemens T3010",
1835                 .type = AC97_TUNE_HP_ONLY
1836         },
1837         {
1838                 .subvendor = 0x10cf,
1839                 .subdevice = 0x1253,
1840                 .name = "Fujitsu S6210",        /* STAC9750/51 */
1841                 .type = AC97_TUNE_HP_ONLY
1842         },
1843         {
1844                 .subvendor = 0x10cf,
1845                 .subdevice = 0x12ec,
1846                 .name = "Fujitsu-Siemens 4010",
1847                 .type = AC97_TUNE_HP_ONLY
1848         },
1849         {
1850                 .subvendor = 0x10f1,
1851                 .subdevice = 0x2665,
1852                 .name = "Fujitsu-Siemens Celsius",      /* AD1981? */
1853                 .type = AC97_TUNE_HP_ONLY
1854         },
1855         {
1856                 .subvendor = 0x10f1,
1857                 .subdevice = 0x2885,
1858                 .name = "AMD64 Mobo",   /* ALC650 */
1859                 .type = AC97_TUNE_HP_ONLY
1860         },
1861         {
1862                 .subvendor = 0x110a,
1863                 .subdevice = 0x0056,
1864                 .name = "Fujitsu-Siemens Scenic",       /* AD1981? */
1865                 .type = AC97_TUNE_HP_ONLY
1866         },
1867         {
1868                 .subvendor = 0x11d4,
1869                 .subdevice = 0x5375,
1870                 .name = "ADI AD1985 (discrete)",
1871                 .type = AC97_TUNE_HP_ONLY
1872         },
1873         {
1874                 .subvendor = 0x1462,
1875                 .subdevice = 0x5470,
1876                 .name = "MSI P4 ATX 645 Ultra",
1877                 .type = AC97_TUNE_HP_ONLY
1878         },
1879         {
1880                 .subvendor = 0x1734,
1881                 .subdevice = 0x0088,
1882                 .name = "Fujitsu-Siemens D1522",        /* AD1981 */
1883                 .type = AC97_TUNE_HP_ONLY
1884         },
1885         {
1886                 .subvendor = 0x8086,
1887                 .subdevice = 0x2000,
1888                 .mask = 0xfff0,
1889                 .name = "Intel ICH5/AD1985",
1890                 .type = AC97_TUNE_AD_SHARING
1891         },
1892         {
1893                 .subvendor = 0x8086,
1894                 .subdevice = 0x4000,
1895                 .mask = 0xfff0,
1896                 .name = "Intel ICH5/AD1985",
1897                 .type = AC97_TUNE_AD_SHARING
1898         },
1899         {
1900                 .subvendor = 0x8086,
1901                 .subdevice = 0x4856,
1902                 .name = "Intel D845WN (82801BA)",
1903                 .type = AC97_TUNE_SWAP_HP
1904         },
1905         {
1906                 .subvendor = 0x8086,
1907                 .subdevice = 0x4d44,
1908                 .name = "Intel D850EMV2",       /* AD1885 */
1909                 .type = AC97_TUNE_HP_ONLY
1910         },
1911         {
1912                 .subvendor = 0x8086,
1913                 .subdevice = 0x4d56,
1914                 .name = "Intel ICH/AD1885",
1915                 .type = AC97_TUNE_HP_ONLY
1916         },
1917         {
1918                 .subvendor = 0x8086,
1919                 .subdevice = 0x6000,
1920                 .mask = 0xfff0,
1921                 .name = "Intel ICH5/AD1985",
1922                 .type = AC97_TUNE_AD_SHARING
1923         },
1924         {
1925                 .subvendor = 0x8086,
1926                 .subdevice = 0xe000,
1927                 .mask = 0xfff0,
1928                 .name = "Intel ICH5/AD1985",
1929                 .type = AC97_TUNE_AD_SHARING
1930         },
1931 #if 0 /* FIXME: this seems wrong on most boards */
1932         {
1933                 .subvendor = 0x8086,
1934                 .subdevice = 0xa000,
1935                 .mask = 0xfff0,
1936                 .name = "Intel ICH5/AD1985",
1937                 .type = AC97_TUNE_HP_ONLY
1938         },
1939 #endif
1940         { } /* terminator */
1941 };
1942
1943 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override)
1944 {
1945         ac97_bus_t *pbus;
1946         ac97_template_t ac97;
1947         int err;
1948         unsigned int i, codecs;
1949         unsigned int glob_sta = 0;
1950         ac97_bus_ops_t *ops;
1951         static ac97_bus_ops_t standard_bus_ops = {
1952                 .write = snd_intel8x0_codec_write,
1953                 .read = snd_intel8x0_codec_read,
1954         };
1955         static ac97_bus_ops_t ali_bus_ops = {
1956                 .write = snd_intel8x0_ali_codec_write,
1957                 .read = snd_intel8x0_ali_codec_read,
1958         };
1959
1960         chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
1961         switch (chip->device_type) {
1962         case DEVICE_NFORCE:
1963                 chip->spdif_idx = NVD_SPBAR;
1964                 break;
1965         case DEVICE_ALI:
1966                 chip->spdif_idx = ALID_AC97SPDIFOUT;
1967                 break;
1968         case DEVICE_INTEL_ICH4:
1969                 chip->spdif_idx = ICHD_SPBAR;
1970                 break;
1971         };
1972
1973         chip->in_ac97_init = 1;
1974
1975         memset(&ac97, 0, sizeof(ac97));
1976         ac97.private_data = chip;
1977         ac97.private_free = snd_intel8x0_mixer_free_ac97;
1978         ac97.scaps = AC97_SCAP_SKIP_MODEM;
1979         if (chip->xbox)
1980                 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
1981         if (chip->device_type != DEVICE_ALI) {
1982                 glob_sta = igetdword(chip, ICHREG(GLOB_STA));
1983                 ops = &standard_bus_ops;
1984                 if (chip->device_type == DEVICE_INTEL_ICH4) {
1985                         codecs = 0;
1986                         if (glob_sta & ICH_PCR)
1987                                 codecs++;
1988                         if (glob_sta & ICH_SCR)
1989                                 codecs++;
1990                         if (glob_sta & ICH_TCR)
1991                                 codecs++;
1992                         chip->in_sdin_init = 1;
1993                         for (i = 0; i < codecs; i++) {
1994                                 snd_intel8x0_codec_read_test(chip, i);
1995                                 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
1996                         }
1997                         chip->in_sdin_init = 0;
1998                 } else {
1999                         codecs = glob_sta & ICH_SCR ? 2 : 1;
2000                 }
2001         } else {
2002                 ops = &ali_bus_ops;
2003                 codecs = 1;
2004                 /* detect the secondary codec */
2005                 for (i = 0; i < 100; i++) {
2006                         unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
2007                         if (reg & 0x40) {
2008                                 codecs = 2;
2009                                 break;
2010                         }
2011                         iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
2012                         udelay(1);
2013                 }
2014         }
2015         if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
2016                 goto __err;
2017         pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
2018         pbus->shared_type = AC97_SHARED_TYPE_ICH;       /* shared with modem driver */
2019         if (ac97_clock >= 8000 && ac97_clock <= 48000)
2020                 pbus->clock = ac97_clock;
2021         /* FIXME: my test board doesn't work well with VRA... */
2022         if (chip->device_type == DEVICE_ALI)
2023                 pbus->no_vra = 1;
2024         else
2025                 pbus->dra = 1;
2026         chip->ac97_bus = pbus;
2027
2028         ac97.pci = chip->pci;
2029         for (i = 0; i < codecs; i++) {
2030                 ac97.num = i;
2031                 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
2032                         if (err != -EACCES)
2033                                 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
2034                         if (i == 0)
2035                                 goto __err;
2036                         continue;
2037                 }
2038         }
2039         /* tune up the primary codec */
2040         snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
2041         /* enable separate SDINs for ICH4 */
2042         if (chip->device_type == DEVICE_INTEL_ICH4)
2043                 pbus->isdin = 1;
2044         /* find the available PCM streams */
2045         i = ARRAY_SIZE(ac97_pcm_defs);
2046         if (chip->device_type != DEVICE_INTEL_ICH4)
2047                 i -= 2;         /* do not allocate PCM2IN and MIC2 */
2048         if (chip->spdif_idx < 0)
2049                 i--;            /* do not allocate S/PDIF */
2050         err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
2051         if (err < 0)
2052                 goto __err;
2053         chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
2054         chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
2055         chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
2056         if (chip->spdif_idx >= 0)
2057                 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
2058         if (chip->device_type == DEVICE_INTEL_ICH4) {
2059                 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
2060                 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
2061         }
2062         /* enable separate SDINs for ICH4 */
2063         if (chip->device_type == DEVICE_INTEL_ICH4) {
2064                 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
2065                 u8 tmp = igetbyte(chip, ICHREG(SDM));
2066                 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
2067                 if (pcm) {
2068                         tmp |= ICH_SE;  /* steer enable for multiple SDINs */
2069                         tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
2070                         for (i = 1; i < 4; i++) {
2071                                 if (pcm->r[0].codec[i]) {
2072                                         tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
2073                                         break;
2074                                 }
2075                         }
2076                 } else {
2077                         tmp &= ~ICH_SE; /* steer disable */
2078                 }
2079                 iputbyte(chip, ICHREG(SDM), tmp);
2080         }
2081         if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
2082                 chip->multi4 = 1;
2083                 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE))
2084                         chip->multi6 = 1;
2085         }
2086         if (pbus->pcms[0].r[1].rslots[0]) {
2087                 chip->dra = 1;
2088         }
2089         if (chip->device_type == DEVICE_INTEL_ICH4) {
2090                 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
2091                         chip->smp20bit = 1;
2092         }
2093         if (chip->device_type == DEVICE_NFORCE) {
2094                 /* 48kHz only */
2095                 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
2096         }
2097         if (chip->device_type == DEVICE_INTEL_ICH4) {
2098                 /* use slot 10/11 for SPDIF */
2099                 u32 val;
2100                 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
2101                 val |= ICH_PCM_SPDIF_1011;
2102                 iputdword(chip, ICHREG(GLOB_CNT), val);
2103                 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
2104         }
2105         chip->in_ac97_init = 0;
2106         return 0;
2107
2108  __err:
2109         /* clear the cold-reset bit for the next chance */
2110         if (chip->device_type != DEVICE_ALI)
2111                 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
2112         return err;
2113 }
2114
2115
2116 /*
2117  *
2118  */
2119
2120 static void do_ali_reset(intel8x0_t *chip)
2121 {
2122         iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
2123         iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
2124         iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
2125         iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
2126         iputdword(chip, ICHREG(ALI_INTERFACECR),
2127                   ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO);
2128         iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
2129         iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
2130 }
2131
2132 #define do_delay(chip) do {\
2133         set_current_state(TASK_UNINTERRUPTIBLE);\
2134         schedule_timeout(1);\
2135 } while (0)
2136
2137 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing)
2138 {
2139         unsigned long end_time;
2140         unsigned int cnt, status, nstatus;
2141
2142         /* put logic to right state */
2143         /* first clear status bits */
2144         status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
2145         if (chip->device_type == DEVICE_NFORCE)
2146                 status |= ICH_NVSPINT;
2147         cnt = igetdword(chip, ICHREG(GLOB_STA));
2148         iputdword(chip, ICHREG(GLOB_STA), cnt & status);
2149
2150         /* ACLink on, 2 channels */
2151         cnt = igetdword(chip, ICHREG(GLOB_CNT));
2152         cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2153         /* finish cold or do warm reset */
2154         cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
2155         iputdword(chip, ICHREG(GLOB_CNT), cnt);
2156         end_time = (jiffies + (HZ / 4)) + 1;
2157         do {
2158                 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2159                         goto __ok;
2160                 do_delay(chip);
2161         } while (time_after_eq(end_time, jiffies));
2162         snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT)));
2163         return -EIO;
2164
2165       __ok:
2166         if (probing) {
2167                 /* wait for any codec ready status.
2168                  * Once it becomes ready it should remain ready
2169                  * as long as we do not disable the ac97 link.
2170                  */
2171                 end_time = jiffies + HZ;
2172                 do {
2173                         status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2174                         if (status)
2175                                 break;
2176                         do_delay(chip);
2177                 } while (time_after_eq(end_time, jiffies));
2178                 if (! status) {
2179                         /* no codec is found */
2180                         snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA)));
2181                         return -EIO;
2182                 }
2183
2184                 if (chip->device_type == DEVICE_INTEL_ICH4)
2185                         /* ICH4 can have three codecs */
2186                         nstatus = ICH_PCR | ICH_SCR | ICH_TCR;
2187                 else
2188                         /* others up to two codecs */
2189                         nstatus = ICH_PCR | ICH_SCR;
2190
2191                 /* wait for other codecs ready status. */
2192                 end_time = jiffies + HZ / 4;
2193                 while (status != nstatus && time_after_eq(end_time, jiffies)) {
2194                         do_delay(chip);
2195                         status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
2196                 }
2197
2198         } else {
2199                 /* resume phase */
2200                 int i;
2201                 status = 0;
2202                 for (i = 0; i < 3; i++)
2203                         if (chip->ac97[i])
2204                                 status |= get_ich_codec_bit(chip, i);
2205                 /* wait until all the probed codecs are ready */
2206                 end_time = jiffies + HZ;
2207                 do {
2208                         nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR);
2209                         if (status == nstatus)
2210                                 break;
2211                         do_delay(chip);
2212                 } while (time_after_eq(end_time, jiffies));
2213         }
2214
2215         if (chip->device_type == DEVICE_SIS) {
2216                 /* unmute the output on SIS7012 */
2217                 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
2218         }
2219         if (chip->device_type == DEVICE_NFORCE) {
2220                 /* enable SPDIF interrupt */
2221                 unsigned int val;
2222                 pci_read_config_dword(chip->pci, 0x4c, &val);
2223                 val |= 0x1000000;
2224                 pci_write_config_dword(chip->pci, 0x4c, val);
2225         }
2226         return 0;
2227 }
2228
2229 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing)
2230 {
2231         u32 reg;
2232         int i = 0;
2233
2234         reg = igetdword(chip, ICHREG(ALI_SCR));
2235         if ((reg & 2) == 0)     /* Cold required */
2236                 reg |= 2;
2237         else
2238                 reg |= 1;       /* Warm */
2239         reg &= ~0x80000000;     /* ACLink on */
2240         iputdword(chip, ICHREG(ALI_SCR), reg);
2241
2242         for (i = 0; i < HZ / 2; i++) {
2243                 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
2244                         goto __ok;
2245                 do_delay(chip);
2246         }
2247         snd_printk(KERN_ERR "AC'97 reset failed.\n");
2248         if (probing)
2249                 return -EIO;
2250
2251  __ok:
2252         for (i = 0; i < HZ / 2; i++) {
2253                 reg = igetdword(chip, ICHREG(ALI_RTSR));
2254                 if (reg & 0x80) /* primary codec */
2255                         break;
2256                 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2257                 do_delay(chip);
2258         }
2259
2260         do_ali_reset(chip);
2261         return 0;
2262 }
2263
2264 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing)
2265 {
2266         unsigned int i;
2267         int err;
2268
2269         if (chip->device_type != DEVICE_ALI) {
2270                 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
2271                         return err;
2272                 iagetword(chip, 0);     /* clear semaphore flag */
2273         } else {
2274                 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
2275                         return err;
2276         }
2277
2278         /* disable interrupts */
2279         for (i = 0; i < chip->bdbars_count; i++)
2280                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2281         /* reset channels */
2282         for (i = 0; i < chip->bdbars_count; i++)
2283                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2284         /* initialize Buffer Descriptor Lists */
2285         for (i = 0; i < chip->bdbars_count; i++)
2286                 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
2287         return 0;
2288 }
2289
2290 static int snd_intel8x0_free(intel8x0_t *chip)
2291 {
2292         unsigned int i;
2293
2294         if (chip->irq < 0)
2295                 goto __hw_end;
2296         /* disable interrupts */
2297         for (i = 0; i < chip->bdbars_count; i++)
2298                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
2299         /* reset channels */
2300         for (i = 0; i < chip->bdbars_count; i++)
2301                 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2302         if (chip->device_type == DEVICE_NFORCE) {
2303                 /* stop the spdif interrupt */
2304                 unsigned int val;
2305                 pci_read_config_dword(chip->pci, 0x4c, &val);
2306                 val &= ~0x1000000;
2307                 pci_write_config_dword(chip->pci, 0x4c, val);
2308         }
2309         /* --- */
2310         synchronize_irq(chip->irq);
2311       __hw_end:
2312         if (chip->irq >= 0)
2313                 free_irq(chip->irq, (void *)chip);
2314         if (chip->bdbars.area) {
2315                 if (chip->fix_nocache)
2316                         fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
2317                 snd_dma_free_pages(&chip->bdbars);
2318         }
2319         if (chip->remap_addr)
2320                 iounmap(chip->remap_addr);
2321         if (chip->remap_bmaddr)
2322                 iounmap(chip->remap_bmaddr);
2323         pci_release_regions(chip->pci);
2324         pci_disable_device(chip->pci);
2325         kfree(chip);
2326         return 0;
2327 }
2328
2329 #ifdef CONFIG_PM
2330 /*
2331  * power management
2332  */
2333 static int intel8x0_suspend(snd_card_t *card, pm_message_t state)
2334 {
2335         intel8x0_t *chip = card->pm_private_data;
2336         int i;
2337
2338         for (i = 0; i < chip->pcm_devs; i++)
2339                 snd_pcm_suspend_all(chip->pcm[i]);
2340         /* clear nocache */
2341         if (chip->fix_nocache) {
2342                 for (i = 0; i < chip->bdbars_count; i++) {
2343                         ichdev_t *ichdev = &chip->ichd[i];
2344                         if (ichdev->substream && ichdev->page_attr_changed) {
2345                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2346                                 if (runtime->dma_area)
2347                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
2348                         }
2349                 }
2350         }
2351         for (i = 0; i < 3; i++)
2352                 if (chip->ac97[i])
2353                         snd_ac97_suspend(chip->ac97[i]);
2354         if (chip->device_type == DEVICE_INTEL_ICH4)
2355                 chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2356
2357         if (chip->irq >= 0)
2358                 free_irq(chip->irq, (void *)chip);
2359         pci_disable_device(chip->pci);
2360         return 0;
2361 }
2362
2363 static int intel8x0_resume(snd_card_t *card)
2364 {
2365         intel8x0_t *chip = card->pm_private_data;
2366         int i;
2367
2368         pci_enable_device(chip->pci);
2369         pci_set_master(chip->pci);
2370         request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip);
2371         synchronize_irq(chip->irq);
2372         snd_intel8x0_chip_init(chip, 1);
2373
2374         /* re-initialize mixer stuff */
2375         if (chip->device_type == DEVICE_INTEL_ICH4) {
2376                 /* enable separate SDINs for ICH4 */
2377                 iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
2378                 /* use slot 10/11 for SPDIF */
2379                 iputdword(chip, ICHREG(GLOB_CNT),
2380                           (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
2381                           ICH_PCM_SPDIF_1011);
2382         }
2383
2384         /* refill nocache */
2385         if (chip->fix_nocache)
2386                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2387
2388         for (i = 0; i < 3; i++)
2389                 if (chip->ac97[i])
2390                         snd_ac97_resume(chip->ac97[i]);
2391
2392         /* refill nocache */
2393         if (chip->fix_nocache) {
2394                 for (i = 0; i < chip->bdbars_count; i++) {
2395                         ichdev_t *ichdev = &chip->ichd[i];
2396                         if (ichdev->substream && ichdev->page_attr_changed) {
2397                                 snd_pcm_runtime_t *runtime = ichdev->substream->runtime;
2398                                 if (runtime->dma_area)
2399                                         fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
2400                         }
2401                 }
2402         }
2403
2404         /* resume status */
2405         for (i = 0; i < chip->bdbars_count; i++) {
2406                 ichdev_t *ichdev = &chip->ichd[i];
2407                 unsigned long port = ichdev->reg_offset;
2408                 if (! ichdev->substream || ! ichdev->suspended)
2409                         continue;
2410                 if (ichdev->ichd == ICHD_PCMOUT)
2411                         snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
2412                 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
2413                 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
2414                 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
2415                 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
2416         }
2417
2418         return 0;
2419 }
2420 #endif /* CONFIG_PM */
2421
2422 #define INTEL8X0_TESTBUF_SIZE   32768   /* enough large for one shot */
2423
2424 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip)
2425 {
2426         snd_pcm_substream_t *subs;
2427         ichdev_t *ichdev;
2428         unsigned long port;
2429         unsigned long pos, t;
2430         struct timeval start_time, stop_time;
2431
2432         if (chip->ac97_bus->clock != 48000)
2433                 return; /* specified in module option */
2434
2435         subs = chip->pcm[0]->streams[0].substream;
2436         if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2437                 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n");
2438                 return;
2439         }
2440         ichdev = &chip->ichd[ICHD_PCMOUT];
2441         ichdev->physbuf = subs->dma_buffer.addr;
2442         ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE;
2443         ichdev->substream = NULL; /* don't process interrupts */
2444
2445         /* set rate */
2446         if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
2447                 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
2448                 return;
2449         }
2450         snd_intel8x0_setup_periods(chip, ichdev);
2451         port = ichdev->reg_offset;
2452         spin_lock_irq(&chip->reg_lock);
2453         chip->in_measurement = 1;
2454         /* trigger */
2455         if (chip->device_type != DEVICE_ALI)
2456                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
2457         else {
2458                 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
2459                 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
2460         }
2461         do_gettimeofday(&start_time);
2462         spin_unlock_irq(&chip->reg_lock);
2463         msleep(50);
2464         spin_lock_irq(&chip->reg_lock);
2465         /* check the position */
2466         pos = ichdev->fragsize1;
2467         pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift;
2468         pos += ichdev->position;
2469         chip->in_measurement = 0;
2470         do_gettimeofday(&stop_time);
2471         /* stop */
2472         if (chip->device_type == DEVICE_ALI) {
2473                 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8));
2474                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2475                 while (igetbyte(chip, port + ICH_REG_OFF_CR))
2476                         ;
2477         } else {
2478                 iputbyte(chip, port + ICH_REG_OFF_CR, 0);
2479                 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
2480                         ;
2481         }
2482         iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
2483         spin_unlock_irq(&chip->reg_lock);
2484
2485         t = stop_time.tv_sec - start_time.tv_sec;
2486         t *= 1000000;
2487         t += stop_time.tv_usec - start_time.tv_usec;
2488         printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t);
2489         if (t == 0) {
2490                 snd_printk(KERN_ERR "?? calculation error..\n");
2491                 return;
2492         }
2493         pos = (pos / 4) * 1000;
2494         pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2495         if (pos < 40000 || pos >= 60000)
2496                 /* abnormal value. hw problem? */
2497                 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2498         else if (pos < 47500 || pos > 48500)
2499                 /* not 48000Hz, tuning the clock.. */
2500                 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2501         printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2502 }
2503
2504 static void snd_intel8x0_proc_read(snd_info_entry_t * entry,
2505                                    snd_info_buffer_t * buffer)
2506 {
2507         intel8x0_t *chip = entry->private_data;
2508         unsigned int tmp;
2509
2510         snd_iprintf(buffer, "Intel8x0\n\n");
2511         if (chip->device_type == DEVICE_ALI)
2512                 return;
2513         tmp = igetdword(chip, ICHREG(GLOB_STA));
2514         snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
2515         snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
2516         if (chip->device_type == DEVICE_INTEL_ICH4)
2517                 snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2518         snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
2519                         tmp & ICH_PCR ? " primary" : "",
2520                         tmp & ICH_SCR ? " secondary" : "",
2521                         tmp & ICH_TCR ? " tertiary" : "",
2522                         (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
2523         if (chip->device_type == DEVICE_INTEL_ICH4)
2524                 snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
2525                         chip->ac97_sdin[0],
2526                         chip->ac97_sdin[1],
2527                         chip->ac97_sdin[2]);
2528 }
2529
2530 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip)
2531 {
2532         snd_info_entry_t *entry;
2533
2534         if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2535                 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read);
2536 }
2537
2538 static int snd_intel8x0_dev_free(snd_device_t *device)
2539 {
2540         intel8x0_t *chip = device->device_data;
2541         return snd_intel8x0_free(chip);
2542 }
2543
2544 struct ich_reg_info {
2545         unsigned int int_sta_mask;
2546         unsigned int offset;
2547 };
2548
2549 static int __devinit snd_intel8x0_create(snd_card_t * card,
2550                                          struct pci_dev *pci,
2551                                          unsigned long device_type,
2552                                          intel8x0_t ** r_intel8x0)
2553 {
2554         intel8x0_t *chip;
2555         int err;
2556         unsigned int i;
2557         unsigned int int_sta_masks;
2558         ichdev_t *ichdev;
2559         static snd_device_ops_t ops = {
2560                 .dev_free =     snd_intel8x0_dev_free,
2561         };
2562
2563         static unsigned int bdbars[] = {
2564                 3, /* DEVICE_INTEL */
2565                 6, /* DEVICE_INTEL_ICH4 */
2566                 3, /* DEVICE_SIS */
2567                 6, /* DEVICE_ALI */
2568                 4, /* DEVICE_NFORCE */
2569         };
2570         static struct ich_reg_info intel_regs[6] = {
2571                 { ICH_PIINT, 0 },
2572                 { ICH_POINT, 0x10 },
2573                 { ICH_MCINT, 0x20 },
2574                 { ICH_M2INT, 0x40 },
2575                 { ICH_P2INT, 0x50 },
2576                 { ICH_SPINT, 0x60 },
2577         };
2578         static struct ich_reg_info nforce_regs[4] = {
2579                 { ICH_PIINT, 0 },
2580                 { ICH_POINT, 0x10 },
2581                 { ICH_MCINT, 0x20 },
2582                 { ICH_NVSPINT, 0x70 },
2583         };
2584         static struct ich_reg_info ali_regs[6] = {
2585                 { ALI_INT_PCMIN, 0x40 },
2586                 { ALI_INT_PCMOUT, 0x50 },
2587                 { ALI_INT_MICIN, 0x60 },
2588                 { ALI_INT_CODECSPDIFOUT, 0x70 },
2589                 { ALI_INT_SPDIFIN, 0xa0 },
2590                 { ALI_INT_SPDIFOUT, 0xb0 },
2591         };
2592         struct ich_reg_info *tbl;
2593
2594         *r_intel8x0 = NULL;
2595
2596         if ((err = pci_enable_device(pci)) < 0)
2597                 return err;
2598
2599         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
2600         if (chip == NULL) {
2601                 pci_disable_device(pci);
2602                 return -ENOMEM;
2603         }
2604         spin_lock_init(&chip->reg_lock);
2605         chip->device_type = device_type;
2606         chip->card = card;
2607         chip->pci = pci;
2608         chip->irq = -1;
2609
2610         if (pci->vendor == PCI_VENDOR_ID_INTEL &&
2611             pci->device == PCI_DEVICE_ID_INTEL_440MX)
2612                 chip->fix_nocache = 1; /* enable workaround */
2613
2614         /* some Nforce[2] and ICH boards have problems with IRQ handling.
2615          * Needs to return IRQ_HANDLED for unknown irqs.
2616          */
2617         if (device_type == DEVICE_NFORCE)
2618                 chip->buggy_irq = 1;
2619
2620         if ((err = pci_request_regions(pci, card->shortname)) < 0) {
2621                 kfree(chip);
2622                 pci_disable_device(pci);
2623                 return err;
2624         }
2625
2626         if (device_type == DEVICE_ALI) {
2627                 /* ALI5455 has no ac97 region */
2628                 chip->bmaddr = pci_resource_start(pci, 0);
2629                 goto port_inited;
2630         }
2631
2632         if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) {      /* ICH4 and Nforce */
2633                 chip->mmio = 1;
2634                 chip->addr = pci_resource_start(pci, 2);
2635                 chip->remap_addr = ioremap_nocache(chip->addr,
2636                                                    pci_resource_len(pci, 2));
2637                 if (chip->remap_addr == NULL) {
2638                         snd_printk("AC'97 space ioremap problem\n");
2639                         snd_intel8x0_free(chip);
2640                         return -EIO;
2641                 }
2642         } else {
2643                 chip->addr = pci_resource_start(pci, 0);
2644         }
2645         if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) {      /* ICH4 */
2646                 chip->bm_mmio = 1;
2647                 chip->bmaddr = pci_resource_start(pci, 3);
2648                 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr,
2649                                                      pci_resource_len(pci, 3));
2650                 if (chip->remap_bmaddr == NULL) {
2651                         snd_printk("Controller space ioremap problem\n");
2652                         snd_intel8x0_free(chip);
2653                         return -EIO;
2654                 }
2655         } else {
2656                 chip->bmaddr = pci_resource_start(pci, 1);
2657         }
2658
2659  port_inited:
2660         if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
2661                 snd_printk("unable to grab IRQ %d\n", pci->irq);
2662                 snd_intel8x0_free(chip);
2663                 return -EBUSY;
2664         }
2665         chip->irq = pci->irq;
2666         pci_set_master(pci);
2667         synchronize_irq(chip->irq);
2668
2669         chip->bdbars_count = bdbars[device_type];
2670
2671         /* initialize offsets */
2672         switch (device_type) {
2673         case DEVICE_NFORCE:
2674                 tbl = nforce_regs;
2675                 break;
2676         case DEVICE_ALI:
2677                 tbl = ali_regs;
2678                 break;
2679         default:
2680                 tbl = intel_regs;
2681                 break;
2682         }
2683         for (i = 0; i < chip->bdbars_count; i++) {
2684                 ichdev = &chip->ichd[i];
2685                 ichdev->ichd = i;
2686                 ichdev->reg_offset = tbl[i].offset;
2687                 ichdev->int_sta_mask = tbl[i].int_sta_mask;
2688                 if (device_type == DEVICE_SIS) {
2689                         /* SiS 7012 swaps the registers */
2690                         ichdev->roff_sr = ICH_REG_OFF_PICB;
2691                         ichdev->roff_picb = ICH_REG_OFF_SR;
2692                 } else {
2693                         ichdev->roff_sr = ICH_REG_OFF_SR;
2694                         ichdev->roff_picb = ICH_REG_OFF_PICB;
2695                 }
2696                 if (device_type == DEVICE_ALI)
2697                         ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
2698                 /* SIS7012 handles the pcm data in bytes, others are in samples */
2699                 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
2700         }
2701
2702         /* allocate buffer descriptor lists */
2703         /* the start of each lists must be aligned to 8 bytes */
2704         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2705                                 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
2706                                 &chip->bdbars) < 0) {
2707                 snd_intel8x0_free(chip);
2708                 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
2709                 return -ENOMEM;
2710         }
2711         /* tables must be aligned to 8 bytes here, but the kernel pages
2712            are much bigger, so we don't care (on i386) */
2713         /* workaround for 440MX */
2714         if (chip->fix_nocache)
2715                 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
2716         int_sta_masks = 0;
2717         for (i = 0; i < chip->bdbars_count; i++) {
2718                 ichdev = &chip->ichd[i];
2719                 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
2720                 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
2721                 int_sta_masks |= ichdev->int_sta_mask;
2722         }
2723         chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
2724         chip->int_sta_mask = int_sta_masks;
2725
2726         if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
2727                 snd_intel8x0_free(chip);
2728                 return err;
2729         }
2730
2731         snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip);
2732
2733         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2734                 snd_intel8x0_free(chip);
2735                 return err;
2736         }
2737
2738         snd_card_set_dev(card, &pci->dev);
2739
2740         *r_intel8x0 = chip;
2741         return 0;
2742 }
2743
2744 static struct shortname_table {
2745         unsigned int id;
2746         const char *s;
2747 } shortnames[] __devinitdata = {
2748         { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
2749         { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
2750         { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
2751         { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
2752         { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
2753         { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
2754         { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
2755         { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
2756         { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
2757         { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
2758         { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
2759         { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
2760         { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
2761         { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
2762         { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
2763         { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
2764         { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
2765         { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
2766         { 0x003a, "NVidia MCP04" },
2767         { 0x746d, "AMD AMD8111" },
2768         { 0x7445, "AMD AMD768" },
2769         { 0x5455, "ALi M5455" },
2770         { 0, NULL },
2771 };
2772
2773 static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
2774                                         const struct pci_device_id *pci_id)
2775 {
2776         static int dev;
2777         snd_card_t *card;
2778         intel8x0_t *chip;
2779         int err;
2780         struct shortname_table *name;
2781
2782         if (dev >= SNDRV_CARDS)
2783                 return -ENODEV;
2784         if (!enable[dev]) {
2785                 dev++;
2786                 return -ENOENT;
2787         }
2788
2789         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2790         if (card == NULL)
2791                 return -ENOMEM;
2792
2793         switch (pci_id->driver_data) {
2794         case DEVICE_NFORCE:
2795                 strcpy(card->driver, "NFORCE");
2796                 break;
2797         case DEVICE_INTEL_ICH4:
2798                 strcpy(card->driver, "ICH4");
2799                 break;
2800         default:
2801                 strcpy(card->driver, "ICH");
2802                 break;
2803         }
2804
2805         strcpy(card->shortname, "Intel ICH");
2806         for (name = shortnames; name->id; name++) {
2807                 if (pci->device == name->id) {
2808                         strcpy(card->shortname, name->s);
2809                         break;
2810                 }
2811         }
2812
2813         if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) {
2814                 snd_card_free(card);
2815                 return err;
2816         }
2817         if (buggy_irq[dev])
2818                 chip->buggy_irq = 1;
2819         if (xbox[dev])
2820                 chip->xbox = 1;
2821
2822         if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) {
2823                 snd_card_free(card);
2824                 return err;
2825         }
2826         if ((err = snd_intel8x0_pcm(chip)) < 0) {
2827                 snd_card_free(card);
2828                 return err;
2829         }
2830
2831         snd_intel8x0_proc_init(chip);
2832
2833         snprintf(card->longname, sizeof(card->longname),
2834                  "%s with %s at %#lx, irq %i", card->shortname,
2835                  snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq);
2836
2837         if (! ac97_clock[dev])
2838                 intel8x0_measure_ac97_clock(chip);
2839
2840         if ((err = snd_card_register(card)) < 0) {
2841                 snd_card_free(card);
2842                 return err;
2843         }
2844         pci_set_drvdata(pci, card);
2845         dev++;
2846         return 0;
2847 }
2848
2849 static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
2850 {
2851         snd_card_free(pci_get_drvdata(pci));
2852         pci_set_drvdata(pci, NULL);
2853 }
2854
2855 static struct pci_driver driver = {
2856         .name = "Intel ICH",
2857         .id_table = snd_intel8x0_ids,
2858         .probe = snd_intel8x0_probe,
2859         .remove = __devexit_p(snd_intel8x0_remove),
2860         SND_PCI_PM_CALLBACKS
2861 };
2862
2863
2864 static int __init alsa_card_intel8x0_init(void)
2865 {
2866         return pci_register_driver(&driver);
2867 }
2868
2869 static void __exit alsa_card_intel8x0_exit(void)
2870 {
2871         pci_unregister_driver(&driver);
2872 }
2873
2874 module_init(alsa_card_intel8x0_init)
2875 module_exit(alsa_card_intel8x0_exit)