3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
68 module_param_array(index, int, NULL, 0444);
69 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
70 module_param_array(id, charp, NULL, 0444);
71 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
74 module_param_array(model, charp, NULL, 0444);
75 MODULE_PARM_DESC(model, "Use the given board model.");
76 module_param_array(position_fix, int, NULL, 0444);
77 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
78 "(0 = auto, 1 = none, 2 = POSBUF).");
79 module_param_array(bdl_pos_adj, int, NULL, 0644);
80 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
81 module_param_array(probe_mask, int, NULL, 0444);
82 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
83 module_param_array(probe_only, bool, NULL, 0444);
84 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
85 module_param(single_cmd, bool, 0444);
86 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
87 "(for debugging only).");
88 module_param(enable_msi, int, 0444);
89 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
90 #ifdef CONFIG_SND_HDA_PATCH_LOADER
91 module_param_array(patch, charp, NULL, 0444);
92 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
95 #ifdef CONFIG_SND_HDA_POWER_SAVE
96 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
97 module_param(power_save, int, 0644);
98 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
99 "(in second, 0 = disable).");
101 /* reset the HD-audio controller in power save mode.
102 * this may give more power-saving, but will take longer time to
105 static int power_save_controller = 1;
106 module_param(power_save_controller, bool, 0644);
107 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
110 MODULE_LICENSE("GPL");
111 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
136 MODULE_DESCRIPTION("Intel HDA driver");
138 #ifdef CONFIG_SND_VERBOSE_PRINTK
139 #define SFX /* nop */
141 #define SFX "hda-intel: "
147 #define ICH6_REG_GCAP 0x00
148 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
149 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
150 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
151 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
152 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
153 #define ICH6_REG_VMIN 0x02
154 #define ICH6_REG_VMAJ 0x03
155 #define ICH6_REG_OUTPAY 0x04
156 #define ICH6_REG_INPAY 0x06
157 #define ICH6_REG_GCTL 0x08
158 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
159 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
160 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
161 #define ICH6_REG_WAKEEN 0x0c
162 #define ICH6_REG_STATESTS 0x0e
163 #define ICH6_REG_GSTS 0x10
164 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
165 #define ICH6_REG_INTCTL 0x20
166 #define ICH6_REG_INTSTS 0x24
167 #define ICH6_REG_WALCLK 0x30
168 #define ICH6_REG_SYNC 0x34
169 #define ICH6_REG_CORBLBASE 0x40
170 #define ICH6_REG_CORBUBASE 0x44
171 #define ICH6_REG_CORBWP 0x48
172 #define ICH6_REG_CORBRP 0x4a
173 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
174 #define ICH6_REG_CORBCTL 0x4c
175 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
176 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
177 #define ICH6_REG_CORBSTS 0x4d
178 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
179 #define ICH6_REG_CORBSIZE 0x4e
181 #define ICH6_REG_RIRBLBASE 0x50
182 #define ICH6_REG_RIRBUBASE 0x54
183 #define ICH6_REG_RIRBWP 0x58
184 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
185 #define ICH6_REG_RINTCNT 0x5a
186 #define ICH6_REG_RIRBCTL 0x5c
187 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
188 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
189 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
190 #define ICH6_REG_RIRBSTS 0x5d
191 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
192 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
193 #define ICH6_REG_RIRBSIZE 0x5e
195 #define ICH6_REG_IC 0x60
196 #define ICH6_REG_IR 0x64
197 #define ICH6_REG_IRS 0x68
198 #define ICH6_IRS_VALID (1<<1)
199 #define ICH6_IRS_BUSY (1<<0)
201 #define ICH6_REG_DPLBASE 0x70
202 #define ICH6_REG_DPUBASE 0x74
203 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
205 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
206 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
208 /* stream register offsets from stream base */
209 #define ICH6_REG_SD_CTL 0x00
210 #define ICH6_REG_SD_STS 0x03
211 #define ICH6_REG_SD_LPIB 0x04
212 #define ICH6_REG_SD_CBL 0x08
213 #define ICH6_REG_SD_LVI 0x0c
214 #define ICH6_REG_SD_FIFOW 0x0e
215 #define ICH6_REG_SD_FIFOSIZE 0x10
216 #define ICH6_REG_SD_FORMAT 0x12
217 #define ICH6_REG_SD_BDLPL 0x18
218 #define ICH6_REG_SD_BDLPU 0x1c
221 #define ICH6_PCIREG_TCSEL 0x44
227 /* max number of SDs */
228 /* ICH, ATI and VIA have 4 playback and 4 capture */
229 #define ICH6_NUM_CAPTURE 4
230 #define ICH6_NUM_PLAYBACK 4
232 /* ULI has 6 playback and 5 capture */
233 #define ULI_NUM_CAPTURE 5
234 #define ULI_NUM_PLAYBACK 6
236 /* ATI HDMI has 1 playback and 0 capture */
237 #define ATIHDMI_NUM_CAPTURE 0
238 #define ATIHDMI_NUM_PLAYBACK 1
240 /* TERA has 4 playback and 3 capture */
241 #define TERA_NUM_CAPTURE 3
242 #define TERA_NUM_PLAYBACK 4
244 /* this number is statically defined for simplicity */
245 #define MAX_AZX_DEV 16
247 /* max number of fragments - we may use more if allocating more pages for BDL */
248 #define BDL_SIZE 4096
249 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
250 #define AZX_MAX_FRAG 32
251 /* max buffer size - no h/w limit, you can increase as you like */
252 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
253 /* max number of PCM devics per card */
254 #define AZX_MAX_PCMS 8
256 /* RIRB int mask: overrun[2], response[0] */
257 #define RIRB_INT_RESPONSE 0x01
258 #define RIRB_INT_OVERRUN 0x04
259 #define RIRB_INT_MASK 0x05
261 /* STATESTS int mask: S3,SD2,SD1,SD0 */
262 #define AZX_MAX_CODECS 4
263 #define STATESTS_INT_MASK 0x0f
266 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
267 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
268 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
269 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
270 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
271 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
272 #define SD_CTL_STREAM_TAG_SHIFT 20
274 /* SD_CTL and SD_STS */
275 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
276 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
277 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
278 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
282 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
284 /* INTCTL and INTSTS */
285 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
286 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
287 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
289 /* below are so far hardcoded - should read registers in future */
290 #define ICH6_MAX_CORB_ENTRIES 256
291 #define ICH6_MAX_RIRB_ENTRIES 256
293 /* position fix mode */
300 /* Defines for ATI HD Audio support in SB450 south bridge */
301 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
302 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
304 /* Defines for Nvidia HDA support */
305 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
306 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
307 #define NVIDIA_HDA_ISTRM_COH 0x4d
308 #define NVIDIA_HDA_OSTRM_COH 0x4c
309 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
311 /* Defines for Intel SCH HDA snoop control */
312 #define INTEL_SCH_HDA_DEVC 0x78
313 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
315 /* Define IN stream 0 FIFO size offset in VIA controller */
316 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
317 /* Define VIA HD Audio Device ID*/
318 #define VIA_HDAC_DEVICE_ID 0x3288
320 /* HD Audio class code */
321 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
327 struct snd_dma_buffer bdl; /* BDL buffer */
328 u32 *posbuf; /* position buffer pointer */
330 unsigned int bufsize; /* size of the play buffer in bytes */
331 unsigned int period_bytes; /* size of the period in bytes */
332 unsigned int frags; /* number for period in the play buffer */
333 unsigned int fifo_size; /* FIFO size */
334 unsigned long start_jiffies; /* start + minimum jiffies */
335 unsigned long min_jiffies; /* minimum jiffies before position is valid */
337 void __iomem *sd_addr; /* stream descriptor pointer */
339 u32 sd_int_sta_mask; /* stream int status mask */
342 struct snd_pcm_substream *substream; /* assigned substream,
345 unsigned int format_val; /* format value to be set in the
346 * controller and the codec
348 unsigned char stream_tag; /* assigned stream */
349 unsigned char index; /* stream index */
351 unsigned int opened :1;
352 unsigned int running :1;
353 unsigned int irq_pending :1;
354 unsigned int start_flag: 1; /* stream full start flag */
357 * A flag to ensure DMA position is 0
358 * when link position is not greater than FIFO size
360 unsigned int insufficient :1;
365 u32 *buf; /* CORB/RIRB buffer
366 * Each CORB entry is 4byte, RIRB is 8byte
368 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
370 unsigned short rp, wp; /* read/write pointers */
371 int cmds; /* number of pending requests */
372 u32 res; /* last read value */
376 struct snd_card *card;
380 /* chip type specific */
382 int playback_streams;
383 int playback_index_offset;
385 int capture_index_offset;
390 void __iomem *remap_addr;
395 struct mutex open_mutex;
397 /* streams (x num_streams) */
398 struct azx_dev *azx_dev;
401 struct snd_pcm *pcm[AZX_MAX_PCMS];
404 unsigned short codec_mask;
405 int codec_probe_mask; /* copied from probe_mask option */
412 /* CORB/RIRB and position buffers */
413 struct snd_dma_buffer rb;
414 struct snd_dma_buffer posbuf;
418 unsigned int running :1;
419 unsigned int initialized :1;
420 unsigned int single_cmd :1;
421 unsigned int polling_mode :1;
423 unsigned int irq_pending_warned :1;
424 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
425 unsigned int probing :1; /* codec probing phase */
428 unsigned int last_cmd; /* last issued command (to sync) */
430 /* for pending irqs */
431 struct work_struct irq_pending_work;
433 /* reboot notifier (for mysterious hangup problem at power-down) */
434 struct notifier_block reboot_notifier;
449 AZX_NUM_DRIVERS, /* keep this as last entry */
452 static char *driver_short_names[] __devinitdata = {
453 [AZX_DRIVER_ICH] = "HDA Intel",
454 [AZX_DRIVER_SCH] = "HDA Intel MID",
455 [AZX_DRIVER_ATI] = "HDA ATI SB",
456 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
457 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
458 [AZX_DRIVER_SIS] = "HDA SIS966",
459 [AZX_DRIVER_ULI] = "HDA ULI M5461",
460 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
461 [AZX_DRIVER_TERA] = "HDA Teradici",
462 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
466 * macros for easy use
468 #define azx_writel(chip,reg,value) \
469 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
470 #define azx_readl(chip,reg) \
471 readl((chip)->remap_addr + ICH6_REG_##reg)
472 #define azx_writew(chip,reg,value) \
473 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
474 #define azx_readw(chip,reg) \
475 readw((chip)->remap_addr + ICH6_REG_##reg)
476 #define azx_writeb(chip,reg,value) \
477 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
478 #define azx_readb(chip,reg) \
479 readb((chip)->remap_addr + ICH6_REG_##reg)
481 #define azx_sd_writel(dev,reg,value) \
482 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
483 #define azx_sd_readl(dev,reg) \
484 readl((dev)->sd_addr + ICH6_REG_##reg)
485 #define azx_sd_writew(dev,reg,value) \
486 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
487 #define azx_sd_readw(dev,reg) \
488 readw((dev)->sd_addr + ICH6_REG_##reg)
489 #define azx_sd_writeb(dev,reg,value) \
490 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
491 #define azx_sd_readb(dev,reg) \
492 readb((dev)->sd_addr + ICH6_REG_##reg)
494 /* for pcm support */
495 #define get_azx_dev(substream) (substream->runtime->private_data)
497 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
500 * Interface for HD codec
504 * CORB / RIRB interface
506 static int azx_alloc_cmd_io(struct azx *chip)
510 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
511 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
512 snd_dma_pci_data(chip->pci),
513 PAGE_SIZE, &chip->rb);
515 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
521 static void azx_init_cmd_io(struct azx *chip)
524 chip->corb.addr = chip->rb.addr;
525 chip->corb.buf = (u32 *)chip->rb.area;
526 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
527 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
529 /* set the corb size to 256 entries (ULI requires explicitly) */
530 azx_writeb(chip, CORBSIZE, 0x02);
531 /* set the corb write pointer to 0 */
532 azx_writew(chip, CORBWP, 0);
533 /* reset the corb hw read pointer */
534 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
535 /* enable corb dma */
536 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
539 chip->rirb.addr = chip->rb.addr + 2048;
540 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
541 chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
542 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
543 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
545 /* set the rirb size to 256 entries (ULI requires explicitly) */
546 azx_writeb(chip, RIRBSIZE, 0x02);
547 /* reset the rirb hw write pointer */
548 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
549 /* set N=1, get RIRB response interrupt for new entry */
550 azx_writew(chip, RINTCNT, 1);
551 /* enable rirb dma and response irq */
552 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
555 static void azx_free_cmd_io(struct azx *chip)
557 /* disable ringbuffer DMAs */
558 azx_writeb(chip, RIRBCTL, 0);
559 azx_writeb(chip, CORBCTL, 0);
563 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
565 struct azx *chip = bus->private_data;
568 /* add command to corb */
569 wp = azx_readb(chip, CORBWP);
571 wp %= ICH6_MAX_CORB_ENTRIES;
573 spin_lock_irq(&chip->reg_lock);
575 chip->corb.buf[wp] = cpu_to_le32(val);
576 azx_writel(chip, CORBWP, wp);
577 spin_unlock_irq(&chip->reg_lock);
582 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
584 /* retrieve RIRB entry - called from interrupt handler */
585 static void azx_update_rirb(struct azx *chip)
590 wp = azx_readb(chip, RIRBWP);
591 if (wp == chip->rirb.wp)
595 while (chip->rirb.rp != wp) {
597 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
599 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
600 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
601 res = le32_to_cpu(chip->rirb.buf[rp]);
602 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
603 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
604 else if (chip->rirb.cmds) {
605 chip->rirb.res = res;
612 /* receive a response */
613 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
615 struct azx *chip = bus->private_data;
616 unsigned long timeout;
619 timeout = jiffies + msecs_to_jiffies(1000);
621 if (chip->polling_mode) {
622 spin_lock_irq(&chip->reg_lock);
623 azx_update_rirb(chip);
624 spin_unlock_irq(&chip->reg_lock);
626 if (!chip->rirb.cmds) {
629 return chip->rirb.res; /* the last value */
631 if (time_after(jiffies, timeout))
633 if (bus->needs_damn_long_delay)
634 msleep(2); /* temporary workaround */
642 snd_printk(KERN_WARNING SFX "No response from codec, "
643 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
644 free_irq(chip->irq, chip);
646 pci_disable_msi(chip->pci);
648 if (azx_acquire_irq(chip, 1) < 0) {
655 if (!chip->polling_mode) {
656 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
657 "switching to polling mode: last cmd=0x%08x\n",
659 chip->polling_mode = 1;
664 /* If this critical timeout happens during the codec probing
665 * phase, this is likely an access to a non-existing codec
666 * slot. Better to return an error and reset the system.
671 /* a fatal communication error; need either to reset or to fallback
672 * to the single_cmd mode
675 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
676 bus->response_reset = 1;
677 return -1; /* give a chance to retry */
680 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
681 "switching to single_cmd mode: last cmd=0x%08x\n",
683 chip->single_cmd = 1;
684 bus->response_reset = 0;
685 /* re-initialize CORB/RIRB */
686 azx_free_cmd_io(chip);
687 azx_init_cmd_io(chip);
692 * Use the single immediate command instead of CORB/RIRB for simplicity
694 * Note: according to Intel, this is not preferred use. The command was
695 * intended for the BIOS only, and may get confused with unsolicited
696 * responses. So, we shouldn't use it for normal operation from the
698 * I left the codes, however, for debugging/testing purposes.
701 /* receive a response */
702 static int azx_single_wait_for_response(struct azx *chip)
707 /* check IRV busy bit */
708 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
709 /* reuse rirb.res as the response return value */
710 chip->rirb.res = azx_readl(chip, IR);
715 if (printk_ratelimit())
716 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
717 azx_readw(chip, IRS));
723 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
725 struct azx *chip = bus->private_data;
730 /* check ICB busy bit */
731 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
732 /* Clear IRV valid bit */
733 azx_writew(chip, IRS, azx_readw(chip, IRS) |
735 azx_writel(chip, IC, val);
736 azx_writew(chip, IRS, azx_readw(chip, IRS) |
738 return azx_single_wait_for_response(chip);
742 if (printk_ratelimit())
743 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
744 azx_readw(chip, IRS), val);
748 /* receive a response */
749 static unsigned int azx_single_get_response(struct hda_bus *bus)
751 struct azx *chip = bus->private_data;
752 return chip->rirb.res;
756 * The below are the main callbacks from hda_codec.
758 * They are just the skeleton to call sub-callbacks according to the
759 * current setting of chip->single_cmd.
763 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
765 struct azx *chip = bus->private_data;
767 chip->last_cmd = val;
768 if (chip->single_cmd)
769 return azx_single_send_cmd(bus, val);
771 return azx_corb_send_cmd(bus, val);
775 static unsigned int azx_get_response(struct hda_bus *bus)
777 struct azx *chip = bus->private_data;
778 if (chip->single_cmd)
779 return azx_single_get_response(bus);
781 return azx_rirb_get_response(bus);
784 #ifdef CONFIG_SND_HDA_POWER_SAVE
785 static void azx_power_notify(struct hda_bus *bus);
788 /* reset codec link */
789 static int azx_reset(struct azx *chip)
794 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
796 /* reset controller */
797 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
800 while (azx_readb(chip, GCTL) && --count)
803 /* delay for >= 100us for codec PLL to settle per spec
804 * Rev 0.9 section 5.5.1
808 /* Bring controller out of reset */
809 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
812 while (!azx_readb(chip, GCTL) && --count)
815 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
818 /* check to see if controller is ready */
819 if (!azx_readb(chip, GCTL)) {
820 snd_printd(SFX "azx_reset: controller not ready!\n");
824 /* Accept unsolicited responses */
825 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
828 if (!chip->codec_mask) {
829 chip->codec_mask = azx_readw(chip, STATESTS);
830 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
841 /* enable interrupts */
842 static void azx_int_enable(struct azx *chip)
844 /* enable controller CIE and GIE */
845 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
846 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
849 /* disable interrupts */
850 static void azx_int_disable(struct azx *chip)
854 /* disable interrupts in stream descriptor */
855 for (i = 0; i < chip->num_streams; i++) {
856 struct azx_dev *azx_dev = &chip->azx_dev[i];
857 azx_sd_writeb(azx_dev, SD_CTL,
858 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
861 /* disable SIE for all streams */
862 azx_writeb(chip, INTCTL, 0);
864 /* disable controller CIE and GIE */
865 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
866 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
869 /* clear interrupts */
870 static void azx_int_clear(struct azx *chip)
874 /* clear stream status */
875 for (i = 0; i < chip->num_streams; i++) {
876 struct azx_dev *azx_dev = &chip->azx_dev[i];
877 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
881 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
883 /* clear rirb status */
884 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
886 /* clear int status */
887 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
891 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
894 * Before stream start, initialize parameter
896 azx_dev->insufficient = 1;
899 azx_writeb(chip, INTCTL,
900 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
901 /* set DMA start and interrupt mask */
902 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
903 SD_CTL_DMA_START | SD_INT_MASK);
907 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
909 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
910 ~(SD_CTL_DMA_START | SD_INT_MASK));
911 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
915 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
917 azx_stream_clear(chip, azx_dev);
919 azx_writeb(chip, INTCTL,
920 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
925 * reset and start the controller registers
927 static void azx_init_chip(struct azx *chip)
929 if (chip->initialized)
932 /* reset controller */
935 /* initialize interrupts */
937 azx_int_enable(chip);
939 /* initialize the codec command I/O */
940 azx_init_cmd_io(chip);
942 /* program the position buffer */
943 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
944 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
946 chip->initialized = 1;
950 * initialize the PCI registers
952 /* update bits in a PCI register byte */
953 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
954 unsigned char mask, unsigned char val)
958 pci_read_config_byte(pci, reg, &data);
960 data |= (val & mask);
961 pci_write_config_byte(pci, reg, data);
964 static void azx_init_pci(struct azx *chip)
966 unsigned short snoop;
968 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
969 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
970 * Ensuring these bits are 0 clears playback static on some HD Audio
973 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
975 switch (chip->driver_type) {
977 /* For ATI SB450 azalia HD audio, we need to enable snoop */
978 update_pci_byte(chip->pci,
979 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
980 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
982 case AZX_DRIVER_NVIDIA:
983 /* For NVIDIA HDA, enable snoop */
984 update_pci_byte(chip->pci,
985 NVIDIA_HDA_TRANSREG_ADDR,
986 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
987 update_pci_byte(chip->pci,
988 NVIDIA_HDA_ISTRM_COH,
989 0x01, NVIDIA_HDA_ENABLE_COHBIT);
990 update_pci_byte(chip->pci,
991 NVIDIA_HDA_OSTRM_COH,
992 0x01, NVIDIA_HDA_ENABLE_COHBIT);
995 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
996 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
997 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
998 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
999 pci_read_config_word(chip->pci,
1000 INTEL_SCH_HDA_DEVC, &snoop);
1001 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1002 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1011 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1016 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1018 struct azx *chip = dev_id;
1019 struct azx_dev *azx_dev;
1023 spin_lock(&chip->reg_lock);
1025 status = azx_readl(chip, INTSTS);
1027 spin_unlock(&chip->reg_lock);
1031 for (i = 0; i < chip->num_streams; i++) {
1032 azx_dev = &chip->azx_dev[i];
1033 if (status & azx_dev->sd_int_sta_mask) {
1034 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1035 if (!azx_dev->substream || !azx_dev->running)
1037 /* check whether this IRQ is really acceptable */
1038 ok = azx_position_ok(chip, azx_dev);
1040 azx_dev->irq_pending = 0;
1041 spin_unlock(&chip->reg_lock);
1042 snd_pcm_period_elapsed(azx_dev->substream);
1043 spin_lock(&chip->reg_lock);
1044 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1045 /* bogus IRQ, process it later */
1046 azx_dev->irq_pending = 1;
1047 queue_work(chip->bus->workq,
1048 &chip->irq_pending_work);
1053 /* clear rirb int */
1054 status = azx_readb(chip, RIRBSTS);
1055 if (status & RIRB_INT_MASK) {
1056 if (status & RIRB_INT_RESPONSE)
1057 azx_update_rirb(chip);
1058 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1062 /* clear state status int */
1063 if (azx_readb(chip, STATESTS) & 0x04)
1064 azx_writeb(chip, STATESTS, 0x04);
1066 spin_unlock(&chip->reg_lock);
1073 * set up a BDL entry
1075 static int setup_bdle(struct snd_pcm_substream *substream,
1076 struct azx_dev *azx_dev, u32 **bdlp,
1077 int ofs, int size, int with_ioc)
1085 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1088 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1089 /* program the address field of the BDL entry */
1090 bdl[0] = cpu_to_le32((u32)addr);
1091 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1092 /* program the size field of the BDL entry */
1093 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1094 bdl[2] = cpu_to_le32(chunk);
1095 /* program the IOC to enable interrupt
1096 * only when the whole fragment is processed
1099 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1109 * set up BDL entries
1111 static int azx_setup_periods(struct azx *chip,
1112 struct snd_pcm_substream *substream,
1113 struct azx_dev *azx_dev)
1116 int i, ofs, periods, period_bytes;
1119 /* reset BDL address */
1120 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1121 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1123 period_bytes = azx_dev->period_bytes;
1124 periods = azx_dev->bufsize / period_bytes;
1126 /* program the initial BDL entries */
1127 bdl = (u32 *)azx_dev->bdl.area;
1130 pos_adj = bdl_pos_adj[chip->dev_index];
1132 struct snd_pcm_runtime *runtime = substream->runtime;
1133 int pos_align = pos_adj;
1134 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1136 pos_adj = pos_align;
1138 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1140 pos_adj = frames_to_bytes(runtime, pos_adj);
1141 if (pos_adj >= period_bytes) {
1142 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1143 bdl_pos_adj[chip->dev_index]);
1146 ofs = setup_bdle(substream, azx_dev,
1147 &bdl, ofs, pos_adj, 1);
1153 for (i = 0; i < periods; i++) {
1154 if (i == periods - 1 && pos_adj)
1155 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1156 period_bytes - pos_adj, 0);
1158 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1166 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1167 azx_dev->bufsize, period_bytes);
1172 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1177 azx_stream_clear(chip, azx_dev);
1179 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1180 SD_CTL_STREAM_RESET);
1183 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1186 val &= ~SD_CTL_STREAM_RESET;
1187 azx_sd_writeb(azx_dev, SD_CTL, val);
1191 /* waiting for hardware to report that the stream is out of reset */
1192 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1196 /* reset first position - may not be synced with hw at this time */
1197 *azx_dev->posbuf = 0;
1201 * set up the SD for streaming
1203 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1205 /* make sure the run bit is zero for SD */
1206 azx_stream_clear(chip, azx_dev);
1207 /* program the stream_tag */
1208 azx_sd_writel(azx_dev, SD_CTL,
1209 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1210 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1212 /* program the length of samples in cyclic buffer */
1213 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1215 /* program the stream format */
1216 /* this value needs to be the same as the one programmed */
1217 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1219 /* program the stream LVI (last valid index) of the BDL */
1220 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1222 /* program the BDL address */
1223 /* lower BDL address */
1224 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1225 /* upper BDL address */
1226 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1228 /* enable the position buffer */
1229 if (chip->position_fix == POS_FIX_POSBUF ||
1230 chip->position_fix == POS_FIX_AUTO ||
1231 chip->via_dmapos_patch) {
1232 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1233 azx_writel(chip, DPLBASE,
1234 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1237 /* set the interrupt enable bits in the descriptor control register */
1238 azx_sd_writel(azx_dev, SD_CTL,
1239 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1245 * Probe the given codec address
1247 static int probe_codec(struct azx *chip, int addr)
1249 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1250 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1254 azx_send_cmd(chip->bus, cmd);
1255 res = azx_get_response(chip->bus);
1259 snd_printdd(SFX "codec #%d probed OK\n", addr);
1263 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1264 struct hda_pcm *cpcm);
1265 static void azx_stop_chip(struct azx *chip);
1267 static void azx_bus_reset(struct hda_bus *bus)
1269 struct azx *chip = bus->private_data;
1272 azx_stop_chip(chip);
1273 azx_init_chip(chip);
1275 if (chip->initialized) {
1278 for (i = 0; i < AZX_MAX_PCMS; i++)
1279 snd_pcm_suspend_all(chip->pcm[i]);
1280 snd_hda_suspend(chip->bus);
1281 snd_hda_resume(chip->bus);
1288 * Codec initialization
1291 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1292 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1293 [AZX_DRIVER_TERA] = 1,
1296 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1298 struct hda_bus_template bus_temp;
1302 memset(&bus_temp, 0, sizeof(bus_temp));
1303 bus_temp.private_data = chip;
1304 bus_temp.modelname = model;
1305 bus_temp.pci = chip->pci;
1306 bus_temp.ops.command = azx_send_cmd;
1307 bus_temp.ops.get_response = azx_get_response;
1308 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1309 bus_temp.ops.bus_reset = azx_bus_reset;
1310 #ifdef CONFIG_SND_HDA_POWER_SAVE
1311 bus_temp.power_save = &power_save;
1312 bus_temp.ops.pm_notify = azx_power_notify;
1315 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1319 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1320 chip->bus->needs_damn_long_delay = 1;
1323 max_slots = azx_max_codecs[chip->driver_type];
1325 max_slots = AZX_MAX_CODECS;
1327 /* First try to probe all given codec slots */
1328 for (c = 0; c < max_slots; c++) {
1329 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1330 if (probe_codec(chip, c) < 0) {
1331 /* Some BIOSen give you wrong codec addresses
1334 snd_printk(KERN_WARNING SFX
1335 "Codec #%d probe error; "
1336 "disabling it...\n", c);
1337 chip->codec_mask &= ~(1 << c);
1338 /* More badly, accessing to a non-existing
1339 * codec often screws up the controller chip,
1340 * and distrubs the further communications.
1341 * Thus if an error occurs during probing,
1342 * better to reset the controller chip to
1343 * get back to the sanity state.
1345 azx_stop_chip(chip);
1346 azx_init_chip(chip);
1351 /* Then create codec instances */
1352 for (c = 0; c < max_slots; c++) {
1353 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1354 struct hda_codec *codec;
1355 err = snd_hda_codec_new(chip->bus, c, &codec);
1362 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1368 /* configure each codec instance */
1369 static int __devinit azx_codec_configure(struct azx *chip)
1371 struct hda_codec *codec;
1372 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1373 snd_hda_codec_configure(codec);
1383 /* assign a stream for the PCM */
1384 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1387 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1388 dev = chip->playback_index_offset;
1389 nums = chip->playback_streams;
1391 dev = chip->capture_index_offset;
1392 nums = chip->capture_streams;
1394 for (i = 0; i < nums; i++, dev++)
1395 if (!chip->azx_dev[dev].opened) {
1396 chip->azx_dev[dev].opened = 1;
1397 return &chip->azx_dev[dev];
1402 /* release the assigned stream */
1403 static inline void azx_release_device(struct azx_dev *azx_dev)
1405 azx_dev->opened = 0;
1408 static struct snd_pcm_hardware azx_pcm_hw = {
1409 .info = (SNDRV_PCM_INFO_MMAP |
1410 SNDRV_PCM_INFO_INTERLEAVED |
1411 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1412 SNDRV_PCM_INFO_MMAP_VALID |
1413 /* No full-resume yet implemented */
1414 /* SNDRV_PCM_INFO_RESUME |*/
1415 SNDRV_PCM_INFO_PAUSE |
1416 SNDRV_PCM_INFO_SYNC_START),
1417 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1418 .rates = SNDRV_PCM_RATE_48000,
1423 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1424 .period_bytes_min = 128,
1425 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1427 .periods_max = AZX_MAX_FRAG,
1433 struct hda_codec *codec;
1434 struct hda_pcm_stream *hinfo[2];
1437 static int azx_pcm_open(struct snd_pcm_substream *substream)
1439 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1440 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1441 struct azx *chip = apcm->chip;
1442 struct azx_dev *azx_dev;
1443 struct snd_pcm_runtime *runtime = substream->runtime;
1444 unsigned long flags;
1447 mutex_lock(&chip->open_mutex);
1448 azx_dev = azx_assign_device(chip, substream->stream);
1449 if (azx_dev == NULL) {
1450 mutex_unlock(&chip->open_mutex);
1453 runtime->hw = azx_pcm_hw;
1454 runtime->hw.channels_min = hinfo->channels_min;
1455 runtime->hw.channels_max = hinfo->channels_max;
1456 runtime->hw.formats = hinfo->formats;
1457 runtime->hw.rates = hinfo->rates;
1458 snd_pcm_limit_hw_rates(runtime);
1459 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1460 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1462 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1464 snd_hda_power_up(apcm->codec);
1465 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1467 azx_release_device(azx_dev);
1468 snd_hda_power_down(apcm->codec);
1469 mutex_unlock(&chip->open_mutex);
1472 snd_pcm_limit_hw_rates(runtime);
1474 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1475 snd_BUG_ON(!runtime->hw.channels_max) ||
1476 snd_BUG_ON(!runtime->hw.formats) ||
1477 snd_BUG_ON(!runtime->hw.rates)) {
1478 azx_release_device(azx_dev);
1479 hinfo->ops.close(hinfo, apcm->codec, substream);
1480 snd_hda_power_down(apcm->codec);
1481 mutex_unlock(&chip->open_mutex);
1484 spin_lock_irqsave(&chip->reg_lock, flags);
1485 azx_dev->substream = substream;
1486 azx_dev->running = 0;
1487 spin_unlock_irqrestore(&chip->reg_lock, flags);
1489 runtime->private_data = azx_dev;
1490 snd_pcm_set_sync(substream);
1491 mutex_unlock(&chip->open_mutex);
1495 static int azx_pcm_close(struct snd_pcm_substream *substream)
1497 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1498 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1499 struct azx *chip = apcm->chip;
1500 struct azx_dev *azx_dev = get_azx_dev(substream);
1501 unsigned long flags;
1503 mutex_lock(&chip->open_mutex);
1504 spin_lock_irqsave(&chip->reg_lock, flags);
1505 azx_dev->substream = NULL;
1506 azx_dev->running = 0;
1507 spin_unlock_irqrestore(&chip->reg_lock, flags);
1508 azx_release_device(azx_dev);
1509 hinfo->ops.close(hinfo, apcm->codec, substream);
1510 snd_hda_power_down(apcm->codec);
1511 mutex_unlock(&chip->open_mutex);
1515 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1516 struct snd_pcm_hw_params *hw_params)
1518 struct azx_dev *azx_dev = get_azx_dev(substream);
1520 azx_dev->bufsize = 0;
1521 azx_dev->period_bytes = 0;
1522 azx_dev->format_val = 0;
1523 return snd_pcm_lib_malloc_pages(substream,
1524 params_buffer_bytes(hw_params));
1527 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1529 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1530 struct azx_dev *azx_dev = get_azx_dev(substream);
1531 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1533 /* reset BDL address */
1534 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1535 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1536 azx_sd_writel(azx_dev, SD_CTL, 0);
1537 azx_dev->bufsize = 0;
1538 azx_dev->period_bytes = 0;
1539 azx_dev->format_val = 0;
1541 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1543 return snd_pcm_lib_free_pages(substream);
1546 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1548 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1549 struct azx *chip = apcm->chip;
1550 struct azx_dev *azx_dev = get_azx_dev(substream);
1551 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1552 struct snd_pcm_runtime *runtime = substream->runtime;
1553 unsigned int bufsize, period_bytes, format_val;
1556 azx_stream_reset(chip, azx_dev);
1557 format_val = snd_hda_calc_stream_format(runtime->rate,
1562 snd_printk(KERN_ERR SFX
1563 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1564 runtime->rate, runtime->channels, runtime->format);
1568 bufsize = snd_pcm_lib_buffer_bytes(substream);
1569 period_bytes = snd_pcm_lib_period_bytes(substream);
1571 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1572 bufsize, format_val);
1574 if (bufsize != azx_dev->bufsize ||
1575 period_bytes != azx_dev->period_bytes ||
1576 format_val != azx_dev->format_val) {
1577 azx_dev->bufsize = bufsize;
1578 azx_dev->period_bytes = period_bytes;
1579 azx_dev->format_val = format_val;
1580 err = azx_setup_periods(chip, substream, azx_dev);
1585 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1586 (runtime->rate * 2);
1587 azx_setup_controller(chip, azx_dev);
1588 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1589 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1591 azx_dev->fifo_size = 0;
1593 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1594 azx_dev->format_val, substream);
1597 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1599 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1600 struct azx *chip = apcm->chip;
1601 struct azx_dev *azx_dev;
1602 struct snd_pcm_substream *s;
1603 int rstart = 0, start, nsync = 0, sbits = 0;
1607 case SNDRV_PCM_TRIGGER_START:
1609 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1610 case SNDRV_PCM_TRIGGER_RESUME:
1613 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1614 case SNDRV_PCM_TRIGGER_SUSPEND:
1615 case SNDRV_PCM_TRIGGER_STOP:
1622 snd_pcm_group_for_each_entry(s, substream) {
1623 if (s->pcm->card != substream->pcm->card)
1625 azx_dev = get_azx_dev(s);
1626 sbits |= 1 << azx_dev->index;
1628 snd_pcm_trigger_done(s, substream);
1631 spin_lock(&chip->reg_lock);
1633 /* first, set SYNC bits of corresponding streams */
1634 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1636 snd_pcm_group_for_each_entry(s, substream) {
1637 if (s->pcm->card != substream->pcm->card)
1639 azx_dev = get_azx_dev(s);
1641 azx_dev->start_flag = 1;
1642 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1645 azx_stream_start(chip, azx_dev);
1647 azx_stream_stop(chip, azx_dev);
1648 azx_dev->running = start;
1650 spin_unlock(&chip->reg_lock);
1654 /* wait until all FIFOs get ready */
1655 for (timeout = 5000; timeout; timeout--) {
1657 snd_pcm_group_for_each_entry(s, substream) {
1658 if (s->pcm->card != substream->pcm->card)
1660 azx_dev = get_azx_dev(s);
1661 if (!(azx_sd_readb(azx_dev, SD_STS) &
1670 /* wait until all RUN bits are cleared */
1671 for (timeout = 5000; timeout; timeout--) {
1673 snd_pcm_group_for_each_entry(s, substream) {
1674 if (s->pcm->card != substream->pcm->card)
1676 azx_dev = get_azx_dev(s);
1677 if (azx_sd_readb(azx_dev, SD_CTL) &
1687 spin_lock(&chip->reg_lock);
1688 /* reset SYNC bits */
1689 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1690 spin_unlock(&chip->reg_lock);
1695 /* get the current DMA position with correction on VIA chips */
1696 static unsigned int azx_via_get_position(struct azx *chip,
1697 struct azx_dev *azx_dev)
1699 unsigned int link_pos, mini_pos, bound_pos;
1700 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1701 unsigned int fifo_size;
1703 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1704 if (azx_dev->index >= 4) {
1705 /* Playback, no problem using link position */
1711 * use mod to get the DMA position just like old chipset
1713 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1714 mod_dma_pos %= azx_dev->period_bytes;
1716 /* azx_dev->fifo_size can't get FIFO size of in stream.
1717 * Get from base address + offset.
1719 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1721 if (azx_dev->insufficient) {
1722 /* Link position never gather than FIFO size */
1723 if (link_pos <= fifo_size)
1726 azx_dev->insufficient = 0;
1729 if (link_pos <= fifo_size)
1730 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1732 mini_pos = link_pos - fifo_size;
1734 /* Find nearest previous boudary */
1735 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1736 mod_link_pos = link_pos % azx_dev->period_bytes;
1737 if (mod_link_pos >= fifo_size)
1738 bound_pos = link_pos - mod_link_pos;
1739 else if (mod_dma_pos >= mod_mini_pos)
1740 bound_pos = mini_pos - mod_mini_pos;
1742 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1743 if (bound_pos >= azx_dev->bufsize)
1747 /* Calculate real DMA position we want */
1748 return bound_pos + mod_dma_pos;
1751 static unsigned int azx_get_position(struct azx *chip,
1752 struct azx_dev *azx_dev)
1756 if (chip->via_dmapos_patch)
1757 pos = azx_via_get_position(chip, azx_dev);
1758 else if (chip->position_fix == POS_FIX_POSBUF ||
1759 chip->position_fix == POS_FIX_AUTO) {
1760 /* use the position buffer */
1761 pos = le32_to_cpu(*azx_dev->posbuf);
1764 pos = azx_sd_readl(azx_dev, SD_LPIB);
1766 if (pos >= azx_dev->bufsize)
1771 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774 struct azx *chip = apcm->chip;
1775 struct azx_dev *azx_dev = get_azx_dev(substream);
1776 return bytes_to_frames(substream->runtime,
1777 azx_get_position(chip, azx_dev));
1781 * Check whether the current DMA position is acceptable for updating
1782 * periods. Returns non-zero if it's OK.
1784 * Many HD-audio controllers appear pretty inaccurate about
1785 * the update-IRQ timing. The IRQ is issued before actually the
1786 * data is processed. So, we need to process it afterwords in a
1789 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1793 if (azx_dev->start_flag &&
1794 time_before_eq(jiffies, azx_dev->start_jiffies))
1795 return -1; /* bogus (too early) interrupt */
1796 azx_dev->start_flag = 0;
1798 pos = azx_get_position(chip, azx_dev);
1799 if (chip->position_fix == POS_FIX_AUTO) {
1802 "hda-intel: Invalid position buffer, "
1803 "using LPIB read method instead.\n");
1804 chip->position_fix = POS_FIX_LPIB;
1805 pos = azx_get_position(chip, azx_dev);
1807 chip->position_fix = POS_FIX_POSBUF;
1810 if (!bdl_pos_adj[chip->dev_index])
1811 return 1; /* no delayed ack */
1812 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1813 return 0; /* NG - it's below the period boundary */
1814 return 1; /* OK, it's fine */
1818 * The work for pending PCM period updates.
1820 static void azx_irq_pending_work(struct work_struct *work)
1822 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1825 if (!chip->irq_pending_warned) {
1827 "hda-intel: IRQ timing workaround is activated "
1828 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1829 chip->card->number);
1830 chip->irq_pending_warned = 1;
1835 spin_lock_irq(&chip->reg_lock);
1836 for (i = 0; i < chip->num_streams; i++) {
1837 struct azx_dev *azx_dev = &chip->azx_dev[i];
1838 if (!azx_dev->irq_pending ||
1839 !azx_dev->substream ||
1842 if (azx_position_ok(chip, azx_dev)) {
1843 azx_dev->irq_pending = 0;
1844 spin_unlock(&chip->reg_lock);
1845 snd_pcm_period_elapsed(azx_dev->substream);
1846 spin_lock(&chip->reg_lock);
1850 spin_unlock_irq(&chip->reg_lock);
1857 /* clear irq_pending flags and assure no on-going workq */
1858 static void azx_clear_irq_pending(struct azx *chip)
1862 spin_lock_irq(&chip->reg_lock);
1863 for (i = 0; i < chip->num_streams; i++)
1864 chip->azx_dev[i].irq_pending = 0;
1865 spin_unlock_irq(&chip->reg_lock);
1868 static struct snd_pcm_ops azx_pcm_ops = {
1869 .open = azx_pcm_open,
1870 .close = azx_pcm_close,
1871 .ioctl = snd_pcm_lib_ioctl,
1872 .hw_params = azx_pcm_hw_params,
1873 .hw_free = azx_pcm_hw_free,
1874 .prepare = azx_pcm_prepare,
1875 .trigger = azx_pcm_trigger,
1876 .pointer = azx_pcm_pointer,
1877 .page = snd_pcm_sgbuf_ops_page,
1880 static void azx_pcm_free(struct snd_pcm *pcm)
1882 struct azx_pcm *apcm = pcm->private_data;
1884 apcm->chip->pcm[pcm->device] = NULL;
1890 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1891 struct hda_pcm *cpcm)
1893 struct azx *chip = bus->private_data;
1894 struct snd_pcm *pcm;
1895 struct azx_pcm *apcm;
1896 int pcm_dev = cpcm->device;
1899 if (pcm_dev >= AZX_MAX_PCMS) {
1900 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1904 if (chip->pcm[pcm_dev]) {
1905 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1908 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1909 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1910 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1914 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1915 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1919 apcm->codec = codec;
1920 pcm->private_data = apcm;
1921 pcm->private_free = azx_pcm_free;
1922 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1923 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1924 chip->pcm[pcm_dev] = pcm;
1926 for (s = 0; s < 2; s++) {
1927 apcm->hinfo[s] = &cpcm->stream[s];
1928 if (cpcm->stream[s].substreams)
1929 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1931 /* buffer pre-allocation */
1932 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1933 snd_dma_pci_data(chip->pci),
1934 1024 * 64, 32 * 1024 * 1024);
1939 * mixer creation - all stuff is implemented in hda module
1941 static int __devinit azx_mixer_create(struct azx *chip)
1943 return snd_hda_build_controls(chip->bus);
1948 * initialize SD streams
1950 static int __devinit azx_init_stream(struct azx *chip)
1954 /* initialize each stream (aka device)
1955 * assign the starting bdl address to each stream (device)
1958 for (i = 0; i < chip->num_streams; i++) {
1959 struct azx_dev *azx_dev = &chip->azx_dev[i];
1960 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1961 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1962 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1963 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1964 azx_dev->sd_int_sta_mask = 1 << i;
1965 /* stream tag: must be non-zero and unique */
1967 azx_dev->stream_tag = i + 1;
1973 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1975 if (request_irq(chip->pci->irq, azx_interrupt,
1976 chip->msi ? 0 : IRQF_SHARED,
1977 "HDA Intel", chip)) {
1978 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1979 "disabling device\n", chip->pci->irq);
1981 snd_card_disconnect(chip->card);
1984 chip->irq = chip->pci->irq;
1985 pci_intx(chip->pci, !chip->msi);
1990 static void azx_stop_chip(struct azx *chip)
1992 if (!chip->initialized)
1995 /* disable interrupts */
1996 azx_int_disable(chip);
1997 azx_int_clear(chip);
1999 /* disable CORB/RIRB */
2000 azx_free_cmd_io(chip);
2002 /* disable position buffer */
2003 azx_writel(chip, DPLBASE, 0);
2004 azx_writel(chip, DPUBASE, 0);
2006 chip->initialized = 0;
2009 #ifdef CONFIG_SND_HDA_POWER_SAVE
2010 /* power-up/down the controller */
2011 static void azx_power_notify(struct hda_bus *bus)
2013 struct azx *chip = bus->private_data;
2014 struct hda_codec *c;
2017 list_for_each_entry(c, &bus->codec_list, list) {
2024 azx_init_chip(chip);
2025 else if (chip->running && power_save_controller)
2026 azx_stop_chip(chip);
2028 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2035 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2037 struct hda_codec *codec;
2039 list_for_each_entry(codec, &bus->codec_list, list) {
2040 if (snd_hda_codec_needs_resume(codec))
2046 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2048 struct snd_card *card = pci_get_drvdata(pci);
2049 struct azx *chip = card->private_data;
2052 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2053 azx_clear_irq_pending(chip);
2054 for (i = 0; i < AZX_MAX_PCMS; i++)
2055 snd_pcm_suspend_all(chip->pcm[i]);
2056 if (chip->initialized)
2057 snd_hda_suspend(chip->bus);
2058 azx_stop_chip(chip);
2059 if (chip->irq >= 0) {
2060 free_irq(chip->irq, chip);
2064 pci_disable_msi(chip->pci);
2065 pci_disable_device(pci);
2066 pci_save_state(pci);
2067 pci_set_power_state(pci, pci_choose_state(pci, state));
2071 static int azx_resume(struct pci_dev *pci)
2073 struct snd_card *card = pci_get_drvdata(pci);
2074 struct azx *chip = card->private_data;
2076 pci_set_power_state(pci, PCI_D0);
2077 pci_restore_state(pci);
2078 if (pci_enable_device(pci) < 0) {
2079 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2080 "disabling device\n");
2081 snd_card_disconnect(card);
2084 pci_set_master(pci);
2086 if (pci_enable_msi(pci) < 0)
2088 if (azx_acquire_irq(chip, 1) < 0)
2092 if (snd_hda_codecs_inuse(chip->bus))
2093 azx_init_chip(chip);
2095 snd_hda_resume(chip->bus);
2096 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2099 #endif /* CONFIG_PM */
2103 * reboot notifier for hang-up problem at power-down
2105 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2107 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2108 azx_stop_chip(chip);
2112 static void azx_notifier_register(struct azx *chip)
2114 chip->reboot_notifier.notifier_call = azx_halt;
2115 register_reboot_notifier(&chip->reboot_notifier);
2118 static void azx_notifier_unregister(struct azx *chip)
2120 if (chip->reboot_notifier.notifier_call)
2121 unregister_reboot_notifier(&chip->reboot_notifier);
2127 static int azx_free(struct azx *chip)
2131 azx_notifier_unregister(chip);
2133 if (chip->initialized) {
2134 azx_clear_irq_pending(chip);
2135 for (i = 0; i < chip->num_streams; i++)
2136 azx_stream_stop(chip, &chip->azx_dev[i]);
2137 azx_stop_chip(chip);
2141 free_irq(chip->irq, (void*)chip);
2143 pci_disable_msi(chip->pci);
2144 if (chip->remap_addr)
2145 iounmap(chip->remap_addr);
2147 if (chip->azx_dev) {
2148 for (i = 0; i < chip->num_streams; i++)
2149 if (chip->azx_dev[i].bdl.area)
2150 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2153 snd_dma_free_pages(&chip->rb);
2154 if (chip->posbuf.area)
2155 snd_dma_free_pages(&chip->posbuf);
2156 pci_release_regions(chip->pci);
2157 pci_disable_device(chip->pci);
2158 kfree(chip->azx_dev);
2164 static int azx_dev_free(struct snd_device *device)
2166 return azx_free(device->device_data);
2170 * white/black-listing for position_fix
2172 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2173 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2174 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2175 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2179 static int __devinit check_position_fix(struct azx *chip, int fix)
2181 const struct snd_pci_quirk *q;
2185 case POS_FIX_POSBUF:
2189 /* Check VIA/ATI HD Audio Controller exist */
2190 switch (chip->driver_type) {
2191 case AZX_DRIVER_VIA:
2192 case AZX_DRIVER_ATI:
2193 chip->via_dmapos_patch = 1;
2194 /* Use link position directly, avoid any transfer problem. */
2195 return POS_FIX_LPIB;
2197 chip->via_dmapos_patch = 0;
2199 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2202 "hda_intel: position_fix set to %d "
2203 "for device %04x:%04x\n",
2204 q->value, q->subvendor, q->subdevice);
2207 return POS_FIX_AUTO;
2211 * black-lists for probe_mask
2213 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2214 /* Thinkpad often breaks the controller communication when accessing
2215 * to the non-working (or non-existing) modem codec slot.
2217 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2218 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2219 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2221 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2222 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2223 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2224 /* forced codec slots */
2225 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2226 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2230 #define AZX_FORCE_CODEC_MASK 0x100
2232 static void __devinit check_probe_mask(struct azx *chip, int dev)
2234 const struct snd_pci_quirk *q;
2236 chip->codec_probe_mask = probe_mask[dev];
2237 if (chip->codec_probe_mask == -1) {
2238 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2241 "hda_intel: probe_mask set to 0x%x "
2242 "for device %04x:%04x\n",
2243 q->value, q->subvendor, q->subdevice);
2244 chip->codec_probe_mask = q->value;
2248 /* check forced option */
2249 if (chip->codec_probe_mask != -1 &&
2250 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2251 chip->codec_mask = chip->codec_probe_mask & 0xff;
2252 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2261 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2262 int dev, int driver_type,
2267 unsigned short gcap;
2268 static struct snd_device_ops ops = {
2269 .dev_free = azx_dev_free,
2274 err = pci_enable_device(pci);
2278 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2280 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2281 pci_disable_device(pci);
2285 spin_lock_init(&chip->reg_lock);
2286 mutex_init(&chip->open_mutex);
2290 chip->driver_type = driver_type;
2291 chip->msi = enable_msi;
2292 chip->dev_index = dev;
2293 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2295 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2296 check_probe_mask(chip, dev);
2298 chip->single_cmd = single_cmd;
2300 if (bdl_pos_adj[dev] < 0) {
2301 switch (chip->driver_type) {
2302 case AZX_DRIVER_ICH:
2303 bdl_pos_adj[dev] = 1;
2306 bdl_pos_adj[dev] = 32;
2311 #if BITS_PER_LONG != 64
2312 /* Fix up base address on ULI M5461 */
2313 if (chip->driver_type == AZX_DRIVER_ULI) {
2315 pci_read_config_word(pci, 0x40, &tmp3);
2316 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2317 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2321 err = pci_request_regions(pci, "ICH HD audio");
2324 pci_disable_device(pci);
2328 chip->addr = pci_resource_start(pci, 0);
2329 chip->remap_addr = pci_ioremap_bar(pci, 0);
2330 if (chip->remap_addr == NULL) {
2331 snd_printk(KERN_ERR SFX "ioremap error\n");
2337 if (pci_enable_msi(pci) < 0)
2340 if (azx_acquire_irq(chip, 0) < 0) {
2345 pci_set_master(pci);
2346 synchronize_irq(chip->irq);
2348 gcap = azx_readw(chip, GCAP);
2349 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2351 /* disable SB600 64bit support for safety */
2352 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2353 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2354 struct pci_dev *p_smbus;
2355 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2356 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2359 if (p_smbus->revision < 0x30)
2360 gcap &= ~ICH6_GCAP_64OK;
2361 pci_dev_put(p_smbus);
2365 /* allow 64bit DMA address if supported by H/W */
2366 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2367 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2369 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2370 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2373 /* read number of streams from GCAP register instead of using
2376 chip->capture_streams = (gcap >> 8) & 0x0f;
2377 chip->playback_streams = (gcap >> 12) & 0x0f;
2378 if (!chip->playback_streams && !chip->capture_streams) {
2379 /* gcap didn't give any info, switching to old method */
2381 switch (chip->driver_type) {
2382 case AZX_DRIVER_ULI:
2383 chip->playback_streams = ULI_NUM_PLAYBACK;
2384 chip->capture_streams = ULI_NUM_CAPTURE;
2386 case AZX_DRIVER_ATIHDMI:
2387 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2388 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2390 case AZX_DRIVER_GENERIC:
2392 chip->playback_streams = ICH6_NUM_PLAYBACK;
2393 chip->capture_streams = ICH6_NUM_CAPTURE;
2397 chip->capture_index_offset = 0;
2398 chip->playback_index_offset = chip->capture_streams;
2399 chip->num_streams = chip->playback_streams + chip->capture_streams;
2400 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2402 if (!chip->azx_dev) {
2403 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2407 for (i = 0; i < chip->num_streams; i++) {
2408 /* allocate memory for the BDL for each stream */
2409 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2410 snd_dma_pci_data(chip->pci),
2411 BDL_SIZE, &chip->azx_dev[i].bdl);
2413 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2417 /* allocate memory for the position buffer */
2418 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2419 snd_dma_pci_data(chip->pci),
2420 chip->num_streams * 8, &chip->posbuf);
2422 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2425 /* allocate CORB/RIRB */
2426 err = azx_alloc_cmd_io(chip);
2430 /* initialize streams */
2431 azx_init_stream(chip);
2433 /* initialize chip */
2435 azx_init_chip(chip);
2437 /* codec detection */
2438 if (!chip->codec_mask) {
2439 snd_printk(KERN_ERR SFX "no codecs found!\n");
2444 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2446 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2450 strcpy(card->driver, "HDA-Intel");
2451 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2452 sizeof(card->shortname));
2453 snprintf(card->longname, sizeof(card->longname),
2454 "%s at 0x%lx irq %i",
2455 card->shortname, chip->addr, chip->irq);
2465 static void power_down_all_codecs(struct azx *chip)
2467 #ifdef CONFIG_SND_HDA_POWER_SAVE
2468 /* The codecs were powered up in snd_hda_codec_new().
2469 * Now all initialization done, so turn them down if possible
2471 struct hda_codec *codec;
2472 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2473 snd_hda_power_down(codec);
2478 static int __devinit azx_probe(struct pci_dev *pci,
2479 const struct pci_device_id *pci_id)
2482 struct snd_card *card;
2486 if (dev >= SNDRV_CARDS)
2493 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2495 snd_printk(KERN_ERR SFX "Error creating card!\n");
2499 /* set this here since it's referred in snd_hda_load_patch() */
2500 snd_card_set_dev(card, &pci->dev);
2502 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2505 card->private_data = chip;
2507 /* create codec instances */
2508 err = azx_codec_create(chip, model[dev]);
2511 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2513 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2515 err = snd_hda_load_patch(chip->bus, patch[dev]);
2520 if (!probe_only[dev]) {
2521 err = azx_codec_configure(chip);
2526 /* create PCM streams */
2527 err = snd_hda_build_pcms(chip->bus);
2531 /* create mixer controls */
2532 err = azx_mixer_create(chip);
2536 err = snd_card_register(card);
2540 pci_set_drvdata(pci, card);
2542 power_down_all_codecs(chip);
2543 azx_notifier_register(chip);
2548 snd_card_free(card);
2552 static void __devexit azx_remove(struct pci_dev *pci)
2554 snd_card_free(pci_get_drvdata(pci));
2555 pci_set_drvdata(pci, NULL);
2559 static struct pci_device_id azx_ids[] = {
2561 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2562 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2563 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2564 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2565 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2566 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2567 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2568 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2569 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2571 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2573 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2574 /* ATI SB 450/600 */
2575 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2576 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2578 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2579 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2580 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2581 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2582 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2583 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2584 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2585 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2586 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2587 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2588 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2589 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2590 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2591 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2592 /* VIA VT8251/VT8237A */
2593 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2595 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2597 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2599 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2600 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2601 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2602 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2603 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2604 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2605 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2606 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2607 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2608 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2609 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2610 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2611 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2612 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2613 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2614 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2615 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2616 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2617 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2618 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2619 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2620 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2622 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2623 /* Creative X-Fi (CA0110-IBG) */
2624 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2625 /* the following entry conflicts with snd-ctxfi driver,
2626 * as ctxfi driver mutates from HD-audio to native mode with
2627 * a special command sequence.
2629 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2630 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2631 .class_mask = 0xffffff,
2632 .driver_data = AZX_DRIVER_GENERIC },
2634 /* this entry seems still valid -- i.e. without emu20kx chip */
2635 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2637 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2638 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2639 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2640 .class_mask = 0xffffff,
2641 .driver_data = AZX_DRIVER_GENERIC },
2644 MODULE_DEVICE_TABLE(pci, azx_ids);
2646 /* pci_driver definition */
2647 static struct pci_driver driver = {
2648 .name = "HDA Intel",
2649 .id_table = azx_ids,
2651 .remove = __devexit_p(azx_remove),
2653 .suspend = azx_suspend,
2654 .resume = azx_resume,
2658 static int __init alsa_card_azx_init(void)
2660 return pci_register_driver(&driver);
2663 static void __exit alsa_card_azx_exit(void)
2665 pci_unregister_driver(&driver);
2668 module_init(alsa_card_azx_init)
2669 module_exit(alsa_card_azx_exit)