2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
23 #include <sound/driver.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
50 "{C-Media,CMI8338B}}");
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
84 * CM8x38 registers definition
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
113 #define CM_REG_CHFORMAT 0x08
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
153 #define CM_CH0_SRATE_128K 0x00000300
154 #define CM_CH0_SRATE_MASK 0x00000300
156 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
157 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
158 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
159 #define CM_SPDLOCKED 0x00000010
161 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
162 #define CM_CH1FMT_SHIFT 2
163 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
164 #define CM_CH0FMT_SHIFT 0
166 #define CM_REG_INT_HLDCLR 0x0C
167 #define CM_CHIP_MASK2 0xff000000
168 #define CM_CHIP_8768 0x20000000
169 #define CM_CHIP_055 0x08000000
170 #define CM_CHIP_039 0x04000000
171 #define CM_CHIP_039_6CH 0x01000000
172 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
173 #define CM_TDMA_INT_EN 0x00040000
174 #define CM_CH1_INT_EN 0x00020000
175 #define CM_CH0_INT_EN 0x00010000
177 #define CM_REG_INT_STATUS 0x10
178 #define CM_INTR 0x80000000
179 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
180 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
181 #define CM_UARTINT 0x00010000
182 #define CM_LTDMAINT 0x00008000
183 #define CM_HTDMAINT 0x00004000
184 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
185 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
186 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
187 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
188 #define CM_CH1BUSY 0x00000008
189 #define CM_CH0BUSY 0x00000004
190 #define CM_CHINT1 0x00000002
191 #define CM_CHINT0 0x00000001
193 #define CM_REG_LEGACY_CTRL 0x14
194 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
195 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
196 #define CM_VMPU_330 0x00000000
197 #define CM_VMPU_320 0x20000000
198 #define CM_VMPU_310 0x40000000
199 #define CM_VMPU_300 0x60000000
200 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
201 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
202 #define CM_VSBSEL_220 0x00000000
203 #define CM_VSBSEL_240 0x04000000
204 #define CM_VSBSEL_260 0x08000000
205 #define CM_VSBSEL_280 0x0C000000
206 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
207 #define CM_FMSEL_388 0x00000000
208 #define CM_FMSEL_3C8 0x01000000
209 #define CM_FMSEL_3E0 0x02000000
210 #define CM_FMSEL_3E8 0x03000000
211 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
212 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
213 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
214 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
215 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
216 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
217 #define CM_C_EECS 0x00040000
218 #define CM_C_EEDI46 0x00020000
219 #define CM_C_EECK46 0x00010000
220 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
221 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
222 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
223 #define CM_EXBASEN 0x00001000 /* external bass input enable */
225 #define CM_REG_MISC_CTRL 0x18
226 #define CM_PWD 0x80000000 /* power down */
227 #define CM_RESET 0x40000000
228 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
229 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
230 #define CM_TXVX 0x08000000 /* model 037? */
231 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
232 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
233 #define CM_SPDIF48K 0x01000000 /* write */
234 #define CM_SPATUS48K 0x01000000 /* read */
235 #define CM_ENDBDAC 0x00800000 /* enable double dac */
236 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
237 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
238 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
239 #define CM_FM_EN 0x00080000 /* enable legacy FM */
240 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
241 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
242 #define CM_VIDWPDSB 0x00010000 /* model 037? */
243 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
244 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
245 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
246 #define CM_VIDWPPRT 0x00002000 /* model 037? */
247 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
248 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
249 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
250 #define CM_ENCENTER 0x00000080
251 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
252 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
253 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
254 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
255 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
256 #define CM_UPDDMA_2048 0x00000000
257 #define CM_UPDDMA_1024 0x00000004
258 #define CM_UPDDMA_512 0x00000008
259 #define CM_UPDDMA_256 0x0000000C
260 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
261 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
262 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
264 #define CM_REG_TDMA_POSITION 0x1C
265 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
266 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
269 #define CM_REG_MIXER0 0x20
270 #define CM_REG_SBVR 0x20 /* write: sb16 version */
271 #define CM_REG_DEV 0x20 /* read: hardware device version */
273 #define CM_REG_MIXER21 0x21
274 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
275 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
276 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
277 #define CM_X_SB16 0x01 /* SB16 compatible */
279 #define CM_REG_SB16_DATA 0x22
280 #define CM_REG_SB16_ADDR 0x23
282 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
283 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
284 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
285 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
287 #define CM_REG_MIXER1 0x24
288 #define CM_FMMUTE 0x80 /* mute FM */
289 #define CM_FMMUTE_SHIFT 7
290 #define CM_WSMUTE 0x40 /* mute PCM */
291 #define CM_WSMUTE_SHIFT 6
292 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
293 #define CM_REAR2LIN_SHIFT 5
294 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
295 #define CM_REAR2FRONT_SHIFT 4
296 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
297 #define CM_WAVEINL_SHIFT 3
298 #define CM_WAVEINR 0x04 /* digical wave rec. right */
299 #define CM_WAVEINR_SHIFT 2
300 #define CM_X3DEN 0x02 /* 3D surround enable */
301 #define CM_X3DEN_SHIFT 1
302 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
303 #define CM_CDPLAY_SHIFT 0
305 #define CM_REG_MIXER2 0x25
306 #define CM_RAUXREN 0x80 /* AUX right capture */
307 #define CM_RAUXREN_SHIFT 7
308 #define CM_RAUXLEN 0x40 /* AUX left capture */
309 #define CM_RAUXLEN_SHIFT 6
310 #define CM_VAUXRM 0x20 /* AUX right mute */
311 #define CM_VAUXRM_SHIFT 5
312 #define CM_VAUXLM 0x10 /* AUX left mute */
313 #define CM_VAUXLM_SHIFT 4
314 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
315 #define CM_VADMIC_SHIFT 1
316 #define CM_MICGAINZ 0x01 /* mic boost */
317 #define CM_MICGAINZ_SHIFT 0
319 #define CM_REG_MIXER3 0x24
320 #define CM_REG_AUX_VOL 0x26
321 #define CM_VAUXL_MASK 0xf0
322 #define CM_VAUXR_MASK 0x0f
324 #define CM_REG_MISC 0x27
325 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
326 #define CM_XGPO1 0x20
327 // #define CM_XGPBIO 0x04
328 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
329 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
330 #define CM_SPDVALID 0x02 /* spdif input valid check */
331 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
333 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
335 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
336 * or identical with AC97 codec?
338 #define CM_REG_EXTERN_CODEC CM_REG_AC97
341 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
343 #define CM_REG_MPU_PCI 0x40
346 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
348 #define CM_REG_FM_PCI 0x50
351 * access from SB-mixer port
353 #define CM_REG_EXTENT_IND 0xf0
354 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
355 #define CM_VPHONE_SHIFT 5
356 #define CM_VPHOM 0x10 /* Phone mute control */
357 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
358 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
359 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
360 #define CM_VADMIC3 0x01 /* Mic record boost */
363 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
364 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
367 #define CM_REG_PLL 0xf8
372 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
373 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
374 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
375 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
377 #define CM_REG_EXT_MISC 0x90
378 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
379 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
380 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
381 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
382 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
383 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
384 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
385 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
390 #define CM_EXTENT_CODEC 0x100
391 #define CM_EXTENT_MIDI 0x2
392 #define CM_EXTENT_SYNTH 0x4
396 * channels for playback / capture
402 * flags to check device open/close
404 #define CM_OPEN_NONE 0
405 #define CM_OPEN_CH_MASK 0x01
406 #define CM_OPEN_DAC 0x10
407 #define CM_OPEN_ADC 0x20
408 #define CM_OPEN_SPDIF 0x40
409 #define CM_OPEN_MCHAN 0x80
410 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
412 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
413 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
414 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
415 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
419 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
420 #define CM_PLAYBACK_SPDF CM_SPDF_1
421 #define CM_CAPTURE_SPDF CM_SPDF_0
423 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
424 #define CM_PLAYBACK_SPDF CM_SPDF_0
425 #define CM_CAPTURE_SPDF CM_SPDF_1
434 struct snd_pcm_substream *substream;
435 u8 running; /* dac/adc running? */
436 u8 fmt; /* format bits */
439 unsigned int dma_size; /* in frames */
441 unsigned int ch; /* channel (0/1) */
442 unsigned int offset; /* physical address of the buffer */
445 /* mixer elements toggled/resumed during ac3 playback */
446 struct cmipci_mixer_auto_switches {
447 const char *name; /* switch to toggle */
448 int toggle_on; /* value to change when ac3 mode */
450 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
451 {"PCM Playback Switch", 0},
452 {"IEC958 Output Switch", 1},
453 {"IEC958 Mix Analog", 0},
454 // {"IEC958 Out To DAC", 1}, // no longer used
457 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
460 struct snd_card *card;
463 unsigned int device; /* device ID */
466 unsigned long iobase;
467 unsigned int ctrl; /* FUNCTRL0 current value */
469 struct snd_pcm *pcm; /* DAC/ADC PCM */
470 struct snd_pcm *pcm2; /* 2nd DAC */
471 struct snd_pcm *pcm_spdif; /* SPDIF */
475 unsigned int can_ac3_sw: 1;
476 unsigned int can_ac3_hw: 1;
477 unsigned int can_multi_ch: 1;
478 unsigned int can_96k: 1; /* samplerate above 48k */
479 unsigned int do_soft_ac3: 1;
481 unsigned int spdif_playback_avail: 1; /* spdif ready? */
482 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
483 int spdif_counter; /* for software AC3 */
485 unsigned int dig_status;
486 unsigned int dig_pcm_status;
488 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
490 int opened[2]; /* open mode */
491 struct mutex open_mutex;
493 unsigned int mixer_insensitive: 1;
494 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
495 int mixer_res_status[CM_SAVED_MIXERS];
497 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
500 struct snd_rawmidi *rmidi;
502 #ifdef SUPPORT_JOYSTICK
503 struct gameport *gameport;
509 unsigned int saved_regs[0x20];
510 unsigned char saved_mixers[0x20];
515 /* read/write operations for dword register */
516 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
518 outl(data, cm->iobase + cmd);
521 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
523 return inl(cm->iobase + cmd);
526 /* read/write operations for word register */
527 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
529 outw(data, cm->iobase + cmd);
532 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
534 return inw(cm->iobase + cmd);
537 /* read/write operations for byte register */
538 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
540 outb(data, cm->iobase + cmd);
543 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
545 return inb(cm->iobase + cmd);
548 /* bit operations for dword register */
549 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
551 unsigned int val, oval;
552 val = oval = inl(cm->iobase + cmd);
556 outl(val, cm->iobase + cmd);
560 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
562 unsigned int val, oval;
563 val = oval = inl(cm->iobase + cmd);
567 outl(val, cm->iobase + cmd);
571 /* bit operations for byte register */
572 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
574 unsigned char val, oval;
575 val = oval = inb(cm->iobase + cmd);
579 outb(val, cm->iobase + cmd);
583 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
585 unsigned char val, oval;
586 val = oval = inb(cm->iobase + cmd);
590 outb(val, cm->iobase + cmd);
600 * calculate frequency
603 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
605 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
609 for (i = 0; i < ARRAY_SIZE(rates); i++) {
610 if (rates[i] == rate)
617 #ifdef USE_VAR48KRATE
619 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
620 * does it this way .. maybe not. Never get any information from C-Media about
621 * that <werner@suse.de>.
623 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
625 unsigned int delta, tolerance;
628 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
633 tolerance = rate*CM_TOLERANCE_RATE;
635 for (xn = (1+2); xn < (0x1f+2); xn++) {
636 for (xm = (1+2); xm < (0xff+2); xm++) {
637 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
645 * If we found one, remember this,
646 * and try to find a closer one
648 if (delta < tolerance) {
660 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
661 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
662 * at the register CM_REG_FUNCTRL1 (0x04).
663 * Problem: other ways are also possible (any information about that?)
665 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
667 unsigned int reg = CM_REG_PLL + slot;
669 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
670 * for DSFC/ASFC (000 upto 111).
673 /* FIXME: Init (Do we've to set an other register first before programming?) */
675 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
676 snd_cmipci_write_b(cm, reg, rate>>8);
677 snd_cmipci_write_b(cm, reg, rate&0xff);
679 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
681 #endif /* USE_VAR48KRATE */
683 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
684 struct snd_pcm_hw_params *hw_params)
686 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
689 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
690 struct snd_pcm_hw_params *hw_params)
692 struct cmipci *cm = snd_pcm_substream_chip(substream);
693 if (params_channels(hw_params) > 2) {
694 mutex_lock(&cm->open_mutex);
695 if (cm->opened[CM_CH_PLAY]) {
696 mutex_unlock(&cm->open_mutex);
699 /* reserve the channel A */
700 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
701 mutex_unlock(&cm->open_mutex);
703 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
706 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
708 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
710 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
714 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
716 return snd_pcm_lib_free_pages(substream);
723 static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
724 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
729 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
734 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
740 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
743 if (!cm->can_multi_ch || !rec->ch)
745 if (rec->fmt != 0x03) /* stereo 16bit only */
749 if (cm->can_multi_ch) {
750 spin_lock_irq(&cm->reg_lock);
752 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
753 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
755 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
759 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
763 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
764 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
766 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
767 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
770 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
773 spin_unlock_irq(&cm->reg_lock);
780 * prepare playback/capture channel
781 * channel to be used must have been set in rec->ch.
783 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
784 struct snd_pcm_substream *substream)
786 unsigned int reg, freq, freq_ext, val;
787 unsigned int period_size;
788 struct snd_pcm_runtime *runtime = substream->runtime;
792 if (snd_pcm_format_width(runtime->format) >= 16) {
794 if (snd_pcm_format_width(runtime->format) > 16)
795 rec->shift++; /* 24/32bit */
797 if (runtime->channels > 1)
799 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
800 snd_printd("cannot set dac channels\n");
804 rec->offset = runtime->dma_addr;
805 /* buffer and period sizes in frame */
806 rec->dma_size = runtime->buffer_size << rec->shift;
807 period_size = runtime->period_size << rec->shift;
808 if (runtime->channels > 2) {
810 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
811 period_size = (period_size * runtime->channels) / 2;
814 spin_lock_irq(&cm->reg_lock);
816 /* set buffer address */
817 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
818 snd_cmipci_write(cm, reg, rec->offset);
819 /* program sample counts */
820 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
821 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
822 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
824 /* set adc/dac flag */
825 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
830 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
831 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
833 /* set sample rate */
836 if (runtime->rate > 48000)
837 switch (runtime->rate) {
838 case 88200: freq_ext = CM_CH0_SRATE_88K; break;
839 case 96000: freq_ext = CM_CH0_SRATE_96K; break;
840 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
841 default: snd_BUG(); break;
844 freq = snd_cmipci_rate_freq(runtime->rate);
845 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
847 val &= ~CM_DSFC_MASK;
848 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
850 val &= ~CM_ASFC_MASK;
851 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
853 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
854 //snd_printd("cmipci: functrl1 = %08x\n", val);
857 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
859 val &= ~CM_CH1FMT_MASK;
860 val |= rec->fmt << CM_CH1FMT_SHIFT;
862 val &= ~CM_CH0FMT_MASK;
863 val |= rec->fmt << CM_CH0FMT_SHIFT;
866 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
867 val |= freq_ext << (rec->ch * 2);
869 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
870 //snd_printd("cmipci: chformat = %08x\n", val);
872 if (!rec->is_dac && cm->chip_version) {
873 if (runtime->rate > 44100)
874 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
876 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
880 spin_unlock_irq(&cm->reg_lock);
888 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
891 unsigned int inthld, chen, reset, pause;
894 inthld = CM_CH0_INT_EN << rec->ch;
895 chen = CM_CHEN0 << rec->ch;
896 reset = CM_RST_CH0 << rec->ch;
897 pause = CM_PAUSE0 << rec->ch;
899 spin_lock(&cm->reg_lock);
901 case SNDRV_PCM_TRIGGER_START:
904 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
907 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
908 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
910 case SNDRV_PCM_TRIGGER_STOP:
912 /* disable interrupt */
913 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
917 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
918 rec->needs_silencing = rec->is_dac;
920 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
921 case SNDRV_PCM_TRIGGER_SUSPEND:
923 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
925 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
926 case SNDRV_PCM_TRIGGER_RESUME:
928 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
934 spin_unlock(&cm->reg_lock);
939 * return the current pointer
941 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
942 struct snd_pcm_substream *substream)
948 #if 1 // this seems better..
949 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
950 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
953 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
954 ptr = snd_cmipci_read(cm, reg) - rec->offset;
955 ptr = bytes_to_frames(substream->runtime, ptr);
957 if (substream->runtime->channels > 2)
958 ptr = (ptr * 2) / substream->runtime->channels;
966 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
969 struct cmipci *cm = snd_pcm_substream_chip(substream);
970 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
973 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
975 struct cmipci *cm = snd_pcm_substream_chip(substream);
976 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
985 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
988 struct cmipci *cm = snd_pcm_substream_chip(substream);
989 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
992 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
994 struct cmipci *cm = snd_pcm_substream_chip(substream);
995 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
1000 * hw preparation for spdif
1003 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1004 struct snd_ctl_elem_info *uinfo)
1006 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1011 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_value *ucontrol)
1014 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1017 spin_lock_irq(&chip->reg_lock);
1018 for (i = 0; i < 4; i++)
1019 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1020 spin_unlock_irq(&chip->reg_lock);
1024 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1025 struct snd_ctl_elem_value *ucontrol)
1027 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1032 spin_lock_irq(&chip->reg_lock);
1033 for (i = 0; i < 4; i++)
1034 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1035 change = val != chip->dig_status;
1036 chip->dig_status = val;
1037 spin_unlock_irq(&chip->reg_lock);
1041 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1043 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1044 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1045 .info = snd_cmipci_spdif_default_info,
1046 .get = snd_cmipci_spdif_default_get,
1047 .put = snd_cmipci_spdif_default_put
1050 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1051 struct snd_ctl_elem_info *uinfo)
1053 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1058 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1059 struct snd_ctl_elem_value *ucontrol)
1061 ucontrol->value.iec958.status[0] = 0xff;
1062 ucontrol->value.iec958.status[1] = 0xff;
1063 ucontrol->value.iec958.status[2] = 0xff;
1064 ucontrol->value.iec958.status[3] = 0xff;
1068 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1070 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1071 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1072 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1073 .info = snd_cmipci_spdif_mask_info,
1074 .get = snd_cmipci_spdif_mask_get,
1077 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1078 struct snd_ctl_elem_info *uinfo)
1080 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1085 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1088 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1091 spin_lock_irq(&chip->reg_lock);
1092 for (i = 0; i < 4; i++)
1093 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1094 spin_unlock_irq(&chip->reg_lock);
1098 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1099 struct snd_ctl_elem_value *ucontrol)
1101 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1106 spin_lock_irq(&chip->reg_lock);
1107 for (i = 0; i < 4; i++)
1108 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1109 change = val != chip->dig_pcm_status;
1110 chip->dig_pcm_status = val;
1111 spin_unlock_irq(&chip->reg_lock);
1115 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1117 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1118 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1119 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1120 .info = snd_cmipci_spdif_stream_info,
1121 .get = snd_cmipci_spdif_stream_get,
1122 .put = snd_cmipci_spdif_stream_put
1128 /* save mixer setting and mute for AC3 playback */
1129 static int save_mixer_state(struct cmipci *cm)
1131 if (! cm->mixer_insensitive) {
1132 struct snd_ctl_elem_value *val;
1135 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1138 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1139 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1142 memset(val, 0, sizeof(*val));
1144 cm->mixer_res_status[i] = val->value.integer.value[0];
1145 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1146 event = SNDRV_CTL_EVENT_MASK_INFO;
1147 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1148 ctl->put(ctl, val); /* toggle */
1149 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1151 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1152 snd_ctl_notify(cm->card, event, &ctl->id);
1156 cm->mixer_insensitive = 1;
1162 /* restore the previously saved mixer status */
1163 static void restore_mixer_state(struct cmipci *cm)
1165 if (cm->mixer_insensitive) {
1166 struct snd_ctl_elem_value *val;
1169 val = kmalloc(sizeof(*val), GFP_KERNEL);
1172 cm->mixer_insensitive = 0; /* at first clear this;
1173 otherwise the changes will be ignored */
1174 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1175 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1179 memset(val, 0, sizeof(*val));
1180 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1182 event = SNDRV_CTL_EVENT_MASK_INFO;
1183 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1184 val->value.integer.value[0] = cm->mixer_res_status[i];
1186 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1188 snd_ctl_notify(cm->card, event, &ctl->id);
1195 /* spinlock held! */
1196 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1200 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1202 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1204 if (cm->can_ac3_hw) {
1205 /* SPD24SEL for 037, 0x02 */
1206 /* SPD24SEL for 039, 0x20, but cannot be set */
1207 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1208 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1209 } else { /* can_ac3_sw */
1210 /* SPD32SEL for 037 & 039, 0x20 */
1211 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1212 /* set 176K sample rate to fix 033 HW bug */
1213 if (cm->chip_version == 33) {
1214 if (rate >= 48000) {
1215 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1217 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1223 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1224 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1226 if (cm->can_ac3_hw) {
1227 /* chip model >= 37 */
1228 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1229 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1230 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1232 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1233 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1236 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1237 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1238 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1243 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1247 rate = subs->runtime->rate;
1250 if ((err = save_mixer_state(cm)) < 0)
1253 spin_lock_irq(&cm->reg_lock);
1254 cm->spdif_playback_avail = up;
1256 /* they are controlled via "IEC958 Output Switch" */
1257 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1258 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1259 if (cm->spdif_playback_enabled)
1260 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1261 setup_ac3(cm, subs, do_ac3, rate);
1263 if (rate == 48000 || rate == 96000)
1264 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1266 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1268 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1270 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1272 /* they are controlled via "IEC958 Output Switch" */
1273 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1274 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1275 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1276 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1277 setup_ac3(cm, subs, 0, 0);
1279 spin_unlock_irq(&cm->reg_lock);
1288 /* playback - enable spdif only on the certain condition */
1289 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1291 struct cmipci *cm = snd_pcm_substream_chip(substream);
1292 int rate = substream->runtime->rate;
1293 int err, do_spdif, do_ac3 = 0;
1295 do_spdif = (rate >= 44100 && rate <= 96000 &&
1296 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1297 substream->runtime->channels == 2);
1298 if (do_spdif && cm->can_ac3_hw)
1299 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1300 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1302 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1305 /* playback (via device #2) - enable spdif always */
1306 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1308 struct cmipci *cm = snd_pcm_substream_chip(substream);
1312 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1314 do_ac3 = 1; /* doesn't matter */
1315 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1317 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1321 * Apparently, the samples last played on channel A stay in some buffer, even
1322 * after the channel is reset, and get added to the data for the rear DACs when
1323 * playing a multichannel stream on channel B. This is likely to generate
1324 * wraparounds and thus distortions.
1325 * To avoid this, we play at least one zero sample after the actual stream has
1328 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1330 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1331 unsigned int reg, val;
1333 if (rec->needs_silencing && runtime && runtime->dma_area) {
1334 /* set up a small silence buffer */
1335 memset(runtime->dma_area, 0, PAGE_SIZE);
1336 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1337 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1338 snd_cmipci_write(cm, reg, val);
1340 /* configure for 16 bits, 2 channels, 8 kHz */
1341 if (runtime->channels > 2)
1342 set_dac_channels(cm, rec, 2);
1343 spin_lock_irq(&cm->reg_lock);
1344 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1345 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1346 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1347 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1348 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1349 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1350 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1352 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1353 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1355 /* start stream (we don't need interrupts) */
1356 cm->ctrl |= CM_CHEN0 << rec->ch;
1357 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1358 spin_unlock_irq(&cm->reg_lock);
1362 /* stop and reset stream */
1363 spin_lock_irq(&cm->reg_lock);
1364 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1365 val = CM_RST_CH0 << rec->ch;
1366 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1367 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1368 spin_unlock_irq(&cm->reg_lock);
1370 rec->needs_silencing = 0;
1374 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1376 struct cmipci *cm = snd_pcm_substream_chip(substream);
1377 setup_spdif_playback(cm, substream, 0, 0);
1378 restore_mixer_state(cm);
1379 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1380 return snd_cmipci_hw_free(substream);
1383 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1385 struct cmipci *cm = snd_pcm_substream_chip(substream);
1386 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1387 return snd_cmipci_hw_free(substream);
1391 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1393 struct cmipci *cm = snd_pcm_substream_chip(substream);
1394 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1397 /* capture with spdif (via device #2) */
1398 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1400 struct cmipci *cm = snd_pcm_substream_chip(substream);
1402 spin_lock_irq(&cm->reg_lock);
1403 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1405 if (substream->runtime->rate > 48000)
1406 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1408 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1410 spin_unlock_irq(&cm->reg_lock);
1412 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1415 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1417 struct cmipci *cm = snd_pcm_substream_chip(subs);
1419 spin_lock_irq(&cm->reg_lock);
1420 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1421 spin_unlock_irq(&cm->reg_lock);
1423 return snd_cmipci_hw_free(subs);
1430 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1432 struct cmipci *cm = dev_id;
1433 unsigned int status, mask = 0;
1435 /* fastpath out, to ease interrupt sharing */
1436 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1437 if (!(status & CM_INTR))
1440 /* acknowledge interrupt */
1441 spin_lock(&cm->reg_lock);
1442 if (status & CM_CHINT0)
1443 mask |= CM_CH0_INT_EN;
1444 if (status & CM_CHINT1)
1445 mask |= CM_CH1_INT_EN;
1446 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1447 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1448 spin_unlock(&cm->reg_lock);
1450 if (cm->rmidi && (status & CM_UARTINT))
1451 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1454 if ((status & CM_CHINT0) && cm->channel[0].running)
1455 snd_pcm_period_elapsed(cm->channel[0].substream);
1456 if ((status & CM_CHINT1) && cm->channel[1].running)
1457 snd_pcm_period_elapsed(cm->channel[1].substream);
1466 /* playback on channel A */
1467 static struct snd_pcm_hardware snd_cmipci_playback =
1469 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1470 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1471 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1472 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1473 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1478 .buffer_bytes_max = (128*1024),
1479 .period_bytes_min = 64,
1480 .period_bytes_max = (128*1024),
1482 .periods_max = 1024,
1486 /* capture on channel B */
1487 static struct snd_pcm_hardware snd_cmipci_capture =
1489 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1490 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1491 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1492 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1493 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1498 .buffer_bytes_max = (128*1024),
1499 .period_bytes_min = 64,
1500 .period_bytes_max = (128*1024),
1502 .periods_max = 1024,
1506 /* playback on channel B - stereo 16bit only? */
1507 static struct snd_pcm_hardware snd_cmipci_playback2 =
1509 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1510 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1511 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1512 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1513 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1518 .buffer_bytes_max = (128*1024),
1519 .period_bytes_min = 64,
1520 .period_bytes_max = (128*1024),
1522 .periods_max = 1024,
1526 /* spdif playback on channel A */
1527 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1529 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1530 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1531 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1532 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1533 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1538 .buffer_bytes_max = (128*1024),
1539 .period_bytes_min = 64,
1540 .period_bytes_max = (128*1024),
1542 .periods_max = 1024,
1546 /* spdif playback on channel A (32bit, IEC958 subframes) */
1547 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1549 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1550 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1551 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1552 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1553 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1558 .buffer_bytes_max = (128*1024),
1559 .period_bytes_min = 64,
1560 .period_bytes_max = (128*1024),
1562 .periods_max = 1024,
1566 /* spdif capture on channel B */
1567 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1569 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1570 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1571 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1572 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1573 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1578 .buffer_bytes_max = (128*1024),
1579 .period_bytes_min = 64,
1580 .period_bytes_max = (128*1024),
1582 .periods_max = 1024,
1586 static unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1587 32000, 44100, 48000, 88200, 96000, 128000 };
1588 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1589 .count = ARRAY_SIZE(rate_constraints),
1590 .list = rate_constraints,
1595 * check device open/close
1597 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1599 int ch = mode & CM_OPEN_CH_MASK;
1601 /* FIXME: a file should wait until the device becomes free
1602 * when it's opened on blocking mode. however, since the current
1603 * pcm framework doesn't pass file pointer before actually opened,
1604 * we can't know whether blocking mode or not in open callback..
1606 mutex_lock(&cm->open_mutex);
1607 if (cm->opened[ch]) {
1608 mutex_unlock(&cm->open_mutex);
1611 cm->opened[ch] = mode;
1612 cm->channel[ch].substream = subs;
1613 if (! (mode & CM_OPEN_DAC)) {
1614 /* disable dual DAC mode */
1615 cm->channel[ch].is_dac = 0;
1616 spin_lock_irq(&cm->reg_lock);
1617 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1618 spin_unlock_irq(&cm->reg_lock);
1620 mutex_unlock(&cm->open_mutex);
1624 static void close_device_check(struct cmipci *cm, int mode)
1626 int ch = mode & CM_OPEN_CH_MASK;
1628 mutex_lock(&cm->open_mutex);
1629 if (cm->opened[ch] == mode) {
1630 if (cm->channel[ch].substream) {
1631 snd_cmipci_ch_reset(cm, ch);
1632 cm->channel[ch].running = 0;
1633 cm->channel[ch].substream = NULL;
1636 if (! cm->channel[ch].is_dac) {
1637 /* enable dual DAC mode again */
1638 cm->channel[ch].is_dac = 1;
1639 spin_lock_irq(&cm->reg_lock);
1640 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1641 spin_unlock_irq(&cm->reg_lock);
1644 mutex_unlock(&cm->open_mutex);
1650 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1652 struct cmipci *cm = snd_pcm_substream_chip(substream);
1653 struct snd_pcm_runtime *runtime = substream->runtime;
1656 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1658 runtime->hw = snd_cmipci_playback;
1659 if (cm->chip_version == 68) {
1660 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1661 SNDRV_PCM_RATE_96000;
1662 runtime->hw.rate_max = 96000;
1663 } else if (cm->chip_version == 55) {
1664 err = snd_pcm_hw_constraint_list(runtime, 0,
1665 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1668 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1669 runtime->hw.rate_max = 128000;
1671 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1672 cm->dig_pcm_status = cm->dig_status;
1676 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1678 struct cmipci *cm = snd_pcm_substream_chip(substream);
1679 struct snd_pcm_runtime *runtime = substream->runtime;
1682 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1684 runtime->hw = snd_cmipci_capture;
1685 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1686 runtime->hw.rate_min = 41000;
1687 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1688 } else if (cm->chip_version == 55) {
1689 err = snd_pcm_hw_constraint_list(runtime, 0,
1690 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1693 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1694 runtime->hw.rate_max = 128000;
1696 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1700 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1702 struct cmipci *cm = snd_pcm_substream_chip(substream);
1703 struct snd_pcm_runtime *runtime = substream->runtime;
1706 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1708 runtime->hw = snd_cmipci_playback2;
1709 mutex_lock(&cm->open_mutex);
1710 if (! cm->opened[CM_CH_PLAY]) {
1711 if (cm->can_multi_ch) {
1712 runtime->hw.channels_max = cm->max_channels;
1713 if (cm->max_channels == 4)
1714 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1715 else if (cm->max_channels == 6)
1716 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1717 else if (cm->max_channels == 8)
1718 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1721 mutex_unlock(&cm->open_mutex);
1722 if (cm->chip_version == 68) {
1723 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1724 SNDRV_PCM_RATE_96000;
1725 runtime->hw.rate_max = 96000;
1726 } else if (cm->chip_version == 55) {
1727 err = snd_pcm_hw_constraint_list(runtime, 0,
1728 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1731 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1732 runtime->hw.rate_max = 128000;
1734 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1738 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1740 struct cmipci *cm = snd_pcm_substream_chip(substream);
1741 struct snd_pcm_runtime *runtime = substream->runtime;
1744 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1746 if (cm->can_ac3_hw) {
1747 runtime->hw = snd_cmipci_playback_spdif;
1748 if (cm->chip_version >= 37) {
1749 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1750 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1753 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1754 SNDRV_PCM_RATE_96000;
1755 runtime->hw.rate_max = 96000;
1758 runtime->hw = snd_cmipci_playback_iec958_subframe;
1760 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1761 cm->dig_pcm_status = cm->dig_status;
1765 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1767 struct cmipci *cm = snd_pcm_substream_chip(substream);
1768 struct snd_pcm_runtime *runtime = substream->runtime;
1771 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1773 runtime->hw = snd_cmipci_capture_spdif;
1774 if (cm->can_96k && !(cm->chip_version == 68)) {
1775 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1776 SNDRV_PCM_RATE_96000;
1777 runtime->hw.rate_max = 96000;
1779 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1787 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1789 struct cmipci *cm = snd_pcm_substream_chip(substream);
1790 close_device_check(cm, CM_OPEN_PLAYBACK);
1794 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1796 struct cmipci *cm = snd_pcm_substream_chip(substream);
1797 close_device_check(cm, CM_OPEN_CAPTURE);
1801 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1803 struct cmipci *cm = snd_pcm_substream_chip(substream);
1804 close_device_check(cm, CM_OPEN_PLAYBACK2);
1805 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1809 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1811 struct cmipci *cm = snd_pcm_substream_chip(substream);
1812 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1816 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1818 struct cmipci *cm = snd_pcm_substream_chip(substream);
1819 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1827 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1828 .open = snd_cmipci_playback_open,
1829 .close = snd_cmipci_playback_close,
1830 .ioctl = snd_pcm_lib_ioctl,
1831 .hw_params = snd_cmipci_hw_params,
1832 .hw_free = snd_cmipci_playback_hw_free,
1833 .prepare = snd_cmipci_playback_prepare,
1834 .trigger = snd_cmipci_playback_trigger,
1835 .pointer = snd_cmipci_playback_pointer,
1838 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1839 .open = snd_cmipci_capture_open,
1840 .close = snd_cmipci_capture_close,
1841 .ioctl = snd_pcm_lib_ioctl,
1842 .hw_params = snd_cmipci_hw_params,
1843 .hw_free = snd_cmipci_hw_free,
1844 .prepare = snd_cmipci_capture_prepare,
1845 .trigger = snd_cmipci_capture_trigger,
1846 .pointer = snd_cmipci_capture_pointer,
1849 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1850 .open = snd_cmipci_playback2_open,
1851 .close = snd_cmipci_playback2_close,
1852 .ioctl = snd_pcm_lib_ioctl,
1853 .hw_params = snd_cmipci_playback2_hw_params,
1854 .hw_free = snd_cmipci_playback2_hw_free,
1855 .prepare = snd_cmipci_capture_prepare, /* channel B */
1856 .trigger = snd_cmipci_capture_trigger, /* channel B */
1857 .pointer = snd_cmipci_capture_pointer, /* channel B */
1860 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1861 .open = snd_cmipci_playback_spdif_open,
1862 .close = snd_cmipci_playback_spdif_close,
1863 .ioctl = snd_pcm_lib_ioctl,
1864 .hw_params = snd_cmipci_hw_params,
1865 .hw_free = snd_cmipci_playback_hw_free,
1866 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1867 .trigger = snd_cmipci_playback_trigger,
1868 .pointer = snd_cmipci_playback_pointer,
1871 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1872 .open = snd_cmipci_capture_spdif_open,
1873 .close = snd_cmipci_capture_spdif_close,
1874 .ioctl = snd_pcm_lib_ioctl,
1875 .hw_params = snd_cmipci_hw_params,
1876 .hw_free = snd_cmipci_capture_spdif_hw_free,
1877 .prepare = snd_cmipci_capture_spdif_prepare,
1878 .trigger = snd_cmipci_capture_trigger,
1879 .pointer = snd_cmipci_capture_pointer,
1886 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1888 struct snd_pcm *pcm;
1891 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1895 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1896 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1898 pcm->private_data = cm;
1899 pcm->info_flags = 0;
1900 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1903 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1904 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1909 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1911 struct snd_pcm *pcm;
1914 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1918 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1920 pcm->private_data = cm;
1921 pcm->info_flags = 0;
1922 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1925 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1926 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1931 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1933 struct snd_pcm *pcm;
1936 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1940 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1941 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1943 pcm->private_data = cm;
1944 pcm->info_flags = 0;
1945 strcpy(pcm->name, "C-Media PCI IEC958");
1946 cm->pcm_spdif = pcm;
1948 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1949 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1956 * - CM8338/8738 has a compatible mixer interface with SB16, but
1957 * lack of some elements like tone control, i/o gain and AGC.
1958 * - Access to native registers:
1960 * - Output mute switches
1963 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1965 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1966 outb(data, s->iobase + CM_REG_SB16_DATA);
1969 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1973 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1974 v = inb(s->iobase + CM_REG_SB16_DATA);
1979 * general mixer element
1981 struct cmipci_sb_reg {
1982 unsigned int left_reg, right_reg;
1983 unsigned int left_shift, right_shift;
1985 unsigned int invert: 1;
1986 unsigned int stereo: 1;
1989 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1990 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1992 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1993 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1994 .info = snd_cmipci_info_volume, \
1995 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1996 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1999 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2000 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2001 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2002 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2004 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2006 r->left_reg = val & 0xff;
2007 r->right_reg = (val >> 8) & 0xff;
2008 r->left_shift = (val >> 16) & 0x07;
2009 r->right_shift = (val >> 19) & 0x07;
2010 r->invert = (val >> 22) & 1;
2011 r->stereo = (val >> 23) & 1;
2012 r->mask = (val >> 24) & 0xff;
2015 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2016 struct snd_ctl_elem_info *uinfo)
2018 struct cmipci_sb_reg reg;
2020 cmipci_sb_reg_decode(®, kcontrol->private_value);
2021 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2022 uinfo->count = reg.stereo + 1;
2023 uinfo->value.integer.min = 0;
2024 uinfo->value.integer.max = reg.mask;
2028 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2029 struct snd_ctl_elem_value *ucontrol)
2031 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2032 struct cmipci_sb_reg reg;
2035 cmipci_sb_reg_decode(®, kcontrol->private_value);
2036 spin_lock_irq(&cm->reg_lock);
2037 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2039 val = reg.mask - val;
2040 ucontrol->value.integer.value[0] = val;
2042 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2044 val = reg.mask - val;
2045 ucontrol->value.integer.value[1] = val;
2047 spin_unlock_irq(&cm->reg_lock);
2051 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2052 struct snd_ctl_elem_value *ucontrol)
2054 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2055 struct cmipci_sb_reg reg;
2057 int left, right, oleft, oright;
2059 cmipci_sb_reg_decode(®, kcontrol->private_value);
2060 left = ucontrol->value.integer.value[0] & reg.mask;
2062 left = reg.mask - left;
2063 left <<= reg.left_shift;
2065 right = ucontrol->value.integer.value[1] & reg.mask;
2067 right = reg.mask - right;
2068 right <<= reg.right_shift;
2071 spin_lock_irq(&cm->reg_lock);
2072 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2073 left |= oleft & ~(reg.mask << reg.left_shift);
2074 change = left != oleft;
2076 if (reg.left_reg != reg.right_reg) {
2077 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2078 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2081 right |= oright & ~(reg.mask << reg.right_shift);
2082 change |= right != oright;
2083 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2085 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2086 spin_unlock_irq(&cm->reg_lock);
2091 * input route (left,right) -> (left,right)
2093 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2094 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2095 .info = snd_cmipci_info_input_sw, \
2096 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2097 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2100 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2101 struct snd_ctl_elem_info *uinfo)
2103 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2105 uinfo->value.integer.min = 0;
2106 uinfo->value.integer.max = 1;
2110 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2111 struct snd_ctl_elem_value *ucontrol)
2113 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2114 struct cmipci_sb_reg reg;
2117 cmipci_sb_reg_decode(®, kcontrol->private_value);
2118 spin_lock_irq(&cm->reg_lock);
2119 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2120 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2121 spin_unlock_irq(&cm->reg_lock);
2122 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2123 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2124 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2125 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2129 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2130 struct snd_ctl_elem_value *ucontrol)
2132 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2133 struct cmipci_sb_reg reg;
2135 int val1, val2, oval1, oval2;
2137 cmipci_sb_reg_decode(®, kcontrol->private_value);
2138 spin_lock_irq(&cm->reg_lock);
2139 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2140 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2141 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2142 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2143 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2144 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2145 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2146 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2147 change = val1 != oval1 || val2 != oval2;
2148 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2149 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2150 spin_unlock_irq(&cm->reg_lock);
2155 * native mixer switches/volumes
2158 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2159 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2160 .info = snd_cmipci_info_native_mixer, \
2161 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2162 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2165 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2166 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2167 .info = snd_cmipci_info_native_mixer, \
2168 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2169 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2172 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2173 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2174 .info = snd_cmipci_info_native_mixer, \
2175 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2176 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2179 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2180 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2181 .info = snd_cmipci_info_native_mixer, \
2182 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2183 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2186 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2187 struct snd_ctl_elem_info *uinfo)
2189 struct cmipci_sb_reg reg;
2191 cmipci_sb_reg_decode(®, kcontrol->private_value);
2192 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2193 uinfo->count = reg.stereo + 1;
2194 uinfo->value.integer.min = 0;
2195 uinfo->value.integer.max = reg.mask;
2200 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2201 struct snd_ctl_elem_value *ucontrol)
2203 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2204 struct cmipci_sb_reg reg;
2205 unsigned char oreg, val;
2207 cmipci_sb_reg_decode(®, kcontrol->private_value);
2208 spin_lock_irq(&cm->reg_lock);
2209 oreg = inb(cm->iobase + reg.left_reg);
2210 val = (oreg >> reg.left_shift) & reg.mask;
2212 val = reg.mask - val;
2213 ucontrol->value.integer.value[0] = val;
2215 val = (oreg >> reg.right_shift) & reg.mask;
2217 val = reg.mask - val;
2218 ucontrol->value.integer.value[1] = val;
2220 spin_unlock_irq(&cm->reg_lock);
2224 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2225 struct snd_ctl_elem_value *ucontrol)
2227 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2228 struct cmipci_sb_reg reg;
2229 unsigned char oreg, nreg, val;
2231 cmipci_sb_reg_decode(®, kcontrol->private_value);
2232 spin_lock_irq(&cm->reg_lock);
2233 oreg = inb(cm->iobase + reg.left_reg);
2234 val = ucontrol->value.integer.value[0] & reg.mask;
2236 val = reg.mask - val;
2237 nreg = oreg & ~(reg.mask << reg.left_shift);
2238 nreg |= (val << reg.left_shift);
2240 val = ucontrol->value.integer.value[1] & reg.mask;
2242 val = reg.mask - val;
2243 nreg &= ~(reg.mask << reg.right_shift);
2244 nreg |= (val << reg.right_shift);
2246 outb(nreg, cm->iobase + reg.left_reg);
2247 spin_unlock_irq(&cm->reg_lock);
2248 return (nreg != oreg);
2252 * special case - check mixer sensitivity
2254 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2255 struct snd_ctl_elem_value *ucontrol)
2257 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2258 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2261 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_value *ucontrol)
2264 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2265 if (cm->mixer_insensitive) {
2269 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2273 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2274 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2275 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2276 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2277 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2278 { /* switch with sensitivity */
2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2280 .name = "PCM Playback Switch",
2281 .info = snd_cmipci_info_native_mixer,
2282 .get = snd_cmipci_get_native_mixer_sensitive,
2283 .put = snd_cmipci_put_native_mixer_sensitive,
2284 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2286 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2287 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2288 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2289 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2290 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2291 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2292 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2293 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2294 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2295 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2296 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2297 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2298 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2299 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2300 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2301 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2302 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2303 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2304 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2305 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2306 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2307 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2308 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2315 struct cmipci_switch_args {
2316 int reg; /* register index */
2317 unsigned int mask; /* mask bits */
2318 unsigned int mask_on; /* mask bits to turn on */
2319 unsigned int is_byte: 1; /* byte access? */
2320 unsigned int ac3_sensitive: 1; /* access forbidden during
2321 * non-audio operation?
2325 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2327 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2328 struct snd_ctl_elem_value *ucontrol,
2329 struct cmipci_switch_args *args)
2332 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2334 spin_lock_irq(&cm->reg_lock);
2335 if (args->ac3_sensitive && cm->mixer_insensitive) {
2336 ucontrol->value.integer.value[0] = 0;
2337 spin_unlock_irq(&cm->reg_lock);
2341 val = inb(cm->iobase + args->reg);
2343 val = snd_cmipci_read(cm, args->reg);
2344 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2345 spin_unlock_irq(&cm->reg_lock);
2349 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2350 struct snd_ctl_elem_value *ucontrol)
2352 struct cmipci_switch_args *args;
2353 args = (struct cmipci_switch_args *)kcontrol->private_value;
2354 snd_assert(args != NULL, return -EINVAL);
2355 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2358 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2359 struct snd_ctl_elem_value *ucontrol,
2360 struct cmipci_switch_args *args)
2364 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2366 spin_lock_irq(&cm->reg_lock);
2367 if (args->ac3_sensitive && cm->mixer_insensitive) {
2369 spin_unlock_irq(&cm->reg_lock);
2373 val = inb(cm->iobase + args->reg);
2375 val = snd_cmipci_read(cm, args->reg);
2376 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2377 args->mask_on : (args->mask & ~args->mask_on));
2380 if (ucontrol->value.integer.value[0])
2381 val |= args->mask_on;
2383 val |= (args->mask & ~args->mask_on);
2385 outb((unsigned char)val, cm->iobase + args->reg);
2387 snd_cmipci_write(cm, args->reg, val);
2389 spin_unlock_irq(&cm->reg_lock);
2393 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2394 struct snd_ctl_elem_value *ucontrol)
2396 struct cmipci_switch_args *args;
2397 args = (struct cmipci_switch_args *)kcontrol->private_value;
2398 snd_assert(args != NULL, return -EINVAL);
2399 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2402 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2403 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2406 .mask_on = xmask_on, \
2407 .is_byte = xis_byte, \
2408 .ac3_sensitive = xac3, \
2411 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2412 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2414 #if 0 /* these will be controlled in pcm device */
2415 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2418 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2419 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2420 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2421 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2422 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2423 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2424 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2425 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2426 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2427 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2428 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2429 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2430 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2431 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2433 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2435 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2437 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2438 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2439 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2440 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2441 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2443 #define DEFINE_SWITCH(sname, stype, sarg) \
2446 .info = snd_cmipci_uswitch_info, \
2447 .get = snd_cmipci_uswitch_get, \
2448 .put = snd_cmipci_uswitch_put, \
2449 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2452 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2453 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2457 * callbacks for spdif output switch
2458 * needs toggle two registers..
2460 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2461 struct snd_ctl_elem_value *ucontrol)
2464 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2465 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2469 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2470 struct snd_ctl_elem_value *ucontrol)
2472 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2474 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2475 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2477 if (ucontrol->value.integer.value[0]) {
2478 if (chip->spdif_playback_avail)
2479 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2481 if (chip->spdif_playback_avail)
2482 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2485 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2490 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2491 struct snd_ctl_elem_info *uinfo)
2493 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2494 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2495 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2497 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2498 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2499 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2500 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2504 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2507 if (cm->chip_version >= 39) {
2508 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2509 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2512 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2513 if (val & CM_REAR2LIN)
2518 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2519 struct snd_ctl_elem_value *ucontrol)
2521 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2523 spin_lock_irq(&cm->reg_lock);
2524 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2525 spin_unlock_irq(&cm->reg_lock);
2529 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2530 struct snd_ctl_elem_value *ucontrol)
2532 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2535 spin_lock_irq(&cm->reg_lock);
2536 if (ucontrol->value.enumerated.item[0] == 2)
2537 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2539 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2540 if (ucontrol->value.enumerated.item[0] == 1)
2541 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2543 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2544 spin_unlock_irq(&cm->reg_lock);
2548 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2549 struct snd_ctl_elem_info *uinfo)
2551 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2552 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2554 uinfo->value.enumerated.items = 2;
2555 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2556 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2557 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2561 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_value *ucontrol)
2564 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2565 /* same bit as spdi_phase */
2566 spin_lock_irq(&cm->reg_lock);
2567 ucontrol->value.enumerated.item[0] =
2568 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2569 spin_unlock_irq(&cm->reg_lock);
2573 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2574 struct snd_ctl_elem_value *ucontrol)
2576 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2579 spin_lock_irq(&cm->reg_lock);
2580 if (ucontrol->value.enumerated.item[0])
2581 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2583 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2584 spin_unlock_irq(&cm->reg_lock);
2588 /* both for CM8338/8738 */
2589 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2590 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2592 .name = "Line-In Mode",
2593 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2594 .info = snd_cmipci_line_in_mode_info,
2595 .get = snd_cmipci_line_in_mode_get,
2596 .put = snd_cmipci_line_in_mode_put,
2600 /* for non-multichannel chips */
2601 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2602 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2604 /* only for CM8738 */
2605 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2606 #if 0 /* controlled in pcm device */
2607 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2608 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2609 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2611 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2612 { .name = "IEC958 Output Switch",
2613 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2614 .info = snd_cmipci_uswitch_info,
2615 .get = snd_cmipci_spdout_enable_get,
2616 .put = snd_cmipci_spdout_enable_put,
2618 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2619 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2620 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2621 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2622 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2623 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2626 /* only for model 033/037 */
2627 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2628 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2629 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2630 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2633 /* only for model 039 or later */
2634 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2635 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2636 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2638 .name = "Mic-In Mode",
2639 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2640 .info = snd_cmipci_mic_in_mode_info,
2641 .get = snd_cmipci_mic_in_mode_get,
2642 .put = snd_cmipci_mic_in_mode_put,
2646 /* card control switches */
2647 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2648 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2649 DEFINE_CARD_SWITCH("Modem", modem),
2653 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2655 struct snd_card *card;
2656 struct snd_kcontrol_new *sw;
2657 struct snd_kcontrol *kctl;
2661 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2665 strcpy(card->mixername, "CMedia PCI");
2667 spin_lock_irq(&cm->reg_lock);
2668 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2669 spin_unlock_irq(&cm->reg_lock);
2671 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2672 if (cm->chip_version == 68) { // 8768 has no PCM volume
2673 if (!strcmp(snd_cmipci_mixers[idx].name,
2674 "PCM Playback Volume"))
2677 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2681 /* mixer switches */
2682 sw = snd_cmipci_mixer_switches;
2683 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2684 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2688 if (! cm->can_multi_ch) {
2689 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2693 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2694 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2695 sw = snd_cmipci_8738_mixer_switches;
2696 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2697 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2701 if (cm->can_ac3_hw) {
2702 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2704 kctl->id.device = pcm_spdif_device;
2705 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2707 kctl->id.device = pcm_spdif_device;
2708 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2710 kctl->id.device = pcm_spdif_device;
2712 if (cm->chip_version <= 37) {
2713 sw = snd_cmipci_old_mixer_switches;
2714 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2715 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2721 if (cm->chip_version >= 39) {
2722 sw = snd_cmipci_extra_mixer_switches;
2723 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2724 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2731 sw = snd_cmipci_control_switches;
2732 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2733 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2738 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2739 struct snd_ctl_elem_id id;
2740 struct snd_kcontrol *ctl;
2741 memset(&id, 0, sizeof(id));
2742 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2743 strcpy(id.name, cm_saved_mixer[idx].name);
2744 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2745 cm->mixer_res_ctl[idx] = ctl;
2756 #ifdef CONFIG_PROC_FS
2757 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2758 struct snd_info_buffer *buffer)
2760 struct cmipci *cm = entry->private_data;
2763 snd_iprintf(buffer, "%s\n", cm->card->longname);
2764 for (i = 0; i < 0x94; i++) {
2767 v = inb(cm->iobase + i);
2769 snd_iprintf(buffer, "\n%02x:", i);
2770 snd_iprintf(buffer, " %02x", v);
2772 snd_iprintf(buffer, "\n");
2775 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2777 struct snd_info_entry *entry;
2779 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2780 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2782 #else /* !CONFIG_PROC_FS */
2783 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2787 static struct pci_device_id snd_cmipci_ids[] = {
2788 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2789 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2790 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2791 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2792 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2798 * check chip version and capabilities
2799 * driver name is modified according to the chip model
2801 static void __devinit query_chip(struct cmipci *cm)
2803 unsigned int detect;
2805 /* check reg 0Ch, bit 24-31 */
2806 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2808 /* check reg 08h, bit 24-28 */
2809 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2812 cm->chip_version = 33;
2813 if (cm->do_soft_ac3)
2819 cm->chip_version = 37;
2823 cm->chip_version = 39;
2827 cm->max_channels = 2;
2829 if (detect & CM_CHIP_039) {
2830 cm->chip_version = 39;
2831 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2832 cm->max_channels = 6;
2834 cm->max_channels = 4;
2835 } else if (detect & CM_CHIP_8768) {
2836 cm->chip_version = 68;
2837 cm->max_channels = 8;
2840 cm->chip_version = 55;
2841 cm->max_channels = 6;
2845 cm->can_multi_ch = 1;
2849 #ifdef SUPPORT_JOYSTICK
2850 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2852 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2853 struct gameport *gp;
2854 struct resource *r = NULL;
2857 if (joystick_port[dev] == 0)
2860 if (joystick_port[dev] == 1) { /* auto-detect */
2861 for (i = 0; ports[i]; i++) {
2863 r = request_region(io_port, 1, "CMIPCI gameport");
2868 io_port = joystick_port[dev];
2869 r = request_region(io_port, 1, "CMIPCI gameport");
2873 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2877 cm->gameport = gp = gameport_allocate_port();
2879 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2880 release_and_free_resource(r);
2883 gameport_set_name(gp, "C-Media Gameport");
2884 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2885 gameport_set_dev_parent(gp, &cm->pci->dev);
2887 gameport_set_port_data(gp, r);
2889 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2891 gameport_register_port(cm->gameport);
2896 static void snd_cmipci_free_gameport(struct cmipci *cm)
2899 struct resource *r = gameport_get_port_data(cm->gameport);
2901 gameport_unregister_port(cm->gameport);
2902 cm->gameport = NULL;
2904 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2905 release_and_free_resource(r);
2909 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2910 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2913 static int snd_cmipci_free(struct cmipci *cm)
2916 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2917 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2918 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2919 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2920 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2921 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2922 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2925 snd_cmipci_mixer_write(cm, 0, 0);
2927 synchronize_irq(cm->irq);
2929 free_irq(cm->irq, cm);
2932 snd_cmipci_free_gameport(cm);
2933 pci_release_regions(cm->pci);
2934 pci_disable_device(cm->pci);
2939 static int snd_cmipci_dev_free(struct snd_device *device)
2941 struct cmipci *cm = device->device_data;
2942 return snd_cmipci_free(cm);
2945 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2949 struct snd_opl3 *opl3;
2955 if (cm->chip_version >= 39) {
2956 /* first try FM regs in PCI port range */
2957 iosynth = cm->iobase + CM_REG_FM_PCI;
2958 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2959 OPL3_HW_OPL3, 1, &opl3);
2964 /* then try legacy ports */
2965 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2968 case 0x3E8: val |= CM_FMSEL_3E8; break;
2969 case 0x3E0: val |= CM_FMSEL_3E0; break;
2970 case 0x3C8: val |= CM_FMSEL_3C8; break;
2971 case 0x388: val |= CM_FMSEL_388; break;
2975 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2977 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2979 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2980 OPL3_HW_OPL3, 0, &opl3) < 0) {
2981 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2982 "skipping...\n", iosynth);
2986 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2987 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2993 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2994 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2998 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2999 int dev, struct cmipci **rcmipci)
3003 static struct snd_device_ops ops = {
3004 .dev_free = snd_cmipci_dev_free,
3008 int integrated_midi = 0;
3010 int pcm_index, pcm_spdif_index;
3011 static struct pci_device_id intel_82437vx[] = {
3012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3018 if ((err = pci_enable_device(pci)) < 0)
3021 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3023 pci_disable_device(pci);
3027 spin_lock_init(&cm->reg_lock);
3028 mutex_init(&cm->open_mutex);
3029 cm->device = pci->device;
3033 cm->channel[0].ch = 0;
3034 cm->channel[1].ch = 1;
3035 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3037 if ((err = pci_request_regions(pci, card->driver)) < 0) {
3039 pci_disable_device(pci);
3042 cm->iobase = pci_resource_start(pci, 0);
3044 if (request_irq(pci->irq, snd_cmipci_interrupt,
3045 IRQF_SHARED, card->driver, cm)) {
3046 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3047 snd_cmipci_free(cm);
3052 pci_set_master(cm->pci);
3055 * check chip version, max channels and capabilities
3058 cm->chip_version = 0;
3059 cm->max_channels = 2;
3060 cm->do_soft_ac3 = soft_ac3[dev];
3062 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3063 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3065 /* added -MCx suffix for chip supporting multi-channels */
3066 if (cm->can_multi_ch)
3067 sprintf(cm->card->driver + strlen(cm->card->driver),
3068 "-MC%d", cm->max_channels);
3069 else if (cm->can_ac3_sw)
3070 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3072 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3073 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3076 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3078 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3081 /* initialize codec registers */
3082 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3083 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3084 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3085 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3086 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3087 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3088 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3090 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3091 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3093 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3095 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3097 if (cm->chip_version) {
3098 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3099 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3101 /* Set Bus Master Request */
3102 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3104 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3105 switch (pci->device) {
3106 case PCI_DEVICE_ID_CMEDIA_CM8738:
3107 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3108 if (!pci_dev_present(intel_82437vx))
3109 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3115 if (cm->chip_version < 68) {
3116 val = pci->device < 0x110 ? 8338 : 8738;
3118 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3126 switch ((pci->subsystem_vendor << 16) |
3127 pci->subsystem_device) {
3142 sprintf(card->shortname, "C-Media CMI%d", val);
3143 if (cm->chip_version < 68)
3144 sprintf(modelstr, " (model %d)", cm->chip_version);
3147 sprintf(card->longname, "%s%s at %#lx, irq %i",
3148 card->shortname, modelstr, cm->iobase, cm->irq);
3150 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3151 snd_cmipci_free(cm);
3155 if (cm->chip_version >= 39) {
3156 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3157 if (val != 0x00 && val != 0xff) {
3158 iomidi = cm->iobase + CM_REG_MPU_PCI;
3159 integrated_midi = 1;
3162 if (!integrated_midi) {
3164 iomidi = mpu_port[dev];
3166 case 0x320: val = CM_VMPU_320; break;
3167 case 0x310: val = CM_VMPU_310; break;
3168 case 0x300: val = CM_VMPU_300; break;
3169 case 0x330: val = CM_VMPU_330; break;
3174 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3176 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3177 if (inb(iomidi + 1) == 0xff) {
3178 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3179 " at %#lx\n", iomidi);
3180 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3187 if (cm->chip_version < 68) {
3188 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3194 snd_cmipci_mixer_write(cm, 0, 0);
3196 snd_cmipci_proc_init(cm);
3198 /* create pcm devices */
3199 pcm_index = pcm_spdif_index = 0;
3200 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3203 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3206 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3207 pcm_spdif_index = pcm_index;
3208 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3212 /* create mixer interface & switches */
3213 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3217 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3220 MPU401_INFO_INTEGRATED : 0),
3221 cm->irq, 0, &cm->rmidi)) < 0) {
3222 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3226 #ifdef USE_VAR48KRATE
3227 for (val = 0; val < ARRAY_SIZE(rates); val++)
3228 snd_cmipci_set_pll(cm, rates[val], val);
3231 * (Re-)Enable external switch spdo_48k
3233 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3234 #endif /* USE_VAR48KRATE */
3236 if (snd_cmipci_create_gameport(cm, dev) < 0)
3237 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3239 snd_card_set_dev(card, &pci->dev);
3248 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3250 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3251 const struct pci_device_id *pci_id)
3254 struct snd_card *card;
3258 if (dev >= SNDRV_CARDS)
3260 if (! enable[dev]) {
3265 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3269 switch (pci->device) {
3270 case PCI_DEVICE_ID_CMEDIA_CM8738:
3271 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3272 strcpy(card->driver, "CMI8738");
3274 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3275 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3276 strcpy(card->driver, "CMI8338");
3279 strcpy(card->driver, "CMIPCI");
3283 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3284 snd_card_free(card);
3287 card->private_data = cm;
3289 if ((err = snd_card_register(card)) < 0) {
3290 snd_card_free(card);
3293 pci_set_drvdata(pci, card);
3299 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3301 snd_card_free(pci_get_drvdata(pci));
3302 pci_set_drvdata(pci, NULL);
3310 static unsigned char saved_regs[] = {
3311 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3312 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3313 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3314 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3315 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3318 static unsigned char saved_mixers[] = {
3319 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3320 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3321 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3322 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3323 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3324 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3325 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3326 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3329 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3331 struct snd_card *card = pci_get_drvdata(pci);
3332 struct cmipci *cm = card->private_data;
3335 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3337 snd_pcm_suspend_all(cm->pcm);
3338 snd_pcm_suspend_all(cm->pcm2);
3339 snd_pcm_suspend_all(cm->pcm_spdif);
3341 /* save registers */
3342 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3343 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3344 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3345 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3348 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3350 pci_disable_device(pci);
3351 pci_save_state(pci);
3352 pci_set_power_state(pci, pci_choose_state(pci, state));
3356 static int snd_cmipci_resume(struct pci_dev *pci)
3358 struct snd_card *card = pci_get_drvdata(pci);
3359 struct cmipci *cm = card->private_data;
3362 pci_set_power_state(pci, PCI_D0);
3363 pci_restore_state(pci);
3364 if (pci_enable_device(pci) < 0) {
3365 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3366 "disabling device\n");
3367 snd_card_disconnect(card);
3370 pci_set_master(pci);
3372 /* reset / initialize to a sane state */
3373 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3374 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3375 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3376 snd_cmipci_mixer_write(cm, 0, 0);
3378 /* restore registers */
3379 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3380 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3381 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3382 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3384 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3387 #endif /* CONFIG_PM */
3389 static struct pci_driver driver = {
3390 .name = "C-Media PCI",
3391 .id_table = snd_cmipci_ids,
3392 .probe = snd_cmipci_probe,
3393 .remove = __devexit_p(snd_cmipci_remove),
3395 .suspend = snd_cmipci_suspend,
3396 .resume = snd_cmipci_resume,
3400 static int __init alsa_card_cmipci_init(void)
3402 return pci_register_driver(&driver);
3405 static void __exit alsa_card_cmipci_exit(void)
3407 pci_unregister_driver(&driver);
3410 module_init(alsa_card_cmipci_init)
3411 module_exit(alsa_card_cmipci_exit)