2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Documentation: ARM DDI 0173B
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/ioport.h>
16 #include <linux/device.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/ac97_codec.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
32 #define DRIVER_NAME "aaci-pl041"
35 * PM support is not complete. Turn it off.
39 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
41 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
44 * Ensure that the slot 1/2 RX registers are empty.
46 v = readl(aaci->base + AACI_SLFR);
48 readl(aaci->base + AACI_SL2RX);
50 readl(aaci->base + AACI_SL1RX);
52 writel(maincr, aaci->base + AACI_MAINCR);
57 * The recommended use of programming the external codec through slot 1
58 * and slot 2 data is to use the channels during setup routines and the
59 * slot register at any other time. The data written into slot 1, slot 2
60 * and slot 12 registers is transmitted only when their corresponding
61 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
64 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
67 struct aaci *aaci = ac97->private_data;
74 mutex_lock(&aaci->ac97_sem);
76 aaci_ac97_select_codec(aaci, ac97);
79 * P54: You must ensure that AACI_SL2TX is always written
80 * to, if required, before data is written to AACI_SL1TX.
82 writel(val << 4, aaci->base + AACI_SL2TX);
83 writel(reg << 12, aaci->base + AACI_SL1TX);
86 * Wait for the transmission of both slots to complete.
89 v = readl(aaci->base + AACI_SLFR);
90 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
93 dev_err(&aaci->dev->dev,
94 "timeout waiting for write to complete\n");
96 mutex_unlock(&aaci->ac97_sem);
100 * Read an AC'97 register.
102 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
104 struct aaci *aaci = ac97->private_data;
112 mutex_lock(&aaci->ac97_sem);
114 aaci_ac97_select_codec(aaci, ac97);
117 * Write the register address to slot 1.
119 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
122 * Wait for the transmission to complete.
125 v = readl(aaci->base + AACI_SLFR);
126 } while ((v & SLFR_1TXB) && --timeout);
129 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
135 * Give the AC'97 codec more than enough time
136 * to respond. (42us = ~2 frames at 48kHz.)
141 * Wait for slot 2 to indicate data.
146 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
147 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
150 dev_err(&aaci->dev->dev, "timeout on RX valid\n");
156 v = readl(aaci->base + AACI_SL1RX) >> 12;
158 v = readl(aaci->base + AACI_SL2RX) >> 4;
160 } else if (--retries) {
161 dev_warn(&aaci->dev->dev,
162 "ac97 read back fail. retry\n");
165 dev_warn(&aaci->dev->dev,
166 "wrong ac97 register read back (%x != %x)\n",
172 mutex_unlock(&aaci->ac97_sem);
176 static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
182 val = readl(aacirun->base + AACI_SR);
183 } while (val & (SR_TXB|SR_RXB) && timeout--);
191 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
193 if (mask & ISR_ORINTR) {
194 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
195 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
198 if (mask & ISR_RXTOINTR) {
199 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
200 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
203 if (mask & ISR_RXINTR) {
204 struct aaci_runtime *aacirun = &aaci->capture;
207 if (!aacirun->substream || !aacirun->start) {
208 dev_warn(&aaci->dev->dev, "RX interrupt???\n");
209 writel(0, aacirun->base + AACI_IE);
215 unsigned int len = aacirun->fifosz;
218 if (aacirun->bytes <= 0) {
219 aacirun->bytes += aacirun->period;
221 spin_unlock(&aaci->lock);
222 snd_pcm_period_elapsed(aacirun->substream);
223 spin_lock(&aaci->lock);
225 if (!(aacirun->cr & CR_EN))
228 val = readl(aacirun->base + AACI_SR);
229 if (!(val & SR_RXHF))
231 if (!(val & SR_RXFF))
234 aacirun->bytes -= len;
236 /* reading 16 bytes at a time */
237 for( ; len > 0; len -= 16) {
239 "ldmia %1, {r0, r1, r2, r3}\n\t"
240 "stmia %0!, {r0, r1, r2, r3}"
242 : "r" (aacirun->fifo)
243 : "r0", "r1", "r2", "r3", "cc");
245 if (ptr >= aacirun->end)
246 ptr = aacirun->start;
252 if (mask & ISR_URINTR) {
253 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
254 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
257 if (mask & ISR_TXINTR) {
258 struct aaci_runtime *aacirun = &aaci->playback;
261 if (!aacirun->substream || !aacirun->start) {
262 dev_warn(&aaci->dev->dev, "TX interrupt???\n");
263 writel(0, aacirun->base + AACI_IE);
269 unsigned int len = aacirun->fifosz;
272 if (aacirun->bytes <= 0) {
273 aacirun->bytes += aacirun->period;
275 spin_unlock(&aaci->lock);
276 snd_pcm_period_elapsed(aacirun->substream);
277 spin_lock(&aaci->lock);
279 if (!(aacirun->cr & CR_EN))
282 val = readl(aacirun->base + AACI_SR);
283 if (!(val & SR_TXHE))
285 if (!(val & SR_TXFE))
288 aacirun->bytes -= len;
290 /* writing 16 bytes at a time */
291 for ( ; len > 0; len -= 16) {
293 "ldmia %0!, {r0, r1, r2, r3}\n\t"
294 "stmia %1, {r0, r1, r2, r3}"
296 : "r" (aacirun->fifo)
297 : "r0", "r1", "r2", "r3", "cc");
299 if (ptr >= aacirun->end)
300 ptr = aacirun->start;
308 static irqreturn_t aaci_irq(int irq, void *devid)
310 struct aaci *aaci = devid;
314 spin_lock(&aaci->lock);
315 mask = readl(aaci->base + AACI_ALLINTS);
318 for (i = 0; i < 4; i++, m >>= 7) {
320 aaci_fifo_irq(aaci, i, m);
324 spin_unlock(&aaci->lock);
326 return mask ? IRQ_HANDLED : IRQ_NONE;
336 unsigned char codec_idx;
337 unsigned char rate_idx;
340 static struct aaci_stream aaci_streams[] = {
343 .rate_idx = AC97_RATES_FRONT_DAC,
345 [ACSTREAM_SURROUND] = {
347 .rate_idx = AC97_RATES_SURR_DAC,
351 .rate_idx = AC97_RATES_LFE_DAC,
355 static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
357 struct aaci_stream *s = aaci_streams + streamid;
358 return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
361 static unsigned int rate_list[] = {
362 5512, 8000, 11025, 16000, 22050, 32000, 44100,
363 48000, 64000, 88200, 96000, 176400, 192000
367 * Double-rate rule: we can support double rate iff channels == 2
371 aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
373 struct aaci *aaci = rule->private;
374 unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
375 struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
379 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
381 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
383 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
386 return snd_interval_list(hw_param_interval(p, rule->var),
387 ARRAY_SIZE(rate_list), rate_list,
391 static struct snd_pcm_hardware aaci_hw_info = {
392 .info = SNDRV_PCM_INFO_MMAP |
393 SNDRV_PCM_INFO_MMAP_VALID |
394 SNDRV_PCM_INFO_INTERLEAVED |
395 SNDRV_PCM_INFO_BLOCK_TRANSFER |
396 SNDRV_PCM_INFO_RESUME,
399 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
400 * words. It also doesn't support 12-bit at all.
402 .formats = SNDRV_PCM_FMTBIT_S16_LE,
404 /* should this be continuous or knot? */
405 .rates = SNDRV_PCM_RATE_CONTINUOUS,
410 .buffer_bytes_max = 64 * 1024,
411 .period_bytes_min = 256,
412 .period_bytes_max = PAGE_SIZE,
414 .periods_max = PAGE_SIZE / 16,
417 static int __aaci_pcm_open(struct aaci *aaci,
418 struct snd_pcm_substream *substream,
419 struct aaci_runtime *aacirun)
421 struct snd_pcm_runtime *runtime = substream->runtime;
424 aacirun->substream = substream;
425 runtime->private_data = aacirun;
426 runtime->hw = aaci_hw_info;
429 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
430 * mode, each 32-bit word contains one sample. If we're in
431 * compact mode, each 32-bit word contains two samples, effectively
432 * halving the FIFO size. However, we don't know for sure which
433 * we'll be using at this point. We set this to the lower limit.
435 runtime->hw.fifo_size = aaci->fifosize * 2;
438 * Add rule describing hardware rate dependency
439 * on the number of channels.
441 ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
442 aaci_rule_rate_by_channels, aaci,
443 SNDRV_PCM_HW_PARAM_CHANNELS,
444 SNDRV_PCM_HW_PARAM_RATE, -1);
448 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
463 static int aaci_pcm_close(struct snd_pcm_substream *substream)
465 struct aaci *aaci = substream->private_data;
466 struct aaci_runtime *aacirun = substream->runtime->private_data;
468 WARN_ON(aacirun->cr & CR_EN);
470 aacirun->substream = NULL;
471 free_irq(aaci->dev->irq[0], aaci);
476 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
478 struct aaci_runtime *aacirun = substream->runtime->private_data;
481 * This must not be called with the device enabled.
483 WARN_ON(aacirun->cr & CR_EN);
485 if (aacirun->pcm_open)
486 snd_ac97_pcm_close(aacirun->pcm);
487 aacirun->pcm_open = 0;
490 * Clear out the DMA and any allocated buffers.
492 devdma_hw_free(NULL, substream);
497 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
498 struct aaci_runtime *aacirun,
499 struct snd_pcm_hw_params *params)
503 aaci_pcm_hw_free(substream);
504 if (aacirun->pcm_open) {
505 snd_ac97_pcm_close(aacirun->pcm);
506 aacirun->pcm_open = 0;
509 err = devdma_hw_alloc(NULL, substream,
510 params_buffer_bytes(params));
514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
515 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
516 params_channels(params),
517 aacirun->pcm->r[0].slots);
519 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
520 params_channels(params),
521 aacirun->pcm->r[0].slots);
526 aacirun->pcm_open = 1;
532 static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
534 struct snd_pcm_runtime *runtime = substream->runtime;
535 struct aaci_runtime *aacirun = runtime->private_data;
537 aacirun->start = (void *)runtime->dma_area;
538 aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
539 aacirun->ptr = aacirun->start;
541 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
546 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
548 struct snd_pcm_runtime *runtime = substream->runtime;
549 struct aaci_runtime *aacirun = runtime->private_data;
550 ssize_t bytes = aacirun->ptr - aacirun->start;
552 return bytes_to_frames(runtime, bytes);
555 static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
557 return devdma_mmap(NULL, substream, vma);
562 * Playback specific ALSA stuff
564 static const u32 channels_to_txmask[] = {
565 [2] = CR_SL3 | CR_SL4,
566 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
567 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
571 * We can support two and four channel audio. Unfortunately
572 * six channel audio requires a non-standard channel ordering:
574 * 4 -> FL(3), FR(4), SL(7), SR(8)
575 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
576 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
577 * This requires an ALSA configuration file to correct.
579 static unsigned int channel_list[] = { 2, 4, 6 };
582 aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
584 struct aaci *aaci = rule->private;
585 unsigned int chan_mask = 1 << 0, slots;
588 * pcms[0] is the our 5.1 PCM instance.
590 slots = aaci->ac97_bus->pcms[0].r[0].slots;
591 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
593 if (slots & (1 << AC97_SLOT_LFE))
597 return snd_interval_list(hw_param_interval(p, rule->var),
598 ARRAY_SIZE(channel_list), channel_list,
602 static int aaci_pcm_open(struct snd_pcm_substream *substream)
604 struct aaci *aaci = substream->private_data;
608 * Add rule describing channel dependency.
610 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
611 SNDRV_PCM_HW_PARAM_CHANNELS,
612 aaci_rule_channels, aaci,
613 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
617 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
618 ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
620 ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
625 static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
626 struct snd_pcm_hw_params *params)
628 struct aaci *aaci = substream->private_data;
629 struct aaci_runtime *aacirun = substream->runtime->private_data;
630 unsigned int channels = params_channels(params);
633 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
634 !channels_to_txmask[channels]);
636 ret = aaci_pcm_hw_params(substream, aacirun, params);
639 * Enable FIFO, compact mode, 16 bits per sample.
640 * FIXME: double rate slots?
643 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
644 aacirun->cr |= channels_to_txmask[channels];
646 aacirun->fifosz = aaci->fifosize * 4;
647 if (aacirun->cr & CR_COMPACT)
648 aacirun->fifosz >>= 1;
653 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
657 ie = readl(aacirun->base + AACI_IE);
658 ie &= ~(IE_URIE|IE_TXIE);
659 writel(ie, aacirun->base + AACI_IE);
660 aacirun->cr &= ~CR_EN;
661 aaci_chan_wait_ready(aacirun);
662 writel(aacirun->cr, aacirun->base + AACI_TXCR);
665 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
669 aaci_chan_wait_ready(aacirun);
670 aacirun->cr |= CR_EN;
672 ie = readl(aacirun->base + AACI_IE);
673 ie |= IE_URIE | IE_TXIE;
674 writel(ie, aacirun->base + AACI_IE);
675 writel(aacirun->cr, aacirun->base + AACI_TXCR);
678 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
680 struct aaci *aaci = substream->private_data;
681 struct aaci_runtime *aacirun = substream->runtime->private_data;
685 spin_lock_irqsave(&aaci->lock, flags);
687 case SNDRV_PCM_TRIGGER_START:
688 aaci_pcm_playback_start(aacirun);
691 case SNDRV_PCM_TRIGGER_RESUME:
692 aaci_pcm_playback_start(aacirun);
695 case SNDRV_PCM_TRIGGER_STOP:
696 aaci_pcm_playback_stop(aacirun);
699 case SNDRV_PCM_TRIGGER_SUSPEND:
700 aaci_pcm_playback_stop(aacirun);
703 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
706 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
712 spin_unlock_irqrestore(&aaci->lock, flags);
717 static struct snd_pcm_ops aaci_playback_ops = {
718 .open = aaci_pcm_open,
719 .close = aaci_pcm_close,
720 .ioctl = snd_pcm_lib_ioctl,
721 .hw_params = aaci_pcm_playback_hw_params,
722 .hw_free = aaci_pcm_hw_free,
723 .prepare = aaci_pcm_prepare,
724 .trigger = aaci_pcm_playback_trigger,
725 .pointer = aaci_pcm_pointer,
726 .mmap = aaci_pcm_mmap,
729 static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
730 struct snd_pcm_hw_params *params)
732 struct aaci *aaci = substream->private_data;
733 struct aaci_runtime *aacirun = substream->runtime->private_data;
736 ret = aaci_pcm_hw_params(substream, aacirun, params);
739 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
741 /* Line in record: slot 3 and 4 */
742 aacirun->cr |= CR_SL3 | CR_SL4;
744 aacirun->fifosz = aaci->fifosize * 4;
746 if (aacirun->cr & CR_COMPACT)
747 aacirun->fifosz >>= 1;
752 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
756 aaci_chan_wait_ready(aacirun);
758 ie = readl(aacirun->base + AACI_IE);
759 ie &= ~(IE_ORIE | IE_RXIE);
760 writel(ie, aacirun->base+AACI_IE);
762 aacirun->cr &= ~CR_EN;
764 writel(aacirun->cr, aacirun->base + AACI_RXCR);
767 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
771 aaci_chan_wait_ready(aacirun);
774 /* RX Timeout value: bits 28:17 in RXCR */
775 aacirun->cr |= 0xf << 17;
778 aacirun->cr |= CR_EN;
779 writel(aacirun->cr, aacirun->base + AACI_RXCR);
781 ie = readl(aacirun->base + AACI_IE);
782 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
783 writel(ie, aacirun->base + AACI_IE);
786 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
788 struct aaci *aaci = substream->private_data;
789 struct aaci_runtime *aacirun = substream->runtime->private_data;
793 spin_lock_irqsave(&aaci->lock, flags);
796 case SNDRV_PCM_TRIGGER_START:
797 aaci_pcm_capture_start(aacirun);
800 case SNDRV_PCM_TRIGGER_RESUME:
801 aaci_pcm_capture_start(aacirun);
804 case SNDRV_PCM_TRIGGER_STOP:
805 aaci_pcm_capture_stop(aacirun);
808 case SNDRV_PCM_TRIGGER_SUSPEND:
809 aaci_pcm_capture_stop(aacirun);
812 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
815 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
822 spin_unlock_irqrestore(&aaci->lock, flags);
827 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
829 struct snd_pcm_runtime *runtime = substream->runtime;
830 struct aaci *aaci = substream->private_data;
832 aaci_pcm_prepare(substream);
834 /* allow changing of sample rate */
835 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
836 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
837 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
839 /* Record select: Mic: 0, Aux: 3, Line: 4 */
840 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
845 static struct snd_pcm_ops aaci_capture_ops = {
846 .open = aaci_pcm_open,
847 .close = aaci_pcm_close,
848 .ioctl = snd_pcm_lib_ioctl,
849 .hw_params = aaci_pcm_capture_hw_params,
850 .hw_free = aaci_pcm_hw_free,
851 .prepare = aaci_pcm_capture_prepare,
852 .trigger = aaci_pcm_capture_trigger,
853 .pointer = aaci_pcm_pointer,
854 .mmap = aaci_pcm_mmap,
861 static int aaci_do_suspend(struct snd_card *card, unsigned int state)
863 struct aaci *aaci = card->private_data;
864 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
865 snd_pcm_suspend_all(aaci->pcm);
869 static int aaci_do_resume(struct snd_card *card, unsigned int state)
871 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
875 static int aaci_suspend(struct amba_device *dev, pm_message_t state)
877 struct snd_card *card = amba_get_drvdata(dev);
878 return card ? aaci_do_suspend(card) : 0;
881 static int aaci_resume(struct amba_device *dev)
883 struct snd_card *card = amba_get_drvdata(dev);
884 return card ? aaci_do_resume(card) : 0;
887 #define aaci_do_suspend NULL
888 #define aaci_do_resume NULL
889 #define aaci_suspend NULL
890 #define aaci_resume NULL
894 static struct ac97_pcm ac97_defs[] __devinitdata = {
895 [0] = { /* Front PCM */
899 .slots = (1 << AC97_SLOT_PCM_LEFT) |
900 (1 << AC97_SLOT_PCM_RIGHT) |
901 (1 << AC97_SLOT_PCM_CENTER) |
902 (1 << AC97_SLOT_PCM_SLEFT) |
903 (1 << AC97_SLOT_PCM_SRIGHT) |
904 (1 << AC97_SLOT_LFE),
913 .slots = (1 << AC97_SLOT_PCM_LEFT) |
914 (1 << AC97_SLOT_PCM_RIGHT),
923 .slots = (1 << AC97_SLOT_MIC),
929 static struct snd_ac97_bus_ops aaci_bus_ops = {
930 .write = aaci_ac97_write,
931 .read = aaci_ac97_read,
934 static int __devinit aaci_probe_ac97(struct aaci *aaci)
936 struct snd_ac97_template ac97_template;
937 struct snd_ac97_bus *ac97_bus;
938 struct snd_ac97 *ac97;
941 writel(0, aaci->base + AC97_POWERDOWN);
943 * Assert AACIRESET for 2us
945 writel(0, aaci->base + AACI_RESET);
947 writel(RESET_NRST, aaci->base + AACI_RESET);
950 * Give the AC'97 codec more than enough time
951 * to wake up. (42us = ~2 frames at 48kHz.)
955 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
959 ac97_bus->clock = 48000;
960 aaci->ac97_bus = ac97_bus;
962 memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
963 ac97_template.private_data = aaci;
964 ac97_template.num = 0;
965 ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
967 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
973 * Disable AC97 PC Beep input on audio codecs.
975 if (ac97_is_audio(ac97))
976 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
978 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
982 aaci->playback.pcm = &ac97_bus->pcms[0];
983 aaci->capture.pcm = &ac97_bus->pcms[1];
989 static void aaci_free_card(struct snd_card *card)
991 struct aaci *aaci = card->private_data;
996 static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
999 struct snd_card *card;
1002 err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
1003 THIS_MODULE, sizeof(struct aaci), &card);
1007 card->private_free = aaci_free_card;
1009 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
1010 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
1011 snprintf(card->longname, sizeof(card->longname),
1012 "%s at 0x%016llx, irq %d",
1013 card->shortname, (unsigned long long)dev->res.start,
1016 aaci = card->private_data;
1017 mutex_init(&aaci->ac97_sem);
1018 spin_lock_init(&aaci->lock);
1022 /* Set MAINCR to allow slot 1 and 2 data IO */
1023 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
1024 MAINCR_SL2RXEN | MAINCR_SL2TXEN;
1029 static int __devinit aaci_init_pcm(struct aaci *aaci)
1031 struct snd_pcm *pcm;
1034 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
1037 pcm->private_data = aaci;
1038 pcm->info_flags = 0;
1040 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
1042 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
1043 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
1049 static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
1051 struct aaci_runtime *aacirun = &aaci->playback;
1054 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
1056 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
1057 writel(0, aacirun->fifo);
1059 writel(0, aacirun->base + AACI_TXCR);
1062 * Re-initialise the AACI after the FIFO depth test, to
1063 * ensure that the FIFOs are empty. Unfortunately, merely
1064 * disabling the channel doesn't clear the FIFO.
1066 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
1067 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1070 * If we hit 4096, we failed. Go back to the specified
1079 static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
1084 ret = amba_request_regions(dev, NULL);
1088 aaci = aaci_init_card(dev);
1094 aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
1101 * Playback uses AACI channel 0
1103 aaci->playback.base = aaci->base + AACI_CSCH1;
1104 aaci->playback.fifo = aaci->base + AACI_DR1;
1107 * Capture uses AACI channel 0
1109 aaci->capture.base = aaci->base + AACI_CSCH1;
1110 aaci->capture.fifo = aaci->base + AACI_DR1;
1112 for (i = 0; i < 4; i++) {
1113 void __iomem *base = aaci->base + i * 0x14;
1115 writel(0, base + AACI_IE);
1116 writel(0, base + AACI_TXCR);
1117 writel(0, base + AACI_RXCR);
1120 writel(0x1fff, aaci->base + AACI_INTCLR);
1121 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1123 ret = aaci_probe_ac97(aaci);
1128 * Size the FIFOs (must be multiple of 16).
1130 aaci->fifosize = aaci_size_fifo(aaci);
1131 if (aaci->fifosize & 15) {
1132 printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
1138 ret = aaci_init_pcm(aaci);
1142 snd_card_set_dev(aaci->card, &dev->dev);
1144 ret = snd_card_register(aaci->card);
1146 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
1148 amba_set_drvdata(dev, aaci->card);
1154 snd_card_free(aaci->card);
1155 amba_release_regions(dev);
1159 static int __devexit aaci_remove(struct amba_device *dev)
1161 struct snd_card *card = amba_get_drvdata(dev);
1163 amba_set_drvdata(dev, NULL);
1166 struct aaci *aaci = card->private_data;
1167 writel(0, aaci->base + AACI_MAINCR);
1169 snd_card_free(card);
1170 amba_release_regions(dev);
1176 static struct amba_id aaci_ids[] = {
1184 static struct amba_driver aaci_driver = {
1186 .name = DRIVER_NAME,
1188 .probe = aaci_probe,
1189 .remove = __devexit_p(aaci_remove),
1190 .suspend = aaci_suspend,
1191 .resume = aaci_resume,
1192 .id_table = aaci_ids,
1195 static int __init aaci_init(void)
1197 return amba_driver_register(&aaci_driver);
1200 static void __exit aaci_exit(void)
1202 amba_driver_unregister(&aaci_driver);
1205 module_init(aaci_init);
1206 module_exit(aaci_exit);
1208 MODULE_LICENSE("GPL");
1209 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");