2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/list.h>
12 #include <linux/netdevice.h>
13 #include <linux/phy.h>
15 #include "mv88e6xxx.h"
18 * If the switch's ADDR[4:0] strap pins are strapped to zero, it will
19 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
20 * will be directly accessible on some {device address,register address}
21 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
22 * will only respond to SMI transactions to that specific address, and
23 * an indirect addressing mechanism needs to be used to access its
26 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
31 for (i = 0; i < 16; i++) {
32 ret = mdiobus_read(bus, sw_addr, 0);
36 if ((ret & 0x8000) == 0)
43 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
48 return mdiobus_read(bus, addr, reg);
51 * Wait for the bus to become free.
53 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
58 * Transmit the read command.
60 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
65 * Wait for the read command to complete.
67 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
74 ret = mdiobus_read(bus, sw_addr, 1);
81 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
83 struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
86 mutex_lock(&ps->smi_mutex);
87 ret = __mv88e6xxx_reg_read(ds->master_mii_bus,
88 ds->pd->sw_addr, addr, reg);
89 mutex_unlock(&ps->smi_mutex);
94 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
100 return mdiobus_write(bus, addr, reg, val);
103 * Wait for the bus to become free.
105 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
110 * Transmit the data to write.
112 ret = mdiobus_write(bus, sw_addr, 1, val);
117 * Transmit the write command.
119 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
124 * Wait for the write command to complete.
126 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
133 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
135 struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
138 mutex_lock(&ps->smi_mutex);
139 ret = __mv88e6xxx_reg_write(ds->master_mii_bus,
140 ds->pd->sw_addr, addr, reg, val);
141 mutex_unlock(&ps->smi_mutex);
146 int mv88e6xxx_config_prio(struct dsa_switch *ds)
149 * Configure the IP ToS mapping registers.
151 REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
152 REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
153 REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
154 REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
155 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
156 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
157 REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
158 REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
161 * Configure the IEEE 802.1p priority mapping register.
163 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
168 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
173 for (i = 0; i < 6; i++) {
177 * Write the MAC address byte.
179 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
182 * Wait for the write to complete.
184 for (j = 0; j < 16; j++) {
185 ret = REG_READ(REG_GLOBAL2, 0x0d);
186 if ((ret & 0x8000) == 0)
196 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
199 return mv88e6xxx_reg_read(ds, addr, regnum);
203 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
206 return mv88e6xxx_reg_write(ds, addr, regnum, val);
210 void mv88e6xxx_poll_link(struct dsa_switch *ds)
214 for (i = 0; i < DSA_MAX_PORTS; i++) {
215 struct net_device *dev;
227 if (dev->flags & IFF_UP) {
228 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
232 link = !!(port_status & 0x0800);
236 if (netif_carrier_ok(dev)) {
237 printk(KERN_INFO "%s: link down\n", dev->name);
238 netif_carrier_off(dev);
243 switch (port_status & 0x0300) {
257 duplex = (port_status & 0x0400) ? 1 : 0;
258 fc = (port_status & 0x8000) ? 1 : 0;
260 if (!netif_carrier_ok(dev)) {
261 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
262 "flow control %sabled\n", dev->name,
263 speed, duplex ? "full" : "half",
265 netif_carrier_on(dev);
270 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
275 for (i = 0; i < 10; i++) {
276 ret = REG_READ(REG_GLOBAL2, 0x1d);
277 if ((ret & 0x8000) == 0)
284 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
289 * Snapshot the hardware statistics counters for this port.
291 REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
294 * Wait for the snapshotting to complete.
296 ret = mv88e6xxx_stats_wait(ds);
303 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
310 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
314 ret = mv88e6xxx_stats_wait(ds);
318 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
324 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
331 void mv88e6xxx_get_strings(struct dsa_switch *ds,
332 int nr_stats, struct mv88e6xxx_hw_stat *stats,
333 int port, uint8_t *data)
337 for (i = 0; i < nr_stats; i++) {
338 memcpy(data + i * ETH_GSTRING_LEN,
339 stats[i].string, ETH_GSTRING_LEN);
343 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
344 int nr_stats, struct mv88e6xxx_hw_stat *stats,
345 int port, uint64_t *data)
347 struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
351 mutex_lock(&ps->stats_mutex);
353 ret = mv88e6xxx_stats_snapshot(ds, port);
355 mutex_unlock(&ps->stats_mutex);
360 * Read each of the counters.
362 for (i = 0; i < nr_stats; i++) {
363 struct mv88e6xxx_hw_stat *s = stats + i;
367 mv88e6xxx_stats_read(ds, s->reg, &low);
368 if (s->sizeof_stat == 8)
369 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
373 data[i] = (((u64)high) << 32) | low;
376 mutex_unlock(&ps->stats_mutex);