1 #ifndef __SOUND_EMU10K1_H
2 #define __SOUND_EMU10K1_H
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
7 * Definitions for EMU10K1 (SB Live!) chips
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <sound/pcm.h>
29 #include <sound/rawmidi.h>
30 #include <sound/hwdep.h>
31 #include <sound/ac97_codec.h>
32 #include <sound/util_mem.h>
33 #include <sound/pcm-indirect.h>
34 #include <sound/timer.h>
35 #include <linux/interrupt.h>
36 #include <linux/mutex.h>
39 /* ------------------- DEFINES -------------------- */
41 #define EMUPAGESIZE 4096
42 #define MAXREQVOICES 8
46 #define NUM_G 64 /* use all channels */
48 #define NUM_EFX_PLAYBACK 16
50 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
51 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
52 #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */
53 /* See ALSA bug #1276 - rlrevell */
55 #define TMEMSIZE 256*1024
58 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
60 // Audigy specify registers are prefixed with 'A_'
62 /************************************************************************************************/
63 /* PCI function 0 registers, address = <val> + PCIBASE0 */
64 /************************************************************************************************/
66 #define PTR 0x00 /* Indexed register set pointer register */
67 /* NOTE: The CHANNELNUM and ADDRESS words can */
68 /* be modified independently of each other. */
69 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
70 /* channel number of the register to be */
71 /* accessed. For non per-channel registers the */
72 /* value should be set to zero. */
73 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
74 #define A_PTR_ADDRESS_MASK 0x0fff0000
76 #define DATA 0x04 /* Indexed register set data register */
78 #define IPR 0x08 /* Global interrupt pending register */
79 /* Clear pending interrupts by writing a 1 to */
80 /* the relevant bits and zero to the other bits */
81 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
83 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
84 which INTE bits enable it) */
86 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
87 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
88 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
90 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
91 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
93 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
94 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
95 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
96 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
97 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
98 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
99 #define IPR_MUTE 0x00040000 /* Mute button pressed */
100 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
101 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
102 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
103 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
104 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
105 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
106 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
107 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
108 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
109 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
110 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
111 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
112 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
113 /* highest set channel in CLIPL, CLIPH, HLIPL, */
114 /* or HLIPH. When IP is written with CL set, */
115 /* the bit in H/CLIPL or H/CLIPH corresponding */
116 /* to the CIN value written will be cleared. */
118 #define INTE 0x0c /* Interrupt enable register */
119 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
120 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
121 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
122 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
123 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
124 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
125 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
126 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
127 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
128 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
129 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
130 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
131 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
132 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
133 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
134 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
135 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
136 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
138 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
139 /* NOTE: There is no reason to use this under */
140 /* Linux, and it will cause odd hardware */
141 /* behavior and possibly random segfaults and */
142 /* lockups if enabled. */
144 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
145 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
146 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
149 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
150 /* NOTE: This bit must always be enabled */
151 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
152 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
153 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
154 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
155 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
156 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
157 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
158 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
159 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
160 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
161 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
162 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
163 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
165 #define WC 0x10 /* Wall Clock register */
166 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
167 #define WC_SAMPLECOUNTER 0x14060010
168 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
169 /* NOTE: Each channel takes 1/64th of a sample */
170 /* period to be serviced. */
172 #define HCFG 0x14 /* Hardware config register */
173 /* NOTE: There is no reason to use the legacy */
174 /* SoundBlaster emulation stuff described below */
175 /* under Linux, and all kinds of weird hardware */
176 /* behavior can result if you try. Don't. */
177 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
178 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
179 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
180 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
181 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
182 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
183 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
184 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
185 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
186 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
187 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
188 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
189 /* NOTE: The rest of the bits in this register */
190 /* _are_ relevant under Linux. */
191 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
192 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
193 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
194 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
196 /* Specific to Alice2, CA0102 */
197 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
198 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
199 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
200 /* will automatically mute their output when */
201 /* they are not rate-locked to the external */
202 /* async audio source */
203 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
204 /* will automatically mute their output when */
205 /* the SPDIF V-bit indicates invalid audio */
206 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
207 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
208 /* 0x00000800 not used on Alice2 */
209 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
210 /* phase track the previous input. */
211 /* I2S0 can phase track the last S/PDIF input */
212 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
213 /* conversion for the corresponding */
214 /* I2S format input */
215 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
220 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
221 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
222 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
223 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
224 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
225 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
226 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
227 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
228 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
229 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
230 /* 1 = Force all 3 async digital inputs to use */
231 /* the same async sample rate tracker (ZVIDEO) */
232 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
233 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
234 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
235 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
236 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
237 /* will automatically mute their output when */
238 /* they are not rate-locked to the external */
239 /* async audio source */
240 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
241 /* NOTE: This should generally never be used. */
242 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
243 /* NOTE: This should generally never be used. */
244 #define HCFG_LOCKTANKCACHE 0x01020014
245 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
246 /* NOTE: This is a 'cheap' way to implement a */
247 /* master mute function on the mute button, and */
248 /* in general should not be used unless a more */
249 /* sophisticated master mute function has not */
251 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
252 /* Should be set to 1 when the EMU10K1 is */
253 /* completely initialized. */
255 //For Audigy, MPU port move to 0x70-0x74 ptr register
257 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
259 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
260 #define MUCMD_RESET 0xff /* RESET command */
261 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
262 /* NOTE: All other commands are ignored */
264 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
265 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
266 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
268 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
269 #define A_GPINPUT_MASK 0xff00
270 #define A_GPOUTPUT_MASK 0x00ff
272 // Audigy output/GPIO stuff taken from the kX drivers
273 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
274 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
275 #define A_IOCFG_ENABLE_DIGITAL 0x0004
276 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
277 #define A_IOCFG_UNKNOWN_20 0x0020
278 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
279 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
280 #define A_IOCFG_GPOUT2 0x0001 /* IR */
281 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
282 /* + digital for generic 10k2 */
283 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
284 #define A_IOCFG_FRONT_JACK 0x4000
285 #define A_IOCFG_REAR_JACK 0x8000
286 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
289 * for audigy2 platinum: 0xa00
290 * for a2 platinum ex: 0x1c00
291 * for a1 platinum: 0x0
294 #define TIMER 0x1a /* Timer terminal count register */
295 /* NOTE: After the rate is changed, a maximum */
296 /* of 1024 sample periods should be allowed */
297 /* before the new rate is guaranteed accurate. */
298 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
299 /* 0 == 1024 periods, [1..4] are not useful */
300 #define TIMER_RATE 0x0a00001a
302 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
304 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
305 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
306 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
308 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
309 #define PTR2 0x20 /* Indexed register set pointer register */
310 #define DATA2 0x24 /* Indexed register set data register */
311 #define IPR2 0x28 /* P16V interrupt pending register */
312 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
313 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
314 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
315 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
316 /* 0x00000100 Playback. Only in once per period.
317 * 0x00110000 Capture. Int on half buffer.
319 #define INTE2 0x2c /* P16V Interrupt enable register. */
320 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
321 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
322 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
323 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
324 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
325 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
326 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
327 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
328 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
329 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
330 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
331 /* 0x00000000 2-channel output. */
332 /* 0x00000200 8-channel output. */
333 /* 0x00000004 pauses stream/irq fail. */
334 /* Rest of bits no nothing to sound output */
335 /* bit 0: Enable P16V audio.
336 * bit 1: Lock P16V record memory cache.
337 * bit 2: Lock P16V playback memory cache.
338 * bit 3: Dummy record insert zero samples.
339 * bit 8: Record 8-channel in phase.
340 * bit 9: Playback 8-channel in phase.
341 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
342 * bit 13: Playback mixer enable.
343 * bit 14: Route SRC48 mixer output to fx engine.
344 * bit 15: Enable IEEE 1394 chip.
346 #define IPR3 0x38 /* Cdif interrupt pending register */
347 #define INTE3 0x3c /* Cdif interrupt enable register. */
348 /************************************************************************************************/
349 /* PCI function 1 registers, address = <val> + PCIBASE1 */
350 /************************************************************************************************/
352 #define JOYSTICK1 0x00 /* Analog joystick port register */
353 #define JOYSTICK2 0x01 /* Analog joystick port register */
354 #define JOYSTICK3 0x02 /* Analog joystick port register */
355 #define JOYSTICK4 0x03 /* Analog joystick port register */
356 #define JOYSTICK5 0x04 /* Analog joystick port register */
357 #define JOYSTICK6 0x05 /* Analog joystick port register */
358 #define JOYSTICK7 0x06 /* Analog joystick port register */
359 #define JOYSTICK8 0x07 /* Analog joystick port register */
361 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
362 /* When reading, use these bitfields: */
363 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
364 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
367 /********************************************************************************************************/
368 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
369 /********************************************************************************************************/
371 #define CPF 0x00 /* Current pitch and fraction register */
372 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
373 #define CPF_CURRENTPITCH 0x10100000
374 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
375 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
376 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
378 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
379 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
380 #define PTRX_PITCHTARGET 0x10100001
381 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
382 #define PTRX_FXSENDAMOUNT_A 0x08080001
383 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
384 #define PTRX_FXSENDAMOUNT_B 0x08000001
386 #define CVCF 0x02 /* Current volume and filter cutoff register */
387 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
388 #define CVCF_CURRENTVOL 0x10100002
389 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
390 #define CVCF_CURRENTFILTER 0x10000002
392 #define VTFT 0x03 /* Volume target and filter cutoff target register */
393 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
394 #define VTFT_VOLUMETARGET 0x10100003
395 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
396 #define VTFT_FILTERTARGET 0x10000003
398 #define Z1 0x05 /* Filter delay memory 1 register */
400 #define Z2 0x04 /* Filter delay memory 2 register */
402 #define PSST 0x06 /* Send C amount and loop start address register */
403 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
405 #define PSST_FXSENDAMOUNT_C 0x08180006
407 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
408 #define PSST_LOOPSTARTADDR 0x18000006
410 #define DSL 0x07 /* Send D amount and loop start address register */
411 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
413 #define DSL_FXSENDAMOUNT_D 0x08180007
415 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
416 #define DSL_LOOPENDADDR 0x18000007
418 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
419 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
420 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
421 /* 1 == full band, 7 == lowpass */
422 /* ROM 0 is used when pitch shifting downward or less */
423 /* then 3 semitones upward. Increasingly higher ROM */
424 /* numbers are used, typically in steps of 3 semitones, */
425 /* as upward pitch shifting is performed. */
426 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
427 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
428 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
429 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
430 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
431 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
432 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
433 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
434 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
435 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
436 #define CCCA_CURRADDR 0x18000008
438 #define CCR 0x09 /* Cache control register */
439 #define CCR_CACHEINVALIDSIZE 0x07190009
440 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
441 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
442 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
443 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
444 #define CCR_READADDRESS 0x06100009
445 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
446 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
447 /* NOTE: This is valid only if CACHELOOPFLAG is set */
448 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
449 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
451 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
452 /* NOTE: This register is normally not used */
453 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
455 #define FXRT 0x0b /* Effects send routing register */
456 /* NOTE: It is illegal to assign the same routing to */
457 /* two effects sends. */
458 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
459 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
460 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
461 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
463 #define MAPA 0x0c /* Cache map A */
465 #define MAPB 0x0d /* Cache map B */
467 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
468 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
470 #define ENVVOL 0x10 /* Volume envelope register */
471 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
472 /* 0x8000-n == 666*n usec delay */
474 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
475 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
476 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
477 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
478 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
480 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
481 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
482 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
483 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
484 /* this channel and from writing to pitch, filter and */
485 /* volume targets. */
486 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
487 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
489 #define LFOVAL1 0x13 /* Modulation LFO value */
490 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
491 /* 0x8000-n == 666*n usec delay */
493 #define ENVVAL 0x14 /* Modulation envelope register */
494 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
495 /* 0x8000-n == 666*n usec delay */
497 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
498 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
499 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
500 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
501 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
503 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
504 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
505 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
506 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
507 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
509 #define LFOVAL2 0x17 /* Vibrato LFO register */
510 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
511 /* 0x8000-n == 666*n usec delay */
513 #define IP 0x18 /* Initial pitch register */
514 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
515 /* 4 bits of octave, 12 bits of fractional octave */
516 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
518 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
519 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
520 /* 6 most significant bits are semitones */
521 /* 2 least significant bits are fractions */
522 #define IFATN_FILTERCUTOFF 0x08080019
523 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
524 #define IFATN_ATTENUATION 0x08000019
527 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
528 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
529 /* Signed 2's complement, +/- one octave peak extremes */
530 #define PEFE_PITCHAMOUNT 0x0808001a
531 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
532 /* Signed 2's complement, +/- six octaves peak extremes */
533 #define PEFE_FILTERAMOUNT 0x0800001a
534 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
535 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
536 /* Signed 2's complement, +/- one octave extremes */
537 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
538 /* Signed 2's complement, +/- three octave extremes */
541 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
542 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
543 /* Signed 2's complement, with +/- 12dB extremes */
545 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
546 /* ??Hz steps, maximum of ?? Hz. */
547 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
548 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
549 /* Signed 2's complement, +/- one octave extremes */
550 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
551 /* 0.039Hz steps, maximum of 9.85 Hz. */
553 #define TEMPENV 0x1e /* Tempory envelope register */
554 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
555 /* NOTE: All channels contain internal variables; do */
556 /* not write to these locations. */
560 #define CD0 0x20 /* Cache data 0 register */
561 #define CD1 0x21 /* Cache data 1 register */
562 #define CD2 0x22 /* Cache data 2 register */
563 #define CD3 0x23 /* Cache data 3 register */
564 #define CD4 0x24 /* Cache data 4 register */
565 #define CD5 0x25 /* Cache data 5 register */
566 #define CD6 0x26 /* Cache data 6 register */
567 #define CD7 0x27 /* Cache data 7 register */
568 #define CD8 0x28 /* Cache data 8 register */
569 #define CD9 0x29 /* Cache data 9 register */
570 #define CDA 0x2a /* Cache data A register */
571 #define CDB 0x2b /* Cache data B register */
572 #define CDC 0x2c /* Cache data C register */
573 #define CDD 0x2d /* Cache data D register */
574 #define CDE 0x2e /* Cache data E register */
575 #define CDF 0x2f /* Cache data F register */
577 /* 0x30-3f seem to be the same as 0x20-2f */
579 #define PTB 0x40 /* Page table base register */
580 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
582 #define TCB 0x41 /* Tank cache base register */
583 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
585 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
586 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
587 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
588 /* NOTE: To guarantee phase coherency, both channels */
589 /* must be disabled prior to enabling both channels. */
590 #define A_ADCCR_RCHANENABLE 0x00000020
591 #define A_ADCCR_LCHANENABLE 0x00000010
593 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
594 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
595 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
596 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
597 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
598 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
599 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
600 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
601 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
602 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
603 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
604 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
605 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
607 #define FXWC 0x43 /* FX output write channels register */
608 /* When set, each bit enables the writing of the */
609 /* corresponding FX output channel (internal registers */
610 /* 0x20-0x3f) to host memory. This mode of recording */
611 /* is 16bit, 48KHz only. All 32 channels can be enabled */
612 /* simultaneously. */
614 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
615 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
616 #define FXWC_DEFAULTROUTE_A (1<<12)
617 #define FXWC_DEFAULTROUTE_D (1<<13)
618 #define FXWC_ADCLEFT (1<<18)
619 #define FXWC_CDROMSPDIFLEFT (1<<18)
620 #define FXWC_ADCRIGHT (1<<19)
621 #define FXWC_CDROMSPDIFRIGHT (1<<19)
622 #define FXWC_MIC (1<<20)
623 #define FXWC_ZOOMLEFT (1<<20)
624 #define FXWC_ZOOMRIGHT (1<<21)
625 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
626 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
628 #define TCBS 0x44 /* Tank cache buffer size register */
629 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
630 #define TCBS_BUFFSIZE_16K 0x00000000
631 #define TCBS_BUFFSIZE_32K 0x00000001
632 #define TCBS_BUFFSIZE_64K 0x00000002
633 #define TCBS_BUFFSIZE_128K 0x00000003
634 #define TCBS_BUFFSIZE_256K 0x00000004
635 #define TCBS_BUFFSIZE_512K 0x00000005
636 #define TCBS_BUFFSIZE_1024K 0x00000006
637 #define TCBS_BUFFSIZE_2048K 0x00000007
639 #define MICBA 0x45 /* AC97 microphone buffer address register */
640 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
642 #define ADCBA 0x46 /* ADC buffer address register */
643 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
645 #define FXBA 0x47 /* FX Buffer Address */
646 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
648 /* 0x48 something - word access, defaults to 3f */
650 #define MICBS 0x49 /* Microphone buffer size register */
652 #define ADCBS 0x4a /* ADC buffer size register */
654 #define FXBS 0x4b /* FX buffer size register */
656 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
658 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
659 #define ADCBS_BUFSIZE_NONE 0x00000000
660 #define ADCBS_BUFSIZE_384 0x00000001
661 #define ADCBS_BUFSIZE_448 0x00000002
662 #define ADCBS_BUFSIZE_512 0x00000003
663 #define ADCBS_BUFSIZE_640 0x00000004
664 #define ADCBS_BUFSIZE_768 0x00000005
665 #define ADCBS_BUFSIZE_896 0x00000006
666 #define ADCBS_BUFSIZE_1024 0x00000007
667 #define ADCBS_BUFSIZE_1280 0x00000008
668 #define ADCBS_BUFSIZE_1536 0x00000009
669 #define ADCBS_BUFSIZE_1792 0x0000000a
670 #define ADCBS_BUFSIZE_2048 0x0000000b
671 #define ADCBS_BUFSIZE_2560 0x0000000c
672 #define ADCBS_BUFSIZE_3072 0x0000000d
673 #define ADCBS_BUFSIZE_3584 0x0000000e
674 #define ADCBS_BUFSIZE_4096 0x0000000f
675 #define ADCBS_BUFSIZE_5120 0x00000010
676 #define ADCBS_BUFSIZE_6144 0x00000011
677 #define ADCBS_BUFSIZE_7168 0x00000012
678 #define ADCBS_BUFSIZE_8192 0x00000013
679 #define ADCBS_BUFSIZE_10240 0x00000014
680 #define ADCBS_BUFSIZE_12288 0x00000015
681 #define ADCBS_BUFSIZE_14366 0x00000016
682 #define ADCBS_BUFSIZE_16384 0x00000017
683 #define ADCBS_BUFSIZE_20480 0x00000018
684 #define ADCBS_BUFSIZE_24576 0x00000019
685 #define ADCBS_BUFSIZE_28672 0x0000001a
686 #define ADCBS_BUFSIZE_32768 0x0000001b
687 #define ADCBS_BUFSIZE_40960 0x0000001c
688 #define ADCBS_BUFSIZE_49152 0x0000001d
689 #define ADCBS_BUFSIZE_57344 0x0000001e
690 #define ADCBS_BUFSIZE_65536 0x0000001f
693 #define CDCS 0x50 /* CD-ROM digital channel status register */
695 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
697 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
699 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
702 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
703 #define A_DBG_ZC 0x40000000 /* zero tram counter */
704 #define A_DBG_STEP_ADDR 0x000003ff
705 #define A_DBG_SATURATION_OCCURED 0x20000000
706 #define A_DBG_SATURATION_ADDR 0x0ffc0000
708 // NOTE: 0x54,55,56: 64-bit
709 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
711 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
713 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
715 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
716 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
717 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
718 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
719 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
720 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
721 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
722 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
723 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
724 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
725 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
726 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
727 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
728 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
729 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
730 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
731 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
732 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
733 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
734 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
735 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
736 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
737 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
739 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
740 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
742 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
744 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
746 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
748 #define SOLEL 0x5c /* Stop on loop enable low register */
750 #define SOLEH 0x5d /* Stop on loop enable high register */
752 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
753 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
754 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
755 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
756 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
758 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
759 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
760 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
761 #define AC97SLOT_CNTR 0x10 /* Center enable */
762 #define AC97SLOT_LFE 0x20 /* LFE enable */
764 // NOTE: 0x60,61,62: 64-bit
765 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
767 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
769 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
770 /* NOTE: This one has no SPDIFLOCKED field */
771 /* Assumes sample lock */
773 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
774 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
775 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
776 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
777 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
779 /* Note that these values can vary +/- by a small amount */
780 #define SRCS_SPDIFRATE_44 0x0003acd9
781 #define SRCS_SPDIFRATE_48 0x00040000
782 #define SRCS_SPDIFRATE_96 0x00080000
784 #define MICIDX 0x63 /* Microphone recording buffer index register */
785 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
786 #define MICIDX_IDX 0x10000063
788 #define ADCIDX 0x64 /* ADC recording buffer index register */
789 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
790 #define ADCIDX_IDX 0x10000064
792 #define A_ADCIDX 0x63
793 #define A_ADCIDX_IDX 0x10000063
795 #define A_MICIDX 0x64
796 #define A_MICIDX_IDX 0x10000064
798 #define FXIDX 0x65 /* FX recording buffer index register */
799 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
800 #define FXIDX_IDX 0x10000065
802 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
803 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
805 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
807 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
809 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
811 // 0x6a,6b,6c used for some recording
813 // 0x6e,6f - tanktable base / offset
815 /* This is the MPU port on the card (via the game port) */
816 #define A_MUDATA1 0x70
817 #define A_MUCMD1 0x71
818 #define A_MUSTAT1 A_MUCMD1
820 /* This is the MPU port on the Audigy Drive */
821 #define A_MUDATA2 0x72
822 #define A_MUCMD2 0x73
823 #define A_MUSTAT2 A_MUCMD2
825 /* The next two are the Audigy equivalent of FXWC */
826 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
827 /* Each bit selects a channel for recording */
828 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
829 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
831 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
832 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
833 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
834 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
835 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
836 #define A_SPDIF_48000 0x00000000
837 #define A_SPDIF_192000 0x00000020
838 #define A_SPDIF_96000 0x00000040
839 #define A_SPDIF_44100 0x00000080
841 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
842 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
843 #define A_I2S_CAPTURE_192000 0x00000200
844 #define A_I2S_CAPTURE_96000 0x00000400
845 #define A_I2S_CAPTURE_44100 0x00000800
847 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
848 #define A_PCM_48000 0x00000000
849 #define A_PCM_192000 0x00002000
850 #define A_PCM_96000 0x00004000
851 #define A_PCM_44100 0x00008000
853 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */
854 /* 0x7a, 0x7b - lookup tables */
857 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
858 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
859 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
860 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
862 #define A_SENDAMOUNTS 0x7d
863 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
864 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
865 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
866 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
867 /* 0x7c, 0x7e "high bit is used for filtering" */
869 /* The send amounts for this one are the same as used with the emu10k1 */
871 #define A_FXRT_CHANNELA 0x0000003f
872 #define A_FXRT_CHANNELB 0x00003f00
873 #define A_FXRT_CHANNELC 0x003f0000
874 #define A_FXRT_CHANNELD 0x3f000000
877 /* Each FX general purpose register is 32 bits in length, all bits are used */
878 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
879 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
881 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
882 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
884 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
885 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
886 /* locations are for external TRAM. */
887 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
888 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
890 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
891 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
892 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
893 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
894 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
895 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
896 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
898 #define MICROCODEBASE 0x400 /* Microcode data base address */
900 /* Each DSP microcode instruction is mapped into 2 doublewords */
901 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
902 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
903 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
904 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
905 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
906 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
909 /* Audigy Soundcard have a different instruction format */
910 #define A_MICROCODEBASE 0x600
911 #define A_LOWORD_OPY_MASK 0x000007ff
912 #define A_LOWORD_OPX_MASK 0x007ff000
913 #define A_HIWORD_OPCODE_MASK 0x0f000000
914 #define A_HIWORD_RESULT_MASK 0x007ff000
915 #define A_HIWORD_OPA_MASK 0x000007ff
917 /************************************************************************************************/
918 /* EMU1010m HANA FPGA registers */
919 /************************************************************************************************/
920 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
921 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
922 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
923 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
924 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
925 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
926 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
927 /* Must be written after power on to reset DLL */
928 /* One is unable to detect the Audio dock without this */
929 #define EMU_HANA_WCLOCK_SRC_MASK 0x07
930 #define EMU_HANA_WCLOCK_INT_48K 0x00
931 #define EMU_HANA_WCLOCK_INT_44_1K 0x01
932 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
933 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
934 #define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
935 #define EMU_HANA_WCLOCK_2ND_HANA 0x05
936 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
937 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
938 #define EMU_HANA_WCLOCK_MULT_MASK 0x18
939 #define EMU_HANA_WCLOCK_1X 0x00
940 #define EMU_HANA_WCLOCK_2X 0x08
941 #define EMU_HANA_WCLOCK_4X 0x10
942 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
944 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
945 #define EMU_HANA_DEFCLOCK_48K 0x00
946 #define EMU_HANA_DEFCLOCK_44_1K 0x01
948 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
949 #define EMU_MUTE 0x00
950 #define EMU_UNMUTE 0x01
952 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
953 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
954 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
956 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
957 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
958 #define EMU_HANA_IRQ_ADAT 0x02
959 #define EMU_HANA_IRQ_DOCK 0x04
960 #define EMU_HANA_IRQ_DOCK_LOST 0x08
962 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
963 #define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
964 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
965 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
966 #define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
967 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
968 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
969 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
971 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
972 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
973 #define EMU_HANA_OPTICAL_IN_ADAT 0x01
974 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
975 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
977 #define EMU_HANA_MIDI 0x0c /* 000000x 1 bit Control MIDI */
978 #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
979 #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
981 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
982 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
983 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
984 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
985 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
987 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
988 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
989 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
990 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
991 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
992 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
993 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
995 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
996 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
997 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
998 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
999 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1000 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1001 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1003 #define EMU_HANA_DOCK_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1004 #define EMU_HANA_DOCK_PAD1 0x01 /* 14dB Attenuation on ADC 1 */
1005 #define EMU_HANA_DOCK_PAD2 0x02 /* 14dB Attenuation on ADC 2 */
1006 #define EMU_HANA_DOCK_PAD3 0x04 /* 14dB Attenuation on ADC 3 */
1008 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1009 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1010 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1011 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1012 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1013 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1014 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1015 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1016 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1018 #define EMU_HANA_UNKNOWN12 0x12 /* 0xxxxxx 6 bit Unknown12 */
1019 #define EMU_HANA_UNKNOWN13 0x13 /* 0xxxxxx 6 bit Unknown13 */
1020 /* 0x14 - 0x1f Unused R/W registers */
1021 #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
1022 #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
1023 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1024 #define EMU_HANA_IRQ_ADAT 0x02
1025 #define EMU_HANA_IRQ_DOCK 0x04
1026 #define EMU_HANA_IRQ_DOCK_LOST 0x08
1029 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1030 #define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
1031 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1032 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
1033 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
1035 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
1037 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1038 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1040 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1041 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1043 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1044 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1045 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1047 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1048 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1050 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1051 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1053 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1054 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1056 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1057 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1058 /* 0x30 - 0x3f Unused Read only registers */
1060 /************************************************************************************************/
1061 /* EMU1010m HANA Destinations */
1062 /************************************************************************************************/
1063 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1064 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1065 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1066 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1067 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1068 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1069 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1070 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1071 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1072 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1073 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1074 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1075 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1076 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1077 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1078 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1079 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1080 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1081 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1082 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1083 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1084 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1085 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1086 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1087 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1088 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1089 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1090 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1091 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1092 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1093 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1094 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1095 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1096 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1097 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1098 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1099 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1100 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1101 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1102 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1103 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1104 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1105 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1106 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1107 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1108 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1109 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1110 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1111 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1112 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1113 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1114 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1115 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1116 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1117 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1118 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1119 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1120 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1121 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1122 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1123 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1124 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1125 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1126 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1127 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1128 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1129 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1130 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1131 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1132 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1133 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1134 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1135 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1136 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1137 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1139 /************************************************************************************************/
1140 /* EMU1010m HANA Sources */
1141 /************************************************************************************************/
1142 #define EMU_SRC_SILENCE 0x0000 /* Silence */
1143 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1144 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1145 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1146 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1147 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1148 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1149 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1150 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1151 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1152 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1153 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1154 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1155 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1156 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1157 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1158 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1159 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1160 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1161 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1162 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1163 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1164 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1165 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1166 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1167 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1168 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1169 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1170 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1171 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1172 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1173 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1174 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1175 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1176 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1177 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1178 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1179 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1180 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1181 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1182 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1183 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1184 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1185 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1186 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1187 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1188 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1189 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1190 /* 0x600 and 0x700 no used */
1192 /* ------------------- STRUCTURES -------------------- */
1203 struct snd_emu10k1_voice {
1204 struct snd_emu10k1 *emu;
1206 unsigned int use: 1,
1211 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1213 struct snd_emu10k1_pcm *epcm;
1224 struct snd_emu10k1_pcm {
1225 struct snd_emu10k1 *emu;
1227 struct snd_pcm_substream *substream;
1228 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1229 struct snd_emu10k1_voice *extra;
1230 unsigned short running;
1231 unsigned short first_ptr;
1232 struct snd_util_memblk *memblk;
1233 unsigned int start_addr;
1234 unsigned int ccca_start_addr;
1235 unsigned int capture_ipr; /* interrupt acknowledge mask */
1236 unsigned int capture_inte; /* interrupt enable mask */
1237 unsigned int capture_ba_reg; /* buffer address register */
1238 unsigned int capture_bs_reg; /* buffer size register */
1239 unsigned int capture_idx_reg; /* buffer index register */
1240 unsigned int capture_cr_val; /* control value */
1241 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1242 unsigned int capture_bs_val; /* buffer size value */
1243 unsigned int capture_bufsize; /* buffer size in bytes */
1246 struct snd_emu10k1_pcm_mixer {
1247 /* mono, left, right x 8 sends (4 on emu10k1) */
1248 unsigned char send_routing[3][8];
1249 unsigned char send_volume[3][8];
1250 unsigned short attn[3];
1251 struct snd_emu10k1_pcm *epcm;
1254 #define snd_emu10k1_compose_send_routing(route) \
1255 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1257 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1258 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1260 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1261 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1263 struct snd_emu10k1_memblk {
1264 struct snd_util_memblk mem;
1266 int first_page, last_page, pages, mapped_page;
1267 unsigned int map_locked;
1268 struct list_head mapped_link;
1269 struct list_head mapped_order_link;
1272 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1274 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1276 struct snd_emu10k1_fx8010_ctl {
1277 struct list_head list; /* list link container */
1278 unsigned int vcount;
1279 unsigned int count; /* count of GPR (1..16) */
1280 unsigned short gpr[32]; /* GPR number(s) */
1281 unsigned int value[32];
1282 unsigned int min; /* minimum range */
1283 unsigned int max; /* maximum range */
1284 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1285 struct snd_kcontrol *kcontrol;
1288 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1290 struct snd_emu10k1_fx8010_irq {
1291 struct snd_emu10k1_fx8010_irq *next;
1292 snd_fx8010_irq_handler_t *handler;
1293 unsigned short gpr_running;
1297 struct snd_emu10k1_fx8010_pcm {
1298 unsigned int valid: 1,
1301 unsigned int channels; /* 16-bit channels count */
1302 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1303 unsigned int buffer_size; /* count of buffered samples */
1304 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1305 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1306 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1307 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1308 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1309 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1310 unsigned char etram[32]; /* external TRAM address & data */
1311 struct snd_pcm_indirect pcm_rec;
1312 unsigned int tram_pos;
1313 unsigned int tram_shift;
1314 struct snd_emu10k1_fx8010_irq *irq;
1317 struct snd_emu10k1_fx8010 {
1318 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1319 unsigned short extin_mask; /* used external inputs (bitmask) */
1320 unsigned short extout_mask; /* used external outputs (bitmask) */
1321 unsigned short pad1;
1322 unsigned int itram_size; /* internal TRAM size in samples */
1323 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1324 unsigned int dbg; /* FX debugger register */
1325 unsigned char name[128];
1326 int gpr_size; /* size of allocated GPR controls */
1327 int gpr_count; /* count of used kcontrols */
1328 struct list_head gpr_ctl; /* GPR controls */
1330 struct snd_emu10k1_fx8010_pcm pcm[8];
1331 spinlock_t irq_lock;
1332 struct snd_emu10k1_fx8010_irq *irq_handlers;
1335 #define emu10k1_gpr_ctl(n) list_entry(n, struct snd_emu10k1_fx8010_ctl, list)
1337 struct snd_emu10k1_midi {
1338 struct snd_emu10k1 *emu;
1339 struct snd_rawmidi *rmidi;
1340 struct snd_rawmidi_substream *substream_input;
1341 struct snd_rawmidi_substream *substream_output;
1342 unsigned int midi_mode;
1343 spinlock_t input_lock;
1344 spinlock_t output_lock;
1345 spinlock_t open_lock;
1346 int tx_enable, rx_enable;
1349 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1352 struct snd_emu_chip_details {
1356 unsigned char revision;
1357 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1358 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1359 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1360 unsigned char ca0108_chip; /* Audigy 2 Value */
1361 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1362 unsigned char ca0151_chip; /* P16V */
1363 unsigned char spk71; /* Has 7.1 speakers */
1364 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1365 unsigned char spdif_bug; /* Has Spdif phasing bug */
1366 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1367 unsigned char ecard; /* APS EEPROM */
1368 unsigned char emu1010; /* EMU 1010m card */
1369 unsigned char spi_dac; /* SPI interface for DAC */
1370 unsigned char i2c_adc; /* I2C interface for ADC */
1371 unsigned char adc_1361t; /* Use Philips 1361T ADC */
1374 const char *id; /* for backward compatibility - can be NULL if not needed */
1377 struct snd_emu1010 {
1378 unsigned int output_source[64];
1379 unsigned int input_source[64];
1382 struct snd_emu10k1 {
1385 unsigned long port; /* I/O port number */
1386 unsigned int tos_link: 1, /* tos link detected */
1387 rear_ac97: 1, /* rear channels are on AC'97 */
1389 /* Contains profile of card capabilities */
1390 const struct snd_emu_chip_details *card_capabilities;
1391 unsigned int audigy; /* is Audigy? */
1392 unsigned int revision; /* chip revision */
1393 unsigned int serial; /* serial number */
1394 unsigned short model; /* subsystem id */
1395 unsigned int card_type; /* EMU10K1_CARD_* */
1396 unsigned int ecard_ctrl; /* ecard control bits */
1397 unsigned long dma_mask; /* PCI DMA mask */
1398 int max_cache_pages; /* max memory size / PAGE_SIZE */
1399 struct snd_dma_buffer silent_page; /* silent page */
1400 struct snd_dma_buffer ptb_pages; /* page table pages */
1401 struct snd_dma_device p16v_dma_dev;
1402 struct snd_dma_buffer p16v_buffer;
1404 struct snd_util_memhdr *memhdr; /* page allocation list */
1405 struct snd_emu10k1_memblk *reserved_page; /* reserved page */
1407 struct list_head mapped_link_head;
1408 struct list_head mapped_order_link_head;
1409 void **page_ptr_table;
1410 unsigned long *page_addr_table;
1411 spinlock_t memblk_lock;
1413 unsigned int spdif_bits[3]; /* s/pdif out setup */
1415 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1418 struct snd_ac97 *ac97;
1420 struct pci_dev *pci;
1421 struct snd_card *card;
1422 struct snd_pcm *pcm;
1423 struct snd_pcm *pcm_mic;
1424 struct snd_pcm *pcm_efx;
1425 struct snd_pcm *pcm_multi;
1426 struct snd_pcm *pcm_p16v;
1428 spinlock_t synth_lock;
1430 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1432 spinlock_t reg_lock;
1433 spinlock_t emu_lock;
1434 spinlock_t voice_lock;
1436 struct snd_emu10k1_voice voices[NUM_G];
1437 struct snd_emu10k1_voice p16v_voices[4];
1438 struct snd_emu10k1_voice p16v_capture_voice;
1439 int p16v_device_offset;
1440 u32 p16v_capture_source;
1441 u32 p16v_capture_channel;
1442 struct snd_emu1010 emu1010;
1443 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1444 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1445 struct snd_kcontrol *ctl_send_routing;
1446 struct snd_kcontrol *ctl_send_volume;
1447 struct snd_kcontrol *ctl_attn;
1448 struct snd_kcontrol *ctl_efx_send_routing;
1449 struct snd_kcontrol *ctl_efx_send_volume;
1450 struct snd_kcontrol *ctl_efx_attn;
1452 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1453 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1454 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1455 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1456 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1457 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1459 struct snd_pcm_substream *pcm_capture_substream;
1460 struct snd_pcm_substream *pcm_capture_mic_substream;
1461 struct snd_pcm_substream *pcm_capture_efx_substream;
1462 struct snd_pcm_substream *pcm_playback_efx_substream;
1464 struct snd_timer *timer;
1466 struct snd_emu10k1_midi midi;
1467 struct snd_emu10k1_midi midi2; /* for audigy */
1469 unsigned int efx_voices_mask[2];
1470 unsigned int next_free_voice;
1473 unsigned int *saved_ptr;
1474 unsigned int *saved_gpr;
1475 unsigned int *tram_val_saved;
1476 unsigned int *tram_addr_saved;
1477 unsigned int *saved_icode;
1478 unsigned int *p16v_saved;
1479 unsigned int saved_a_iocfg, saved_hcfg;
1484 int snd_emu10k1_create(struct snd_card *card,
1485 struct pci_dev *pci,
1486 unsigned short extin_mask,
1487 unsigned short extout_mask,
1488 long max_cache_bytes,
1491 struct snd_emu10k1 ** remu);
1493 int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1494 int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1495 int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1496 int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1497 int snd_p16v_free(struct snd_emu10k1 * emu);
1498 int snd_p16v_mixer(struct snd_emu10k1 * emu);
1499 int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1500 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1501 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1502 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1503 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
1505 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1507 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1508 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1509 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1510 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1511 int snd_emu10k1_done(struct snd_emu10k1 * emu);
1514 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1515 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1516 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1517 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1518 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1519 int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, int reg, int value);
1520 int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, int reg, int *value);
1521 int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, int dst, int src);
1522 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1523 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1524 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1525 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1526 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1527 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1528 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1529 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1530 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1531 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1532 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1533 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1534 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1535 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1536 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1537 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1540 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1541 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1542 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1543 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1544 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1545 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1546 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1547 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1548 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1549 void snd_p16v_suspend(struct snd_emu10k1 *emu);
1550 void snd_p16v_resume(struct snd_emu10k1 *emu);
1553 /* memory allocation */
1554 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1555 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1556 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1557 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1558 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1559 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1560 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1562 /* voice allocation */
1563 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1564 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1567 int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1568 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1570 /* proc interface */
1571 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1573 /* fx8010 irq handler */
1574 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1575 snd_fx8010_irq_handler_t *handler,
1576 unsigned char gpr_running,
1578 struct snd_emu10k1_fx8010_irq **r_irq);
1579 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1580 struct snd_emu10k1_fx8010_irq *irq);
1582 #endif /* __KERNEL__ */
1588 #define EMU10K1_CARD_CREATIVE 0x00000000
1589 #define EMU10K1_CARD_EMUAPS 0x00000001
1591 #define EMU10K1_FX8010_PCM_COUNT 8
1593 /* instruction set */
1594 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1595 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1596 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1597 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1598 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1599 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1600 #define iACC3 0x06 /* R = A + X + Y ; saturation */
1601 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1602 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
1603 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1604 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1605 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1606 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1607 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1608 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1609 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1612 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1613 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1614 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1615 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
1616 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
1618 #define C_00000000 0x40
1619 #define C_00000001 0x41
1620 #define C_00000002 0x42
1621 #define C_00000003 0x43
1622 #define C_00000004 0x44
1623 #define C_00000008 0x45
1624 #define C_00000010 0x46
1625 #define C_00000020 0x47
1626 #define C_00000100 0x48
1627 #define C_00010000 0x49
1628 #define C_00080000 0x4a
1629 #define C_10000000 0x4b
1630 #define C_20000000 0x4c
1631 #define C_40000000 0x4d
1632 #define C_80000000 0x4e
1633 #define C_7fffffff 0x4f
1634 #define C_ffffffff 0x50
1635 #define C_fffffffe 0x51
1636 #define C_c0000000 0x52
1637 #define C_4f1bbcdc 0x53
1638 #define C_5a7ef9db 0x54
1639 #define C_00100000 0x55 /* ?? */
1640 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
1641 #define GPR_COND 0x57 /* CCR, condition register */
1642 #define GPR_NOISE0 0x58 /* noise source */
1643 #define GPR_NOISE1 0x59 /* noise source */
1644 #define GPR_IRQ 0x5a /* IRQ register */
1645 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1646 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1647 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1648 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1649 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1650 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1652 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1653 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1654 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1655 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1656 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1657 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1659 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1660 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1661 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1662 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1663 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1664 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1665 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1666 #define A_GPR(x) (A_FXGPREGBASE + (x))
1668 /* cc_reg constants */
1669 #define CC_REG_NORMALIZED C_00000001
1670 #define CC_REG_BORROW C_00000002
1671 #define CC_REG_MINUS C_00000004
1672 #define CC_REG_ZERO C_00000008
1673 #define CC_REG_SATURATE C_00000010
1674 #define CC_REG_NONZERO C_00000100
1677 #define FXBUS_PCM_LEFT 0x00
1678 #define FXBUS_PCM_RIGHT 0x01
1679 #define FXBUS_PCM_LEFT_REAR 0x02
1680 #define FXBUS_PCM_RIGHT_REAR 0x03
1681 #define FXBUS_MIDI_LEFT 0x04
1682 #define FXBUS_MIDI_RIGHT 0x05
1683 #define FXBUS_PCM_CENTER 0x06
1684 #define FXBUS_PCM_LFE 0x07
1685 #define FXBUS_PCM_LEFT_FRONT 0x08
1686 #define FXBUS_PCM_RIGHT_FRONT 0x09
1687 #define FXBUS_MIDI_REVERB 0x0c
1688 #define FXBUS_MIDI_CHORUS 0x0d
1689 #define FXBUS_PCM_LEFT_SIDE 0x0e
1690 #define FXBUS_PCM_RIGHT_SIDE 0x0f
1691 #define FXBUS_PT_LEFT 0x14
1692 #define FXBUS_PT_RIGHT 0x15
1695 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1696 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1697 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
1698 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
1699 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
1700 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
1701 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
1702 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
1703 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
1704 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
1705 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
1706 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
1707 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
1708 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
1711 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
1712 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
1713 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
1714 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
1715 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
1716 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
1717 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
1718 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
1719 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
1720 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
1721 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
1722 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
1723 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
1724 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
1725 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
1726 #define EXTOUT_ACENTER 0x11 /* Analog Center */
1727 #define EXTOUT_ALFE 0x12 /* Analog LFE */
1730 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1731 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1732 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
1733 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
1734 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
1735 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
1736 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
1737 #define A_EXTIN_LINE2_R 0x09 /* right */
1738 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
1739 #define A_EXTIN_ADC_R 0x0b /* right */
1740 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
1741 #define A_EXTIN_AUX2_R 0x0d /* - right */
1743 /* Audigiy Outputs */
1744 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
1745 #define A_EXTOUT_FRONT_R 0x01 /* right */
1746 #define A_EXTOUT_CENTER 0x02 /* digital front center */
1747 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
1748 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
1749 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
1750 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
1751 #define A_EXTOUT_REAR_R 0x07 /* right */
1752 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
1753 #define A_EXTOUT_AFRONT_R 0x09 /* right */
1754 #define A_EXTOUT_ACENTER 0x0a /* analog center */
1755 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
1756 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
1757 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
1758 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
1759 #define A_EXTOUT_AREAR_R 0x0f /* right */
1760 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
1761 #define A_EXTOUT_AC97_R 0x11 /* right */
1762 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
1763 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
1764 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
1766 /* Audigy constants */
1767 #define A_C_00000000 0xc0
1768 #define A_C_00000001 0xc1
1769 #define A_C_00000002 0xc2
1770 #define A_C_00000003 0xc3
1771 #define A_C_00000004 0xc4
1772 #define A_C_00000008 0xc5
1773 #define A_C_00000010 0xc6
1774 #define A_C_00000020 0xc7
1775 #define A_C_00000100 0xc8
1776 #define A_C_00010000 0xc9
1777 #define A_C_00000800 0xca
1778 #define A_C_10000000 0xcb
1779 #define A_C_20000000 0xcc
1780 #define A_C_40000000 0xcd
1781 #define A_C_80000000 0xce
1782 #define A_C_7fffffff 0xcf
1783 #define A_C_ffffffff 0xd0
1784 #define A_C_fffffffe 0xd1
1785 #define A_C_c0000000 0xd2
1786 #define A_C_4f1bbcdc 0xd3
1787 #define A_C_5a7ef9db 0xd4
1788 #define A_C_00100000 0xd5
1789 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
1790 #define A_GPR_COND 0xd7 /* CCR, condition register */
1791 #define A_GPR_NOISE0 0xd8 /* noise source */
1792 #define A_GPR_NOISE1 0xd9 /* noise source */
1793 #define A_GPR_IRQ 0xda /* IRQ register */
1794 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
1795 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
1797 /* definitions for debug register */
1798 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
1799 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
1800 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
1801 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
1802 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
1803 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
1804 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
1806 /* tank memory address line */
1808 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1809 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
1810 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
1811 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
1812 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
1815 struct snd_emu10k1_fx8010_info {
1816 unsigned int internal_tram_size; /* in samples */
1817 unsigned int external_tram_size; /* in samples */
1818 char fxbus_names[16][32]; /* names of FXBUSes */
1819 char extin_names[16][32]; /* names of external inputs */
1820 char extout_names[32][32]; /* names of external outputs */
1821 unsigned int gpr_controls; /* count of GPR controls */
1824 #define EMU10K1_GPR_TRANSLATION_NONE 0
1825 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
1826 #define EMU10K1_GPR_TRANSLATION_BASS 2
1827 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
1828 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
1830 struct snd_emu10k1_fx8010_control_gpr {
1831 struct snd_ctl_elem_id id; /* full control ID definition */
1832 unsigned int vcount; /* visible count */
1833 unsigned int count; /* count of GPR (1..16) */
1834 unsigned short gpr[32]; /* GPR number(s) */
1835 unsigned int value[32]; /* initial values */
1836 unsigned int min; /* minimum range */
1837 unsigned int max; /* maximum range */
1839 snd_kcontrol_tlv_rw_t *c;
1842 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1845 struct snd_emu10k1_fx8010_code {
1848 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
1849 u_int32_t __user *gpr_map; /* initializers */
1851 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
1852 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */
1854 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
1855 struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */
1857 unsigned int gpr_list_control_count; /* count of GPR controls to list */
1858 unsigned int gpr_list_control_total; /* total count of GPR controls */
1859 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */
1861 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
1862 u_int32_t __user *tram_data_map; /* data initializers */
1863 u_int32_t __user *tram_addr_map; /* map initializers */
1865 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
1866 u_int32_t __user *code; /* one instruction - 64 bits */
1869 struct snd_emu10k1_fx8010_tram {
1870 unsigned int address; /* 31.bit == 1 -> external TRAM */
1871 unsigned int size; /* size in samples (4 bytes) */
1872 unsigned int *samples; /* pointer to samples (20-bit) */
1873 /* NULL->clear memory */
1876 struct snd_emu10k1_fx8010_pcm_rec {
1877 unsigned int substream; /* substream number */
1878 unsigned int res1; /* reserved */
1879 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
1880 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
1881 unsigned int buffer_size; /* count of buffered samples */
1882 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
1883 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1884 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1885 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1886 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1887 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1888 unsigned char pad; /* reserved */
1889 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
1890 unsigned int res2; /* reserved */
1893 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
1894 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
1895 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
1896 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
1897 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
1898 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
1899 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
1900 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
1901 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
1902 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
1903 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
1904 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
1905 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
1907 /* typedefs for compatibility to user-space */
1908 typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
1909 typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
1910 typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
1911 typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
1912 typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
1914 #endif /* __SOUND_EMU10K1_H */
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