4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/pci_regs.h> /* The pci register defines */
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
43 #include <linux/mod_devicetable.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
55 #include <linux/irqreturn.h>
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
60 /* pci_slot represents a physical slot */
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
71 return kobject_name(&slot->kobj);
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
87 * For PCI devices, the region numbers are assigned this way:
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = 5,
94 /* #6: expansion ROM resource */
97 /* device specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* total resources associated with a PCI device */
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
117 typedef int __bitwise pci_power_t;
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
130 static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state];
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
143 typedef unsigned int __bitwise pci_channel_state_t;
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
156 typedef unsigned int __bitwise pcie_reset_state_t;
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
169 typedef unsigned short __bitwise pci_dev_flags_t;
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
184 typedef unsigned short __bitwise pci_bus_flags_t;
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
217 struct pci_cap_saved_state {
218 struct hlist_node next;
223 struct pcie_link_state;
229 * The pci_dev structure is used to describe PCI devices.
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
260 struct device_dma_parameters dma_parms;
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
269 unsigned int d1_support:1; /* Low power state D1 is supported */
270 unsigned int d2_support:1; /* Low power state D2 is supported */
271 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
272 unsigned int wakeup_prepared:1;
273 unsigned int d3_delay; /* D3->D0 transition time in ms */
275 #ifdef CONFIG_PCIEASPM
276 struct pcie_link_state *link_state; /* ASPM link state. */
279 pci_channel_state_t error_state; /* current connectivity state */
280 struct device dev; /* Generic device interface */
282 int cfg_size; /* Size of configuration space */
285 * Instead of touching interrupt line and base address registers
286 * directly, use the values stored here. They might be different!
289 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
291 /* These fields are used by common fixups */
292 unsigned int transparent:1; /* Transparent PCI bridge */
293 unsigned int multifunction:1;/* Part of multi-function device */
294 /* keep track of device state */
295 unsigned int is_added:1;
296 unsigned int is_busmaster:1; /* device is busmaster */
297 unsigned int no_msi:1; /* device may not use msi */
298 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
299 unsigned int broken_parity_status:1; /* Device generates false positive parity */
300 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
301 unsigned int msi_enabled:1;
302 unsigned int msix_enabled:1;
303 unsigned int ari_enabled:1; /* ARI forwarding */
304 unsigned int is_managed:1;
305 unsigned int is_pcie:1; /* Obsolete. Will be removed.
306 Use pci_is_pcie() instead */
307 unsigned int needs_freset:1; /* Dev requires fundamental reset */
308 unsigned int state_saved:1;
309 unsigned int is_physfn:1;
310 unsigned int is_virtfn:1;
311 unsigned int reset_fn:1;
312 unsigned int is_hotplug_bridge:1;
313 unsigned int aer_firmware_first:1;
314 pci_dev_flags_t dev_flags;
315 atomic_t enable_cnt; /* pci_enable_device has been called */
317 u32 saved_config_space[16]; /* config space saved at suspend time */
318 struct hlist_head saved_cap_space;
319 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
320 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
321 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
322 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
323 #ifdef CONFIG_PCI_MSI
324 struct list_head msi_list;
327 #ifdef CONFIG_PCI_IOV
329 struct pci_sriov *sriov; /* SR-IOV capability related */
330 struct pci_dev *physfn; /* the PF this VF is associated with */
332 struct pci_ats *ats; /* Address Translation Service */
336 extern struct pci_dev *alloc_pci_dev(void);
338 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
339 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
340 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
342 static inline int pci_channel_offline(struct pci_dev *pdev)
344 return (pdev->error_state != pci_channel_io_normal);
347 static inline struct pci_cap_saved_state *pci_find_saved_cap(
348 struct pci_dev *pci_dev, char cap)
350 struct pci_cap_saved_state *tmp;
351 struct hlist_node *pos;
353 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
354 if (tmp->cap_nr == cap)
360 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
361 struct pci_cap_saved_state *new_cap)
363 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
366 #ifndef PCI_BUS_NUM_RESOURCES
367 #define PCI_BUS_NUM_RESOURCES 16
370 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
373 struct list_head node; /* node in list of buses */
374 struct pci_bus *parent; /* parent bus this bridge is on */
375 struct list_head children; /* list of child buses */
376 struct list_head devices; /* list of devices on this bus */
377 struct pci_dev *self; /* bridge device as seen by parent */
378 struct list_head slots; /* list of slots on this bus */
379 struct resource *resource[PCI_BUS_NUM_RESOURCES];
380 /* address space routed to this bus */
382 struct pci_ops *ops; /* configuration access functions */
383 void *sysdata; /* hook for sys-specific extension */
384 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
386 unsigned char number; /* bus number */
387 unsigned char primary; /* number of primary bridge */
388 unsigned char secondary; /* number of secondary bridge */
389 unsigned char subordinate; /* max number of subordinate buses */
390 unsigned char max_bus_speed; /* enum pci_bus_speed */
391 unsigned char cur_bus_speed; /* enum pci_bus_speed */
395 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
396 pci_bus_flags_t bus_flags; /* Inherited by child busses */
397 struct device *bridge;
399 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
400 struct bin_attribute *legacy_mem; /* legacy mem */
401 unsigned int is_added:1;
404 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
405 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
408 * Returns true if the pci bus is root (behind host-pci bridge),
411 static inline bool pci_is_root_bus(struct pci_bus *pbus)
413 return !(pbus->parent);
416 #ifdef CONFIG_PCI_MSI
417 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
419 return pci_dev->msi_enabled || pci_dev->msix_enabled;
422 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
426 * Error values that may be returned by PCI functions.
428 #define PCIBIOS_SUCCESSFUL 0x00
429 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
430 #define PCIBIOS_BAD_VENDOR_ID 0x83
431 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
432 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
433 #define PCIBIOS_SET_FAILED 0x88
434 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
436 /* Low-level architecture-dependent routines */
439 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
440 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
444 * ACPI needs to be able to access PCI config space before we've done a
445 * PCI bus scan and created pci_bus structures.
447 extern int raw_pci_read(unsigned int domain, unsigned int bus,
448 unsigned int devfn, int reg, int len, u32 *val);
449 extern int raw_pci_write(unsigned int domain, unsigned int bus,
450 unsigned int devfn, int reg, int len, u32 val);
452 struct pci_bus_region {
453 resource_size_t start;
458 spinlock_t lock; /* protects list, index */
459 struct list_head list; /* for IDs added at runtime */
462 /* ---------------------------------------------------------------- */
463 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
464 * a set of callbacks in struct pci_error_handlers, then that device driver
465 * will be notified of PCI bus errors, and will be driven to recovery
466 * when an error occurs.
469 typedef unsigned int __bitwise pci_ers_result_t;
471 enum pci_ers_result {
472 /* no result/none/not supported in device driver */
473 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
475 /* Device driver can recover without slot reset */
476 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
478 /* Device driver wants slot to be reset. */
479 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
481 /* Device has completely failed, is unrecoverable */
482 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
484 /* Device driver is fully recovered and operational */
485 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
488 /* PCI bus error event callbacks */
489 struct pci_error_handlers {
490 /* PCI bus error detected on this device */
491 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
492 enum pci_channel_state error);
494 /* MMIO has been re-enabled, but not DMA */
495 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
497 /* PCI Express link has been reset */
498 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
500 /* PCI slot has been reset */
501 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
503 /* Device driver may resume normal operations */
504 void (*resume)(struct pci_dev *dev);
507 /* ---------------------------------------------------------------- */
511 struct list_head node;
513 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
514 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
515 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
516 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
517 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
518 int (*resume_early) (struct pci_dev *dev);
519 int (*resume) (struct pci_dev *dev); /* Device woken up */
520 void (*shutdown) (struct pci_dev *dev);
521 struct pci_error_handlers *err_handler;
522 struct device_driver driver;
523 struct pci_dynids dynids;
526 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
529 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
530 * @_table: device table name
532 * This macro is used to create a struct pci_device_id array (a device table)
533 * in a generic manner.
535 #define DEFINE_PCI_DEVICE_TABLE(_table) \
536 const struct pci_device_id _table[] __devinitconst
539 * PCI_DEVICE - macro used to describe a specific pci device
540 * @vend: the 16 bit PCI Vendor ID
541 * @dev: the 16 bit PCI Device ID
543 * This macro is used to create a struct pci_device_id that matches a
544 * specific device. The subvendor and subdevice fields will be set to
547 #define PCI_DEVICE(vend,dev) \
548 .vendor = (vend), .device = (dev), \
549 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
552 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
553 * @dev_class: the class, subclass, prog-if triple for this device
554 * @dev_class_mask: the class mask for this device
556 * This macro is used to create a struct pci_device_id that matches a
557 * specific PCI class. The vendor, device, subvendor, and subdevice
558 * fields will be set to PCI_ANY_ID.
560 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
561 .class = (dev_class), .class_mask = (dev_class_mask), \
562 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
563 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
566 * PCI_VDEVICE - macro used to describe a specific pci device in short form
567 * @vendor: the vendor name
568 * @device: the 16 bit PCI Device ID
570 * This macro is used to create a struct pci_device_id that matches a
571 * specific PCI device. The subvendor, and subdevice fields will be set
572 * to PCI_ANY_ID. The macro allows the next field to follow as the device
576 #define PCI_VDEVICE(vendor, device) \
577 PCI_VENDOR_ID_##vendor, (device), \
578 PCI_ANY_ID, PCI_ANY_ID, 0, 0
580 /* these external functions are only available when PCI support is enabled */
583 extern struct bus_type pci_bus_type;
585 /* Do NOT directly access these two variables, unless you are arch specific pci
586 * code, or pci core code. */
587 extern struct list_head pci_root_buses; /* list of all known PCI buses */
588 /* Some device drivers need know if pci is initiated */
589 extern int no_pci_devices(void);
591 void pcibios_fixup_bus(struct pci_bus *);
592 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
593 char *pcibios_setup(char *str);
595 /* Used only when drivers/pci/setup.c is used */
596 resource_size_t pcibios_align_resource(void *, const struct resource *,
599 void pcibios_update_irq(struct pci_dev *, int irq);
601 /* Weak but can be overriden by arch */
602 void pci_fixup_cardbus(struct pci_bus *);
604 /* Generic PCI functions used internally */
606 extern struct pci_bus *pci_find_bus(int domain, int busnr);
607 void pci_bus_add_devices(const struct pci_bus *bus);
608 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
609 struct pci_ops *ops, void *sysdata);
610 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
613 struct pci_bus *root_bus;
614 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
616 pci_bus_add_devices(root_bus);
619 struct pci_bus *pci_create_bus(struct device *parent, int bus,
620 struct pci_ops *ops, void *sysdata);
621 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
623 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
624 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
626 struct hotplug_slot *hotplug);
627 void pci_destroy_slot(struct pci_slot *slot);
628 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
629 int pci_scan_slot(struct pci_bus *bus, int devfn);
630 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
631 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
632 unsigned int pci_scan_child_bus(struct pci_bus *bus);
633 int __must_check pci_bus_add_device(struct pci_dev *dev);
634 void pci_read_bridge_bases(struct pci_bus *child);
635 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
636 struct resource *res);
637 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
638 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
639 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
640 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
641 extern void pci_dev_put(struct pci_dev *dev);
642 extern void pci_remove_bus(struct pci_bus *b);
643 extern void pci_remove_bus_device(struct pci_dev *dev);
644 extern void pci_stop_bus_device(struct pci_dev *dev);
645 void pci_setup_cardbus(struct pci_bus *bus);
646 extern void pci_sort_breadthfirst(void);
648 /* Generic PCI functions exported to card drivers */
650 enum pci_lost_interrupt_reason {
651 PCI_LOST_IRQ_NO_INFORMATION = 0,
652 PCI_LOST_IRQ_DISABLE_MSI,
653 PCI_LOST_IRQ_DISABLE_MSIX,
654 PCI_LOST_IRQ_DISABLE_ACPI,
656 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
657 int pci_find_capability(struct pci_dev *dev, int cap);
658 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
659 int pci_find_ext_capability(struct pci_dev *dev, int cap);
660 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
661 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
662 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
664 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
665 struct pci_dev *from);
666 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
667 unsigned int ss_vendor, unsigned int ss_device,
668 struct pci_dev *from);
669 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
670 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
672 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
675 return pci_get_domain_bus_and_slot(0, bus, devfn);
677 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
678 int pci_dev_present(const struct pci_device_id *ids);
680 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
682 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
683 int where, u16 *val);
684 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
685 int where, u32 *val);
686 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
688 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
690 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
692 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
694 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
696 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
698 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
700 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
702 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
705 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
707 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
709 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
711 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
713 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
715 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
718 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
721 int __must_check pci_enable_device(struct pci_dev *dev);
722 int __must_check pci_enable_device_io(struct pci_dev *dev);
723 int __must_check pci_enable_device_mem(struct pci_dev *dev);
724 int __must_check pci_reenable_device(struct pci_dev *);
725 int __must_check pcim_enable_device(struct pci_dev *pdev);
726 void pcim_pin_device(struct pci_dev *pdev);
728 static inline int pci_is_enabled(struct pci_dev *pdev)
730 return (atomic_read(&pdev->enable_cnt) > 0);
733 static inline int pci_is_managed(struct pci_dev *pdev)
735 return pdev->is_managed;
738 void pci_disable_device(struct pci_dev *dev);
739 void pci_set_master(struct pci_dev *dev);
740 void pci_clear_master(struct pci_dev *dev);
741 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
742 int pci_set_cacheline_size(struct pci_dev *dev);
743 #define HAVE_PCI_SET_MWI
744 int __must_check pci_set_mwi(struct pci_dev *dev);
745 int pci_try_set_mwi(struct pci_dev *dev);
746 void pci_clear_mwi(struct pci_dev *dev);
747 void pci_intx(struct pci_dev *dev, int enable);
748 void pci_msi_off(struct pci_dev *dev);
749 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
750 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
751 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
752 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
753 int pcix_get_max_mmrbc(struct pci_dev *dev);
754 int pcix_get_mmrbc(struct pci_dev *dev);
755 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
756 int pcie_get_readrq(struct pci_dev *dev);
757 int pcie_set_readrq(struct pci_dev *dev, int rq);
758 int __pci_reset_function(struct pci_dev *dev);
759 int pci_reset_function(struct pci_dev *dev);
760 void pci_update_resource(struct pci_dev *dev, int resno);
761 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
762 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
764 /* ROM control related routines */
765 int pci_enable_rom(struct pci_dev *pdev);
766 void pci_disable_rom(struct pci_dev *pdev);
767 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
768 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
769 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
771 /* Power management related routines */
772 int pci_save_state(struct pci_dev *dev);
773 int pci_restore_state(struct pci_dev *dev);
774 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
775 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
776 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
777 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
778 void pci_pme_active(struct pci_dev *dev, bool enable);
779 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
780 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
781 pci_power_t pci_target_state(struct pci_dev *dev);
782 int pci_prepare_to_sleep(struct pci_dev *dev);
783 int pci_back_from_sleep(struct pci_dev *dev);
785 /* For use by arch with custom probe code */
786 void set_pcie_port_type(struct pci_dev *pdev);
787 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
789 /* Functions for PCI Hotplug drivers to use */
790 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
791 #ifdef CONFIG_HOTPLUG
792 unsigned int pci_rescan_bus(struct pci_bus *bus);
795 /* Vital product data routines */
796 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
797 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
798 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
800 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
801 void pci_bus_assign_resources(const struct pci_bus *bus);
802 void pci_bus_size_bridges(struct pci_bus *bus);
803 int pci_claim_resource(struct pci_dev *, int);
804 void pci_assign_unassigned_resources(void);
805 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
806 void pdev_enable_device(struct pci_dev *);
807 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
808 int pci_enable_resources(struct pci_dev *, int mask);
809 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
810 int (*)(struct pci_dev *, u8, u8));
811 #define HAVE_PCI_REQ_REGIONS 2
812 int __must_check pci_request_regions(struct pci_dev *, const char *);
813 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
814 void pci_release_regions(struct pci_dev *);
815 int __must_check pci_request_region(struct pci_dev *, int, const char *);
816 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
817 void pci_release_region(struct pci_dev *, int);
818 int pci_request_selected_regions(struct pci_dev *, int, const char *);
819 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
820 void pci_release_selected_regions(struct pci_dev *, int);
822 /* drivers/pci/bus.c */
823 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
824 struct resource *res, resource_size_t size,
825 resource_size_t align, resource_size_t min,
826 unsigned int type_mask,
827 resource_size_t (*alignf)(void *,
828 const struct resource *,
832 void pci_enable_bridges(struct pci_bus *bus);
834 /* Proper probing supporting hot-pluggable devices */
835 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
836 const char *mod_name);
839 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
841 #define pci_register_driver(driver) \
842 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
844 void pci_unregister_driver(struct pci_driver *dev);
845 void pci_remove_behind_bridge(struct pci_dev *dev);
846 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
847 int pci_add_dynid(struct pci_driver *drv,
848 unsigned int vendor, unsigned int device,
849 unsigned int subvendor, unsigned int subdevice,
850 unsigned int class, unsigned int class_mask,
851 unsigned long driver_data);
852 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
853 struct pci_dev *dev);
854 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
857 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
859 int pci_cfg_space_size_ext(struct pci_dev *dev);
860 int pci_cfg_space_size(struct pci_dev *dev);
861 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
863 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
864 unsigned int command_bits, bool change_bridge);
865 /* kmem_cache style wrapper around pci_alloc_consistent() */
867 #include <linux/dmapool.h>
869 #define pci_pool dma_pool
870 #define pci_pool_create(name, pdev, size, align, allocation) \
871 dma_pool_create(name, &pdev->dev, size, align, allocation)
872 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
873 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
874 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
876 enum pci_dma_burst_strategy {
877 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
878 strategy_parameter is N/A */
879 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
881 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
882 strategy_parameter byte boundaries */
886 u32 vector; /* kernel uses to write allocated vector */
887 u16 entry; /* driver uses to specify entry, OS writes */
891 #ifndef CONFIG_PCI_MSI
892 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
897 static inline void pci_msi_shutdown(struct pci_dev *dev)
899 static inline void pci_disable_msi(struct pci_dev *dev)
902 static inline int pci_msix_table_size(struct pci_dev *dev)
906 static inline int pci_enable_msix(struct pci_dev *dev,
907 struct msix_entry *entries, int nvec)
912 static inline void pci_msix_shutdown(struct pci_dev *dev)
914 static inline void pci_disable_msix(struct pci_dev *dev)
917 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
920 static inline void pci_restore_msi_state(struct pci_dev *dev)
922 static inline int pci_msi_enabled(void)
927 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
928 extern void pci_msi_shutdown(struct pci_dev *dev);
929 extern void pci_disable_msi(struct pci_dev *dev);
930 extern int pci_msix_table_size(struct pci_dev *dev);
931 extern int pci_enable_msix(struct pci_dev *dev,
932 struct msix_entry *entries, int nvec);
933 extern void pci_msix_shutdown(struct pci_dev *dev);
934 extern void pci_disable_msix(struct pci_dev *dev);
935 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
936 extern void pci_restore_msi_state(struct pci_dev *dev);
937 extern int pci_msi_enabled(void);
940 #ifndef CONFIG_PCIEASPM
941 static inline int pcie_aspm_enabled(void)
946 extern int pcie_aspm_enabled(void);
949 #ifndef CONFIG_PCIE_ECRC
950 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
954 static inline void pcie_ecrc_get_policy(char *str) {};
956 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
957 extern void pcie_ecrc_get_policy(char *str);
960 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
963 /* The functions a driver should call */
964 int ht_create_irq(struct pci_dev *dev, int idx);
965 void ht_destroy_irq(unsigned int irq);
966 #endif /* CONFIG_HT_IRQ */
968 extern void pci_block_user_cfg_access(struct pci_dev *dev);
969 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
972 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
973 * a PCI domain is defined to be a set of PCI busses which share
974 * configuration space.
976 #ifdef CONFIG_PCI_DOMAINS
977 extern int pci_domains_supported;
979 enum { pci_domains_supported = 0 };
980 static inline int pci_domain_nr(struct pci_bus *bus)
985 static inline int pci_proc_domain(struct pci_bus *bus)
989 #endif /* CONFIG_PCI_DOMAINS */
991 #else /* CONFIG_PCI is not enabled */
994 * If the system does not have PCI, clearly these return errors. Define
995 * these as simple inline functions to avoid hair in drivers.
998 #define _PCI_NOP(o, s, t) \
999 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1001 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1003 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1004 _PCI_NOP(o, word, u16 x) \
1005 _PCI_NOP(o, dword, u32 x)
1006 _PCI_NOP_ALL(read, *)
1007 _PCI_NOP_ALL(write,)
1009 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1010 unsigned int device,
1011 struct pci_dev *from)
1016 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1017 unsigned int device,
1018 unsigned int ss_vendor,
1019 unsigned int ss_device,
1020 struct pci_dev *from)
1025 static inline struct pci_dev *pci_get_class(unsigned int class,
1026 struct pci_dev *from)
1031 #define pci_dev_present(ids) (0)
1032 #define no_pci_devices() (1)
1033 #define pci_dev_put(dev) do { } while (0)
1035 static inline void pci_set_master(struct pci_dev *dev)
1038 static inline int pci_enable_device(struct pci_dev *dev)
1043 static inline void pci_disable_device(struct pci_dev *dev)
1046 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1051 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1056 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1062 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1068 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1073 static inline int __pci_register_driver(struct pci_driver *drv,
1074 struct module *owner)
1079 static inline int pci_register_driver(struct pci_driver *drv)
1084 static inline void pci_unregister_driver(struct pci_driver *drv)
1087 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1092 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1098 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1103 /* Power management related routines */
1104 static inline int pci_save_state(struct pci_dev *dev)
1109 static inline int pci_restore_state(struct pci_dev *dev)
1114 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1119 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1125 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1131 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1136 static inline void pci_release_regions(struct pci_dev *dev)
1139 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1141 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1144 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1147 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1150 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1154 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1158 #endif /* CONFIG_PCI */
1160 /* Include architecture-dependent settings and functions */
1162 #include <asm/pci.h>
1164 #ifndef PCIBIOS_MAX_MEM_32
1165 #define PCIBIOS_MAX_MEM_32 (-1)
1168 /* these helpers provide future and backwards compatibility
1169 * for accessing popular PCI BAR info */
1170 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1171 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1172 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1173 #define pci_resource_len(dev,bar) \
1174 ((pci_resource_start((dev), (bar)) == 0 && \
1175 pci_resource_end((dev), (bar)) == \
1176 pci_resource_start((dev), (bar))) ? 0 : \
1178 (pci_resource_end((dev), (bar)) - \
1179 pci_resource_start((dev), (bar)) + 1))
1181 /* Similar to the helpers above, these manipulate per-pci_dev
1182 * driver-specific data. They are really just a wrapper around
1183 * the generic device structure functions of these calls.
1185 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1187 return dev_get_drvdata(&pdev->dev);
1190 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1192 dev_set_drvdata(&pdev->dev, data);
1195 /* If you want to know what to call your pci_dev, ask this function.
1196 * Again, it's a wrapper around the generic device.
1198 static inline const char *pci_name(const struct pci_dev *pdev)
1200 return dev_name(&pdev->dev);
1204 /* Some archs don't want to expose struct resource to userland as-is
1205 * in sysfs and /proc
1207 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1208 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1209 const struct resource *rsrc, resource_size_t *start,
1210 resource_size_t *end)
1212 *start = rsrc->start;
1215 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1219 * The world is not perfect and supplies us with broken PCI devices.
1220 * For at least a part of these bugs we need a work-around, so both
1221 * generic (drivers/pci/quirks.c) and per-architecture code can define
1222 * fixup hooks to be called for particular buggy devices.
1226 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1227 void (*hook)(struct pci_dev *dev);
1230 enum pci_fixup_pass {
1231 pci_fixup_early, /* Before probing BARs */
1232 pci_fixup_header, /* After reading configuration header */
1233 pci_fixup_final, /* Final phase of device fixups */
1234 pci_fixup_enable, /* pci_enable_device() time */
1235 pci_fixup_resume, /* pci_device_resume() */
1236 pci_fixup_suspend, /* pci_device_suspend */
1237 pci_fixup_resume_early, /* pci_device_resume_early() */
1240 /* Anonymous variables would be nice... */
1241 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1242 static const struct pci_fixup __pci_fixup_##name __used \
1243 __attribute__((__section__(#section))) = { vendor, device, hook };
1244 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1245 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1246 vendor##device##hook, vendor, device, hook)
1247 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1248 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1249 vendor##device##hook, vendor, device, hook)
1250 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1251 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1252 vendor##device##hook, vendor, device, hook)
1253 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1254 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1255 vendor##device##hook, vendor, device, hook)
1256 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1257 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1258 resume##vendor##device##hook, vendor, device, hook)
1259 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1260 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1261 resume_early##vendor##device##hook, vendor, device, hook)
1262 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1263 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1264 suspend##vendor##device##hook, vendor, device, hook)
1266 #ifdef CONFIG_PCI_QUIRKS
1267 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1269 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1270 struct pci_dev *dev) {}
1273 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1274 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1275 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1276 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1277 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1279 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1281 extern int pci_pci_problems;
1282 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1283 #define PCIPCI_TRITON 2
1284 #define PCIPCI_NATOMA 4
1285 #define PCIPCI_VIAETBF 8
1286 #define PCIPCI_VSFX 16
1287 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1288 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1290 extern unsigned long pci_cardbus_io_size;
1291 extern unsigned long pci_cardbus_mem_size;
1292 extern u8 __devinitdata pci_dfl_cache_line_size;
1293 extern u8 pci_cache_line_size;
1295 extern unsigned long pci_hotplug_io_size;
1296 extern unsigned long pci_hotplug_mem_size;
1298 int pcibios_add_platform_entries(struct pci_dev *dev);
1299 void pcibios_disable_device(struct pci_dev *dev);
1300 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1301 enum pcie_reset_state state);
1303 #ifdef CONFIG_PCI_MMCONFIG
1304 extern void __init pci_mmcfg_early_init(void);
1305 extern void __init pci_mmcfg_late_init(void);
1307 static inline void pci_mmcfg_early_init(void) { }
1308 static inline void pci_mmcfg_late_init(void) { }
1311 int pci_ext_cfg_avail(struct pci_dev *dev);
1313 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1315 #ifdef CONFIG_PCI_IOV
1316 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1317 extern void pci_disable_sriov(struct pci_dev *dev);
1318 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1320 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1324 static inline void pci_disable_sriov(struct pci_dev *dev)
1327 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1333 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1334 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1335 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1339 * pci_pcie_cap - get the saved PCIe capability offset
1342 * PCIe capability offset is calculated at PCI device initialization
1343 * time and saved in the data structure. This function returns saved
1344 * PCIe capability offset. Using this instead of pci_find_capability()
1345 * reduces unnecessary search in the PCI configuration space. If you
1346 * need to calculate PCIe capability offset from raw device for some
1347 * reasons, please use pci_find_capability() instead.
1349 static inline int pci_pcie_cap(struct pci_dev *dev)
1351 return dev->pcie_cap;
1355 * pci_is_pcie - check if the PCI device is PCI Express capable
1358 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1360 static inline bool pci_is_pcie(struct pci_dev *dev)
1362 return !!pci_pcie_cap(dev);
1365 void pci_request_acs(void);
1367 #endif /* __KERNEL__ */
1368 #endif /* LINUX_PCI_H */