4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/pci_regs.h> /* The pci register defines */
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
43 #include <linux/mod_devicetable.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <asm/atomic.h>
53 #include <linux/device.h>
55 #include <linux/irqreturn.h>
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
60 /* pci_slot represents a physical slot */
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
71 return kobject_name(&slot->kobj);
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
87 * For PCI devices, the region numbers are assigned this way:
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = 5,
94 /* #6: expansion ROM resource */
97 /* device specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* total resources associated with a PCI device */
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
117 typedef int __bitwise pci_power_t;
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
130 static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state];
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
143 typedef unsigned int __bitwise pci_channel_state_t;
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
156 typedef unsigned int __bitwise pcie_reset_state_t;
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
169 typedef unsigned short __bitwise pci_dev_flags_t;
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
179 enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
184 typedef unsigned short __bitwise pci_bus_flags_t;
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
190 /* Based on the PCI Hotplug Spec, but some values are made up by us */
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 PCI_SPEED_66MHz_PCIX_533 = 0x11,
204 PCI_SPEED_100MHz_PCIX_533 = 0x12,
205 PCI_SPEED_133MHz_PCIX_533 = 0x13,
206 PCIE_SPEED_2_5GT = 0x14,
207 PCIE_SPEED_5_0GT = 0x15,
208 PCI_SPEED_UNKNOWN = 0xff,
211 struct pci_cap_saved_state {
212 struct hlist_node next;
217 struct pcie_link_state;
223 * The pci_dev structure is used to describe PCI devices.
226 struct list_head bus_list; /* node in per-bus list */
227 struct pci_bus *bus; /* bus this device is on */
228 struct pci_bus *subordinate; /* bus this device bridges to */
230 void *sysdata; /* hook for sys-specific extension */
231 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
232 struct pci_slot *slot; /* Physical slot this device is in */
234 unsigned int devfn; /* encoded device & function index */
235 unsigned short vendor;
236 unsigned short device;
237 unsigned short subsystem_vendor;
238 unsigned short subsystem_device;
239 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
240 u8 revision; /* PCI revision, low byte of class word */
241 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
242 u8 pcie_cap; /* PCI-E capability offset */
243 u8 pcie_type; /* PCI-E device/port type */
244 u8 rom_base_reg; /* which config register controls the ROM */
245 u8 pin; /* which interrupt pin this device uses */
247 struct pci_driver *driver; /* which driver has allocated this device */
248 u64 dma_mask; /* Mask of the bits of bus address this
249 device implements. Normally this is
250 0xffffffff. You only need to change
251 this if your device has broken DMA
252 or supports 64-bit transfers. */
254 struct device_dma_parameters dma_parms;
256 pci_power_t current_state; /* Current operating state. In ACPI-speak,
257 this is D0-D3, D0 being fully functional,
259 int pm_cap; /* PM capability offset in the
260 configuration space */
261 unsigned int pme_support:5; /* Bitmask of states from which PME#
263 unsigned int d1_support:1; /* Low power state D1 is supported */
264 unsigned int d2_support:1; /* Low power state D2 is supported */
265 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
266 unsigned int wakeup_prepared:1;
267 unsigned int d3_delay; /* D3->D0 transition time in ms */
269 #ifdef CONFIG_PCIEASPM
270 struct pcie_link_state *link_state; /* ASPM link state. */
273 pci_channel_state_t error_state; /* current connectivity state */
274 struct device dev; /* Generic device interface */
276 int cfg_size; /* Size of configuration space */
279 * Instead of touching interrupt line and base address registers
280 * directly, use the values stored here. They might be different!
283 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
285 /* These fields are used by common fixups */
286 unsigned int transparent:1; /* Transparent PCI bridge */
287 unsigned int multifunction:1;/* Part of multi-function device */
288 /* keep track of device state */
289 unsigned int is_added:1;
290 unsigned int is_busmaster:1; /* device is busmaster */
291 unsigned int no_msi:1; /* device may not use msi */
292 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
293 unsigned int broken_parity_status:1; /* Device generates false positive parity */
294 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
295 unsigned int msi_enabled:1;
296 unsigned int msix_enabled:1;
297 unsigned int ari_enabled:1; /* ARI forwarding */
298 unsigned int is_managed:1;
299 unsigned int is_pcie:1;
300 unsigned int needs_freset:1; /* Dev requires fundamental reset */
301 unsigned int state_saved:1;
302 unsigned int is_physfn:1;
303 unsigned int is_virtfn:1;
304 unsigned int reset_fn:1;
305 unsigned int is_hotplug_bridge:1;
306 unsigned int aer_firmware_first:1;
307 pci_dev_flags_t dev_flags;
308 atomic_t enable_cnt; /* pci_enable_device has been called */
310 u32 saved_config_space[16]; /* config space saved at suspend time */
311 struct hlist_head saved_cap_space;
312 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
313 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
314 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
315 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
316 #ifdef CONFIG_PCI_MSI
317 struct list_head msi_list;
320 #ifdef CONFIG_PCI_IOV
322 struct pci_sriov *sriov; /* SR-IOV capability related */
323 struct pci_dev *physfn; /* the PF this VF is associated with */
325 struct pci_ats *ats; /* Address Translation Service */
329 extern struct pci_dev *alloc_pci_dev(void);
331 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
332 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
333 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
335 static inline int pci_channel_offline(struct pci_dev *pdev)
337 return (pdev->error_state != pci_channel_io_normal);
340 static inline struct pci_cap_saved_state *pci_find_saved_cap(
341 struct pci_dev *pci_dev, char cap)
343 struct pci_cap_saved_state *tmp;
344 struct hlist_node *pos;
346 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
347 if (tmp->cap_nr == cap)
353 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
354 struct pci_cap_saved_state *new_cap)
356 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
359 #ifndef PCI_BUS_NUM_RESOURCES
360 #define PCI_BUS_NUM_RESOURCES 16
363 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
366 struct list_head node; /* node in list of buses */
367 struct pci_bus *parent; /* parent bus this bridge is on */
368 struct list_head children; /* list of child buses */
369 struct list_head devices; /* list of devices on this bus */
370 struct pci_dev *self; /* bridge device as seen by parent */
371 struct list_head slots; /* list of slots on this bus */
372 struct resource *resource[PCI_BUS_NUM_RESOURCES];
373 /* address space routed to this bus */
375 struct pci_ops *ops; /* configuration access functions */
376 void *sysdata; /* hook for sys-specific extension */
377 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
379 unsigned char number; /* bus number */
380 unsigned char primary; /* number of primary bridge */
381 unsigned char secondary; /* number of secondary bridge */
382 unsigned char subordinate; /* max number of subordinate buses */
386 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
387 pci_bus_flags_t bus_flags; /* Inherited by child busses */
388 struct device *bridge;
390 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
391 struct bin_attribute *legacy_mem; /* legacy mem */
392 unsigned int is_added:1;
395 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
396 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
399 * Returns true if the pci bus is root (behind host-pci bridge),
402 static inline bool pci_is_root_bus(struct pci_bus *pbus)
404 return !(pbus->parent);
407 #ifdef CONFIG_PCI_MSI
408 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
410 return pci_dev->msi_enabled || pci_dev->msix_enabled;
413 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
417 * Error values that may be returned by PCI functions.
419 #define PCIBIOS_SUCCESSFUL 0x00
420 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
421 #define PCIBIOS_BAD_VENDOR_ID 0x83
422 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
423 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
424 #define PCIBIOS_SET_FAILED 0x88
425 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
427 /* Low-level architecture-dependent routines */
430 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
431 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
435 * ACPI needs to be able to access PCI config space before we've done a
436 * PCI bus scan and created pci_bus structures.
438 extern int raw_pci_read(unsigned int domain, unsigned int bus,
439 unsigned int devfn, int reg, int len, u32 *val);
440 extern int raw_pci_write(unsigned int domain, unsigned int bus,
441 unsigned int devfn, int reg, int len, u32 val);
443 struct pci_bus_region {
444 resource_size_t start;
449 spinlock_t lock; /* protects list, index */
450 struct list_head list; /* for IDs added at runtime */
453 /* ---------------------------------------------------------------- */
454 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
455 * a set of callbacks in struct pci_error_handlers, then that device driver
456 * will be notified of PCI bus errors, and will be driven to recovery
457 * when an error occurs.
460 typedef unsigned int __bitwise pci_ers_result_t;
462 enum pci_ers_result {
463 /* no result/none/not supported in device driver */
464 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
466 /* Device driver can recover without slot reset */
467 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
469 /* Device driver wants slot to be reset. */
470 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
472 /* Device has completely failed, is unrecoverable */
473 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
475 /* Device driver is fully recovered and operational */
476 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
479 /* PCI bus error event callbacks */
480 struct pci_error_handlers {
481 /* PCI bus error detected on this device */
482 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
483 enum pci_channel_state error);
485 /* MMIO has been re-enabled, but not DMA */
486 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
488 /* PCI Express link has been reset */
489 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
491 /* PCI slot has been reset */
492 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
494 /* Device driver may resume normal operations */
495 void (*resume)(struct pci_dev *dev);
498 /* ---------------------------------------------------------------- */
502 struct list_head node;
504 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
505 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
506 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
507 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
508 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
509 int (*resume_early) (struct pci_dev *dev);
510 int (*resume) (struct pci_dev *dev); /* Device woken up */
511 void (*shutdown) (struct pci_dev *dev);
512 struct pci_error_handlers *err_handler;
513 struct device_driver driver;
514 struct pci_dynids dynids;
517 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
520 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
521 * @_table: device table name
523 * This macro is used to create a struct pci_device_id array (a device table)
524 * in a generic manner.
526 #define DEFINE_PCI_DEVICE_TABLE(_table) \
527 const struct pci_device_id _table[] __devinitconst
530 * PCI_DEVICE - macro used to describe a specific pci device
531 * @vend: the 16 bit PCI Vendor ID
532 * @dev: the 16 bit PCI Device ID
534 * This macro is used to create a struct pci_device_id that matches a
535 * specific device. The subvendor and subdevice fields will be set to
538 #define PCI_DEVICE(vend,dev) \
539 .vendor = (vend), .device = (dev), \
540 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
543 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
544 * @dev_class: the class, subclass, prog-if triple for this device
545 * @dev_class_mask: the class mask for this device
547 * This macro is used to create a struct pci_device_id that matches a
548 * specific PCI class. The vendor, device, subvendor, and subdevice
549 * fields will be set to PCI_ANY_ID.
551 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
552 .class = (dev_class), .class_mask = (dev_class_mask), \
553 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
554 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
557 * PCI_VDEVICE - macro used to describe a specific pci device in short form
558 * @vendor: the vendor name
559 * @device: the 16 bit PCI Device ID
561 * This macro is used to create a struct pci_device_id that matches a
562 * specific PCI device. The subvendor, and subdevice fields will be set
563 * to PCI_ANY_ID. The macro allows the next field to follow as the device
567 #define PCI_VDEVICE(vendor, device) \
568 PCI_VENDOR_ID_##vendor, (device), \
569 PCI_ANY_ID, PCI_ANY_ID, 0, 0
571 /* these external functions are only available when PCI support is enabled */
574 extern struct bus_type pci_bus_type;
576 /* Do NOT directly access these two variables, unless you are arch specific pci
577 * code, or pci core code. */
578 extern struct list_head pci_root_buses; /* list of all known PCI buses */
579 /* Some device drivers need know if pci is initiated */
580 extern int no_pci_devices(void);
582 void pcibios_fixup_bus(struct pci_bus *);
583 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
584 char *pcibios_setup(char *str);
586 /* Used only when drivers/pci/setup.c is used */
587 void pcibios_align_resource(void *, struct resource *, resource_size_t,
589 void pcibios_update_irq(struct pci_dev *, int irq);
591 /* Weak but can be overriden by arch */
592 void pci_fixup_cardbus(struct pci_bus *);
594 /* Generic PCI functions used internally */
596 extern struct pci_bus *pci_find_bus(int domain, int busnr);
597 void pci_bus_add_devices(const struct pci_bus *bus);
598 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
599 struct pci_ops *ops, void *sysdata);
600 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
603 struct pci_bus *root_bus;
604 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
606 pci_bus_add_devices(root_bus);
609 struct pci_bus *pci_create_bus(struct device *parent, int bus,
610 struct pci_ops *ops, void *sysdata);
611 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
613 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
615 struct hotplug_slot *hotplug);
616 void pci_destroy_slot(struct pci_slot *slot);
617 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
618 int pci_scan_slot(struct pci_bus *bus, int devfn);
619 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
620 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
621 unsigned int pci_scan_child_bus(struct pci_bus *bus);
622 int __must_check pci_bus_add_device(struct pci_dev *dev);
623 void pci_read_bridge_bases(struct pci_bus *child);
624 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
625 struct resource *res);
626 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
627 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
628 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
629 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
630 extern void pci_dev_put(struct pci_dev *dev);
631 extern void pci_remove_bus(struct pci_bus *b);
632 extern void pci_remove_bus_device(struct pci_dev *dev);
633 extern void pci_stop_bus_device(struct pci_dev *dev);
634 void pci_setup_cardbus(struct pci_bus *bus);
635 extern void pci_sort_breadthfirst(void);
637 /* Generic PCI functions exported to card drivers */
639 #ifdef CONFIG_PCI_LEGACY
640 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
642 struct pci_dev *from);
643 #endif /* CONFIG_PCI_LEGACY */
645 enum pci_lost_interrupt_reason {
646 PCI_LOST_IRQ_NO_INFORMATION = 0,
647 PCI_LOST_IRQ_DISABLE_MSI,
648 PCI_LOST_IRQ_DISABLE_MSIX,
649 PCI_LOST_IRQ_DISABLE_ACPI,
651 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
652 int pci_find_capability(struct pci_dev *dev, int cap);
653 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
654 int pci_find_ext_capability(struct pci_dev *dev, int cap);
655 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
656 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
657 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
659 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
660 struct pci_dev *from);
661 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
662 unsigned int ss_vendor, unsigned int ss_device,
663 struct pci_dev *from);
664 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
665 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
667 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
670 return pci_get_domain_bus_and_slot(0, bus, devfn);
672 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
673 int pci_dev_present(const struct pci_device_id *ids);
675 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
677 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
678 int where, u16 *val);
679 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
680 int where, u32 *val);
681 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
683 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
685 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
687 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
689 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
691 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
693 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
695 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
697 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
700 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
702 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
704 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
706 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
708 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
710 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
713 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
716 int __must_check pci_enable_device(struct pci_dev *dev);
717 int __must_check pci_enable_device_io(struct pci_dev *dev);
718 int __must_check pci_enable_device_mem(struct pci_dev *dev);
719 int __must_check pci_reenable_device(struct pci_dev *);
720 int __must_check pcim_enable_device(struct pci_dev *pdev);
721 void pcim_pin_device(struct pci_dev *pdev);
723 static inline int pci_is_enabled(struct pci_dev *pdev)
725 return (atomic_read(&pdev->enable_cnt) > 0);
728 static inline int pci_is_managed(struct pci_dev *pdev)
730 return pdev->is_managed;
733 void pci_disable_device(struct pci_dev *dev);
734 void pci_set_master(struct pci_dev *dev);
735 void pci_clear_master(struct pci_dev *dev);
736 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
737 int pci_set_cacheline_size(struct pci_dev *dev);
738 #define HAVE_PCI_SET_MWI
739 int __must_check pci_set_mwi(struct pci_dev *dev);
740 int pci_try_set_mwi(struct pci_dev *dev);
741 void pci_clear_mwi(struct pci_dev *dev);
742 void pci_intx(struct pci_dev *dev, int enable);
743 void pci_msi_off(struct pci_dev *dev);
744 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
745 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
746 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
747 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
748 int pcix_get_max_mmrbc(struct pci_dev *dev);
749 int pcix_get_mmrbc(struct pci_dev *dev);
750 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
751 int pcie_get_readrq(struct pci_dev *dev);
752 int pcie_set_readrq(struct pci_dev *dev, int rq);
753 int __pci_reset_function(struct pci_dev *dev);
754 int pci_reset_function(struct pci_dev *dev);
755 void pci_update_resource(struct pci_dev *dev, int resno);
756 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
757 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
759 /* ROM control related routines */
760 int pci_enable_rom(struct pci_dev *pdev);
761 void pci_disable_rom(struct pci_dev *pdev);
762 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
763 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
764 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
766 /* Power management related routines */
767 int pci_save_state(struct pci_dev *dev);
768 int pci_restore_state(struct pci_dev *dev);
769 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
770 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
771 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
772 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
773 void pci_pme_active(struct pci_dev *dev, bool enable);
774 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
775 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
776 pci_power_t pci_target_state(struct pci_dev *dev);
777 int pci_prepare_to_sleep(struct pci_dev *dev);
778 int pci_back_from_sleep(struct pci_dev *dev);
780 /* For use by arch with custom probe code */
781 void set_pcie_port_type(struct pci_dev *pdev);
782 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
784 /* Functions for PCI Hotplug drivers to use */
785 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
786 #ifdef CONFIG_HOTPLUG
787 unsigned int pci_rescan_bus(struct pci_bus *bus);
790 /* Vital product data routines */
791 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
792 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
793 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
795 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
796 void pci_bus_assign_resources(const struct pci_bus *bus);
797 void pci_bus_size_bridges(struct pci_bus *bus);
798 int pci_claim_resource(struct pci_dev *, int);
799 void pci_assign_unassigned_resources(void);
800 void pdev_enable_device(struct pci_dev *);
801 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
802 int pci_enable_resources(struct pci_dev *, int mask);
803 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
804 int (*)(struct pci_dev *, u8, u8));
805 #define HAVE_PCI_REQ_REGIONS 2
806 int __must_check pci_request_regions(struct pci_dev *, const char *);
807 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
808 void pci_release_regions(struct pci_dev *);
809 int __must_check pci_request_region(struct pci_dev *, int, const char *);
810 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
811 void pci_release_region(struct pci_dev *, int);
812 int pci_request_selected_regions(struct pci_dev *, int, const char *);
813 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
814 void pci_release_selected_regions(struct pci_dev *, int);
816 /* drivers/pci/bus.c */
817 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
818 struct resource *res, resource_size_t size,
819 resource_size_t align, resource_size_t min,
820 unsigned int type_mask,
821 void (*alignf)(void *, struct resource *,
822 resource_size_t, resource_size_t),
824 void pci_enable_bridges(struct pci_bus *bus);
826 /* Proper probing supporting hot-pluggable devices */
827 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
828 const char *mod_name);
831 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
833 #define pci_register_driver(driver) \
834 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
836 void pci_unregister_driver(struct pci_driver *dev);
837 void pci_remove_behind_bridge(struct pci_dev *dev);
838 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
839 int pci_add_dynid(struct pci_driver *drv,
840 unsigned int vendor, unsigned int device,
841 unsigned int subvendor, unsigned int subdevice,
842 unsigned int class, unsigned int class_mask,
843 unsigned long driver_data);
844 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
845 struct pci_dev *dev);
846 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
849 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
851 int pci_cfg_space_size_ext(struct pci_dev *dev);
852 int pci_cfg_space_size(struct pci_dev *dev);
853 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
855 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
856 unsigned int command_bits, bool change_bridge);
857 /* kmem_cache style wrapper around pci_alloc_consistent() */
859 #include <linux/dmapool.h>
861 #define pci_pool dma_pool
862 #define pci_pool_create(name, pdev, size, align, allocation) \
863 dma_pool_create(name, &pdev->dev, size, align, allocation)
864 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
865 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
866 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
868 enum pci_dma_burst_strategy {
869 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
870 strategy_parameter is N/A */
871 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
873 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
874 strategy_parameter byte boundaries */
878 u32 vector; /* kernel uses to write allocated vector */
879 u16 entry; /* driver uses to specify entry, OS writes */
883 #ifndef CONFIG_PCI_MSI
884 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
889 static inline void pci_msi_shutdown(struct pci_dev *dev)
891 static inline void pci_disable_msi(struct pci_dev *dev)
894 static inline int pci_msix_table_size(struct pci_dev *dev)
898 static inline int pci_enable_msix(struct pci_dev *dev,
899 struct msix_entry *entries, int nvec)
904 static inline void pci_msix_shutdown(struct pci_dev *dev)
906 static inline void pci_disable_msix(struct pci_dev *dev)
909 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
912 static inline void pci_restore_msi_state(struct pci_dev *dev)
914 static inline int pci_msi_enabled(void)
919 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
920 extern void pci_msi_shutdown(struct pci_dev *dev);
921 extern void pci_disable_msi(struct pci_dev *dev);
922 extern int pci_msix_table_size(struct pci_dev *dev);
923 extern int pci_enable_msix(struct pci_dev *dev,
924 struct msix_entry *entries, int nvec);
925 extern void pci_msix_shutdown(struct pci_dev *dev);
926 extern void pci_disable_msix(struct pci_dev *dev);
927 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
928 extern void pci_restore_msi_state(struct pci_dev *dev);
929 extern int pci_msi_enabled(void);
932 #ifndef CONFIG_PCIEASPM
933 static inline int pcie_aspm_enabled(void)
938 extern int pcie_aspm_enabled(void);
941 #ifndef CONFIG_PCIE_ECRC
942 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
946 static inline void pcie_ecrc_get_policy(char *str) {};
948 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
949 extern void pcie_ecrc_get_policy(char *str);
952 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
955 /* The functions a driver should call */
956 int ht_create_irq(struct pci_dev *dev, int idx);
957 void ht_destroy_irq(unsigned int irq);
958 #endif /* CONFIG_HT_IRQ */
960 extern void pci_block_user_cfg_access(struct pci_dev *dev);
961 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
964 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
965 * a PCI domain is defined to be a set of PCI busses which share
966 * configuration space.
968 #ifdef CONFIG_PCI_DOMAINS
969 extern int pci_domains_supported;
971 enum { pci_domains_supported = 0 };
972 static inline int pci_domain_nr(struct pci_bus *bus)
977 static inline int pci_proc_domain(struct pci_bus *bus)
981 #endif /* CONFIG_PCI_DOMAINS */
983 #else /* CONFIG_PCI is not enabled */
986 * If the system does not have PCI, clearly these return errors. Define
987 * these as simple inline functions to avoid hair in drivers.
990 #define _PCI_NOP(o, s, t) \
991 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
993 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
995 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
996 _PCI_NOP(o, word, u16 x) \
997 _PCI_NOP(o, dword, u32 x)
998 _PCI_NOP_ALL(read, *)
1001 static inline struct pci_dev *pci_find_device(unsigned int vendor,
1002 unsigned int device,
1003 struct pci_dev *from)
1008 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1009 unsigned int device,
1010 struct pci_dev *from)
1015 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1016 unsigned int device,
1017 unsigned int ss_vendor,
1018 unsigned int ss_device,
1019 struct pci_dev *from)
1024 static inline struct pci_dev *pci_get_class(unsigned int class,
1025 struct pci_dev *from)
1030 #define pci_dev_present(ids) (0)
1031 #define no_pci_devices() (1)
1032 #define pci_dev_put(dev) do { } while (0)
1034 static inline void pci_set_master(struct pci_dev *dev)
1037 static inline int pci_enable_device(struct pci_dev *dev)
1042 static inline void pci_disable_device(struct pci_dev *dev)
1045 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1050 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1055 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1061 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1067 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1072 static inline int __pci_register_driver(struct pci_driver *drv,
1073 struct module *owner)
1078 static inline int pci_register_driver(struct pci_driver *drv)
1083 static inline void pci_unregister_driver(struct pci_driver *drv)
1086 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1091 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1097 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1102 /* Power management related routines */
1103 static inline int pci_save_state(struct pci_dev *dev)
1108 static inline int pci_restore_state(struct pci_dev *dev)
1113 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1118 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1124 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1130 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1135 static inline void pci_release_regions(struct pci_dev *dev)
1138 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1140 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1143 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1146 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1149 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1153 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1157 #endif /* CONFIG_PCI */
1159 /* Include architecture-dependent settings and functions */
1161 #include <asm/pci.h>
1163 #ifndef PCIBIOS_MAX_MEM_32
1164 #define PCIBIOS_MAX_MEM_32 (-1)
1167 /* these helpers provide future and backwards compatibility
1168 * for accessing popular PCI BAR info */
1169 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1170 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1171 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1172 #define pci_resource_len(dev,bar) \
1173 ((pci_resource_start((dev), (bar)) == 0 && \
1174 pci_resource_end((dev), (bar)) == \
1175 pci_resource_start((dev), (bar))) ? 0 : \
1177 (pci_resource_end((dev), (bar)) - \
1178 pci_resource_start((dev), (bar)) + 1))
1180 /* Similar to the helpers above, these manipulate per-pci_dev
1181 * driver-specific data. They are really just a wrapper around
1182 * the generic device structure functions of these calls.
1184 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1186 return dev_get_drvdata(&pdev->dev);
1189 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1191 dev_set_drvdata(&pdev->dev, data);
1194 /* If you want to know what to call your pci_dev, ask this function.
1195 * Again, it's a wrapper around the generic device.
1197 static inline const char *pci_name(const struct pci_dev *pdev)
1199 return dev_name(&pdev->dev);
1203 /* Some archs don't want to expose struct resource to userland as-is
1204 * in sysfs and /proc
1206 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1207 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1208 const struct resource *rsrc, resource_size_t *start,
1209 resource_size_t *end)
1211 *start = rsrc->start;
1214 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1218 * The world is not perfect and supplies us with broken PCI devices.
1219 * For at least a part of these bugs we need a work-around, so both
1220 * generic (drivers/pci/quirks.c) and per-architecture code can define
1221 * fixup hooks to be called for particular buggy devices.
1225 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1226 void (*hook)(struct pci_dev *dev);
1229 enum pci_fixup_pass {
1230 pci_fixup_early, /* Before probing BARs */
1231 pci_fixup_header, /* After reading configuration header */
1232 pci_fixup_final, /* Final phase of device fixups */
1233 pci_fixup_enable, /* pci_enable_device() time */
1234 pci_fixup_resume, /* pci_device_resume() */
1235 pci_fixup_suspend, /* pci_device_suspend */
1236 pci_fixup_resume_early, /* pci_device_resume_early() */
1239 /* Anonymous variables would be nice... */
1240 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1241 static const struct pci_fixup __pci_fixup_##name __used \
1242 __attribute__((__section__(#section))) = { vendor, device, hook };
1243 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1244 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1245 vendor##device##hook, vendor, device, hook)
1246 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1247 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1248 vendor##device##hook, vendor, device, hook)
1249 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1250 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1251 vendor##device##hook, vendor, device, hook)
1252 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1254 vendor##device##hook, vendor, device, hook)
1255 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1256 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1257 resume##vendor##device##hook, vendor, device, hook)
1258 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1260 resume_early##vendor##device##hook, vendor, device, hook)
1261 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1262 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1263 suspend##vendor##device##hook, vendor, device, hook)
1266 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1268 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1269 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1270 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1271 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1272 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1274 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1276 extern int pci_pci_problems;
1277 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1278 #define PCIPCI_TRITON 2
1279 #define PCIPCI_NATOMA 4
1280 #define PCIPCI_VIAETBF 8
1281 #define PCIPCI_VSFX 16
1282 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1283 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1285 extern unsigned long pci_cardbus_io_size;
1286 extern unsigned long pci_cardbus_mem_size;
1287 extern u8 __devinitdata pci_dfl_cache_line_size;
1288 extern u8 pci_cache_line_size;
1290 extern unsigned long pci_hotplug_io_size;
1291 extern unsigned long pci_hotplug_mem_size;
1293 int pcibios_add_platform_entries(struct pci_dev *dev);
1294 void pcibios_disable_device(struct pci_dev *dev);
1295 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1296 enum pcie_reset_state state);
1298 #ifdef CONFIG_PCI_MMCONFIG
1299 extern void __init pci_mmcfg_early_init(void);
1300 extern void __init pci_mmcfg_late_init(void);
1302 static inline void pci_mmcfg_early_init(void) { }
1303 static inline void pci_mmcfg_late_init(void) { }
1306 int pci_ext_cfg_avail(struct pci_dev *dev);
1308 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1310 #ifdef CONFIG_PCI_IOV
1311 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1312 extern void pci_disable_sriov(struct pci_dev *dev);
1313 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1315 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1319 static inline void pci_disable_sriov(struct pci_dev *dev)
1322 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1328 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1329 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1330 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1334 * pci_pcie_cap - get the saved PCIe capability offset
1337 * PCIe capability offset is calculated at PCI device initialization
1338 * time and saved in the data structure. This function returns saved
1339 * PCIe capability offset. Using this instead of pci_find_capability()
1340 * reduces unnecessary search in the PCI configuration space. If you
1341 * need to calculate PCIe capability offset from raw device for some
1342 * reasons, please use pci_find_capability() instead.
1344 static inline int pci_pcie_cap(struct pci_dev *dev)
1346 return dev->pcie_cap;
1350 * pci_is_pcie - check if the PCI device is PCI Express capable
1353 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1355 static inline bool pci_is_pcie(struct pci_dev *dev)
1357 return !!pci_pcie_cap(dev);
1360 void pci_request_acs(void);
1362 #endif /* __KERNEL__ */
1363 #endif /* LINUX_PCI_H */