2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/dma-mapping.h>
29 * typedef dma_cookie_t - an opaque DMA cookie
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
33 typedef s32 dma_cookie_t;
35 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
38 * enum dma_status - DMA transaction status
39 * @DMA_SUCCESS: transaction completed successfully
40 * @DMA_IN_PROGRESS: transaction not yet processed
41 * @DMA_ERROR: transaction failed
50 * enum dma_transaction_type - DMA transaction types/indexes
52 enum dma_transaction_type {
67 /* last transaction type for creation of the capabilities mask */
68 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
72 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
73 * control completion, and communicate status.
74 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
76 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
77 * acknowledges receipt, i.e. has has a chance to establish any dependency
79 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
80 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
81 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
82 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
83 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
84 * sources that were the result of a previous operation, in the case of a PQ
85 * operation it continues the calculation with new sources
88 DMA_PREP_INTERRUPT = (1 << 0),
89 DMA_CTRL_ACK = (1 << 1),
90 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
91 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
92 DMA_PREP_PQ_DISABLE_P = (1 << 4),
93 DMA_PREP_PQ_DISABLE_Q = (1 << 5),
94 DMA_PREP_CONTINUE = (1 << 6),
98 * enum sum_check_bits - bit position of pq_check_flags
100 enum sum_check_bits {
106 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
107 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
108 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
110 enum sum_check_flags {
111 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
112 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
117 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
118 * See linux/cpumask.h
120 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
123 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
124 * @memcpy_count: transaction counter
125 * @bytes_transferred: byte counter
128 struct dma_chan_percpu {
130 unsigned long memcpy_count;
131 unsigned long bytes_transferred;
135 * struct dma_chan - devices supply DMA channels, clients use them
136 * @device: ptr to the dma device who supplies this channel, always !%NULL
137 * @cookie: last cookie value returned to client
138 * @chan_id: channel ID for sysfs
139 * @dev: class device for sysfs
140 * @device_node: used to add this to the device chan list
141 * @local: per-cpu pointer to a struct dma_chan_percpu
142 * @client-count: how many clients are using this channel
143 * @table_count: number of appearances in the mem-to-mem allocation table
144 * @private: private data for certain client-channel associations
147 struct dma_device *device;
152 struct dma_chan_dev *dev;
154 struct list_head device_node;
155 struct dma_chan_percpu *local;
162 * struct dma_chan_dev - relate sysfs device node to backing channel device
163 * @chan - driver channel device
164 * @device - sysfs device
165 * @dev_id - parent dma_device dev_id
166 * @idr_ref - reference count to gate release of dma_device dev_id
168 struct dma_chan_dev {
169 struct dma_chan *chan;
170 struct device device;
175 static inline const char *dma_chan_name(struct dma_chan *chan)
177 return dev_name(&chan->dev->device);
180 void dma_chan_cleanup(struct kref *kref);
183 * typedef dma_filter_fn - callback filter for dma_request_channel
184 * @chan: channel to be reviewed
185 * @filter_param: opaque parameter passed through dma_request_channel
187 * When this optional parameter is specified in a call to dma_request_channel a
188 * suitable channel is passed to this routine for further dispositioning before
189 * being returned. Where 'suitable' indicates a non-busy channel that
190 * satisfies the given capability mask. It returns 'true' to indicate that the
191 * channel is suitable.
193 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
195 typedef void (*dma_async_tx_callback)(void *dma_async_param);
197 * struct dma_async_tx_descriptor - async transaction descriptor
198 * ---dma generic offload fields---
199 * @cookie: tracking cookie for this transaction, set to -EBUSY if
200 * this tx is sitting on a dependency list
201 * @flags: flags to augment operation preparation, control completion, and
203 * @phys: physical address of the descriptor
204 * @tx_list: driver common field for operations that require multiple
206 * @chan: target channel for this operation
207 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
208 * @callback: routine to call after this operation is complete
209 * @callback_param: general parameter to pass to the callback routine
210 * ---async_tx api specific fields---
211 * @next: at completion submit this descriptor
212 * @parent: pointer to the next level up in the dependency chain
213 * @lock: protect the parent and next pointers
215 struct dma_async_tx_descriptor {
217 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
219 struct list_head tx_list;
220 struct dma_chan *chan;
221 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
222 dma_async_tx_callback callback;
223 void *callback_param;
224 struct dma_async_tx_descriptor *next;
225 struct dma_async_tx_descriptor *parent;
230 * struct dma_device - info on the entity supplying DMA services
231 * @chancnt: how many DMA channels are supported
232 * @privatecnt: how many DMA channels are requested by dma_request_channel
233 * @channels: the list of struct dma_chan
234 * @global_node: list_head for global dma_device_list
235 * @cap_mask: one or more dma_capability flags
236 * @max_xor: maximum number of xor sources, 0 if no capability
237 * @max_pq: maximum number of PQ sources and PQ-continue capability
238 * @dev_id: unique device ID
239 * @dev: struct device reference for dma mapping api
240 * @device_alloc_chan_resources: allocate resources and return the
241 * number of allocated descriptors
242 * @device_free_chan_resources: release DMA channel's resources
243 * @device_prep_dma_memcpy: prepares a memcpy operation
244 * @device_prep_dma_xor: prepares a xor operation
245 * @device_prep_dma_xor_val: prepares a xor validation operation
246 * @device_prep_dma_pq: prepares a pq operation
247 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
248 * @device_prep_dma_memset: prepares a memset operation
249 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
250 * @device_prep_slave_sg: prepares a slave dma operation
251 * @device_terminate_all: terminate all pending operations
252 * @device_is_tx_complete: poll for transaction completion
253 * @device_issue_pending: push pending transactions to hardware
257 unsigned int chancnt;
258 unsigned int privatecnt;
259 struct list_head channels;
260 struct list_head global_node;
261 dma_cap_mask_t cap_mask;
262 unsigned short max_xor;
263 unsigned short max_pq;
264 #define DMA_HAS_PQ_CONTINUE (1 << 15)
269 int (*device_alloc_chan_resources)(struct dma_chan *chan);
270 void (*device_free_chan_resources)(struct dma_chan *chan);
272 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
273 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
274 size_t len, unsigned long flags);
275 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
276 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
277 unsigned int src_cnt, size_t len, unsigned long flags);
278 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
279 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
280 size_t len, enum sum_check_flags *result, unsigned long flags);
281 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
282 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
283 unsigned int src_cnt, const unsigned char *scf,
284 size_t len, unsigned long flags);
285 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
286 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
287 unsigned int src_cnt, const unsigned char *scf, size_t len,
288 enum sum_check_flags *pqres, unsigned long flags);
289 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
290 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
291 unsigned long flags);
292 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
293 struct dma_chan *chan, unsigned long flags);
295 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
296 struct dma_chan *chan, struct scatterlist *sgl,
297 unsigned int sg_len, enum dma_data_direction direction,
298 unsigned long flags);
299 void (*device_terminate_all)(struct dma_chan *chan);
301 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
302 dma_cookie_t cookie, dma_cookie_t *last,
304 void (*device_issue_pending)(struct dma_chan *chan);
308 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
312 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
315 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
317 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
320 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
322 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
324 return (flags & mask) == mask;
327 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
329 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
332 static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
334 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
337 /* dma_maxpq - reduce maxpq in the face of continued operations
338 * @dma - dma device with PQ capability
339 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
341 * When an engine does not support native continuation we need 3 extra
342 * source slots to reuse P and Q with the following coefficients:
343 * 1/ {00} * P : remove P from Q', but use it as a source for P'
344 * 2/ {01} * Q : use Q to continue Q' calculation
345 * 3/ {00} * Q : subtract Q from P' to cancel (2)
347 * In the case where P is disabled we only need 1 extra source:
348 * 1/ {01} * Q : use Q to continue Q' calculation
350 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
352 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
353 return dma_dev_to_maxpq(dma);
354 else if (dmaf_p_disabled_continue(flags))
355 return dma_dev_to_maxpq(dma) - 1;
356 else if (dmaf_continue(flags))
357 return dma_dev_to_maxpq(dma) - 3;
361 /* --- public DMA engine API --- */
363 #ifdef CONFIG_DMA_ENGINE
364 void dmaengine_get(void);
365 void dmaengine_put(void);
367 static inline void dmaengine_get(void)
370 static inline void dmaengine_put(void)
375 #ifdef CONFIG_NET_DMA
376 #define net_dmaengine_get() dmaengine_get()
377 #define net_dmaengine_put() dmaengine_put()
379 static inline void net_dmaengine_get(void)
382 static inline void net_dmaengine_put(void)
387 #ifdef CONFIG_ASYNC_TX_DMA
388 #define async_dmaengine_get() dmaengine_get()
389 #define async_dmaengine_put() dmaengine_put()
390 #define async_dma_find_channel(type) dma_find_channel(type)
392 static inline void async_dmaengine_get(void)
395 static inline void async_dmaengine_put(void)
398 static inline struct dma_chan *
399 async_dma_find_channel(enum dma_transaction_type type)
405 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
406 void *dest, void *src, size_t len);
407 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
408 struct page *page, unsigned int offset, void *kdata, size_t len);
409 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
410 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
411 unsigned int src_off, size_t len);
412 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
413 struct dma_chan *chan);
415 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
417 tx->flags |= DMA_CTRL_ACK;
420 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
422 tx->flags &= ~DMA_CTRL_ACK;
425 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
427 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
430 #define first_dma_cap(mask) __first_dma_cap(&(mask))
431 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
433 return min_t(int, DMA_TX_TYPE_END,
434 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
437 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
438 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
440 return min_t(int, DMA_TX_TYPE_END,
441 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
444 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
446 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
448 set_bit(tx_type, dstp->bits);
451 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
453 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
455 clear_bit(tx_type, dstp->bits);
458 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
459 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
461 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
464 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
466 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
468 return test_bit(tx_type, srcp->bits);
471 #define for_each_dma_cap_mask(cap, mask) \
472 for ((cap) = first_dma_cap(mask); \
473 (cap) < DMA_TX_TYPE_END; \
474 (cap) = next_dma_cap((cap), (mask)))
477 * dma_async_issue_pending - flush pending transactions to HW
478 * @chan: target DMA channel
480 * This allows drivers to push copies to HW in batches,
481 * reducing MMIO writes where possible.
483 static inline void dma_async_issue_pending(struct dma_chan *chan)
485 chan->device->device_issue_pending(chan);
488 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
491 * dma_async_is_tx_complete - poll for transaction completion
493 * @cookie: transaction identifier to check status of
494 * @last: returns last completed cookie, can be NULL
495 * @used: returns last issued cookie, can be NULL
497 * If @last and @used are passed in, upon return they reflect the driver
498 * internal state and can be used with dma_async_is_complete() to check
499 * the status of multiple cookies without re-checking hardware state.
501 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
502 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
504 return chan->device->device_is_tx_complete(chan, cookie, last, used);
507 #define dma_async_memcpy_complete(chan, cookie, last, used)\
508 dma_async_is_tx_complete(chan, cookie, last, used)
511 * dma_async_is_complete - test a cookie against chan state
512 * @cookie: transaction identifier to test status of
513 * @last_complete: last know completed transaction
514 * @last_used: last cookie value handed out
516 * dma_async_is_complete() is used in dma_async_memcpy_complete()
517 * the test logic is separated for lightweight testing of multiple cookies
519 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
520 dma_cookie_t last_complete, dma_cookie_t last_used)
522 if (last_complete <= last_used) {
523 if ((cookie <= last_complete) || (cookie > last_used))
526 if ((cookie <= last_complete) && (cookie > last_used))
529 return DMA_IN_PROGRESS;
532 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
533 #ifdef CONFIG_DMA_ENGINE
534 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
535 void dma_issue_pending_all(void);
537 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
541 static inline void dma_issue_pending_all(void)
547 /* --- DMA device --- */
549 int dma_async_device_register(struct dma_device *device);
550 void dma_async_device_unregister(struct dma_device *device);
551 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
552 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
553 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
554 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
555 void dma_release_channel(struct dma_chan *chan);
557 /* --- Helper iov-locking functions --- */
559 struct dma_page_list {
560 char __user *base_address;
565 struct dma_pinned_list {
567 struct dma_page_list page_list[0];
570 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
571 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
573 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
574 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
575 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
576 struct dma_pinned_list *pinned_list, struct page *page,
577 unsigned int offset, size_t len);
579 #endif /* DMAENGINE_H */