2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/kref.h>
27 #include <linux/completion.h>
28 #include <linux/rcupdate.h>
29 #include <linux/dma-mapping.h>
32 * enum dma_state_client - state of the channel in the client
33 * @DMA_ACK: client would like to use, or was using this channel
34 * @DMA_DUP: client has already seen this channel, or is not using this channel
35 * @DMA_NAK: client does not want to see any more channels
37 enum dma_state_client {
44 * typedef dma_cookie_t - an opaque DMA cookie
46 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
48 typedef s32 dma_cookie_t;
50 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
53 * enum dma_status - DMA transaction status
54 * @DMA_SUCCESS: transaction completed successfully
55 * @DMA_IN_PROGRESS: transaction not yet processed
56 * @DMA_ERROR: transaction failed
65 * enum dma_transaction_type - DMA transaction types/indexes
67 enum dma_transaction_type {
82 /* last transaction type for creation of the capabilities mask */
83 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
87 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
88 * control completion, and communicate status.
89 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
91 * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
92 * acknowledges receipt, i.e. has has a chance to establish any
94 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
95 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
98 DMA_PREP_INTERRUPT = (1 << 0),
99 DMA_CTRL_ACK = (1 << 1),
100 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
101 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
105 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
106 * See linux/cpumask.h
108 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
111 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
112 * @refcount: local_t used for open-coded "bigref" counting
113 * @memcpy_count: transaction counter
114 * @bytes_transferred: byte counter
117 struct dma_chan_percpu {
119 unsigned long memcpy_count;
120 unsigned long bytes_transferred;
124 * struct dma_chan - devices supply DMA channels, clients use them
125 * @device: ptr to the dma device who supplies this channel, always !%NULL
126 * @cookie: last cookie value returned to client
127 * @chan_id: channel ID for sysfs
128 * @class_dev: class device for sysfs
129 * @refcount: kref, used in "bigref" slow-mode
130 * @slow_ref: indicates that the DMA channel is free
131 * @rcu: the DMA channel's RCU head
132 * @device_node: used to add this to the device chan list
133 * @local: per-cpu pointer to a struct dma_chan_percpu
134 * @client-count: how many clients are using this channel
135 * @table_count: number of appearances in the mem-to-mem allocation table
138 struct dma_device *device;
145 struct kref refcount;
149 struct list_head device_node;
150 struct dma_chan_percpu *local;
155 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
157 void dma_chan_cleanup(struct kref *kref);
160 * typedef dma_filter_fn - callback filter for dma_request_channel
161 * @chan: channel to be reviewed
162 * @filter_param: opaque parameter passed through dma_request_channel
164 * When this optional parameter is specified in a call to dma_request_channel a
165 * suitable channel is passed to this routine for further dispositioning before
166 * being returned. Where 'suitable' indicates a non-busy channel that
167 * satisfies the given capability mask.
169 typedef enum dma_state_client (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
171 typedef void (*dma_async_tx_callback)(void *dma_async_param);
173 * struct dma_async_tx_descriptor - async transaction descriptor
174 * ---dma generic offload fields---
175 * @cookie: tracking cookie for this transaction, set to -EBUSY if
176 * this tx is sitting on a dependency list
177 * @flags: flags to augment operation preparation, control completion, and
179 * @phys: physical address of the descriptor
180 * @tx_list: driver common field for operations that require multiple
182 * @chan: target channel for this operation
183 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
184 * @callback: routine to call after this operation is complete
185 * @callback_param: general parameter to pass to the callback routine
186 * ---async_tx api specific fields---
187 * @next: at completion submit this descriptor
188 * @parent: pointer to the next level up in the dependency chain
189 * @lock: protect the parent and next pointers
191 struct dma_async_tx_descriptor {
193 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
195 struct list_head tx_list;
196 struct dma_chan *chan;
197 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
198 dma_async_tx_callback callback;
199 void *callback_param;
200 struct dma_async_tx_descriptor *next;
201 struct dma_async_tx_descriptor *parent;
206 * struct dma_device - info on the entity supplying DMA services
207 * @chancnt: how many DMA channels are supported
208 * @channels: the list of struct dma_chan
209 * @global_node: list_head for global dma_device_list
210 * @cap_mask: one or more dma_capability flags
211 * @max_xor: maximum number of xor sources, 0 if no capability
212 * @refcount: reference count
213 * @done: IO completion struct
214 * @dev_id: unique device ID
215 * @dev: struct device reference for dma mapping api
216 * @device_alloc_chan_resources: allocate resources and return the
217 * number of allocated descriptors
218 * @device_free_chan_resources: release DMA channel's resources
219 * @device_prep_dma_memcpy: prepares a memcpy operation
220 * @device_prep_dma_xor: prepares a xor operation
221 * @device_prep_dma_zero_sum: prepares a zero_sum operation
222 * @device_prep_dma_memset: prepares a memset operation
223 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
224 * @device_prep_slave_sg: prepares a slave dma operation
225 * @device_terminate_all: terminate all pending operations
226 * @device_issue_pending: push pending transactions to hardware
230 unsigned int chancnt;
231 struct list_head channels;
232 struct list_head global_node;
233 dma_cap_mask_t cap_mask;
236 struct kref refcount;
237 struct completion done;
242 int (*device_alloc_chan_resources)(struct dma_chan *chan);
243 void (*device_free_chan_resources)(struct dma_chan *chan);
245 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
246 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
247 size_t len, unsigned long flags);
248 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
249 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
250 unsigned int src_cnt, size_t len, unsigned long flags);
251 struct dma_async_tx_descriptor *(*device_prep_dma_zero_sum)(
252 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
253 size_t len, u32 *result, unsigned long flags);
254 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
255 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
256 unsigned long flags);
257 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
258 struct dma_chan *chan, unsigned long flags);
260 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
261 struct dma_chan *chan, struct scatterlist *sgl,
262 unsigned int sg_len, enum dma_data_direction direction,
263 unsigned long flags);
264 void (*device_terminate_all)(struct dma_chan *chan);
266 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
267 dma_cookie_t cookie, dma_cookie_t *last,
269 void (*device_issue_pending)(struct dma_chan *chan);
272 /* --- public DMA engine API --- */
274 void dmaengine_get(void);
275 void dmaengine_put(void);
276 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
277 void *dest, void *src, size_t len);
278 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
279 struct page *page, unsigned int offset, void *kdata, size_t len);
280 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
281 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
282 unsigned int src_off, size_t len);
283 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
284 struct dma_chan *chan);
286 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
288 tx->flags |= DMA_CTRL_ACK;
291 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
293 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
296 #define first_dma_cap(mask) __first_dma_cap(&(mask))
297 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
299 return min_t(int, DMA_TX_TYPE_END,
300 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
303 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
304 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
306 return min_t(int, DMA_TX_TYPE_END,
307 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
310 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
312 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
314 set_bit(tx_type, dstp->bits);
317 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
318 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
320 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
323 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
325 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
327 return test_bit(tx_type, srcp->bits);
330 #define for_each_dma_cap_mask(cap, mask) \
331 for ((cap) = first_dma_cap(mask); \
332 (cap) < DMA_TX_TYPE_END; \
333 (cap) = next_dma_cap((cap), (mask)))
336 * dma_async_issue_pending - flush pending transactions to HW
337 * @chan: target DMA channel
339 * This allows drivers to push copies to HW in batches,
340 * reducing MMIO writes where possible.
342 static inline void dma_async_issue_pending(struct dma_chan *chan)
344 chan->device->device_issue_pending(chan);
347 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
350 * dma_async_is_tx_complete - poll for transaction completion
352 * @cookie: transaction identifier to check status of
353 * @last: returns last completed cookie, can be NULL
354 * @used: returns last issued cookie, can be NULL
356 * If @last and @used are passed in, upon return they reflect the driver
357 * internal state and can be used with dma_async_is_complete() to check
358 * the status of multiple cookies without re-checking hardware state.
360 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
361 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
363 return chan->device->device_is_tx_complete(chan, cookie, last, used);
366 #define dma_async_memcpy_complete(chan, cookie, last, used)\
367 dma_async_is_tx_complete(chan, cookie, last, used)
370 * dma_async_is_complete - test a cookie against chan state
371 * @cookie: transaction identifier to test status of
372 * @last_complete: last know completed transaction
373 * @last_used: last cookie value handed out
375 * dma_async_is_complete() is used in dma_async_memcpy_complete()
376 * the test logic is separated for lightweight testing of multiple cookies
378 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
379 dma_cookie_t last_complete, dma_cookie_t last_used)
381 if (last_complete <= last_used) {
382 if ((cookie <= last_complete) || (cookie > last_used))
385 if ((cookie <= last_complete) && (cookie > last_used))
388 return DMA_IN_PROGRESS;
391 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
392 #ifdef CONFIG_DMA_ENGINE
393 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
395 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
401 /* --- DMA device --- */
403 int dma_async_device_register(struct dma_device *device);
404 void dma_async_device_unregister(struct dma_device *device);
405 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
406 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
407 void dma_issue_pending_all(void);
408 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
409 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
410 void dma_release_channel(struct dma_chan *chan);
412 /* --- Helper iov-locking functions --- */
414 struct dma_page_list {
415 char __user *base_address;
420 struct dma_pinned_list {
422 struct dma_page_list page_list[0];
425 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
426 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
428 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
429 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
430 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
431 struct dma_pinned_list *pinned_list, struct page *page,
432 unsigned int offset, size_t len);
434 #endif /* DMAENGINE_H */