2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
24 #include <linux/device.h>
25 #include <linux/uio.h>
26 #include <linux/dma-mapping.h>
29 * typedef dma_cookie_t - an opaque DMA cookie
31 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
33 typedef s32 dma_cookie_t;
34 #define DMA_MIN_COOKIE 1
35 #define DMA_MAX_COOKIE INT_MAX
37 #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
40 * enum dma_status - DMA transaction status
41 * @DMA_SUCCESS: transaction completed successfully
42 * @DMA_IN_PROGRESS: transaction not yet processed
43 * @DMA_ERROR: transaction failed
52 * enum dma_transaction_type - DMA transaction types/indexes
54 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
55 * automatically set as dma devices are registered.
57 enum dma_transaction_type {
70 /* last transaction type for creation of the capabilities mask */
71 #define DMA_TX_TYPE_END (DMA_SLAVE + 1)
75 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
76 * control completion, and communicate status.
77 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
79 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
80 * acknowledges receipt, i.e. has has a chance to establish any dependency
82 * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
83 * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
84 * @DMA_COMPL_SRC_UNMAP_SINGLE - set to do the source dma-unmapping as single
85 * (if not set, do the source dma-unmapping as page)
86 * @DMA_COMPL_DEST_UNMAP_SINGLE - set to do the destination dma-unmapping as single
87 * (if not set, do the destination dma-unmapping as page)
88 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
89 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
90 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
91 * sources that were the result of a previous operation, in the case of a PQ
92 * operation it continues the calculation with new sources
93 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
94 * on the result of this operation
97 DMA_PREP_INTERRUPT = (1 << 0),
98 DMA_CTRL_ACK = (1 << 1),
99 DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
100 DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
101 DMA_COMPL_SRC_UNMAP_SINGLE = (1 << 4),
102 DMA_COMPL_DEST_UNMAP_SINGLE = (1 << 5),
103 DMA_PREP_PQ_DISABLE_P = (1 << 6),
104 DMA_PREP_PQ_DISABLE_Q = (1 << 7),
105 DMA_PREP_CONTINUE = (1 << 8),
106 DMA_PREP_FENCE = (1 << 9),
110 * enum sum_check_bits - bit position of pq_check_flags
112 enum sum_check_bits {
118 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
119 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
120 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
122 enum sum_check_flags {
123 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
124 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
129 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
130 * See linux/cpumask.h
132 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
135 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
136 * @memcpy_count: transaction counter
137 * @bytes_transferred: byte counter
140 struct dma_chan_percpu {
142 unsigned long memcpy_count;
143 unsigned long bytes_transferred;
147 * struct dma_chan - devices supply DMA channels, clients use them
148 * @device: ptr to the dma device who supplies this channel, always !%NULL
149 * @cookie: last cookie value returned to client
150 * @chan_id: channel ID for sysfs
151 * @dev: class device for sysfs
152 * @device_node: used to add this to the device chan list
153 * @local: per-cpu pointer to a struct dma_chan_percpu
154 * @client-count: how many clients are using this channel
155 * @table_count: number of appearances in the mem-to-mem allocation table
156 * @private: private data for certain client-channel associations
159 struct dma_device *device;
164 struct dma_chan_dev *dev;
166 struct list_head device_node;
167 struct dma_chan_percpu __percpu *local;
174 * struct dma_chan_dev - relate sysfs device node to backing channel device
175 * @chan - driver channel device
176 * @device - sysfs device
177 * @dev_id - parent dma_device dev_id
178 * @idr_ref - reference count to gate release of dma_device dev_id
180 struct dma_chan_dev {
181 struct dma_chan *chan;
182 struct device device;
187 static inline const char *dma_chan_name(struct dma_chan *chan)
189 return dev_name(&chan->dev->device);
192 void dma_chan_cleanup(struct kref *kref);
195 * typedef dma_filter_fn - callback filter for dma_request_channel
196 * @chan: channel to be reviewed
197 * @filter_param: opaque parameter passed through dma_request_channel
199 * When this optional parameter is specified in a call to dma_request_channel a
200 * suitable channel is passed to this routine for further dispositioning before
201 * being returned. Where 'suitable' indicates a non-busy channel that
202 * satisfies the given capability mask. It returns 'true' to indicate that the
203 * channel is suitable.
205 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
207 typedef void (*dma_async_tx_callback)(void *dma_async_param);
209 * struct dma_async_tx_descriptor - async transaction descriptor
210 * ---dma generic offload fields---
211 * @cookie: tracking cookie for this transaction, set to -EBUSY if
212 * this tx is sitting on a dependency list
213 * @flags: flags to augment operation preparation, control completion, and
215 * @phys: physical address of the descriptor
216 * @chan: target channel for this operation
217 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
218 * @callback: routine to call after this operation is complete
219 * @callback_param: general parameter to pass to the callback routine
220 * ---async_tx api specific fields---
221 * @next: at completion submit this descriptor
222 * @parent: pointer to the next level up in the dependency chain
223 * @lock: protect the parent and next pointers
225 struct dma_async_tx_descriptor {
227 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
229 struct dma_chan *chan;
230 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
231 dma_async_tx_callback callback;
232 void *callback_param;
233 #ifndef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
234 struct dma_async_tx_descriptor *next;
235 struct dma_async_tx_descriptor *parent;
240 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
241 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
244 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
247 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
251 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
254 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
257 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
261 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
267 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
269 spin_lock_bh(&txd->lock);
271 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
273 spin_unlock_bh(&txd->lock);
275 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
280 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
284 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
288 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
292 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
299 * struct dma_device - info on the entity supplying DMA services
300 * @chancnt: how many DMA channels are supported
301 * @privatecnt: how many DMA channels are requested by dma_request_channel
302 * @channels: the list of struct dma_chan
303 * @global_node: list_head for global dma_device_list
304 * @cap_mask: one or more dma_capability flags
305 * @max_xor: maximum number of xor sources, 0 if no capability
306 * @max_pq: maximum number of PQ sources and PQ-continue capability
307 * @copy_align: alignment shift for memcpy operations
308 * @xor_align: alignment shift for xor operations
309 * @pq_align: alignment shift for pq operations
310 * @fill_align: alignment shift for memset operations
311 * @dev_id: unique device ID
312 * @dev: struct device reference for dma mapping api
313 * @device_alloc_chan_resources: allocate resources and return the
314 * number of allocated descriptors
315 * @device_free_chan_resources: release DMA channel's resources
316 * @device_prep_dma_memcpy: prepares a memcpy operation
317 * @device_prep_dma_xor: prepares a xor operation
318 * @device_prep_dma_xor_val: prepares a xor validation operation
319 * @device_prep_dma_pq: prepares a pq operation
320 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
321 * @device_prep_dma_memset: prepares a memset operation
322 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
323 * @device_prep_slave_sg: prepares a slave dma operation
324 * @device_terminate_all: terminate all pending operations
325 * @device_is_tx_complete: poll for transaction completion
326 * @device_issue_pending: push pending transactions to hardware
330 unsigned int chancnt;
331 unsigned int privatecnt;
332 struct list_head channels;
333 struct list_head global_node;
334 dma_cap_mask_t cap_mask;
335 unsigned short max_xor;
336 unsigned short max_pq;
341 #define DMA_HAS_PQ_CONTINUE (1 << 15)
346 int (*device_alloc_chan_resources)(struct dma_chan *chan);
347 void (*device_free_chan_resources)(struct dma_chan *chan);
349 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
350 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
351 size_t len, unsigned long flags);
352 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
353 struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
354 unsigned int src_cnt, size_t len, unsigned long flags);
355 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
356 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
357 size_t len, enum sum_check_flags *result, unsigned long flags);
358 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
359 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
360 unsigned int src_cnt, const unsigned char *scf,
361 size_t len, unsigned long flags);
362 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
363 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
364 unsigned int src_cnt, const unsigned char *scf, size_t len,
365 enum sum_check_flags *pqres, unsigned long flags);
366 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
367 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
368 unsigned long flags);
369 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
370 struct dma_chan *chan, unsigned long flags);
372 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
373 struct dma_chan *chan, struct scatterlist *sgl,
374 unsigned int sg_len, enum dma_data_direction direction,
375 unsigned long flags);
376 void (*device_terminate_all)(struct dma_chan *chan);
378 enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
379 dma_cookie_t cookie, dma_cookie_t *last,
381 void (*device_issue_pending)(struct dma_chan *chan);
384 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
390 mask = (1 << align) - 1;
391 if (mask & (off1 | off2 | len))
396 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
397 size_t off2, size_t len)
399 return dmaengine_check_align(dev->copy_align, off1, off2, len);
402 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
403 size_t off2, size_t len)
405 return dmaengine_check_align(dev->xor_align, off1, off2, len);
408 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
409 size_t off2, size_t len)
411 return dmaengine_check_align(dev->pq_align, off1, off2, len);
414 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
415 size_t off2, size_t len)
417 return dmaengine_check_align(dev->fill_align, off1, off2, len);
421 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
425 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
428 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
430 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
433 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
435 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
437 return (flags & mask) == mask;
440 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
442 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
445 static unsigned short dma_dev_to_maxpq(struct dma_device *dma)
447 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
450 /* dma_maxpq - reduce maxpq in the face of continued operations
451 * @dma - dma device with PQ capability
452 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
454 * When an engine does not support native continuation we need 3 extra
455 * source slots to reuse P and Q with the following coefficients:
456 * 1/ {00} * P : remove P from Q', but use it as a source for P'
457 * 2/ {01} * Q : use Q to continue Q' calculation
458 * 3/ {00} * Q : subtract Q from P' to cancel (2)
460 * In the case where P is disabled we only need 1 extra source:
461 * 1/ {01} * Q : use Q to continue Q' calculation
463 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
465 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
466 return dma_dev_to_maxpq(dma);
467 else if (dmaf_p_disabled_continue(flags))
468 return dma_dev_to_maxpq(dma) - 1;
469 else if (dmaf_continue(flags))
470 return dma_dev_to_maxpq(dma) - 3;
474 /* --- public DMA engine API --- */
476 #ifdef CONFIG_DMA_ENGINE
477 void dmaengine_get(void);
478 void dmaengine_put(void);
480 static inline void dmaengine_get(void)
483 static inline void dmaengine_put(void)
488 #ifdef CONFIG_NET_DMA
489 #define net_dmaengine_get() dmaengine_get()
490 #define net_dmaengine_put() dmaengine_put()
492 static inline void net_dmaengine_get(void)
495 static inline void net_dmaengine_put(void)
500 #ifdef CONFIG_ASYNC_TX_DMA
501 #define async_dmaengine_get() dmaengine_get()
502 #define async_dmaengine_put() dmaengine_put()
503 #ifdef CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH
504 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
506 #define async_dma_find_channel(type) dma_find_channel(type)
507 #endif /* CONFIG_ASYNC_TX_DISABLE_CHANNEL_SWITCH */
509 static inline void async_dmaengine_get(void)
512 static inline void async_dmaengine_put(void)
515 static inline struct dma_chan *
516 async_dma_find_channel(enum dma_transaction_type type)
520 #endif /* CONFIG_ASYNC_TX_DMA */
522 dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
523 void *dest, void *src, size_t len);
524 dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
525 struct page *page, unsigned int offset, void *kdata, size_t len);
526 dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
527 struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
528 unsigned int src_off, size_t len);
529 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
530 struct dma_chan *chan);
532 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
534 tx->flags |= DMA_CTRL_ACK;
537 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
539 tx->flags &= ~DMA_CTRL_ACK;
542 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
544 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
547 #define first_dma_cap(mask) __first_dma_cap(&(mask))
548 static inline int __first_dma_cap(const dma_cap_mask_t *srcp)
550 return min_t(int, DMA_TX_TYPE_END,
551 find_first_bit(srcp->bits, DMA_TX_TYPE_END));
554 #define next_dma_cap(n, mask) __next_dma_cap((n), &(mask))
555 static inline int __next_dma_cap(int n, const dma_cap_mask_t *srcp)
557 return min_t(int, DMA_TX_TYPE_END,
558 find_next_bit(srcp->bits, DMA_TX_TYPE_END, n+1));
561 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
563 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
565 set_bit(tx_type, dstp->bits);
568 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
570 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
572 clear_bit(tx_type, dstp->bits);
575 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
576 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
578 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
581 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
583 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
585 return test_bit(tx_type, srcp->bits);
588 #define for_each_dma_cap_mask(cap, mask) \
589 for ((cap) = first_dma_cap(mask); \
590 (cap) < DMA_TX_TYPE_END; \
591 (cap) = next_dma_cap((cap), (mask)))
594 * dma_async_issue_pending - flush pending transactions to HW
595 * @chan: target DMA channel
597 * This allows drivers to push copies to HW in batches,
598 * reducing MMIO writes where possible.
600 static inline void dma_async_issue_pending(struct dma_chan *chan)
602 chan->device->device_issue_pending(chan);
605 #define dma_async_memcpy_issue_pending(chan) dma_async_issue_pending(chan)
608 * dma_async_is_tx_complete - poll for transaction completion
610 * @cookie: transaction identifier to check status of
611 * @last: returns last completed cookie, can be NULL
612 * @used: returns last issued cookie, can be NULL
614 * If @last and @used are passed in, upon return they reflect the driver
615 * internal state and can be used with dma_async_is_complete() to check
616 * the status of multiple cookies without re-checking hardware state.
618 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
619 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
621 return chan->device->device_is_tx_complete(chan, cookie, last, used);
624 #define dma_async_memcpy_complete(chan, cookie, last, used)\
625 dma_async_is_tx_complete(chan, cookie, last, used)
628 * dma_async_is_complete - test a cookie against chan state
629 * @cookie: transaction identifier to test status of
630 * @last_complete: last know completed transaction
631 * @last_used: last cookie value handed out
633 * dma_async_is_complete() is used in dma_async_memcpy_complete()
634 * the test logic is separated for lightweight testing of multiple cookies
636 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
637 dma_cookie_t last_complete, dma_cookie_t last_used)
639 if (last_complete <= last_used) {
640 if ((cookie <= last_complete) || (cookie > last_used))
643 if ((cookie <= last_complete) && (cookie > last_used))
646 return DMA_IN_PROGRESS;
649 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
650 #ifdef CONFIG_DMA_ENGINE
651 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
652 void dma_issue_pending_all(void);
654 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
658 static inline void dma_issue_pending_all(void)
664 /* --- DMA device --- */
666 int dma_async_device_register(struct dma_device *device);
667 void dma_async_device_unregister(struct dma_device *device);
668 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
669 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
670 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
671 struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param);
672 void dma_release_channel(struct dma_chan *chan);
674 /* --- Helper iov-locking functions --- */
676 struct dma_page_list {
677 char __user *base_address;
682 struct dma_pinned_list {
684 struct dma_page_list page_list[0];
687 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
688 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
690 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
691 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
692 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
693 struct dma_pinned_list *pinned_list, struct page *page,
694 unsigned int offset, size_t len);
696 #endif /* DMAENGINE_H */