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   1 #ifndef _X86_SPINLOCK_H_
   2 #define _X86_SPINLOCK_H_
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * These are fair FIFO ticket locks, which are currently limited to 256
  17  * CPUs.
  18  *
  19  * (the type definitions are in asm/spinlock_types.h)
  20  */
  21
  22 #ifdef CONFIG_X86_32
  23 typedef char _slock_t;
  24 # define LOCK_INS_DEC "decb"
  25 # define LOCK_INS_XCH "xchgb"
  26 # define LOCK_INS_MOV "movb"
  27 # define LOCK_INS_CMP "cmpb"
  28 # define LOCK_PTR_REG "a"
  29 #else
  30 typedef int _slock_t;
  31 # define LOCK_INS_DEC "decl"
  32 # define LOCK_INS_XCH "xchgl"
  33 # define LOCK_INS_MOV "movl"
  34 # define LOCK_INS_CMP "cmpl"
  35 # define LOCK_PTR_REG "D"
  36 #endif
  37
  38 #if (NR_CPUS > 256)
  39 #error spinlock supports a maximum of 256 CPUs
  40 #endif
  41
  42 static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
  43 {
  44         int tmp = *(volatile signed int *)(&(lock)->slock);
  45
  46         return (((tmp >> 8) & 0xff) != (tmp & 0xff));
  47 }
  48
  49 static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
  50 {
  51         int tmp = *(volatile signed int *)(&(lock)->slock);
  52
  53         return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
  54 }
  55
  56 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  57 {
  58         short inc = 0x0100;
  59
  60         /*
  61          * Ticket locks are conceptually two bytes, one indicating the current
  62          * head of the queue, and the other indicating the current tail. The
  63          * lock is acquired by atomically noting the tail and incrementing it
  64          * by one (thus adding ourself to the queue and noting our position),
  65          * then waiting until the head becomes equal to the the initial value
  66          * of the tail.
  67          *
  68          * This uses a 16-bit xadd to increment the tail and also load the
  69          * position of the head, which takes care of memory ordering issues
  70          * and should be optimal for the uncontended case. Note the tail must
  71          * be in the high byte, otherwise the 16-bit wide increment of the low
  72          * byte would carry up and contaminate the high byte.
  73          */
  74
  75         __asm__ __volatile__ (
  76                 LOCK_PREFIX "xaddw %w0, %1\n"
  77                 "1:\t"
  78                 "cmpb %h0, %b0\n\t"
  79                 "je 2f\n\t"
  80                 "rep ; nop\n\t"
  81                 "movb %1, %b0\n\t"
  82                 /* don't need lfence here, because loads are in-order */
  83                 "jmp 1b\n"
  84                 "2:"
  85                 :"+Q" (inc), "+m" (lock->slock)
  86                 :
  87                 :"memory", "cc");
  88 }
  89
  90 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  91
  92 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  93 {
  94         int tmp;
  95         short new;
  96
  97         asm volatile(
  98                 "movw %2,%w0\n\t"
  99                 "cmpb %h0,%b0\n\t"
 100                 "jne 1f\n\t"
 101                 "movw %w0,%w1\n\t"
 102                 "incb %h1\n\t"
 103                 "lock ; cmpxchgw %w1,%2\n\t"
 104                 "1:"
 105                 "sete %b1\n\t"
 106                 "movzbl %b1,%0\n\t"
 107                 :"=&a" (tmp), "=Q" (new), "+m" (lock->slock)
 108                 :
 109                 : "memory", "cc");
 110
 111         return tmp;
 112 }
 113
 114 #if defined(CONFIG_X86_32) && \
 115         (defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE))
 116 /*
 117  * On PPro SMP or if we are using OOSTORE, we use a locked operation to unlock
 118  * (PPro errata 66, 92)
 119  */
 120 # define UNLOCK_LOCK_PREFIX LOCK_PREFIX
 121 #else
 122 # define UNLOCK_LOCK_PREFIX
 123 #endif
 124
 125 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 126 {
 127         __asm__ __volatile__(
 128                 UNLOCK_LOCK_PREFIX "incb %0"
 129                 :"+m" (lock->slock)
 130                 :
 131                 :"memory", "cc");
 132 }
 133
 134 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 135 {
 136         while (__raw_spin_is_locked(lock))
 137                 cpu_relax();
 138 }
 139
 140 /*
 141  * Read-write spinlocks, allowing multiple readers
 142  * but only one writer.
 143  *
 144  * NOTE! it is quite common to have readers in interrupts
 145  * but no interrupt writers. For those circumstances we
 146  * can "mix" irq-safe locks - any writer needs to get a
 147  * irq-safe write-lock, but readers can get non-irqsafe
 148  * read-locks.
 149  *
 150  * On x86, we implement read-write locks as a 32-bit counter
 151  * with the high bit (sign) being the "contended" bit.
 152  */
 153
 154 /**
 155  * read_can_lock - would read_trylock() succeed?
 156  * @lock: the rwlock in question.
 157  */
 158 static inline int __raw_read_can_lock(raw_rwlock_t *lock)
 159 {
 160         return (int)(lock)->lock > 0;
 161 }
 162
 163 /**
 164  * write_can_lock - would write_trylock() succeed?
 165  * @lock: the rwlock in question.
 166  */
 167 static inline int __raw_write_can_lock(raw_rwlock_t *lock)
 168 {
 169         return (lock)->lock == RW_LOCK_BIAS;
 170 }
 171
 172 static inline void __raw_read_lock(raw_rwlock_t *rw)
 173 {
 174         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 175                      "jns 1f\n"
 176                      "call __read_lock_failed\n\t"
 177                      "1:\n"
 178                      ::LOCK_PTR_REG (rw) : "memory");
 179 }
 180
 181 static inline void __raw_write_lock(raw_rwlock_t *rw)
 182 {
 183         asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
 184                      "jz 1f\n"
 185                      "call __write_lock_failed\n\t"
 186                      "1:\n"
 187                      ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
 188 }
 189
 190 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 191 {
 192         atomic_t *count = (atomic_t *)lock;
 193
 194         atomic_dec(count);
 195         if (atomic_read(count) >= 0)
 196                 return 1;
 197         atomic_inc(count);
 198         return 0;
 199 }
 200
 201 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 202 {
 203         atomic_t *count = (atomic_t *)lock;
 204
 205         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 206                 return 1;
 207         atomic_add(RW_LOCK_BIAS, count);
 208         return 0;
 209 }
 210
 211 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 212 {
 213         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 214 }
 215
 216 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 217 {
 218         asm volatile(LOCK_PREFIX "addl %1, %0"
 219                      : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
 220 }
 221
 222 #define _raw_spin_relax(lock)   cpu_relax()
 223 #define _raw_read_relax(lock)   cpu_relax()
 224 #define _raw_write_relax(lock)  cpu_relax()
 225
 226 #endif