1 /* cpudata.h: Per-cpu parameters.
3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
6 #ifndef _SPARC64_CPUDATA_H
7 #define _SPARC64_CPUDATA_H
9 #include <asm/hypervisor.h>
14 #include <linux/percpu.h>
15 #include <linux/threads.h>
19 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
20 unsigned int multiplier;
22 unsigned int idle_volume;
23 unsigned long clock_tick; /* %tick's per second */
24 unsigned long udelay_val;
26 /* Dcache line 2, rarely used */
27 unsigned int dcache_size;
28 unsigned int dcache_line_size;
29 unsigned int icache_size;
30 unsigned int icache_line_size;
31 unsigned int ecache_size;
32 unsigned int ecache_line_size;
37 DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
38 #define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
39 #define local_cpu_data() __get_cpu_var(__cpu_data)
41 /* Trap handling code needs to get at a few critical values upon
42 * trap entry and to process TSB misses. These cannot be in the
43 * per_cpu() area as we really need to lock them into the TLB and
44 * thus make them part of the main kernel image. As a result we
45 * try to make this as small as possible.
47 * This is padded out and aligned to 64-bytes to avoid false sharing
51 /* If you modify the size of this structure, please update
52 * TRAP_BLOCK_SZ_SHIFT below.
56 /* D-cache line 1: Basic thread information */
57 struct thread_info *thread;
58 unsigned long pgd_paddr;
59 unsigned long __pad1[2];
61 /* D-cache line 2: Sun4V Mondo Queue pointers */
62 unsigned long cpu_mondo_pa;
63 unsigned long dev_mondo_pa;
64 unsigned long resum_mondo_pa;
65 unsigned long nonresum_mondo_pa;
67 /* Dcache lines 3 and 4: Hypervisor Fault Status */
68 struct hv_fault_status fault_info;
69 } __attribute__((aligned(64)));
70 extern struct trap_per_cpu trap_block[NR_CPUS];
71 extern void init_cur_cpu_trap(void);
72 extern void setup_tba(void);
75 struct cpuid_patch_entry {
77 unsigned int cheetah_safari[4];
78 unsigned int cheetah_jbus[4];
79 unsigned int starfire[4];
80 unsigned int sun4v[4];
82 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
85 struct sun4v_1insn_patch_entry {
89 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
90 __sun4v_1insn_patch_end;
92 struct sun4v_2insn_patch_entry {
94 unsigned int insns[2];
96 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
97 __sun4v_2insn_patch_end;
99 #endif /* !(__ASSEMBLY__) */
101 #define TRAP_PER_CPU_THREAD 0x00
102 #define TRAP_PER_CPU_PGD_PADDR 0x08
103 #define TRAP_PER_CPU_CPU_MONDO_PA 0x20
104 #define TRAP_PER_CPU_DEV_MONDO_PA 0x28
105 #define TRAP_PER_CPU_RESUM_MONDO_PA 0x30
106 #define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x38
107 #define TRAP_PER_CPU_FAULT_INFO 0x40
109 #define TRAP_BLOCK_SZ_SHIFT 7
111 #include <asm/scratchpad.h>
115 #define __GET_CPUID(REG) \
116 /* Spitfire implementation (default). */ \
117 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
119 and REG, 0x1f, REG; \
121 .section .cpuid_patch, "ax"; \
122 /* Instruction location. */ \
124 /* Cheetah Safari implementation. */ \
125 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
127 and REG, 0x3ff, REG; \
129 /* Cheetah JBUS implementation. */ \
130 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
132 and REG, 0x1f, REG; \
134 /* Starfire implementation. */ \
135 sethi %hi(0x1fff40000d0 >> 9), REG; \
138 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
139 /* sun4v implementation. */ \
140 mov SCRATCHPAD_CPUID, REG; \
141 ldxa [REG] ASI_SCRATCHPAD, REG; \
146 /* Clobbers TMP, current address space PGD phys address into DEST. */
147 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
149 sethi %hi(trap_block), DEST; \
150 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
151 or DEST, %lo(trap_block), DEST; \
152 add DEST, TMP, DEST; \
153 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
155 /* Clobbers TMP, loads local processor's IRQ work area into DEST. */
156 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
158 sethi %hi(__irq_work), DEST; \
160 or DEST, %lo(__irq_work), DEST; \
163 /* Clobbers TMP, loads DEST with current thread info pointer. */
164 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
166 sethi %hi(trap_block), DEST; \
167 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
168 or DEST, %lo(trap_block), DEST; \
169 ldx [DEST + TMP], DEST;
171 /* Given the current thread info pointer in THR, load the per-cpu
172 * area base of the current processor into DEST. REG1, REG2, and REG3 are
175 * You absolutely cannot use DEST as a temporary in this code. The
176 * reason is that traps can happen during execution, and return from
177 * trap will load the fully resolved DEST per-cpu base. This can corrupt
178 * the calculations done by the macro mid-stream.
180 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
181 ldub [THR + TI_CPU], REG1; \
182 sethi %hi(__per_cpu_shift), REG3; \
183 sethi %hi(__per_cpu_base), REG2; \
184 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
185 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
186 sllx REG1, REG3, REG3; \
187 add REG3, REG2, DEST;
191 /* Uniprocessor versions, we know the cpuid is zero. */
192 #define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
193 sethi %hi(trap_block), DEST; \
194 or DEST, %lo(trap_block), DEST; \
195 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
197 #define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
198 sethi %hi(__irq_work), DEST; \
199 or DEST, %lo(__irq_work), DEST;
201 #define TRAP_LOAD_THREAD_REG(DEST, TMP) \
202 sethi %hi(trap_block), DEST; \
203 ldx [DEST + %lo(trap_block)], DEST;
205 /* No per-cpu areas on uniprocessor, so no need to load DEST. */
206 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
208 #endif /* !(CONFIG_SMP) */
210 #endif /* _SPARC64_CPUDATA_H */