4 /* asi.h: Address Space Identifier values for the V9.
6 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
9 /* V9 Architecture mandary ASIs. */
10 #define ASI_N 0x04 /* Nucleus */
11 #define ASI_NL 0x0c /* Nucleus, little endian */
12 #define ASI_AIUP 0x10 /* Primary, user */
13 #define ASI_AIUS 0x11 /* Secondary, user */
14 #define ASI_AIUPL 0x18 /* Primary, user, little endian */
15 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
16 #define ASI_P 0x80 /* Primary, implicit */
17 #define ASI_S 0x81 /* Secondary, implicit */
18 #define ASI_PNF 0x82 /* Primary, no fault */
19 #define ASI_SNF 0x83 /* Secondary, no fault */
20 #define ASI_PL 0x88 /* Primary, implicit, l-endian */
21 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
22 #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
23 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
25 /* SpitFire and later extended ASIs. The "(III)" marker designates
26 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
27 * Chip Multi Threading specific ASIs. "(NG)" designates Niagara specific
28 * ASIs, "(4V)" designates SUN4V specific ASIs.
30 #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
31 #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
32 #define ASI_BLK_AIUP_4V 0x16 /* (4V) Prim, user, block ld/st */
33 #define ASI_BLK_AIUS_4V 0x17 /* (4V) Sec, user, block ld/st */
34 #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian*/
35 #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
36 #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
37 #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
38 #define ASI_SCRATCHPAD 0x20 /* (4V) Scratch Pad Registers */
39 #define ASI_MMU 0x21 /* (4V) MMU Context Registers */
40 #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
43 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
44 #define ASI_QUEUE 0x25 /* (4V) Interrupt Queue Registers */
45 #define ASI_QUAD_LDD_PHYS_4V 0x26 /* (4V) Physical, qword load */
46 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, l-endian */
47 #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
48 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
49 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
50 #define ASI_PCACHE_TAG 0x32 /* (III) PCache tag RAM diag */
51 #define ASI_PCACHE_SNOOP_TAG 0x33 /* (III) PCache snoop tag RAM diag */
52 #define ASI_QUAD_LDD_PHYS 0x34 /* (III+) PADDR, qword load */
53 #define ASI_WCACHE_VALID_BITS 0x38 /* (III) WCache Valid Bits diag */
54 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
55 #define ASI_WCACHE_TAG 0x3a /* (III) WCache tag RAM diag */
56 #define ASI_WCACHE_SNOOP_TAG 0x3b /* (III) WCache snoop tag RAM diag */
57 #define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
58 #define ASI_SRAM_FAST_INIT 0x40 /* (III+) Fast SRAM init */
59 #define ASI_CORE_AVAILABLE 0x41 /* (CMT) LP Available */
60 #define ASI_CORE_ENABLE_STAT 0x41 /* (CMT) LP Enable Status */
61 #define ASI_CORE_ENABLE 0x41 /* (CMT) LP Enable RW */
62 #define ASI_XIR_STEERING 0x41 /* (CMT) XIR Steering RW */
63 #define ASI_CORE_RUNNING_RW 0x41 /* (CMT) LP Running RW */
64 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
65 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
66 #define ASI_CORE_RUNNING_STAT 0x41 /* (CMT) LP Running Status */
67 #define ASI_CMT_ERROR_STEERING 0x41 /* (CMT) Error Steering RW */
68 #define ASI_DCACHE_INVALIDATE 0x42 /* (III) DCache Invalidate diag */
69 #define ASI_DCACHE_UTAG 0x43 /* (III) DCache uTag diag */
70 #define ASI_DCACHE_SNOOP_TAG 0x44 /* (III) DCache snoop tag RAM diag */
71 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
72 #define ASI_DCU_CONTROL_REG 0x45 /* (III) DCache Unit Control reg */
73 #define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
74 #define ASI_DCACHE_TAG 0x47 /* Dcache tag/valid ram diag access*/
75 #define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
76 #define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
77 #define ASI_UPA_CONFIG 0x4a /* UPA config space */
78 #define ASI_JBUS_CONFIG 0x4a /* (IIIi) JBUS Config Register */
79 #define ASI_SAFARI_CONFIG 0x4a /* (III) Safari Config Register */
80 #define ASI_SAFARI_ADDRESS 0x4a /* (III) Safari Address Register */
81 #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
82 #define ASI_AFSR 0x4c /* Async fault status register */
83 #define ASI_AFAR 0x4d /* Async fault address register */
84 #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
85 #define ASI_IMMU 0x50 /* Insn-MMU main register space */
86 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
87 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
88 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
89 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
90 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
91 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
92 #define ASI_DMMU 0x58 /* Data-MMU main register space */
93 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
94 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
95 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
96 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
97 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
98 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
99 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
100 #define ASI_IIU_INST_TRAP 0x60 /* (III) Instruction Breakpoint */
101 #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */
102 #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */
103 #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */
104 #define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */
105 #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */
106 #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */
107 #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
108 #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
109 #define ASI_BRPRED_ARRAY 0x6f /* (III) Branch Prediction RAM diag*/
110 #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
111 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
112 #define ASI_MCU_CTRL_REG 0x72 /* (III) Memory controller regs */
113 #define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
114 #define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
115 #define ASI_EC_W 0x76 /* E-cache diag write access */
116 #define ASI_UDB_ERROR_W 0x77 /* External UDB error regs W */
117 #define ASI_UDB_CONTROL_W 0x77 /* External UDB control regs W */
118 #define ASI_INTR_W 0x77 /* IRQ vector dispatch write */
119 #define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
120 #define ASI_INTR_DISPATCH_W 0x77 /* (III) Interrupt vector dispatch */
121 #define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
122 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
123 #define ASI_EC_R 0x7e /* E-cache diag read access */
124 #define ASI_UDBH_ERROR_R 0x7f /* External UDB error regs rd hi */
125 #define ASI_UDBL_ERROR_R 0x7f /* External UDB error regs rd low */
126 #define ASI_UDBH_CONTROL_R 0x7f /* External UDB control regs rd hi */
127 #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control regs rd low*/
128 #define ASI_INTR_R 0x7f /* IRQ vector dispatch read */
129 #define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
130 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
131 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
132 #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
133 #define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
134 #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
135 #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
136 #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
137 #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
138 #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
139 #define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
140 #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
141 #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
142 #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
143 #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
144 #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
145 #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
146 #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
147 #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
148 #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
149 #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
150 #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
151 #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
152 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
155 #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
156 #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
157 #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
158 #define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
160 #endif /* _SPARC64_ASI_H */
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