2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QUICC Engine (QE) external definitions and structure.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #ifndef _ASM_POWERPC_QE_H
16 #define _ASM_POWERPC_QE_H
19 #include <linux/spinlock.h>
20 #include <asm/immap_qe.h>
22 #define QE_NUM_OF_SNUM 28
23 #define QE_NUM_OF_BRGS 16
24 #define QE_NUM_OF_PORTS 1024
28 #define MEM_PART_SYSTEM 0
29 #define MEM_PART_SECONDARY 1
30 #define MEM_PART_MURAM 2
35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
44 QE_BRG10, /* Baud Rate Generator 10 */
45 QE_BRG11, /* Baud Rate Generator 11 */
46 QE_BRG12, /* Baud Rate Generator 12 */
47 QE_BRG13, /* Baud Rate Generator 13 */
48 QE_BRG14, /* Baud Rate Generator 14 */
49 QE_BRG15, /* Baud Rate Generator 15 */
50 QE_BRG16, /* Baud Rate Generator 16 */
51 QE_CLK1, /* Clock 1 */
52 QE_CLK2, /* Clock 2 */
53 QE_CLK3, /* Clock 3 */
54 QE_CLK4, /* Clock 4 */
55 QE_CLK5, /* Clock 5 */
56 QE_CLK6, /* Clock 6 */
57 QE_CLK7, /* Clock 7 */
58 QE_CLK8, /* Clock 8 */
59 QE_CLK9, /* Clock 9 */
60 QE_CLK10, /* Clock 10 */
61 QE_CLK11, /* Clock 11 */
62 QE_CLK12, /* Clock 12 */
63 QE_CLK13, /* Clock 13 */
64 QE_CLK14, /* Clock 14 */
65 QE_CLK15, /* Clock 15 */
66 QE_CLK16, /* Clock 16 */
67 QE_CLK17, /* Clock 17 */
68 QE_CLK18, /* Clock 18 */
69 QE_CLK19, /* Clock 19 */
70 QE_CLK20, /* Clock 20 */
71 QE_CLK21, /* Clock 21 */
72 QE_CLK22, /* Clock 22 */
73 QE_CLK23, /* Clock 23 */
74 QE_CLK24, /* Clock 24 */
78 static inline bool qe_clock_is_brg(enum qe_clock clk)
80 return clk >= QE_BRG1 && clk <= QE_BRG16;
83 extern spinlock_t cmxgcr_lock;
85 /* Export QE common operations */
86 extern void qe_reset(void);
89 #define QE_PIO_PINS 32
92 __be32 cpodr; /* Open drain register */
93 __be32 cpdata; /* Data register */
94 __be32 cpdir1; /* Direction register */
95 __be32 cpdir2; /* Direction register */
96 __be32 cppar1; /* Pin assignment register */
97 __be32 cppar2; /* Pin assignment register */
98 #ifdef CONFIG_PPC_85xx
103 extern int par_io_init(struct device_node *np);
104 extern int par_io_of_config(struct device_node *np);
105 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
106 int dir, int open_drain, int assignment,
108 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
109 int assignment, int has_irq);
110 extern int par_io_data_set(u8 port, u8 pin, u8 val);
112 /* QE internal API */
113 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
114 enum qe_clock qe_clock_source(const char *source);
115 unsigned int qe_get_brg_clk(void);
116 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
117 int qe_get_snum(void);
118 void qe_put_snum(u8 snum);
119 unsigned long qe_muram_alloc(int size, int align);
120 int qe_muram_free(unsigned long offset);
121 unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
122 void qe_muram_dump(void);
124 static inline void __iomem *qe_muram_addr(unsigned long offset)
126 return (void __iomem *)&qe_immr->muram[offset];
129 static inline unsigned long qe_muram_offset(void __iomem *addr)
131 return addr - (void __iomem *)qe_immr->muram;
134 /* Structure that defines QE firmware binary files.
136 * See Documentation/powerpc/qe-firmware.txt for a description of these
141 __be32 length; /* Length of the entire structure, in bytes */
142 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
143 u8 version; /* Version of this layout. First ver is '1' */
145 u8 id[62]; /* Null-terminated identifier string */
146 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
147 u8 count; /* Number of microcode[] structures */
149 __be16 model; /* The SOC model */
150 u8 major; /* The SOC revision major */
151 u8 minor; /* The SOC revision minor */
152 } __attribute__ ((packed)) soc;
153 u8 padding[4]; /* Reserved, for alignment */
154 __be64 extended_modes; /* Extended modes */
155 __be32 vtraps[8]; /* Virtual trap addresses */
156 u8 reserved[4]; /* Reserved, for future expansion */
157 struct qe_microcode {
158 u8 id[32]; /* Null-terminated identifier */
159 __be32 traps[16]; /* Trap addresses, 0 == ignore */
160 __be32 eccr; /* The value for the ECCR register */
161 __be32 iram_offset; /* Offset into I-RAM for the code */
162 __be32 count; /* Number of 32-bit words of the code */
163 __be32 code_offset; /* Offset of the actual microcode */
164 u8 major; /* The microcode version major */
165 u8 minor; /* The microcode version minor */
166 u8 revision; /* The microcode version revision */
167 u8 padding; /* Reserved, for alignment */
168 u8 reserved[4]; /* Reserved, for future expansion */
169 } __attribute__ ((packed)) microcode[1];
170 /* All microcode binaries should be located here */
171 /* CRC32 should be located here, after the microcode binaries */
172 } __attribute__ ((packed));
174 struct qe_firmware_info {
175 char id[64]; /* Firmware name */
176 u32 vtraps[8]; /* Virtual trap addresses */
177 u64 extended_modes; /* Extended modes */
180 /* Upload a firmware to the QE */
181 int qe_upload_firmware(const struct qe_firmware *firmware);
183 /* Obtain information on the uploaded firmware */
184 struct qe_firmware_info *qe_get_firmware_info(void);
187 int qe_usb_clock_set(enum qe_clock clk, int rate);
189 /* Buffer descriptors */
194 } __attribute__ ((packed));
196 #define BD_STATUS_MASK 0xffff0000
197 #define BD_LENGTH_MASK 0x0000ffff
199 #define BD_SC_EMPTY 0x8000 /* Receive is empty */
200 #define BD_SC_READY 0x8000 /* Transmit is ready */
201 #define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
202 #define BD_SC_INTRPT 0x1000 /* Interrupt on change */
203 #define BD_SC_LAST 0x0800 /* Last buffer in frame */
204 #define BD_SC_CM 0x0200 /* Continous mode */
205 #define BD_SC_ID 0x0100 /* Rec'd too many idles */
206 #define BD_SC_P 0x0100 /* xmt preamble */
207 #define BD_SC_BR 0x0020 /* Break received */
208 #define BD_SC_FR 0x0010 /* Framing error */
209 #define BD_SC_PR 0x0008 /* Parity error */
210 #define BD_SC_OV 0x0002 /* Overrun */
211 #define BD_SC_CD 0x0001 /* ?? */
214 #define QE_INTR_TABLE_ALIGN 16 /* ??? */
215 #define QE_ALIGNMENT_OF_BD 8
216 #define QE_ALIGNMENT_OF_PRAM 64
218 /* RISC allocation */
219 enum qe_risc_allocation {
220 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
221 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
222 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
226 /* QE extended filtering Table Lookup Key Size */
227 enum qe_fltr_tbl_lookup_key_size {
228 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
229 = 0x3f, /* LookupKey parsed by the Generate LookupKey
230 CMD is truncated to 8 bytes */
231 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
232 = 0x5f, /* LookupKey parsed by the Generate LookupKey
233 CMD is truncated to 16 bytes */
236 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
237 enum qe_fltr_largest_external_tbl_lookup_key_size {
238 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
240 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
241 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
242 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
243 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
246 /* structure representing QE parameter RAM */
247 struct qe_timer_tables {
248 u16 tm_base; /* QE timer table base adr */
249 u16 tm_ptr; /* QE timer table pointer */
250 u16 r_tmr; /* QE timer mode register */
251 u16 r_tmv; /* QE timer valid register */
252 u32 tm_cmd; /* QE timer cmd register */
253 u32 tm_cnt; /* QE timer internal cnt */
254 } __attribute__ ((packed));
256 #define QE_FLTR_TAD_SIZE 8
258 /* QE extended filtering Termination Action Descriptor (TAD) */
260 u8 serialized[QE_FLTR_TAD_SIZE];
261 } __attribute__ ((packed));
263 /* Communication Direction */
268 COMM_DIR_RX_AND_TX = 3
271 /* QE CMXUCR Registers.
272 * There are two UCCs represented in each of the four CMXUCR registers.
273 * These values are for the UCC in the LSBs
275 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
276 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
277 #define QE_CMXUCR_GRANT 0x00008000
278 #define QE_CMXUCR_TSA 0x00004000
279 #define QE_CMXUCR_BKPT 0x00000100
280 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
282 /* QE CMXGCR Registers.
284 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
285 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
286 #define QE_CMXGCR_USBCS 0x0000000f
287 #define QE_CMXGCR_USBCS_CLK3 0x1
288 #define QE_CMXGCR_USBCS_CLK5 0x2
289 #define QE_CMXGCR_USBCS_CLK7 0x3
290 #define QE_CMXGCR_USBCS_CLK9 0x4
291 #define QE_CMXGCR_USBCS_CLK13 0x5
292 #define QE_CMXGCR_USBCS_CLK17 0x6
293 #define QE_CMXGCR_USBCS_CLK19 0x7
294 #define QE_CMXGCR_USBCS_CLK21 0x8
295 #define QE_CMXGCR_USBCS_BRG9 0x9
296 #define QE_CMXGCR_USBCS_BRG10 0xa
300 #define QE_CR_FLG 0x00010000
301 #define QE_RESET 0x80000000
302 #define QE_INIT_TX_RX 0x00000000
303 #define QE_INIT_RX 0x00000001
304 #define QE_INIT_TX 0x00000002
305 #define QE_ENTER_HUNT_MODE 0x00000003
306 #define QE_STOP_TX 0x00000004
307 #define QE_GRACEFUL_STOP_TX 0x00000005
308 #define QE_RESTART_TX 0x00000006
309 #define QE_CLOSE_RX_BD 0x00000007
310 #define QE_SWITCH_COMMAND 0x00000007
311 #define QE_SET_GROUP_ADDRESS 0x00000008
312 #define QE_START_IDMA 0x00000009
313 #define QE_MCC_STOP_RX 0x00000009
314 #define QE_ATM_TRANSMIT 0x0000000a
315 #define QE_HPAC_CLEAR_ALL 0x0000000b
316 #define QE_GRACEFUL_STOP_RX 0x0000001a
317 #define QE_RESTART_RX 0x0000001b
318 #define QE_HPAC_SET_PRIORITY 0x0000010b
319 #define QE_HPAC_STOP_TX 0x0000020b
320 #define QE_HPAC_STOP_RX 0x0000030b
321 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
322 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
323 #define QE_HPAC_START_TX 0x0000060b
324 #define QE_HPAC_START_RX 0x0000070b
325 #define QE_USB_STOP_TX 0x0000000a
326 #define QE_USB_RESTART_TX 0x0000000c
327 #define QE_QMC_STOP_TX 0x0000000c
328 #define QE_QMC_STOP_RX 0x0000000d
329 #define QE_SS7_SU_FIL_RESET 0x0000000e
330 /* jonathbr added from here down for 83xx */
331 #define QE_RESET_BCS 0x0000000a
332 #define QE_MCC_INIT_TX_RX_16 0x00000003
333 #define QE_MCC_STOP_TX 0x00000004
334 #define QE_MCC_INIT_TX_1 0x00000005
335 #define QE_MCC_INIT_RX_1 0x00000006
336 #define QE_MCC_RESET 0x00000007
337 #define QE_SET_TIMER 0x00000008
338 #define QE_RANDOM_NUMBER 0x0000000c
339 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
340 #define QE_ASSIGN_PAGE 0x00000012
341 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
342 #define QE_START_FLOW_CONTROL 0x00000014
343 #define QE_STOP_FLOW_CONTROL 0x00000015
344 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
346 #define QE_ASSIGN_RISC 0x00000010
347 #define QE_CR_MCN_NORMAL_SHIFT 6
348 #define QE_CR_MCN_USB_SHIFT 4
349 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
350 #define QE_CR_SNUM_SHIFT 17
352 /* QE CECR Sub Block - sub block of QE command.
354 #define QE_CR_SUBBLOCK_INVALID 0x00000000
355 #define QE_CR_SUBBLOCK_USB 0x03200000
356 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
357 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
358 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
359 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
360 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
361 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
362 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
363 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
364 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
365 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
366 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
367 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
368 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
369 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
370 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
371 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
372 #define QE_CR_SUBBLOCK_MCC1 0x03800000
373 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
374 #define QE_CR_SUBBLOCK_MCC3 0x03000000
375 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
376 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
377 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
378 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
379 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
380 #define QE_CR_SUBBLOCK_SPI1 0x01400000
381 #define QE_CR_SUBBLOCK_SPI2 0x01600000
382 #define QE_CR_SUBBLOCK_RAND 0x01c00000
383 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
384 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
386 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
387 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
388 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
389 #define QE_CR_PROTOCOL_QMC 0x02
390 #define QE_CR_PROTOCOL_UART 0x04
391 #define QE_CR_PROTOCOL_ATM_POS 0x0A
392 #define QE_CR_PROTOCOL_ETHERNET 0x0C
393 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
395 /* BRG configuration register */
396 #define QE_BRGC_ENABLE 0x00010000
397 #define QE_BRGC_DIVISOR_SHIFT 1
398 #define QE_BRGC_DIVISOR_MAX 0xFFF
399 #define QE_BRGC_DIV16 1
401 /* QE Timers registers */
402 #define QE_GTCFR1_PCAS 0x80
403 #define QE_GTCFR1_STP2 0x20
404 #define QE_GTCFR1_RST2 0x10
405 #define QE_GTCFR1_GM2 0x08
406 #define QE_GTCFR1_GM1 0x04
407 #define QE_GTCFR1_STP1 0x02
408 #define QE_GTCFR1_RST1 0x01
411 #define QE_SDSR_BER1 0x02000000
412 #define QE_SDSR_BER2 0x01000000
414 #define QE_SDMR_GLB_1_MSK 0x80000000
415 #define QE_SDMR_ADR_SEL 0x20000000
416 #define QE_SDMR_BER1_MSK 0x02000000
417 #define QE_SDMR_BER2_MSK 0x01000000
418 #define QE_SDMR_EB1_MSK 0x00800000
419 #define QE_SDMR_ER1_MSK 0x00080000
420 #define QE_SDMR_ER2_MSK 0x00040000
421 #define QE_SDMR_CEN_MASK 0x0000E000
422 #define QE_SDMR_SBER_1 0x00000200
423 #define QE_SDMR_SBER_2 0x00000200
424 #define QE_SDMR_EB1_PR_MASK 0x000000C0
425 #define QE_SDMR_ER1_PR 0x00000008
427 #define QE_SDMR_CEN_SHIFT 13
428 #define QE_SDMR_EB1_PR_SHIFT 6
430 #define QE_SDTM_MSNUM_SHIFT 24
432 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
434 /* Communication Processor */
435 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
436 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
437 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
440 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
441 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
444 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
445 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
446 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
447 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
448 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
450 /* UCC GUEMR register */
451 #define UCC_GUEMR_MODE_MASK_RX 0x02
452 #define UCC_GUEMR_MODE_FAST_RX 0x02
453 #define UCC_GUEMR_MODE_SLOW_RX 0x00
454 #define UCC_GUEMR_MODE_MASK_TX 0x01
455 #define UCC_GUEMR_MODE_FAST_TX 0x01
456 #define UCC_GUEMR_MODE_SLOW_TX 0x00
457 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
458 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
461 /* structure representing UCC SLOW parameter RAM */
462 struct ucc_slow_pram {
463 __be16 rbase; /* RX BD base address */
464 __be16 tbase; /* TX BD base address */
465 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
466 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
467 __be16 mrblr; /* Rx buffer length */
468 __be32 rstate; /* Rx internal state */
469 __be32 rptr; /* Rx internal data pointer */
470 __be16 rbptr; /* rb BD Pointer */
471 __be16 rcount; /* Rx internal byte count */
472 __be32 rtemp; /* Rx temp */
473 __be32 tstate; /* Tx internal state */
474 __be32 tptr; /* Tx internal data pointer */
475 __be16 tbptr; /* Tx BD pointer */
476 __be16 tcount; /* Tx byte count */
477 __be32 ttemp; /* Tx temp */
478 __be32 rcrc; /* temp receive CRC */
479 __be32 tcrc; /* temp transmit CRC */
480 } __attribute__ ((packed));
482 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
483 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
484 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
485 #define UCC_SLOW_GUMR_H_REVD 0x00002000
486 #define UCC_SLOW_GUMR_H_TRX 0x00001000
487 #define UCC_SLOW_GUMR_H_TTX 0x00000800
488 #define UCC_SLOW_GUMR_H_CDP 0x00000400
489 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
490 #define UCC_SLOW_GUMR_H_CDS 0x00000100
491 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
492 #define UCC_SLOW_GUMR_H_TFL 0x00000040
493 #define UCC_SLOW_GUMR_H_RFW 0x00000020
494 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
495 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
496 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
497 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
498 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
499 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
501 #define UCC_SLOW_GUMR_L_TCI 0x10000000
502 #define UCC_SLOW_GUMR_L_RINV 0x02000000
503 #define UCC_SLOW_GUMR_L_TINV 0x01000000
504 #define UCC_SLOW_GUMR_L_TEND 0x00040000
505 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
506 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
507 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
508 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
509 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
510 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
511 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
512 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
513 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
514 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
515 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
516 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
517 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
518 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
519 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
520 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
521 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
522 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
523 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
524 #define UCC_SLOW_GUMR_L_ENR 0x00000020
525 #define UCC_SLOW_GUMR_L_ENT 0x00000010
526 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
527 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
528 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
529 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
530 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
532 /* General UCC FAST Mode Register */
533 #define UCC_FAST_GUMR_TCI 0x20000000
534 #define UCC_FAST_GUMR_TRX 0x10000000
535 #define UCC_FAST_GUMR_TTX 0x08000000
536 #define UCC_FAST_GUMR_CDP 0x04000000
537 #define UCC_FAST_GUMR_CTSP 0x02000000
538 #define UCC_FAST_GUMR_CDS 0x01000000
539 #define UCC_FAST_GUMR_CTSS 0x00800000
540 #define UCC_FAST_GUMR_TXSY 0x00020000
541 #define UCC_FAST_GUMR_RSYN 0x00010000
542 #define UCC_FAST_GUMR_RTSM 0x00002000
543 #define UCC_FAST_GUMR_REVD 0x00000400
544 #define UCC_FAST_GUMR_ENR 0x00000020
545 #define UCC_FAST_GUMR_ENT 0x00000010
547 /* UART Slow UCC Event Register (UCCE) */
548 #define UCC_UART_UCCE_AB 0x0200
549 #define UCC_UART_UCCE_IDLE 0x0100
550 #define UCC_UART_UCCE_GRA 0x0080
551 #define UCC_UART_UCCE_BRKE 0x0040
552 #define UCC_UART_UCCE_BRKS 0x0020
553 #define UCC_UART_UCCE_CCR 0x0008
554 #define UCC_UART_UCCE_BSY 0x0004
555 #define UCC_UART_UCCE_TX 0x0002
556 #define UCC_UART_UCCE_RX 0x0001
558 /* HDLC Slow UCC Event Register (UCCE) */
559 #define UCC_HDLC_UCCE_GLR 0x1000
560 #define UCC_HDLC_UCCE_GLT 0x0800
561 #define UCC_HDLC_UCCE_IDLE 0x0100
562 #define UCC_HDLC_UCCE_BRKE 0x0040
563 #define UCC_HDLC_UCCE_BRKS 0x0020
564 #define UCC_HDLC_UCCE_TXE 0x0010
565 #define UCC_HDLC_UCCE_RXF 0x0008
566 #define UCC_HDLC_UCCE_BSY 0x0004
567 #define UCC_HDLC_UCCE_TXB 0x0002
568 #define UCC_HDLC_UCCE_RXB 0x0001
570 /* BISYNC Slow UCC Event Register (UCCE) */
571 #define UCC_BISYNC_UCCE_GRA 0x0080
572 #define UCC_BISYNC_UCCE_TXE 0x0010
573 #define UCC_BISYNC_UCCE_RCH 0x0008
574 #define UCC_BISYNC_UCCE_BSY 0x0004
575 #define UCC_BISYNC_UCCE_TXB 0x0002
576 #define UCC_BISYNC_UCCE_RXB 0x0001
578 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
579 #define UCC_GETH_UCCE_MPD 0x80000000
580 #define UCC_GETH_UCCE_SCAR 0x40000000
581 #define UCC_GETH_UCCE_GRA 0x20000000
582 #define UCC_GETH_UCCE_CBPR 0x10000000
583 #define UCC_GETH_UCCE_BSY 0x08000000
584 #define UCC_GETH_UCCE_RXC 0x04000000
585 #define UCC_GETH_UCCE_TXC 0x02000000
586 #define UCC_GETH_UCCE_TXE 0x01000000
587 #define UCC_GETH_UCCE_TXB7 0x00800000
588 #define UCC_GETH_UCCE_TXB6 0x00400000
589 #define UCC_GETH_UCCE_TXB5 0x00200000
590 #define UCC_GETH_UCCE_TXB4 0x00100000
591 #define UCC_GETH_UCCE_TXB3 0x00080000
592 #define UCC_GETH_UCCE_TXB2 0x00040000
593 #define UCC_GETH_UCCE_TXB1 0x00020000
594 #define UCC_GETH_UCCE_TXB0 0x00010000
595 #define UCC_GETH_UCCE_RXB7 0x00008000
596 #define UCC_GETH_UCCE_RXB6 0x00004000
597 #define UCC_GETH_UCCE_RXB5 0x00002000
598 #define UCC_GETH_UCCE_RXB4 0x00001000
599 #define UCC_GETH_UCCE_RXB3 0x00000800
600 #define UCC_GETH_UCCE_RXB2 0x00000400
601 #define UCC_GETH_UCCE_RXB1 0x00000200
602 #define UCC_GETH_UCCE_RXB0 0x00000100
603 #define UCC_GETH_UCCE_RXF7 0x00000080
604 #define UCC_GETH_UCCE_RXF6 0x00000040
605 #define UCC_GETH_UCCE_RXF5 0x00000020
606 #define UCC_GETH_UCCE_RXF4 0x00000010
607 #define UCC_GETH_UCCE_RXF3 0x00000008
608 #define UCC_GETH_UCCE_RXF2 0x00000004
609 #define UCC_GETH_UCCE_RXF1 0x00000002
610 #define UCC_GETH_UCCE_RXF0 0x00000001
612 /* UPSMR, when used as a UART */
613 #define UCC_UART_UPSMR_FLC 0x8000
614 #define UCC_UART_UPSMR_SL 0x4000
615 #define UCC_UART_UPSMR_CL_MASK 0x3000
616 #define UCC_UART_UPSMR_CL_8 0x3000
617 #define UCC_UART_UPSMR_CL_7 0x2000
618 #define UCC_UART_UPSMR_CL_6 0x1000
619 #define UCC_UART_UPSMR_CL_5 0x0000
620 #define UCC_UART_UPSMR_UM_MASK 0x0c00
621 #define UCC_UART_UPSMR_UM_NORMAL 0x0000
622 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
623 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
624 #define UCC_UART_UPSMR_FRZ 0x0200
625 #define UCC_UART_UPSMR_RZS 0x0100
626 #define UCC_UART_UPSMR_SYN 0x0080
627 #define UCC_UART_UPSMR_DRT 0x0040
628 #define UCC_UART_UPSMR_PEN 0x0010
629 #define UCC_UART_UPSMR_RPM_MASK 0x000c
630 #define UCC_UART_UPSMR_RPM_ODD 0x0000
631 #define UCC_UART_UPSMR_RPM_LOW 0x0004
632 #define UCC_UART_UPSMR_RPM_EVEN 0x0008
633 #define UCC_UART_UPSMR_RPM_HIGH 0x000C
634 #define UCC_UART_UPSMR_TPM_MASK 0x0003
635 #define UCC_UART_UPSMR_TPM_ODD 0x0000
636 #define UCC_UART_UPSMR_TPM_LOW 0x0001
637 #define UCC_UART_UPSMR_TPM_EVEN 0x0002
638 #define UCC_UART_UPSMR_TPM_HIGH 0x0003
640 /* UCC Transmit On Demand Register (UTODR) */
641 #define UCC_SLOW_TOD 0x8000
642 #define UCC_FAST_TOD 0x8000
644 /* UCC Bus Mode Register masks */
645 /* Not to be confused with the Bundle Mode Register */
646 #define UCC_BMR_GBL 0x20
647 #define UCC_BMR_BO_BE 0x10
648 #define UCC_BMR_CETM 0x04
649 #define UCC_BMR_DTB 0x02
650 #define UCC_BMR_BDB 0x01
652 /* Function code masks */
654 #define FC_DTB_LCL 0x02
655 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
656 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
657 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
659 #endif /* __KERNEL__ */
660 #endif /* _ASM_POWERPC_QE_H */