1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
4 #include <asm/asm-compat.h>
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25 #define PPC_FEATURE_ARCH_2_05 0x00001000
30 /* This structure can grow, it's real size is used by head.S code
31 * via the mkdefs mechanism.
35 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
37 enum powerpc_oprofile_type {
38 PPC_OPROFILE_INVALID = 0,
39 PPC_OPROFILE_RS64 = 1,
40 PPC_OPROFILE_POWER4 = 2,
42 PPC_OPROFILE_BOOKE = 4,
46 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
47 unsigned int pvr_mask;
48 unsigned int pvr_value;
51 unsigned long cpu_features; /* Kernel features */
52 unsigned int cpu_user_features; /* Userland features */
54 /* cache line sizes */
55 unsigned int icache_bsize;
56 unsigned int dcache_bsize;
58 /* number of performance monitor counters */
59 unsigned int num_pmcs;
61 /* this is called to initialize various CPU bits like L1 cache,
62 * BHT, SPD, etc... from head.S before branching to identify_machine
64 cpu_setup_t cpu_setup;
66 /* Used by oprofile userspace to select the right counters */
67 char *oprofile_cpu_type;
69 /* Processor specific oprofile operations */
70 enum powerpc_oprofile_type oprofile_type;
72 /* Bit locations inside the mmcra change */
73 unsigned long oprofile_mmcra_sihv;
74 unsigned long oprofile_mmcra_sipr;
76 /* Bits to clear during an oprofile exception */
77 unsigned long oprofile_mmcra_clear;
79 /* Name of processor class, for the ELF AT_PLATFORM entry */
83 extern struct cpu_spec *cur_cpu_spec;
85 extern void identify_cpu(unsigned long offset, unsigned long cpu);
86 extern void do_cpu_ftr_fixups(unsigned long offset);
88 #endif /* __ASSEMBLY__ */
90 /* CPU kernel features */
92 /* Retain the 32b definitions all use bottom half of word */
93 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
94 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
95 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
96 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
97 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
98 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
99 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
100 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
101 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
102 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
103 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
104 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
105 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
106 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
107 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
108 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
109 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
110 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
111 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
112 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
113 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
116 /* Add the 64b processor unique features in the top half of the word */
117 #define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
118 #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
119 #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
120 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
121 #define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
122 #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
123 #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
124 #define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
125 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
126 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
127 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
128 #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
129 #define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
131 /* ensure on 32b processors the flags are available for compiling but
132 * don't do anything */
133 #define CPU_FTR_SLB ASM_CONST(0x0)
134 #define CPU_FTR_16M_PAGE ASM_CONST(0x0)
135 #define CPU_FTR_TLBIEL ASM_CONST(0x0)
136 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
137 #define CPU_FTR_IABR ASM_CONST(0x0)
138 #define CPU_FTR_MMCRA ASM_CONST(0x0)
139 #define CPU_FTR_CTRL ASM_CONST(0x0)
140 #define CPU_FTR_SMT ASM_CONST(0x0)
141 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
142 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
143 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
144 #define CPU_FTR_PURR ASM_CONST(0x0)
149 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
150 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
151 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
153 /* iSeries doesn't support large pages */
154 #ifdef CONFIG_PPC_ISERIES
155 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
157 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
158 #endif /* CONFIG_PPC_ISERIES */
160 /* We only set the altivec features if the kernel was compiled with altivec
163 #ifdef CONFIG_ALTIVEC
164 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
165 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
167 #define CPU_FTR_ALTIVEC_COMP 0
168 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
171 /* We need to mark all pages as being coherent if we're SMP or we
172 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
173 * it for PCI "streaming/prefetch" to work properly.
175 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
176 || defined(CONFIG_PPC_83xx)
177 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
179 #define CPU_FTR_COMMON 0
182 /* The powersave features NAP & DOZE seems to confuse BDI when
183 debugging. So if a BDI is used, disable theses
185 #ifndef CONFIG_BDI_SWITCH
186 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
187 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
189 #define CPU_FTR_MAYBE_CAN_DOZE 0
190 #define CPU_FTR_MAYBE_CAN_NAP 0
193 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
194 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
195 !defined(CONFIG_BOOKE))
197 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
198 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
200 CPU_FTR_MAYBE_CAN_NAP)
201 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
202 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE)
203 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
204 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
205 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
206 #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
207 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
208 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
209 #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
211 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
212 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
213 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
214 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
215 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
216 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
217 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
218 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
220 #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
221 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
222 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
223 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
224 #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
225 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
226 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
227 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
228 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
229 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
230 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
231 CPU_FTR_MAYBE_CAN_NAP)
232 #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
233 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
234 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
235 CPU_FTR_MAYBE_CAN_NAP)
236 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
237 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
239 CPU_FTR_NEED_COHERENT)
240 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
243 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
244 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
245 CPU_FTR_NEED_COHERENT)
246 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT)
251 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
253 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
254 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
255 CPU_FTR_NEED_COHERENT)
256 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
258 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
259 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
260 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
261 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS)
262 #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
264 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
265 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
266 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
267 CPU_FTR_NEED_COHERENT)
268 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
271 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
272 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
273 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC)
274 #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
277 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
278 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
279 CPU_FTR_NEED_COHERENT)
280 #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
283 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
285 CPU_FTR_NEED_COHERENT)
286 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
287 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
288 #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
289 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
290 #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
291 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
293 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
294 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
295 #define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
296 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
297 #define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
298 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN)
299 #define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
300 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
302 #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
303 #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
304 CPU_FTR_NODSISRALIGN)
305 #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
308 #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
309 CPU_FTR_NODSISRALIGN)
310 #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
312 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
314 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
315 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR)
316 #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
317 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
318 CPU_FTR_MMCRA | CPU_FTR_CTRL)
319 #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
321 #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
322 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
323 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
324 #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
326 CPU_FTR_MMCRA | CPU_FTR_SMT | \
327 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
329 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
330 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
331 CPU_FTR_MMCRA | CPU_FTR_SMT | \
332 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
333 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE)
334 #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
335 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
336 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
337 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
338 #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
339 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
343 #define CPU_FTRS_POSSIBLE \
344 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
345 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
346 CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
351 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
352 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
353 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
354 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
355 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
356 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
357 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
358 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
360 CPU_FTRS_GENERIC_32 |
362 #ifdef CONFIG_PPC64BRIDGE
366 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
381 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
385 #endif /* __powerpc64__ */
388 #define CPU_FTRS_ALWAYS \
389 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
390 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
391 CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
396 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
397 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
398 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
399 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
400 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
401 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
402 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
403 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
405 CPU_FTRS_GENERIC_32 &
407 #ifdef CONFIG_PPC64BRIDGE
411 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
426 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
430 #endif /* __powerpc64__ */
432 static inline int cpu_has_feature(unsigned long feature)
434 return (CPU_FTRS_ALWAYS & feature) ||
436 & cur_cpu_spec->cpu_features
440 #endif /* !__ASSEMBLY__ */
444 #define BEGIN_FTR_SECTION 98:
446 #ifndef __powerpc64__
447 #define END_FTR_SECTION(msk, val) \
449 .section __ftr_fixup,"a"; \
456 #else /* __powerpc64__ */
457 #define END_FTR_SECTION(msk, val) \
459 .section __ftr_fixup,"a"; \
466 #endif /* __powerpc64__ */
468 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
469 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
470 #endif /* __ASSEMBLY__ */
472 #endif /* __KERNEL__ */
473 #endif /* __ASM_POWERPC_CPUTABLE_H */