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   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/types.h>
  16 #include <linux/irqflags.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/barrier.h>
  20 #include <asm/cmpxchg.h>
  21 #include <asm/cpu-features.h>
  22 #include <asm/dsp.h>
  23 #include <asm/war.h>
  24
  25
  26 /*
  27  * switch_to(n) should switch tasks to task nr n, first
  28  * checking that n isn't the current task, in which case it does nothing.
  29  */
  30 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
  31
  32 struct task_struct;
  33
  34 #ifdef CONFIG_MIPS_MT_FPAFF
  35
  36 /*
  37  * Handle the scheduler resume end of FPU affinity management.  We do this
  38  * inline to try to keep the overhead down. If we have been forced to run on
  39  * a "CPU" with an FPU because of a previous high level of FP computation,
  40  * but did not actually use the FPU during the most recent time-slice (CU1
  41  * isn't set), we undo the restriction on cpus_allowed.
  42  *
  43  * We're not calling set_cpus_allowed() here, because we have no need to
  44  * force prompt migration - we're already switching the current CPU to a
  45  * different thread.
  46  */
  47
  48 #define __mips_mt_fpaff_switch_to(prev)                                 \
  49 do {                                                                    \
  50         struct thread_info *__prev_ti = task_thread_info(prev);         \
  51                                                                         \
  52         if (cpu_has_fpu &&                                              \
  53             test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
  54             (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
  55                 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
  56                 prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
  57         }                                                               \
  58         next->thread.emulated_fp = 0;                                   \
  59 } while(0)
  60
  61 #else
  62 #define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
  63 #endif
  64
  65 #define switch_to(prev,next,last)                                       \
  66 do {                                                                    \
  67         __mips_mt_fpaff_switch_to(prev);                                \
  68         if (cpu_has_dsp)                                                \
  69                 __save_dsp(prev);                                       \
  70         (last) = resume(prev, next, task_thread_info(next));            \
  71         if (cpu_has_dsp)                                                \
  72                 __restore_dsp(current);                                 \
  73         if (cpu_has_userlocal)                                          \
  74                 write_c0_userlocal(task_thread_info(current)->tp_value);\
  75 } while(0)
  76
  77 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
  78 {
  79         __u32 retval;
  80
  81         if (cpu_has_llsc && R10000_LLSC_WAR) {
  82                 unsigned long dummy;
  83
  84                 __asm__ __volatile__(
  85                 "       .set    mips3                                   \n"
  86                 "1:     ll      %0, %3                  # xchg_u32      \n"
  87                 "       .set    mips0                                   \n"
  88                 "       move    %2, %z4                                 \n"
  89                 "       .set    mips3                                   \n"
  90                 "       sc      %2, %1                                  \n"
  91                 "       beqzl   %2, 1b                                  \n"
  92                 "       .set    mips0                                   \n"
  93                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
  94                 : "R" (*m), "Jr" (val)
  95                 : "memory");
  96         } else if (cpu_has_llsc) {
  97                 unsigned long dummy;
  98
  99                 __asm__ __volatile__(
 100                 "       .set    mips3                                   \n"
 101                 "1:     ll      %0, %3                  # xchg_u32      \n"
 102                 "       .set    mips0                                   \n"
 103                 "       move    %2, %z4                                 \n"
 104                 "       .set    mips3                                   \n"
 105                 "       sc      %2, %1                                  \n"
 106                 "       beqz    %2, 2f                                  \n"
 107                 "       .subsection 2                                   \n"
 108                 "2:     b       1b                                      \n"
 109                 "       .previous                                       \n"
 110                 "       .set    mips0                                   \n"
 111                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 112                 : "R" (*m), "Jr" (val)
 113                 : "memory");
 114         } else {
 115                 unsigned long flags;
 116
 117                 raw_local_irq_save(flags);
 118                 retval = *m;
 119                 *m = val;
 120                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 121         }
 122
 123         smp_llsc_mb();
 124
 125         return retval;
 126 }
 127
 128 #ifdef CONFIG_64BIT
 129 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 130 {
 131         __u64 retval;
 132
 133         if (cpu_has_llsc && R10000_LLSC_WAR) {
 134                 unsigned long dummy;
 135
 136                 __asm__ __volatile__(
 137                 "       .set    mips3                                   \n"
 138                 "1:     lld     %0, %3                  # xchg_u64      \n"
 139                 "       move    %2, %z4                                 \n"
 140                 "       scd     %2, %1                                  \n"
 141                 "       beqzl   %2, 1b                                  \n"
 142                 "       .set    mips0                                   \n"
 143                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 144                 : "R" (*m), "Jr" (val)
 145                 : "memory");
 146         } else if (cpu_has_llsc) {
 147                 unsigned long dummy;
 148
 149                 __asm__ __volatile__(
 150                 "       .set    mips3                                   \n"
 151                 "1:     lld     %0, %3                  # xchg_u64      \n"
 152                 "       move    %2, %z4                                 \n"
 153                 "       scd     %2, %1                                  \n"
 154                 "       beqz    %2, 2f                                  \n"
 155                 "       .subsection 2                                   \n"
 156                 "2:     b       1b                                      \n"
 157                 "       .previous                                       \n"
 158                 "       .set    mips0                                   \n"
 159                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 160                 : "R" (*m), "Jr" (val)
 161                 : "memory");
 162         } else {
 163                 unsigned long flags;
 164
 165                 raw_local_irq_save(flags);
 166                 retval = *m;
 167                 *m = val;
 168                 raw_local_irq_restore(flags);   /* implies memory barrier  */
 169         }
 170
 171         smp_llsc_mb();
 172
 173         return retval;
 174 }
 175 #else
 176 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 177 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 178 #endif
 179
 180 /* This function doesn't exist, so you'll get a linker error
 181    if something tries to do an invalid xchg().  */
 182 extern void __xchg_called_with_bad_pointer(void);
 183
 184 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 185 {
 186         switch (size) {
 187         case 4:
 188                 return __xchg_u32(ptr, x);
 189         case 8:
 190                 return __xchg_u64(ptr, x);
 191         }
 192         __xchg_called_with_bad_pointer();
 193         return x;
 194 }
 195
 196 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 197
 198 extern void set_handler(unsigned long offset, void *addr, unsigned long len);
 199 extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
 200
 201 typedef void (*vi_handler_t)(void);
 202 extern void *set_vi_handler(int n, vi_handler_t addr);
 203
 204 extern void *set_except_vector(int n, void *addr);
 205 extern unsigned long ebase;
 206 extern void per_cpu_trap_init(void);
 207
 208 extern int stop_a_enabled;
 209
 210 /*
 211  * See include/asm-ia64/system.h; prevents deadlock on SMP
 212  * systems.
 213  */
 214 #define __ARCH_WANT_UNLOCKED_CTXSW
 215
 216 extern unsigned long arch_align_stack(unsigned long sp);
 217
 218 #endif /* _ASM_SYSTEM_H */