SAFE public projects git trees. - safe/jmp/linux-2.6/blob - include/asm-mips/spinlock.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1999, 2000 by Ralf Baechle
   7  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   8  */
   9 #ifndef _ASM_SPINLOCK_H
  10 #define _ASM_SPINLOCK_H
  11
  12 #include <linux/config.h>
  13 #include <asm/war.h>
  14
  15 /*
  16  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  17  */
  18
  19 #define __raw_spin_is_locked(x) ((x)->lock != 0)
  20 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  21 #define __raw_spin_unlock_wait(x) \
  22                 do { cpu_relax(); } while ((x)->lock)
  23
  24 /*
  25  * Simple spin lock operations.  There are two variants, one clears IRQ's
  26  * on the local processor, one does not.
  27  *
  28  * We make no fairness assumptions.  They have a cost.
  29  */
  30
  31 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  32 {
  33         unsigned int tmp;
  34
  35         if (R10000_LLSC_WAR) {
  36                 __asm__ __volatile__(
  37                 "       .set    noreorder       # __raw_spin_lock       \n"
  38                 "1:     ll      %1, %2                                  \n"
  39                 "       bnez    %1, 1b                                  \n"
  40                 "        li     %1, 1                                   \n"
  41                 "       sc      %1, %0                                  \n"
  42                 "       beqzl   %1, 1b                                  \n"
  43                 "        nop                                            \n"
  44                 "       sync                                            \n"
  45                 "       .set    reorder                                 \n"
  46                 : "=m" (lock->lock), "=&r" (tmp)
  47                 : "m" (lock->lock)
  48                 : "memory");
  49         } else {
  50                 __asm__ __volatile__(
  51                 "       .set    noreorder       # __raw_spin_lock       \n"
  52                 "1:     ll      %1, %2                                  \n"
  53                 "       bnez    %1, 1b                                  \n"
  54                 "        li     %1, 1                                   \n"
  55                 "       sc      %1, %0                                  \n"
  56                 "       beqz    %1, 1b                                  \n"
  57                 "        sync                                           \n"
  58                 "       .set    reorder                                 \n"
  59                 : "=m" (lock->lock), "=&r" (tmp)
  60                 : "m" (lock->lock)
  61                 : "memory");
  62         }
  63 }
  64
  65 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  66 {
  67         __asm__ __volatile__(
  68         "       .set    noreorder       # __raw_spin_unlock     \n"
  69         "       sync                                            \n"
  70         "       sw      $0, %0                                  \n"
  71         "       .set\treorder                                   \n"
  72         : "=m" (lock->lock)
  73         : "m" (lock->lock)
  74         : "memory");
  75 }
  76
  77 static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
  78 {
  79         unsigned int temp, res;
  80
  81         if (R10000_LLSC_WAR) {
  82                 __asm__ __volatile__(
  83                 "       .set    noreorder       # __raw_spin_trylock    \n"
  84                 "1:     ll      %0, %3                                  \n"
  85                 "       ori     %2, %0, 1                               \n"
  86                 "       sc      %2, %1                                  \n"
  87                 "       beqzl   %2, 1b                                  \n"
  88                 "        nop                                            \n"
  89                 "       andi    %2, %0, 1                               \n"
  90                 "       sync                                            \n"
  91                 "       .set    reorder"
  92                 : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
  93                 : "m" (lock->lock)
  94                 : "memory");
  95         } else {
  96                 __asm__ __volatile__(
  97                 "       .set    noreorder       # __raw_spin_trylock    \n"
  98                 "1:     ll      %0, %3                                  \n"
  99                 "       ori     %2, %0, 1                               \n"
 100                 "       sc      %2, %1                                  \n"
 101                 "       beqz    %2, 1b                                  \n"
 102                 "        andi   %2, %0, 1                               \n"
 103                 "       sync                                            \n"
 104                 "       .set    reorder"
 105                 : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
 106                 : "m" (lock->lock)
 107                 : "memory");
 108         }
 109
 110         return res == 0;
 111 }
 112
 113 /*
 114  * Read-write spinlocks, allowing multiple readers but only one writer.
 115  *
 116  * NOTE! it is quite common to have readers in interrupts but no interrupt
 117  * writers. For those circumstances we can "mix" irq-safe locks - any writer
 118  * needs to get a irq-safe write-lock, but readers can get non-irqsafe
 119  * read-locks.
 120  */
 121
 122 /*
 123  * read_can_lock - would read_trylock() succeed?
 124  * @lock: the rwlock in question.
 125  */
 126 #define __raw_read_can_lock(rw) ((rw)->lock >= 0)
 127
 128 /*
 129  * write_can_lock - would write_trylock() succeed?
 130  * @lock: the rwlock in question.
 131  */
 132 #define __raw_write_can_lock(rw)        (!(rw)->lock)
 133
 134 static inline void __raw_read_lock(raw_rwlock_t *rw)
 135 {
 136         unsigned int tmp;
 137
 138         if (R10000_LLSC_WAR) {
 139                 __asm__ __volatile__(
 140                 "       .set    noreorder       # __raw_read_lock       \n"
 141                 "1:     ll      %1, %2                                  \n"
 142                 "       bltz    %1, 1b                                  \n"
 143                 "        addu   %1, 1                                   \n"
 144                 "       sc      %1, %0                                  \n"
 145                 "       beqzl   %1, 1b                                  \n"
 146                 "        nop                                            \n"
 147                 "       sync                                            \n"
 148                 "       .set    reorder                                 \n"
 149                 : "=m" (rw->lock), "=&r" (tmp)
 150                 : "m" (rw->lock)
 151                 : "memory");
 152         } else {
 153                 __asm__ __volatile__(
 154                 "       .set    noreorder       # __raw_read_lock       \n"
 155                 "1:     ll      %1, %2                                  \n"
 156                 "       bltz    %1, 1b                                  \n"
 157                 "        addu   %1, 1                                   \n"
 158                 "       sc      %1, %0                                  \n"
 159                 "       beqz    %1, 1b                                  \n"
 160                 "        sync                                           \n"
 161                 "       .set    reorder                                 \n"
 162                 : "=m" (rw->lock), "=&r" (tmp)
 163                 : "m" (rw->lock)
 164                 : "memory");
 165         }
 166 }
 167
 168 /* Note the use of sub, not subu which will make the kernel die with an
 169    overflow exception if we ever try to unlock an rwlock that is already
 170    unlocked or is being held by a writer.  */
 171 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 172 {
 173         unsigned int tmp;
 174
 175         if (R10000_LLSC_WAR) {
 176                 __asm__ __volatile__(
 177                 "1:     ll      %1, %2          # __raw_read_unlock     \n"
 178                 "       sub     %1, 1                                   \n"
 179                 "       sc      %1, %0                                  \n"
 180                 "       beqzl   %1, 1b                                  \n"
 181                 "       sync                                            \n"
 182                 : "=m" (rw->lock), "=&r" (tmp)
 183                 : "m" (rw->lock)
 184                 : "memory");
 185         } else {
 186                 __asm__ __volatile__(
 187                 "       .set    noreorder       # __raw_read_unlock     \n"
 188                 "1:     ll      %1, %2                                  \n"
 189                 "       sub     %1, 1                                   \n"
 190                 "       sc      %1, %0                                  \n"
 191                 "       beqz    %1, 1b                                  \n"
 192                 "        sync                                           \n"
 193                 "       .set    reorder                                 \n"
 194                 : "=m" (rw->lock), "=&r" (tmp)
 195                 : "m" (rw->lock)
 196                 : "memory");
 197         }
 198 }
 199
 200 static inline void __raw_write_lock(raw_rwlock_t *rw)
 201 {
 202         unsigned int tmp;
 203
 204         if (R10000_LLSC_WAR) {
 205                 __asm__ __volatile__(
 206                 "       .set    noreorder       # __raw_write_lock      \n"
 207                 "1:     ll      %1, %2                                  \n"
 208                 "       bnez    %1, 1b                                  \n"
 209                 "        lui    %1, 0x8000                              \n"
 210                 "       sc      %1, %0                                  \n"
 211                 "       beqzl   %1, 1b                                  \n"
 212                 "        sync                                           \n"
 213                 "       .set    reorder                                 \n"
 214                 : "=m" (rw->lock), "=&r" (tmp)
 215                 : "m" (rw->lock)
 216                 : "memory");
 217         } else {
 218                 __asm__ __volatile__(
 219                 "       .set    noreorder       # __raw_write_lock      \n"
 220                 "1:     ll      %1, %2                                  \n"
 221                 "       bnez    %1, 1b                                  \n"
 222                 "        lui    %1, 0x8000                              \n"
 223                 "       sc      %1, %0                                  \n"
 224                 "       beqz    %1, 1b                                  \n"
 225                 "        sync                                           \n"
 226                 "       .set    reorder                                 \n"
 227                 : "=m" (rw->lock), "=&r" (tmp)
 228                 : "m" (rw->lock)
 229                 : "memory");
 230         }
 231 }
 232
 233 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 234 {
 235         __asm__ __volatile__(
 236         "       sync                    # __raw_write_unlock    \n"
 237         "       sw      $0, %0                                  \n"
 238         : "=m" (rw->lock)
 239         : "m" (rw->lock)
 240         : "memory");
 241 }
 242
 243 #define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
 244
 245 static inline int __raw_write_trylock(raw_rwlock_t *rw)
 246 {
 247         unsigned int tmp;
 248         int ret;
 249
 250         if (R10000_LLSC_WAR) {
 251                 __asm__ __volatile__(
 252                 "       .set    noreorder       # __raw_write_trylock   \n"
 253                 "       li      %2, 0                                   \n"
 254                 "1:     ll      %1, %3                                  \n"
 255                 "       bnez    %1, 2f                                  \n"
 256                 "        lui    %1, 0x8000                              \n"
 257                 "       sc      %1, %0                                  \n"
 258                 "       beqzl   %1, 1b                                  \n"
 259                 "        sync                                           \n"
 260                 "       li      %2, 1                                   \n"
 261                 "       .set    reorder                                 \n"
 262                 "2:                                                     \n"
 263                 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
 264                 : "m" (rw->lock)
 265                 : "memory");
 266         } else {
 267                 __asm__ __volatile__(
 268                 "       .set    noreorder       # __raw_write_trylock   \n"
 269                 "       li      %2, 0                                   \n"
 270                 "1:     ll      %1, %3                                  \n"
 271                 "       bnez    %1, 2f                                  \n"
 272                 "       lui     %1, 0x8000                              \n"
 273                 "       sc      %1, %0                                  \n"
 274                 "       beqz    %1, 1b                                  \n"
 275                 "        sync                                           \n"
 276                 "       li      %2, 1                                   \n"
 277                 "       .set    reorder                                 \n"
 278                 "2:                                                     \n"
 279                 : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
 280                 : "m" (rw->lock)
 281                 : "memory");
 282         }
 283
 284         return ret;
 285 }
 286
 287 #endif /* _ASM_SPINLOCK_H */