1 /* *********************************************************************
2 * BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
4 * Register Definitions File: bcm1480_regs.h
6 * This module contains the addresses of the on-chip peripherals
7 * on the BCM1280 and BCM1480.
9 * BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
11 *********************************************************************
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 ********************************************************************* */
32 #ifndef _BCM1480_REGS_H
33 #define _BCM1480_REGS_H
35 #include "sb1250_defs.h"
37 /* *********************************************************************
38 * Pull in the BCM1250's registers since a great deal of the 1480's
39 * functions are the same as the BCM1250.
40 ********************************************************************* */
42 #include "sb1250_regs.h"
45 /* *********************************************************************
48 * Register addresses are grouped by function and follow the order
51 * For the most part, when there is more than one peripheral
52 * of the same type on the SOC, the constants below will be
53 * offsets from the base of each peripheral. For example,
54 * the MAC registers are described as offsets from the first
55 * MAC register, and there will be a MAC_REGISTER() macro
56 * to calculate the base address of a given MAC.
58 * The information in this file is based on the BCM1X55/BCM1X80
59 * User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
61 * This file is basically a "what's new" header file. Since the
62 * BCM1250 and the new BCM1480 (and derivatives) share many common
63 * features, this file contains only what's new or changed from
64 * the 1250. (above, you can see that we include the 1250 symbols
65 * to get the base functionality).
67 * In software, be sure to use the correct symbols, particularly
68 * for blocks that are different between the two chip families.
69 * All BCM1480-specific symbols have _BCM1480_ in their names,
70 * and all BCM1250-specific and "base" functions that are common in
71 * both chips have no special names (this is for compatibility with
72 * older include files). Therefore, if you're working with the
73 * SCD, which is very different on each chip, A_SCD_xxx implies
74 * the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
76 ********************************************************************* */
79 /* *********************************************************************
80 * Memory Controller Registers (Section 6)
81 ********************************************************************* */
83 #define A_BCM1480_MC_BASE_0 0x0010050000
84 #define A_BCM1480_MC_BASE_1 0x0010051000
85 #define A_BCM1480_MC_BASE_2 0x0010052000
86 #define A_BCM1480_MC_BASE_3 0x0010053000
87 #define BCM1480_MC_REGISTER_SPACING 0x1000
89 #define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
90 #define A_BCM1480_MC_REGISTER(ctlid,reg) (A_BCM1480_MC_BASE(ctlid)+(reg))
92 #define R_BCM1480_MC_CONFIG 0x0000000100
93 #define R_BCM1480_MC_CS_START 0x0000000120
94 #define R_BCM1480_MC_CS_END 0x0000000140
95 #define S_BCM1480_MC_CS_STARTEND 24
97 #define R_BCM1480_MC_CS01_ROW0 0x0000000180
98 #define R_BCM1480_MC_CS01_ROW1 0x00000001A0
99 #define R_BCM1480_MC_CS23_ROW0 0x0000000200
100 #define R_BCM1480_MC_CS23_ROW1 0x0000000220
101 #define R_BCM1480_MC_CS01_COL0 0x0000000280
102 #define R_BCM1480_MC_CS01_COL1 0x00000002A0
103 #define R_BCM1480_MC_CS23_COL0 0x0000000300
104 #define R_BCM1480_MC_CS23_COL1 0x0000000320
106 #define R_BCM1480_MC_CSX_BASE 0x0000000180
107 #define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */
108 #define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */
109 #define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */
110 #define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */
111 #define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */
113 #define R_BCM1480_MC_CS01_BA 0x0000000380
114 #define R_BCM1480_MC_CS23_BA 0x00000003A0
115 #define R_BCM1480_MC_DRAMCMD 0x0000000400
116 #define R_BCM1480_MC_DRAMMODE 0x0000000420
117 #define R_BCM1480_MC_CLOCK_CFG 0x0000000440
118 #define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG
119 #define R_BCM1480_MC_TEST_DATA 0x0000000480
120 #define R_BCM1480_MC_TEST_ECC 0x00000004A0
121 #define R_BCM1480_MC_TIMING1 0x00000004C0
122 #define R_BCM1480_MC_TIMING2 0x00000004E0
123 #define R_BCM1480_MC_DLL_CFG 0x0000000500
124 #define R_BCM1480_MC_DRIVE_CFG 0x0000000520
126 #if SIBYTE_HDR_FEATURE(1480, PASS2)
127 #define R_BCM1480_MC_ODT 0x0000000460
128 #define R_BCM1480_MC_ECC_STATUS 0x0000000540
131 /* Global registers (single instance) */
132 #define A_BCM1480_MC_GLB_CONFIG 0x0010054100
133 #define A_BCM1480_MC_GLB_INTLV 0x0010054120
134 #define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140
135 #define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160
136 #define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180
137 #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0
139 /* *********************************************************************
140 * L2 Cache Control Registers (Section 5)
141 ********************************************************************* */
143 #define A_BCM1480_L2_BASE 0x0010040000
145 #define A_BCM1480_L2_READ_TAG 0x0010040018
146 #define A_BCM1480_L2_ECC_TAG 0x0010040038
147 #define A_BCM1480_L2_MISC0_VALUE 0x0010040058
148 #define A_BCM1480_L2_MISC1_VALUE 0x0010040078
149 #define A_BCM1480_L2_MISC2_VALUE 0x0010040098
150 #define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */
151 #define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */
152 #define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
153 #define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */
154 #define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */
155 #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
156 #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
157 #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
158 #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
159 #define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */
160 #define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */
161 #define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */
162 #define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */
163 #define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */
164 #define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */
165 #define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8))
166 #define A_BCM1480_L2_BANK_BASE 0x00D0300000
167 #define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
168 #define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000
171 /* *********************************************************************
172 * PCI-X Interface Registers (Section 7)
173 ********************************************************************* */
175 #define A_BCM1480_PCI_BASE 0x0010061400
177 #define A_BCM1480_PCI_RESET 0x0010061400
178 #define A_BCM1480_PCI_DLL 0x0010061500
180 #define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000
182 /* *********************************************************************
183 * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
184 ********************************************************************* */
186 /* No register changes with Rev.C BCM1250, but one additional MAC */
188 #define A_BCM1480_MAC_BASE_2 0x0010066000
191 #define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2
194 #define A_BCM1480_MAC_BASE_3 0x0010067000
195 #define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3
197 #define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038
199 #ifndef R_MAC_DMA_OODPKTLOST
200 #define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST
204 /* *********************************************************************
205 * DUART Registers (Section 14)
206 ********************************************************************* */
208 /* No significant differences from BCM1250, two DUARTs */
210 /* Conventions, per user manual:
211 * DUART generic, channels A,B,C,D
212 * DUART0 implementing channels A,B
213 * DUART1 inplementing channels C,D
216 #define BCM1480_DUART_NUM_PORTS 4
218 #define A_BCM1480_DUART0 0x0010060000
219 #define A_BCM1480_DUART1 0x0010060400
220 #define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
222 #define BCM1480_DUART_CHANREG_SPACING 0x100
223 #define A_BCM1480_DUART_CHANREG(chan, reg) \
224 (A_BCM1480_DUART(chan) + \
225 BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
226 #define A_BCM1480_DUART_CTRLREG(chan, reg) \
227 (A_BCM1480_DUART(chan) + \
228 BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
230 #define R_BCM1480_DUART_IMRREG(chan) \
231 (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
232 #define R_BCM1480_DUART_ISRREG(chan) \
233 (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
235 #define A_BCM1480_DUART_IMRREG(chan) \
236 (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
237 #define A_BCM1480_DUART_ISRREG(chan) \
238 (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan)))
240 #define A_BCM1480_DUART_IN_PORT(chan) \
241 (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT))
244 * These constants are the absolute addresses.
247 #define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400
248 #define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410
249 #define A_BCM1480_DUART_STATUS_C 0x0010060420
250 #define A_BCM1480_DUART_CLK_SEL_C 0x0010060430
251 #define A_BCM1480_DUART_FULL_CTL_C 0x0010060440
252 #define A_BCM1480_DUART_CMD_C 0x0010060450
253 #define A_BCM1480_DUART_RX_HOLD_C 0x0010060460
254 #define A_BCM1480_DUART_TX_HOLD_C 0x0010060470
255 #define A_BCM1480_DUART_OPCR_C 0x0010060480
256 #define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490
258 #define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500
259 #define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510
260 #define A_BCM1480_DUART_STATUS_D 0x0010060520
261 #define A_BCM1480_DUART_CLK_SEL_D 0x0010060530
262 #define A_BCM1480_DUART_FULL_CTL_D 0x0010060540
263 #define A_BCM1480_DUART_CMD_D 0x0010060550
264 #define A_BCM1480_DUART_RX_HOLD_D 0x0010060560
265 #define A_BCM1480_DUART_TX_HOLD_D 0x0010060570
266 #define A_BCM1480_DUART_OPCR_D 0x0010060580
267 #define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590
269 #define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600
270 #define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610
271 #define A_BCM1480_DUART_ISR_C 0x0010060620
272 #define A_BCM1480_DUART_IMR_C 0x0010060630
273 #define A_BCM1480_DUART_ISR_D 0x0010060640
274 #define A_BCM1480_DUART_IMR_D 0x0010060650
275 #define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660
276 #define A_BCM1480_DUART_OPCR_CD 0x0010060670
277 #define A_BCM1480_DUART_IN_PORT_CD 0x0010060680
278 #define A_BCM1480_DUART_ISR_CD 0x0010060690
279 #define A_BCM1480_DUART_IMR_CD 0x00100606A0
280 #define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0
281 #define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0
282 #define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0
283 #define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0
286 /* *********************************************************************
287 * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
288 ********************************************************************* */
290 #define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58
291 #define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68
293 /* *********************************************************************
294 * GPIO Registers (Section 17)
295 ********************************************************************* */
297 /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
299 #define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78
300 #define R_BCM1480_GPIO_INT_ADD_TYPE (-8)
302 #define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE
303 #define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE
305 /* *********************************************************************
306 * SMBus Registers (Section 18)
307 ********************************************************************* */
309 /* No changes from BCM1250 */
311 /* *********************************************************************
312 * Timer Registers (Sections 4.6)
313 ********************************************************************* */
315 /* BCM1480 has two additional watchdogs */
317 /* Watchdog timers */
319 #define A_BCM1480_SCD_WDOG_2 0x0010022050
320 #define A_BCM1480_SCD_WDOG_3 0x0010022150
322 #define BCM1480_SCD_NUM_WDOGS 4
324 #define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
325 #define A_BCM1480_SCD_WDOG_REGISTER(w,r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
327 #define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050
328 #define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058
329 #define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060
331 #define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150
332 #define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158
333 #define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160
335 /* BCM1480 has two additional compare registers */
337 #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT
338 #define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00
339 #define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0
340 #define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1
341 #define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10
342 #define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18
344 /* *********************************************************************
345 * System Control Registers (Section 4.2)
346 ********************************************************************* */
348 /* Scratch register in different place */
350 #define A_BCM1480_SCD_SCRATCH 0x100200A0
352 /* *********************************************************************
353 * System Address Trap Registers (Section 4.9)
354 ********************************************************************* */
356 /* No changes from BCM1250 */
358 /* *********************************************************************
359 * System Interrupt Mapper Registers (Sections 4.3-4.5)
360 ********************************************************************* */
362 #define A_BCM1480_IMR_CPU0_BASE 0x0010020000
363 #define A_BCM1480_IMR_CPU1_BASE 0x0010022000
364 #define A_BCM1480_IMR_CPU2_BASE 0x0010024000
365 #define A_BCM1480_IMR_CPU3_BASE 0x0010026000
366 #define BCM1480_IMR_REGISTER_SPACING 0x2000
367 #define BCM1480_IMR_REGISTER_SPACING_SHIFT 13
369 #define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
370 #define A_BCM1480_IMR_REGISTER(cpu,reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
372 /* Most IMR registers are 128 bits, implemented as non-contiguous
373 64-bit registers high (_H) and low (_L) */
374 #define BCM1480_IMR_HL_SPACING 0x1000
376 #define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010
377 #define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018
378 #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020
379 #define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028
380 #define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038
381 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
382 #define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048
383 #define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0
384 #define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8
385 #define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0
386 #define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0
387 #define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8
388 #define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0
389 #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100
390 #define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8
391 #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200
392 #define BCM1480_IMR_INTERRUPT_MAP_COUNT 64
394 #define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010
395 #define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018
396 #define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020
397 #define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028
398 #define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038
399 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
400 #define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100
401 #define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200
403 #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000
404 #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100
405 #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200
406 #define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300
407 #define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100
409 #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
410 (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
411 #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu,reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
413 #define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
414 #define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
417 * these macros work together to build the address of a mailbox
418 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
419 * for mbox_0_set_cpu2 returns 0x00100240C8
421 #define R_BCM1480_IMR_MAILBOX_CPU 0x00
422 #define R_BCM1480_IMR_MAILBOX_SET 0x08
423 #define R_BCM1480_IMR_MAILBOX_CLR 0x10
424 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
425 #define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \
426 (A_BCM1480_IMR_CPU0_BASE + \
427 (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
428 (cpu * BCM1480_IMR_REGISTER_SPACING) + \
429 (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
431 /* *********************************************************************
432 * System Performance Counter Registers (Section 4.7)
433 ********************************************************************* */
435 /* BCM1480 has four more performance counter registers, and two control
438 #define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0
440 #define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0
441 #define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0
442 #define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8
443 #define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1
445 #define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0
446 #define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1
447 #define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2
448 #define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3
450 #define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0
451 #define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8
452 #define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
453 #define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
455 #define BCM1480_SCD_NUM_PERF_CNT 8
456 #define BCM1480_SCD_PERF_CNT_SPACING 8
457 #define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
459 /* *********************************************************************
460 * System Bus Watcher Registers (Section 4.8)
461 ********************************************************************* */
464 /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
466 #define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8
468 /* *********************************************************************
469 * System Debug Controller Registers (Section 19)
470 ********************************************************************* */
474 /* *********************************************************************
475 * System Trace Unit Registers (Sections 4.10)
476 ********************************************************************* */
480 /* *********************************************************************
481 * Data Mover DMA Registers (Section 10.7)
482 ********************************************************************* */
487 /* *********************************************************************
488 * HyperTransport Interface Registers (Section 8)
489 ********************************************************************* */
491 #define BCM1480_HT_NUM_PORTS 3
492 #define BCM1480_HT_PORT_SPACING 0x800
493 #define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
495 #define A_BCM1480_HT_PORT0_HEADER 0x00FE000000
496 #define A_BCM1480_HT_PORT1_HEADER 0x00FE000800
497 #define A_BCM1480_HT_PORT2_HEADER 0x00FE001000
498 #define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000
501 /* *********************************************************************
502 * Node Controller Registers (Section 9)
503 ********************************************************************* */
505 #define A_BCM1480_NC_BASE 0x00DFBD0000
507 #define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000
508 #define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020
509 #define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040
510 #define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060
511 #define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080
512 #define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0
513 #define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0
515 #define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0
516 #define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100
517 #define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120
518 #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140
520 #define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200
521 #define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220
522 #define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240
523 #define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260
524 #define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280
525 #define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0
526 #define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0
527 #define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0
528 #define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300
529 #define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320
530 #define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000
531 #define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020
532 #define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040
534 #define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060
535 #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
538 /* *********************************************************************
539 * H&R Block Configuration Registers (Section 12.4)
540 ********************************************************************* */
542 #define A_BCM1480_HR_BASE_0 0x00DF820000
543 #define A_BCM1480_HR_BASE_1 0x00DF8A0000
544 #define A_BCM1480_HR_BASE_2 0x00DF920000
545 #define BCM1480_HR_REGISTER_SPACING 0x80000
547 #define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
548 #define A_BCM1480_HR_REGISTER(idx,reg) (A_BCM1480_HR_BASE(idx) + (reg))
550 #define R_BCM1480_HR_CFG 0x0000000000
552 #define R_BCM1480_HR_MAPPING 0x0000010010
554 #define BCM1480_HR_RULE_SPACING 0x0000000010
555 #define BCM1480_HR_NUM_RULES 16
556 #define BCM1480_HR_OP_OFFSET 0x0000000100
557 #define BCM1480_HR_TYPE_OFFSET 0x0000000108
558 #define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
559 #define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
561 #define BCM1480_HR_LEAF_SPACING 0x0000000010
562 #define BCM1480_HR_NUM_LEAVES 10
563 #define BCM1480_HR_LEAF_OFFSET 0x0000000300
564 #define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
566 #define R_BCM1480_HR_EX_LEAF0 0x00000003A0
568 #define BCM1480_HR_PATH_SPACING 0x0000000010
569 #define BCM1480_HR_NUM_PATHS 16
570 #define BCM1480_HR_PATH_OFFSET 0x0000000600
571 #define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
573 #define R_BCM1480_HR_PATH_DEFAULT 0x0000000700
575 #define BCM1480_HR_ROUTE_SPACING 8
576 #define BCM1480_HR_NUM_ROUTES 512
577 #define BCM1480_HR_ROUTE_OFFSET 0x0000001000
578 #define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
581 /* checked to here - ehs */
582 /* *********************************************************************
583 * Packet Manager DMA Registers (Section 12.5)
584 ********************************************************************* */
586 #define A_BCM1480_PM_BASE 0x0010056000
588 #define A_BCM1480_PMI_LCL_0 0x0010058000
589 #define A_BCM1480_PMO_LCL_0 0x001005C000
590 #define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
591 #define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
593 #define BCM1480_PM_LCL_REGISTER_SPACING 0x100
594 #define BCM1480_PM_NUM_CHANNELS 32
596 #define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
597 #define A_BCM1480_PMI_LCL_REGISTER(idx,reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
598 #define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
599 #define A_BCM1480_PMO_LCL_REGISTER(idx,reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
601 #define BCM1480_PM_INT_PACKING 8
602 #define BCM1480_PM_INT_FUNCTION_SPACING 0x40
603 #define BCM1480_PM_INT_NUM_FUNCTIONS 3
606 * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
609 #define R_BCM1480_PM_BASE_SIZE 0x0000000000
610 #define R_BCM1480_PM_CNT 0x0000000008
611 #define R_BCM1480_PM_PFCNT 0x0000000010
612 #define R_BCM1480_PM_LAST 0x0000000018
613 #define R_BCM1480_PM_PFINDX 0x0000000020
614 #define R_BCM1480_PM_INT_WMK 0x0000000028
615 #define R_BCM1480_PM_CONFIG0 0x0000000030
616 #define R_BCM1480_PM_LOCALDEBUG 0x0000000078
617 #define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */
618 #define R_BCM1480_PM_INT_CNFG 0x0000000088
619 #define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090
620 #define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */
621 #define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */
624 * Global Registers (Not Channelized)
627 #define A_BCM1480_PMI_GLB_0 0x0010056000
628 #define A_BCM1480_PMO_GLB_0 0x0010057000
631 * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
634 #define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */
636 #define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
639 * Interrupt mapping registers
643 #define A_BCM1480_PMI_INT_0 0x0010056800
644 #define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
645 #define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
646 #define A_BCM1480_PMO_INT_0 0x0010057800
647 #define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
648 #define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
651 * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
654 #define R_BCM1480_PM_INT_ST 0x0000000000
655 #define R_BCM1480_PM_INT_MSK 0x0000000040
656 #define R_BCM1480_PM_INT_CLR 0x0000000080
657 #define R_BCM1480_PM_MRGD_INT 0x00000000C0
660 * Debug registers (global)
663 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000
664 #define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8
665 #define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8
666 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000
667 #define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8
668 #define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8
670 /* *********************************************************************
671 * Switch performance counters
672 ********************************************************************* */
674 #define A_BCM1480_SWPERF_CFG 0xdfb91800
675 #define A_BCM1480_SWPERF_CNT0 0xdfb91880
676 #define A_BCM1480_SWPERF_CNT1 0xdfb91888
677 #define A_BCM1480_SWPERF_CNT2 0xdfb91890
678 #define A_BCM1480_SWPERF_CNT3 0xdfb91898
681 /* *********************************************************************
683 ********************************************************************* */
685 #define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000
686 #define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100
687 #define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108
688 #define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200
689 #define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208
690 #define A_BCM1480_SWTRC_EVENT_0 0xDFB91300
691 #define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400
693 #define A_BCM1480_SWTRC_CFG 0xDFB91500
694 #define A_BCM1480_SWTRC_READ 0xDFB91508
696 #define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000
698 #define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
699 #define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
700 #define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
702 #define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
703 #define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
704 #define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
705 #define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
709 /* *********************************************************************
710 * High-Speed Port Registers (Section 13)
711 ********************************************************************* */
713 #define A_BCM1480_HSP_BASE_0 0x00DF810000
714 #define A_BCM1480_HSP_BASE_1 0x00DF890000
715 #define A_BCM1480_HSP_BASE_2 0x00DF910000
716 #define BCM1480_HSP_REGISTER_SPACING 0x80000
718 #define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
719 #define A_BCM1480_HSP_REGISTER(idx,reg) (A_BCM1480_HSP_BASE(idx) + (reg))
721 #define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000
722 #define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008
723 #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
724 #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
725 #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020
726 #define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
728 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200
729 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208
731 #define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800
732 #define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808
733 #define R_BCM1480_HSP_RX_TEST 0x0000000810
734 #define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818
735 #define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820
736 #define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828
737 #define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830
738 #define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838
740 #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870
742 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020
743 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028
744 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030
745 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038
746 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040
747 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048
748 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050
749 #define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058
750 #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
752 /* XXX Following registers were shuffled. Renamed/renumbered per errata. */
753 #define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078
754 #define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080
755 #define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088
756 #define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090
757 #define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098
758 #define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0
760 #define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0
761 #define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8
762 #define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0
763 #define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8
764 #define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0
765 #define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8
766 #define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0
767 #define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8
768 #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
770 #define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0
771 #define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8
772 #define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100
773 #define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108
774 #define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110
775 #define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118
776 #define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120
778 #define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000
779 #define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008
780 #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010
782 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020
783 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028
784 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030
785 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038
786 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040
787 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048
788 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050
789 #define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058
790 #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
791 #define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078
792 #define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080
793 #define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088
794 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090
795 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098
796 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0
798 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0
799 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8
800 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0
801 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8
802 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
803 #define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0
804 #define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8
806 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0
807 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8
808 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0
809 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8
810 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
811 #define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100
812 #define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108
814 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200
815 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208
817 #define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800
818 #define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808
819 #define R_BCM1480_HSP_TX_TEST 0x0000040810
821 #define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840
822 #define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848
823 #define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850
824 #define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860
825 #define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868
826 #define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870
827 #define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878
829 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
830 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888
832 #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
833 #define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
837 /* *********************************************************************
838 * Physical Address Map (Table 10 and Figure 7)
839 ********************************************************************* */
841 #define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
842 #define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
843 #define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
844 #define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
845 #define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000)
846 #define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000)
847 #define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000)
848 #define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000)
849 #define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000)
850 #define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000)
851 #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000)
852 #define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000)
853 #define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000)
854 #define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000)
855 #define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
856 #define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
857 #define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000)
858 #define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000)
859 #define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000)
860 #define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000)
861 #define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000)
862 #define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000)
863 #define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
864 #define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
865 #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
866 #define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
867 #define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
868 #define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000)
869 #define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
870 #define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
871 #define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
872 #define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
873 #define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
874 #define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000)
875 #define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000)
876 #define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000)
877 #define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000)
878 #define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000)
881 /* *********************************************************************
882 * L2 Cache as RAM (Table 54)
883 ********************************************************************* */
885 #define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
886 #define BCM1480_PHYS_L2CACHE_NUM_WAYS 8
887 #define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000)
888 #define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000)
889 #define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000)
890 #define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000)
891 #define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000)
892 #define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000)
893 #define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000)
894 #define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000)
895 #define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000)
897 #endif /* _BCM1480_REGS_H */
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