2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
15 #include <linux/config.h>
16 #include <linux/compiler.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
20 #include <asm/addrspace.h>
22 #include <asm/byteorder.h>
24 #include <asm/cpu-features.h>
26 #include <asm/pgtable-bits.h>
27 #include <asm/processor.h>
29 #include <mangle-port.h>
32 * Slowdown I/O port space accesses for antique hardware.
34 #undef CONF_SLOWDOWN_IO
37 * Raw operations are never swapped in software. OTOH values that raw
38 * operations are working on may or may not have been swapped by the bus
39 * hardware. An example use would be for flash memory that's used for
42 # define __raw_ioswabb(x) (x)
43 # define __raw_ioswabw(x) (x)
44 # define __raw_ioswabl(x) (x)
45 # define __raw_ioswabq(x) (x)
46 # define ____raw_ioswabq(x) (x)
49 * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
50 * less sane hardware forces software to fiddle with this...
52 * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
53 * you can't have the numerical value of data and byte addresses within
54 * multibyte quantities both preserved at the same time. Hence two
55 * variations of functions: non-prefixed ones that preserve the value
56 * and prefixed ones that preserve byte addresses. The latters are
57 * typically used for moving raw data between a peripheral and memory (cf.
58 * string I/O functions), hence the "mem_" prefix.
60 #if defined(CONFIG_SWAP_IO_SPACE)
62 # define ioswabb(x) (x)
63 # define mem_ioswabb(x) (x)
64 # ifdef CONFIG_SGI_IP22
66 * IP22 seems braindead enough to swap 16bits values in hardware, but
67 * not 32bits. Go figure... Can't tell without documentation.
69 # define ioswabw(x) (x)
70 # define mem_ioswabw(x) le16_to_cpu(x)
72 # define ioswabw(x) le16_to_cpu(x)
73 # define mem_ioswabw(x) (x)
75 # define ioswabl(x) le32_to_cpu(x)
76 # define mem_ioswabl(x) (x)
77 # define ioswabq(x) le64_to_cpu(x)
78 # define mem_ioswabq(x) (x)
82 # define ioswabb(x) (x)
83 # define mem_ioswabb(x) (x)
84 # define ioswabw(x) (x)
85 # define mem_ioswabw(x) cpu_to_le16(x)
86 # define ioswabl(x) (x)
87 # define mem_ioswabl(x) cpu_to_le32(x)
88 # define ioswabq(x) (x)
89 # define mem_ioswabq(x) cpu_to_le32(x)
93 #define IO_SPACE_LIMIT 0xffff
96 * On MIPS I/O ports are memory mapped, so we access them using normal
97 * load/store instructions. mips_io_port_base is the virtual address to
98 * which all ports are being mapped. For sake of efficiency some code
99 * assumes that this is an address that can be loaded with a single lui
100 * instruction, so the lower 16 bits must be zero. Should be true on
101 * on any sane architecture; generic code does not use this assumption.
103 extern const unsigned long mips_io_port_base;
105 #define set_io_port_base(base) \
106 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
109 * Thanks to James van Artsdalen for a better timing-fix than
110 * the two short jumps: using outb's to a nonexistent port seems
111 * to guarantee better timings even on fast machines.
113 * On the other hand, I'd like to be sure of a non-existent port:
114 * I feel a bit unsafe about using 0x80 (should be safe, though)
120 #define __SLOW_DOWN_IO \
121 __asm__ __volatile__( \
123 : : "r" (mips_io_port_base));
125 #ifdef CONF_SLOWDOWN_IO
126 #ifdef REALLY_SLOW_IO
127 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
129 #define SLOW_DOWN_IO __SLOW_DOWN_IO
136 * virt_to_phys - map virtual addresses to physical
137 * @address: address to remap
139 * The returned physical address is the physical (CPU) mapping for
140 * the memory address given. It is only valid to use this function on
141 * addresses directly mapped or allocated via kmalloc.
143 * This function does not give bus mappings for DMA transfers. In
144 * almost all conceivable cases a device driver should not be using
147 static inline unsigned long virt_to_phys(volatile void * address)
149 return (unsigned long)address - PAGE_OFFSET;
153 * phys_to_virt - map physical address to virtual
154 * @address: address to remap
156 * The returned virtual address is a current CPU mapping for
157 * the memory address given. It is only valid to use this function on
158 * addresses that have a kernel mapping
160 * This function does not handle bus mappings for DMA transfers. In
161 * almost all conceivable cases a device driver should not be using
164 static inline void * phys_to_virt(unsigned long address)
166 return (void *)(address + PAGE_OFFSET);
170 * ISA I/O bus memory addresses are 1:1 with the physical address.
172 static inline unsigned long isa_virt_to_bus(volatile void * address)
174 return (unsigned long)address - PAGE_OFFSET;
177 static inline void * isa_bus_to_virt(unsigned long address)
179 return (void *)(address + PAGE_OFFSET);
182 #define isa_page_to_bus page_to_phys
185 * However PCI ones are not necessarily 1:1 and therefore these interfaces
186 * are forbidden in portable PCI drivers.
188 * Allow them for x86 for legacy drivers, though.
190 #define virt_to_bus virt_to_phys
191 #define bus_to_virt phys_to_virt
194 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
195 * for the processor. This implies the assumption that there is only
196 * one of these busses.
198 extern unsigned long isa_slot_offset;
201 * Change "struct page" to physical address.
203 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
205 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
206 extern void __iounmap(volatile void __iomem *addr);
208 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
211 if (cpu_has_64bit_addresses) {
212 u64 base = UNCAC_BASE;
215 * R10000 supports a 2 bit uncached attribute therefore
216 * UNCAC_BASE may not equal IO_BASE.
218 if (flags == _CACHE_UNCACHED)
219 base = (u64) IO_BASE;
220 return (void *) (unsigned long) (base + offset);
223 return __ioremap(offset, size, flags);
227 * ioremap - map bus memory into CPU space
228 * @offset: bus address of the memory
229 * @size: size of the resource to map
231 * ioremap performs a platform specific sequence of operations to
232 * make bus memory CPU accessible via the readb/readw/readl/writeb/
233 * writew/writel functions and the other mmio helpers. The returned
234 * address is not guaranteed to be usable directly as a virtual
237 #define ioremap(offset, size) \
238 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
241 * ioremap_nocache - map bus memory into CPU space
242 * @offset: bus address of the memory
243 * @size: size of the resource to map
245 * ioremap_nocache performs a platform specific sequence of operations to
246 * make bus memory CPU accessible via the readb/readw/readl/writeb/
247 * writew/writel functions and the other mmio helpers. The returned
248 * address is not guaranteed to be usable directly as a virtual
251 * This version of ioremap ensures that the memory is marked uncachable
252 * on the CPU as well as honouring existing caching rules from things like
253 * the PCI bus. Note that there are other caches and buffers on many
254 * busses. In paticular driver authors should read up on PCI writes
256 * It's useful if some control registers are in such an area and
257 * write combining or read caching is not desirable:
259 #define ioremap_nocache(offset, size) \
260 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
263 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
264 * requests a cachable mapping, ioremap_uncached_accelerated requests a
265 * mapping using the uncached accelerated mode which isn't supported on
268 #define ioremap_cacheable_cow(offset, size) \
269 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
270 #define ioremap_uncached_accelerated(offset, size) \
271 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
273 static inline void iounmap(volatile void __iomem *addr)
275 if (cpu_has_64bit_addresses)
282 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
284 static inline void pfx##write##bwlq(type val, \
285 volatile void __iomem *mem) \
287 volatile type *__mem; \
290 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
292 __val = pfx##ioswab##bwlq(val); \
294 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
296 else if (cpu_has_64bits) { \
297 unsigned long __flags; \
301 local_irq_save(__flags); \
302 __asm__ __volatile__( \
303 ".set mips3" "\t\t# __writeq""\n\t" \
304 "dsll32 %L0, %L0, 0" "\n\t" \
305 "dsrl32 %L0, %L0, 0" "\n\t" \
306 "dsll32 %M0, %M0, 0" "\n\t" \
307 "or %L0, %L0, %M0" "\n\t" \
308 "sd %L0, %2" "\n\t" \
311 : "0" (__val), "m" (*__mem)); \
313 local_irq_restore(__flags); \
318 static inline type pfx##read##bwlq(volatile void __iomem *mem) \
320 volatile type *__mem; \
323 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
325 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
327 else if (cpu_has_64bits) { \
328 unsigned long __flags; \
331 local_irq_save(__flags); \
332 __asm__ __volatile__( \
333 ".set mips3" "\t\t# __readq" "\n\t" \
334 "ld %L0, %1" "\n\t" \
335 "dsra32 %M0, %L0, 0" "\n\t" \
336 "sll %L0, %L0, 0" "\n\t" \
341 local_irq_restore(__flags); \
347 return pfx##ioswab##bwlq(__val); \
350 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
352 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
354 volatile type *__addr; \
357 port = __swizzle_addr_##bwlq(port); \
358 __addr = (void *)(mips_io_port_base + port); \
360 __val = pfx##ioswab##bwlq(val); \
362 if (sizeof(type) != sizeof(u64)) { \
369 static inline type pfx##in##bwlq##p(unsigned long port) \
371 volatile type *__addr; \
374 port = __swizzle_addr_##bwlq(port); \
375 __addr = (void *)(mips_io_port_base + port); \
377 if (sizeof(type) != sizeof(u64)) { \
385 return pfx##ioswab##bwlq(__val); \
388 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
390 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
392 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
394 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
395 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
397 #define BUILDIO(bwlq, type) \
399 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
400 __BUILD_MEMORY_PFX(, bwlq, type) \
401 __BUILD_MEMORY_PFX(mem_, bwlq, type) \
402 __BUILD_IOPORT_PFX(, bwlq, type) \
403 __BUILD_IOPORT_PFX(mem_, bwlq, type)
405 #define __BUILDIO(bwlq, type) \
407 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
416 #define readb_relaxed readb
417 #define readw_relaxed readw
418 #define readl_relaxed readl
419 #define readq_relaxed readq
422 * Some code tests for these symbols
425 #define writeq writeq
427 #define __BUILD_MEMORY_STRING(bwlq, type) \
429 static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \
430 unsigned int count) \
432 volatile type *__addr = addr; \
435 mem_write##bwlq(*__addr, mem); \
440 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
441 unsigned int count) \
443 volatile type *__addr = addr; \
446 *__addr = mem_read##bwlq(mem); \
451 #define __BUILD_IOPORT_STRING(bwlq, type) \
453 static inline void outs##bwlq(unsigned long port, void *addr, \
454 unsigned int count) \
456 volatile type *__addr = addr; \
459 mem_out##bwlq(*__addr, port); \
464 static inline void ins##bwlq(unsigned long port, void *addr, \
465 unsigned int count) \
467 volatile type *__addr = addr; \
470 *__addr = mem_in##bwlq(port); \
475 #define BUILDSTRING(bwlq, type) \
477 __BUILD_MEMORY_STRING(bwlq, type) \
478 __BUILD_IOPORT_STRING(bwlq, type)
486 /* Depends on MIPS II instruction set */
487 #define mmiowb() asm volatile ("sync" ::: "memory")
489 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
490 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
491 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
496 #define ioread8(addr) readb(addr)
497 #define ioread16(addr) readw(addr)
498 #define ioread32(addr) readl(addr)
500 #define iowrite8(b,addr) writeb(b,addr)
501 #define iowrite16(w,addr) writew(w,addr)
502 #define iowrite32(l,addr) writel(l,addr)
504 #define ioread8_rep(a,b,c) readsb(a,b,c)
505 #define ioread16_rep(a,b,c) readsw(a,b,c)
506 #define ioread32_rep(a,b,c) readsl(a,b,c)
508 #define iowrite8_rep(a,b,c) writesb(a,b,c)
509 #define iowrite16_rep(a,b,c) writesw(a,b,c)
510 #define iowrite32_rep(a,b,c) writesl(a,b,c)
512 /* Create a virtual mapping cookie for an IO port range */
513 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
514 extern void ioport_unmap(void __iomem *);
516 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
518 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
519 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
522 * ISA space is 'always mapped' on currently supported MIPS systems, no need
523 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
524 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
525 * are physical addresses. The following constant pointer can be
526 * used as the IO-area pointer (it can be iounmapped as well, so the
527 * analogy with PCI is quite large):
529 #define __ISA_IO_base ((char *)(isa_slot_offset))
531 #define isa_readb(a) readb(__ISA_IO_base + (a))
532 #define isa_readw(a) readw(__ISA_IO_base + (a))
533 #define isa_readl(a) readl(__ISA_IO_base + (a))
534 #define isa_readq(a) readq(__ISA_IO_base + (a))
535 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
536 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
537 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
538 #define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
539 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
540 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
541 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
544 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
545 * just copy it. The net code will then do the checksum later.
547 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
548 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
551 * check_signature - find BIOS signatures
552 * @io_addr: mmio address to check
553 * @signature: signature block
554 * @length: length of signature
556 * Perform a signature comparison with the mmio address io_addr. This
557 * address should have been obtained by ioremap.
558 * Returns 1 on a match.
560 static inline int check_signature(char __iomem *io_addr,
561 const unsigned char *signature, int length)
565 if (readb(io_addr) != *signature)
577 * The caches on some architectures aren't dma-coherent and have need to
578 * handle this in software. There are three types of operations that
579 * can be applied to dma buffers.
581 * - dma_cache_wback_inv(start, size) makes caches and coherent by
582 * writing the content of the caches back to memory, if necessary.
583 * The function also invalidates the affected part of the caches as
584 * necessary before DMA transfers from outside to memory.
585 * - dma_cache_wback(start, size) makes caches and coherent by
586 * writing the content of the caches back to memory, if necessary.
587 * The function also invalidates the affected part of the caches as
588 * necessary before DMA transfers from outside to memory.
589 * - dma_cache_inv(start, size) invalidates the affected parts of the
590 * caches. Dirty lines of the caches may be written back or simply
591 * be discarded. This operation is necessary before dma operations
594 #ifdef CONFIG_DMA_NONCOHERENT
596 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
597 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
598 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
600 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
601 #define dma_cache_wback(start, size) _dma_cache_wback(start,size)
602 #define dma_cache_inv(start, size) _dma_cache_inv(start,size)
604 #else /* Sane hardware */
606 #define dma_cache_wback_inv(start,size) \
607 do { (void) (start); (void) (size); } while (0)
608 #define dma_cache_wback(start,size) \
609 do { (void) (start); (void) (size); } while (0)
610 #define dma_cache_inv(start,size) \
611 do { (void) (start); (void) (size); } while (0)
613 #endif /* CONFIG_DMA_NONCOHERENT */
616 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
617 * Avoid interrupt mucking, just adjust the address for 4-byte access.
618 * Assume the addresses are 8-byte aligned.
621 #define __CSR_32_ADJUST 4
623 #define __CSR_32_ADJUST 0
626 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
627 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
630 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
633 #define xlate_dev_mem_ptr(p) __va(p)
636 * Convert a virtual cached pointer to an uncached pointer
638 #define xlate_dev_kmem_ptr(p) p
640 #endif /* _ASM_IO_H */