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   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <asm/processor.h>
   8 #include <linux/compiler.h>
   9
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * We make no fairness assumptions. They have a cost.
  17  *
  18  * (the type definitions are in asm/spinlock_types.h)
  19  */
  20
  21 static inline int __raw_spin_is_locked(raw_spinlock_t *x)
  22 {
  23         return *(volatile signed char *)(&(x)->slock) <= 0;
  24 }
  25
  26 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  27 {
  28         asm volatile("\n1:\t"
  29                      LOCK_PREFIX " ; decb %0\n\t"
  30                      "jns 3f\n"
  31                      "2:\t"
  32                      "rep;nop\n\t"
  33                      "cmpb $0,%0\n\t"
  34                      "jle 2b\n\t"
  35                      "jmp 1b\n"
  36                      "3:\n\t"
  37                      : "+m" (lock->slock) : : "memory");
  38 }
  39
  40 /*
  41  * It is easier for the lock validator if interrupts are not re-enabled
  42  * in the middle of a lock-acquire. This is a performance feature anyway
  43  * so we turn it off:
  44  *
  45  * NOTE: there's an irqs-on section here, which normally would have to be
  46  * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
  47  */
  48 #ifndef CONFIG_PROVE_LOCKING
  49 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  50 {
  51         asm volatile(
  52                 "\n1:\t"
  53                 LOCK_PREFIX " ; decb %0\n\t"
  54                 "jns 5f\n"
  55                 "2:\t"
  56                 "testl $0x200, %1\n\t"
  57                 "jz 4f\n\t"
  58                 "sti\n"
  59                 "3:\t"
  60                 "rep;nop\n\t"
  61                 "cmpb $0, %0\n\t"
  62                 "jle 3b\n\t"
  63                 "cli\n\t"
  64                 "jmp 1b\n"
  65                 "4:\t"
  66                 "rep;nop\n\t"
  67                 "cmpb $0, %0\n\t"
  68                 "jg 1b\n\t"
  69                 "jmp 4b\n"
  70                 "5:\n\t"
  71                 : "+m" (lock->slock) : "r" (flags) : "memory");
  72 }
  73 #endif
  74
  75 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  76 {
  77         char oldval;
  78         asm volatile(
  79                 "xchgb %b0,%1"
  80                 :"=q" (oldval), "+m" (lock->slock)
  81                 :"0" (0) : "memory");
  82         return oldval > 0;
  83 }
  84
  85 /*
  86  * __raw_spin_unlock based on writing $1 to the low byte.
  87  * This method works. Despite all the confusion.
  88  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
  89  * (PPro errata 66, 92)
  90  */
  91
  92 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
  93
  94 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  95 {
  96         asm volatile("movb $1,%0" : "+m" (lock->slock) :: "memory");
  97 }
  98
  99 #else
 100
 101 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 102 {
 103         char oldval = 1;
 104
 105         asm volatile("xchgb %b0, %1"
 106                      : "=q" (oldval), "+m" (lock->slock)
 107                      : "0" (oldval) : "memory");
 108 }
 109
 110 #endif
 111
 112 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
 113 {
 114         while (__raw_spin_is_locked(lock))
 115                 cpu_relax();
 116 }
 117
 118 /*
 119  * Read-write spinlocks, allowing multiple readers
 120  * but only one writer.
 121  *
 122  * NOTE! it is quite common to have readers in interrupts
 123  * but no interrupt writers. For those circumstances we
 124  * can "mix" irq-safe locks - any writer needs to get a
 125  * irq-safe write-lock, but readers can get non-irqsafe
 126  * read-locks.
 127  *
 128  * On x86, we implement read-write locks as a 32-bit counter
 129  * with the high bit (sign) being the "contended" bit.
 130  *
 131  * The inline assembly is non-obvious. Think about it.
 132  *
 133  * Changed to use the same technique as rw semaphores.  See
 134  * semaphore.h for details.  -ben
 135  *
 136  * the helpers are in arch/i386/kernel/semaphore.c
 137  */
 138
 139 /**
 140  * read_can_lock - would read_trylock() succeed?
 141  * @lock: the rwlock in question.
 142  */
 143 static inline int __raw_read_can_lock(raw_rwlock_t *x)
 144 {
 145         return (int)(x)->lock > 0;
 146 }
 147
 148 /**
 149  * write_can_lock - would write_trylock() succeed?
 150  * @lock: the rwlock in question.
 151  */
 152 static inline int __raw_write_can_lock(raw_rwlock_t *x)
 153 {
 154         return (x)->lock == RW_LOCK_BIAS;
 155 }
 156
 157 static inline void __raw_read_lock(raw_rwlock_t *rw)
 158 {
 159         asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
 160                      "jns 1f\n"
 161                      "call __read_lock_failed\n\t"
 162                      "1:\n"
 163                      ::"a" (rw) : "memory");
 164 }
 165
 166 static inline void __raw_write_lock(raw_rwlock_t *rw)
 167 {
 168         asm volatile(LOCK_PREFIX " subl $" RW_LOCK_BIAS_STR ",(%0)\n\t"
 169                      "jz 1f\n"
 170                      "call __write_lock_failed\n\t"
 171                      "1:\n"
 172                      ::"a" (rw) : "memory");
 173 }
 174
 175 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 176 {
 177         atomic_t *count = (atomic_t *)lock;
 178         atomic_dec(count);
 179         if (atomic_read(count) >= 0)
 180                 return 1;
 181         atomic_inc(count);
 182         return 0;
 183 }
 184
 185 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 186 {
 187         atomic_t *count = (atomic_t *)lock;
 188         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 189                 return 1;
 190         atomic_add(RW_LOCK_BIAS, count);
 191         return 0;
 192 }
 193
 194 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 195 {
 196         asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
 197 }
 198
 199 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 200 {
 201         asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
 202                                  : "+m" (rw->lock) : : "memory");
 203 }
 204
 205 #endif /* __ASM_SPINLOCK_H */