2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
23 #include <linux/init.h>
24 #include <asm/processor-flags.h>
26 /* flag for disabling the tsc */
27 extern int tsc_disable;
33 #define desc_empty(desc) \
34 (!((desc)->a | (desc)->b))
36 #define desc_equal(desc1, desc2) \
37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
39 * Default implementation of macro that returns current
40 * instruction pointer ("program counter").
42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
45 * CPU type and hardware bug flags. Kept separately for each CPU.
46 * Members of this structure are referenced in head.S, so think twice
47 * before touching them. [mj]
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 char wp_works_ok; /* It doesn't on 386's */
56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
60 unsigned long x86_capability[NCAPINTS];
61 char x86_vendor_id[16];
62 char x86_model_id[64];
63 int x86_cache_size; /* in KB - valid for CPUS which support this
65 int x86_cache_alignment; /* In bytes */
71 unsigned long loops_per_jiffy;
73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
75 unsigned char x86_max_cores; /* cpuid returned max cores value */
77 unsigned short x86_clflush_size;
79 unsigned char booted_cores; /* number of cores as seen by OS */
80 __u8 phys_proc_id; /* Physical processor id. */
81 __u8 cpu_core_id; /* Core id */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_RISE 6
92 #define X86_VENDOR_TRANSMETA 7
93 #define X86_VENDOR_NSC 8
94 #define X86_VENDOR_NUM 9
95 #define X86_VENDOR_UNKNOWN 0xff
98 * capabilities of CPUs
101 extern struct cpuinfo_x86 boot_cpu_data;
102 extern struct cpuinfo_x86 new_cpu_data;
103 extern struct tss_struct doublefault_tss;
104 DECLARE_PER_CPU(struct tss_struct, init_tss);
107 extern struct cpuinfo_x86 cpu_data[];
108 #define current_cpu_data cpu_data[smp_processor_id()]
110 #define cpu_data (&boot_cpu_data)
111 #define current_cpu_data boot_cpu_data
114 extern int cpu_llc_id[NR_CPUS];
115 extern char ignore_fpu_irq;
117 void __init cpu_detect(struct cpuinfo_x86 *c);
119 extern void identify_boot_cpu(void);
120 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
121 extern void print_cpu_info(struct cpuinfo_x86 *);
122 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
123 extern unsigned short num_cache_leaves;
126 extern void detect_ht(struct cpuinfo_x86 *c);
128 static inline void detect_ht(struct cpuinfo_x86 *c) {}
131 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
132 unsigned int *ecx, unsigned int *edx)
134 /* ecx is often an input as well as an output. */
140 : "0" (*eax), "2" (*ecx));
143 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
146 * Save the cr4 feature set we're using (ie
147 * Pentium 4MB enable and PPro Global page
148 * enable), so that any CPU's that boot up
149 * after us can get the correct flags.
151 extern unsigned long mmu_cr4_features;
153 static inline void set_in_cr4 (unsigned long mask)
156 mmu_cr4_features |= mask;
162 static inline void clear_in_cr4 (unsigned long mask)
165 mmu_cr4_features &= ~mask;
172 * NSC/Cyrix CPU indexed register access macros
175 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
177 #define setCx86(reg, data) do { \
179 outb((data), 0x23); \
182 /* Stop speculative execution */
183 static inline void sync_core(void)
186 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
189 static inline void __monitor(const void *eax, unsigned long ecx,
192 /* "monitor %eax,%ecx,%edx;" */
194 ".byte 0x0f,0x01,0xc8;"
195 : :"a" (eax), "c" (ecx), "d"(edx));
198 static inline void __mwait(unsigned long eax, unsigned long ecx)
200 /* "mwait %eax,%ecx;" */
202 ".byte 0x0f,0x01,0xc9;"
203 : :"a" (eax), "c" (ecx));
206 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
208 /* from system description table in BIOS. Mostly for MCA use, but
209 others may find it useful. */
210 extern unsigned int machine_id;
211 extern unsigned int machine_submodel_id;
212 extern unsigned int BIOS_revision;
213 extern unsigned int mca_pentium_flag;
215 /* Boot loader type from the setup header */
216 extern int bootloader_type;
219 * User space process size: 3GB (default).
221 #define TASK_SIZE (PAGE_OFFSET)
223 /* This decides where the kernel will search for a free chunk of vm
224 * space during mmap's.
226 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
228 #define HAVE_ARCH_PICK_MMAP_LAYOUT
233 #define IO_BITMAP_BITS 65536
234 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
235 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
236 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
237 #define INVALID_IO_BITMAP_OFFSET 0x8000
238 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
240 struct i387_fsave_struct {
248 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
249 long status; /* software status information */
252 struct i387_fxsave_struct {
263 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
264 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
266 } __attribute__ ((aligned (16)));
268 struct i387_soft_struct {
276 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
277 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
279 unsigned long entry_eip;
283 struct i387_fsave_struct fsave;
284 struct i387_fxsave_struct fxsave;
285 struct i387_soft_struct soft;
292 struct thread_struct;
295 unsigned short back_link,__blh;
297 unsigned short ss0,__ss0h;
299 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
301 unsigned short ss2,__ss2h;
304 unsigned long eflags;
305 unsigned long eax,ecx,edx,ebx;
310 unsigned short es, __esh;
311 unsigned short cs, __csh;
312 unsigned short ss, __ssh;
313 unsigned short ds, __dsh;
314 unsigned short fs, __fsh;
315 unsigned short gs, __gsh;
316 unsigned short ldt, __ldth;
317 unsigned short trace, io_bitmap_base;
319 * The extra 1 is there because the CPU will access an
320 * additional byte beyond the end of the IO permission
321 * bitmap. The extra byte must be all 1 bits, and must
322 * be within the limit.
324 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
326 * Cache the current maximum and the last task that used the bitmap:
328 unsigned long io_bitmap_max;
329 struct thread_struct *io_bitmap_owner;
331 * pads the TSS to be cacheline-aligned (size is 0x100)
333 unsigned long __cacheline_filler[35];
335 * .. and then another 0x100 bytes for emergency kernel stack
337 unsigned long stack[64];
338 } __attribute__((packed));
340 #define ARCH_MIN_TASKALIGN 16
342 struct thread_struct {
343 /* cached TLS descriptors. */
344 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
346 unsigned long sysenter_cs;
351 /* Hardware debugging registers */
352 unsigned long debugreg[8]; /* %%db0-7 debug registers */
354 unsigned long cr2, trap_no, error_code;
355 /* floating point info */
356 union i387_union i387;
357 /* virtual 86 mode info */
358 struct vm86_struct __user * vm86_info;
359 unsigned long screen_bitmap;
360 unsigned long v86flags, v86mask, saved_esp0;
361 unsigned int saved_fs, saved_gs;
363 unsigned long *io_bitmap_ptr;
365 /* max allowed port in the bitmap, in bytes: */
366 unsigned long io_bitmap_max;
369 #define INIT_THREAD { \
370 .esp0 = sizeof(init_stack) + (long)&init_stack, \
372 .sysenter_cs = __KERNEL_CS, \
373 .io_bitmap_ptr = NULL, \
374 .fs = __KERNEL_PDA, \
378 * Note that the .io_bitmap member must be extra-big. This is because
379 * the CPU will access an additional byte beyond the end of the IO
380 * permission bitmap. The extra byte must be all 1 bits, and must
381 * be within the limit.
384 .esp0 = sizeof(init_stack) + (long)&init_stack, \
385 .ss0 = __KERNEL_DS, \
386 .ss1 = __KERNEL_CS, \
387 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
388 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
391 #define start_thread(regs, new_eip, new_esp) do { \
392 __asm__("movl %0,%%gs": :"r" (0)); \
395 regs->xds = __USER_DS; \
396 regs->xes = __USER_DS; \
397 regs->xss = __USER_DS; \
398 regs->xcs = __USER_CS; \
399 regs->eip = new_eip; \
400 regs->esp = new_esp; \
403 /* Forward declaration, a strange C thing */
407 /* Free all resources held by a thread. */
408 extern void release_thread(struct task_struct *);
410 /* Prepare to copy thread state - unlazy all lazy status */
411 extern void prepare_to_copy(struct task_struct *tsk);
414 * create a kernel thread without removing it from tasklists
416 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
418 extern unsigned long thread_saved_pc(struct task_struct *tsk);
419 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
421 unsigned long get_wchan(struct task_struct *p);
423 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
424 #define KSTK_TOP(info) \
426 unsigned long *__ptr = (unsigned long *)(info); \
427 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
431 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
432 * This is necessary to guarantee that the entire "struct pt_regs"
433 * is accessable even if the CPU haven't stored the SS/ESP registers
434 * on the stack (interrupt gate does not save these registers
435 * when switching to the same priv ring).
436 * Therefore beware: accessing the xss/esp fields of the
437 * "struct pt_regs" is possible, but they may contain the
438 * completely wrong values.
440 #define task_pt_regs(task) \
442 struct pt_regs *__regs__; \
443 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
447 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
448 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
451 struct microcode_header {
459 unsigned int datasize;
460 unsigned int totalsize;
461 unsigned int reserved[3];
465 struct microcode_header hdr;
466 unsigned int bits[0];
469 typedef struct microcode microcode_t;
470 typedef struct microcode_header microcode_header_t;
472 /* microcode format is extended from prescott processors */
473 struct extended_signature {
479 struct extended_sigtable {
482 unsigned int reserved[3];
483 struct extended_signature sigs[0];
486 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
487 static inline void rep_nop(void)
489 __asm__ __volatile__("rep;nop": : :"memory");
492 #define cpu_relax() rep_nop()
494 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
496 tss->esp0 = thread->esp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
499 tss->ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
505 static inline unsigned long native_get_debugreg(int regno)
507 unsigned long val = 0; /* Damn you, gcc! */
511 asm("movl %%db0, %0" :"=r" (val)); break;
513 asm("movl %%db1, %0" :"=r" (val)); break;
515 asm("movl %%db2, %0" :"=r" (val)); break;
517 asm("movl %%db3, %0" :"=r" (val)); break;
519 asm("movl %%db6, %0" :"=r" (val)); break;
521 asm("movl %%db7, %0" :"=r" (val)); break;
528 static inline void native_set_debugreg(int regno, unsigned long value)
532 asm("movl %0,%%db0" : /* no output */ :"r" (value));
535 asm("movl %0,%%db1" : /* no output */ :"r" (value));
538 asm("movl %0,%%db2" : /* no output */ :"r" (value));
541 asm("movl %0,%%db3" : /* no output */ :"r" (value));
544 asm("movl %0,%%db6" : /* no output */ :"r" (value));
547 asm("movl %0,%%db7" : /* no output */ :"r" (value));
555 * Set IOPL bits in EFLAGS from given mask
557 static inline void native_set_iopl_mask(unsigned mask)
560 __asm__ __volatile__ ("pushfl;"
567 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
570 #ifdef CONFIG_PARAVIRT
571 #include <asm/paravirt.h>
573 #define paravirt_enabled() 0
574 #define __cpuid native_cpuid
576 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
578 native_load_esp0(tss, thread);
582 * These special macros can be used to get or set a debugging register
584 #define get_debugreg(var, register) \
585 (var) = native_get_debugreg(register)
586 #define set_debugreg(value, register) \
587 native_set_debugreg(register, value)
589 #define set_iopl_mask native_set_iopl_mask
590 #endif /* CONFIG_PARAVIRT */
593 * Generic CPUID function
594 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
595 * resulting in stale register contents being returned.
597 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
601 __cpuid(eax, ebx, ecx, edx);
604 /* Some CPUID calls want 'count' to be placed in ecx */
605 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
610 __cpuid(eax, ebx, ecx, edx);
614 * CPUID functions returning a single datum
616 static inline unsigned int cpuid_eax(unsigned int op)
618 unsigned int eax, ebx, ecx, edx;
620 cpuid(op, &eax, &ebx, &ecx, &edx);
623 static inline unsigned int cpuid_ebx(unsigned int op)
625 unsigned int eax, ebx, ecx, edx;
627 cpuid(op, &eax, &ebx, &ecx, &edx);
630 static inline unsigned int cpuid_ecx(unsigned int op)
632 unsigned int eax, ebx, ecx, edx;
634 cpuid(op, &eax, &ebx, &ecx, &edx);
637 static inline unsigned int cpuid_edx(unsigned int op)
639 unsigned int eax, ebx, ecx, edx;
641 cpuid(op, &eax, &ebx, &ecx, &edx);
645 /* generic versions from gas */
646 #define GENERIC_NOP1 ".byte 0x90\n"
647 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
648 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
649 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
650 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
651 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
652 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
653 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
656 #define K8_NOP1 GENERIC_NOP1
657 #define K8_NOP2 ".byte 0x66,0x90\n"
658 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
659 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
660 #define K8_NOP5 K8_NOP3 K8_NOP2
661 #define K8_NOP6 K8_NOP3 K8_NOP3
662 #define K8_NOP7 K8_NOP4 K8_NOP3
663 #define K8_NOP8 K8_NOP4 K8_NOP4
666 /* uses eax dependencies (arbitary choice) */
667 #define K7_NOP1 GENERIC_NOP1
668 #define K7_NOP2 ".byte 0x8b,0xc0\n"
669 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
670 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
671 #define K7_NOP5 K7_NOP4 ASM_NOP1
672 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
673 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
674 #define K7_NOP8 K7_NOP7 ASM_NOP1
677 #define ASM_NOP1 K8_NOP1
678 #define ASM_NOP2 K8_NOP2
679 #define ASM_NOP3 K8_NOP3
680 #define ASM_NOP4 K8_NOP4
681 #define ASM_NOP5 K8_NOP5
682 #define ASM_NOP6 K8_NOP6
683 #define ASM_NOP7 K8_NOP7
684 #define ASM_NOP8 K8_NOP8
685 #elif defined(CONFIG_MK7)
686 #define ASM_NOP1 K7_NOP1
687 #define ASM_NOP2 K7_NOP2
688 #define ASM_NOP3 K7_NOP3
689 #define ASM_NOP4 K7_NOP4
690 #define ASM_NOP5 K7_NOP5
691 #define ASM_NOP6 K7_NOP6
692 #define ASM_NOP7 K7_NOP7
693 #define ASM_NOP8 K7_NOP8
695 #define ASM_NOP1 GENERIC_NOP1
696 #define ASM_NOP2 GENERIC_NOP2
697 #define ASM_NOP3 GENERIC_NOP3
698 #define ASM_NOP4 GENERIC_NOP4
699 #define ASM_NOP5 GENERIC_NOP5
700 #define ASM_NOP6 GENERIC_NOP6
701 #define ASM_NOP7 GENERIC_NOP7
702 #define ASM_NOP8 GENERIC_NOP8
705 #define ASM_NOP_MAX 8
707 /* Prefetch instructions for Pentium III and AMD Athlon */
708 /* It's not worth to care about 3dnow! prefetches for the K6
709 because they are microcoded there and very slow.
710 However we don't do prefetches for pre XP Athlons currently
711 That should be fixed. */
712 #define ARCH_HAS_PREFETCH
713 static inline void prefetch(const void *x)
715 alternative_input(ASM_NOP4,
721 #define ARCH_HAS_PREFETCH
722 #define ARCH_HAS_PREFETCHW
723 #define ARCH_HAS_SPINLOCK_PREFETCH
725 /* 3dnow! prefetch to get an exclusive cache line. Useful for
726 spinlocks to avoid one state transition in the cache coherency protocol. */
727 static inline void prefetchw(const void *x)
729 alternative_input(ASM_NOP4,
734 #define spin_lock_prefetch(x) prefetchw(x)
736 extern void select_idle_routine(const struct cpuinfo_x86 *c);
738 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
740 extern unsigned long boot_option_idle_override;
741 extern void enable_sep_cpu(void);
742 extern int sysenter_setup(void);
744 extern void cpu_set_gdt(int);
745 extern void cpu_init(void);
747 extern int force_mwait;
749 #endif /* __ASM_I386_PROCESSOR_H */