SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/via/lcd.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include "global.h"
  23 #include "lcdtbl.h"
  24
  25 #define viafb_compact_res(x, y) (((x)<<16)|(y))
  26
  27 static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = {
  28         /* IGA2 Shadow Horizontal Total */
  29         {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
  30         /* IGA2 Shadow Horizontal Blank End */
  31         {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
  32         /* IGA2 Shadow Vertical Total */
  33         {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
  34         /* IGA2 Shadow Vertical Addressable Video */
  35         {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
  36         /* IGA2 Shadow Vertical Blank Start */
  37         {IGA2_SHADOW_VER_BLANK_START_REG_NUM,
  38          {{CR72, 0, 7}, {CR74, 4, 6} } },
  39         /* IGA2 Shadow Vertical Blank End */
  40         {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
  41         /* IGA2 Shadow Vertical Sync Start */
  42         {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
  43         /* IGA2 Shadow Vertical Sync End */
  44         {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
  45 };
  46
  47 static struct _lcd_scaling_factor lcd_scaling_factor = {
  48         /* LCD Horizontal Scaling Factor Register */
  49         {LCD_HOR_SCALING_FACTOR_REG_NUM,
  50          {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
  51         /* LCD Vertical Scaling Factor Register */
  52         {LCD_VER_SCALING_FACTOR_REG_NUM,
  53          {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
  54 };
  55 static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
  56         /* LCD Horizontal Scaling Factor Register */
  57         {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
  58         /* LCD Vertical Scaling Factor Register */
  59         {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
  60 };
  61
  62 static int check_lvds_chip(int device_id_subaddr, int device_id);
  63 static bool lvds_identify_integratedlvds(void);
  64 static void fp_id_to_vindex(int panel_id);
  65 static int lvds_register_read(int index);
  66 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  67                       int panel_vres);
  68 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
  69         int panel_id);
  70 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
  71         int panel_id);
  72 static void load_lcd_patch_regs(int set_hres, int set_vres,
  73         int panel_id, int set_iga);
  74 static void via_pitch_alignment_patch_lcd(
  75         struct lvds_setting_information *plvds_setting_info,
  76                                    struct lvds_chip_information
  77                                    *plvds_chip_info);
  78 static void lcd_patch_skew_dvp0(struct lvds_setting_information
  79                          *plvds_setting_info,
  80                          struct lvds_chip_information *plvds_chip_info);
  81 static void lcd_patch_skew_dvp1(struct lvds_setting_information
  82                          *plvds_setting_info,
  83                          struct lvds_chip_information *plvds_chip_info);
  84 static void lcd_patch_skew(struct lvds_setting_information
  85         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
  86
  87 static void integrated_lvds_disable(struct lvds_setting_information
  88                              *plvds_setting_info,
  89                              struct lvds_chip_information *plvds_chip_info);
  90 static void integrated_lvds_enable(struct lvds_setting_information
  91                             *plvds_setting_info,
  92                             struct lvds_chip_information *plvds_chip_info);
  93 static void lcd_powersequence_off(void);
  94 static void lcd_powersequence_on(void);
  95 static void fill_lcd_format(void);
  96 static void check_diport_of_integrated_lvds(
  97         struct lvds_chip_information *plvds_chip_info,
  98                                      struct lvds_setting_information
  99                                      *plvds_setting_info);
 100 static struct display_timing lcd_centering_timging(struct display_timing
 101                                             mode_crt_reg,
 102                                            struct display_timing panel_crt_reg);
 103 static void load_crtc_shadow_timing(struct display_timing mode_timing,
 104                              struct display_timing panel_timing);
 105 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
 106         int set_vres, int panel_hres, int panel_vres);
 107
 108 static int check_lvds_chip(int device_id_subaddr, int device_id)
 109 {
 110         if (lvds_register_read(device_id_subaddr) == device_id)
 111                 return OK;
 112         else
 113                 return FAIL;
 114 }
 115
 116 void viafb_init_lcd_size(void)
 117 {
 118         DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
 119         DEBUG_MSG(KERN_INFO
 120                 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
 121                 viaparinfo->lvds_setting_info->get_lcd_size_method);
 122
 123         switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
 124         case GET_LCD_SIZE_BY_SYSTEM_BIOS:
 125                 break;
 126         case GET_LCD_SZIE_BY_HW_STRAPPING:
 127                 break;
 128         case GET_LCD_SIZE_BY_VGA_BIOS:
 129                 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
 130                 fp_id_to_vindex(viafb_lcd_panel_id);
 131                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
 132                           viaparinfo->lvds_setting_info->lcd_panel_id);
 133                 break;
 134         case GET_LCD_SIZE_BY_USER_SETTING:
 135                 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
 136                 fp_id_to_vindex(viafb_lcd_panel_id);
 137                 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
 138                           viaparinfo->lvds_setting_info->lcd_panel_id);
 139                 break;
 140         default:
 141                 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
 142                 viaparinfo->lvds_setting_info->lcd_panel_id =
 143                         LCD_PANEL_ID1_800X600;
 144                 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
 145         }
 146         viaparinfo->lvds_setting_info2->lcd_panel_id =
 147                 viaparinfo->lvds_setting_info->lcd_panel_id;
 148         viaparinfo->lvds_setting_info2->lcd_panel_hres =
 149                 viaparinfo->lvds_setting_info->lcd_panel_hres;
 150         viaparinfo->lvds_setting_info2->lcd_panel_vres =
 151                 viaparinfo->lvds_setting_info->lcd_panel_vres;
 152         viaparinfo->lvds_setting_info2->device_lcd_dualedge =
 153             viaparinfo->lvds_setting_info->device_lcd_dualedge;
 154         viaparinfo->lvds_setting_info2->LCDDithering =
 155                 viaparinfo->lvds_setting_info->LCDDithering;
 156 }
 157
 158 static bool lvds_identify_integratedlvds(void)
 159 {
 160         if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
 161                 /* Two dual channel LCD (Internal LVDS + External LVDS): */
 162                 /* If we have an external LVDS, such as VT1636, we should
 163                    have its chip ID already. */
 164                 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
 165                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
 166                             INTEGRATED_LVDS;
 167                         DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\
 168                                   (Internal LVDS + External LVDS)\n");
 169                 } else {
 170                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
 171                             INTEGRATED_LVDS;
 172                         DEBUG_MSG(KERN_INFO "Not found external LVDS,\
 173                                   so can't support two dual channel LVDS!\n");
 174                 }
 175         } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
 176                 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
 177                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
 178                 INTEGRATED_LVDS;
 179                 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
 180                         INTEGRATED_LVDS;
 181                 DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\
 182                           (Internal LVDS + Internal LVDS)\n");
 183         } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
 184                 /* If we have found external LVDS, just use it,
 185                    otherwise, we will use internal LVDS as default. */
 186                 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
 187                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
 188                             INTEGRATED_LVDS;
 189                         DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
 190                 }
 191         } else {
 192                 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
 193                         NON_LVDS_TRANSMITTER;
 194                 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
 195                 return false;
 196         }
 197
 198         return true;
 199 }
 200
 201 int viafb_lvds_trasmitter_identify(void)
 202 {
 203         viaparinfo->shared->i2c_stuff.i2c_port = I2CPORTINDEX;
 204         if (viafb_lvds_identify_vt1636()) {
 205                 viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
 206                 DEBUG_MSG(KERN_INFO
 207                           "Found VIA VT1636 LVDS on port i2c 0x31 \n");
 208         } else {
 209                 viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
 210                 if (viafb_lvds_identify_vt1636()) {
 211                         viaparinfo->chip_info->lvds_chip_info.i2c_port =
 212                                 GPIOPORTINDEX;
 213                         DEBUG_MSG(KERN_INFO
 214                                   "Found VIA VT1636 LVDS on port gpio 0x2c \n");
 215                 }
 216         }
 217
 218         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
 219                 lvds_identify_integratedlvds();
 220
 221         if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
 222                 return true;
 223         /* Check for VT1631: */
 224         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
 225         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
 226                 VT1631_LVDS_I2C_ADDR;
 227
 228         if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
 229                 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
 230                 DEBUG_MSG(KERN_INFO "\n %2d",
 231                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
 232                 DEBUG_MSG(KERN_INFO "\n %2d",
 233                           viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
 234                 return OK;
 235         }
 236
 237         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
 238                 NON_LVDS_TRANSMITTER;
 239         viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
 240                 VT1631_LVDS_I2C_ADDR;
 241         return FAIL;
 242 }
 243
 244 static void fp_id_to_vindex(int panel_id)
 245 {
 246         DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
 247
 248         if (panel_id > LCD_PANEL_ID_MAXIMUM)
 249                 viafb_lcd_panel_id = panel_id =
 250                 viafb_read_reg(VIACR, CR3F) & 0x0F;
 251
 252         switch (panel_id) {
 253         case 0x0:
 254                 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
 255                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
 256                 viaparinfo->lvds_setting_info->lcd_panel_id =
 257                         LCD_PANEL_ID0_640X480;
 258                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 259                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 260                 break;
 261         case 0x1:
 262                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
 263                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
 264                 viaparinfo->lvds_setting_info->lcd_panel_id =
 265                         LCD_PANEL_ID1_800X600;
 266                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 267                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 268                 break;
 269         case 0x2:
 270                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
 271                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 272                 viaparinfo->lvds_setting_info->lcd_panel_id =
 273                         LCD_PANEL_ID2_1024X768;
 274                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 275                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 276                 break;
 277         case 0x3:
 278                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 279                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 280                 viaparinfo->lvds_setting_info->lcd_panel_id =
 281                         LCD_PANEL_ID3_1280X768;
 282                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 283                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 284                 break;
 285         case 0x4:
 286                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 287                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
 288                 viaparinfo->lvds_setting_info->lcd_panel_id =
 289                         LCD_PANEL_ID4_1280X1024;
 290                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 291                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 292                 break;
 293         case 0x5:
 294                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
 295                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
 296                 viaparinfo->lvds_setting_info->lcd_panel_id =
 297                         LCD_PANEL_ID5_1400X1050;
 298                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 299                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 300                 break;
 301         case 0x6:
 302                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
 303                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
 304                 viaparinfo->lvds_setting_info->lcd_panel_id =
 305                         LCD_PANEL_ID6_1600X1200;
 306                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 307                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 308                 break;
 309         case 0x8:
 310                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
 311                 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
 312                 viaparinfo->lvds_setting_info->lcd_panel_id =
 313                         LCD_PANEL_IDA_800X480;
 314                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 315                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 316                 break;
 317         case 0x9:
 318                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
 319                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 320                 viaparinfo->lvds_setting_info->lcd_panel_id =
 321                         LCD_PANEL_ID2_1024X768;
 322                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 323                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 324                 break;
 325         case 0xA:
 326                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
 327                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 328                 viaparinfo->lvds_setting_info->lcd_panel_id =
 329                         LCD_PANEL_ID2_1024X768;
 330                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 331                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 332                 break;
 333         case 0xB:
 334                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
 335                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 336                 viaparinfo->lvds_setting_info->lcd_panel_id =
 337                         LCD_PANEL_ID2_1024X768;
 338                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 339                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 340                 break;
 341         case 0xC:
 342                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 343                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 344                 viaparinfo->lvds_setting_info->lcd_panel_id =
 345                         LCD_PANEL_ID3_1280X768;
 346                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 347                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 348                 break;
 349         case 0xD:
 350                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 351                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
 352                 viaparinfo->lvds_setting_info->lcd_panel_id =
 353                         LCD_PANEL_ID4_1280X1024;
 354                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 355                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 356                 break;
 357         case 0xE:
 358                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
 359                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
 360                 viaparinfo->lvds_setting_info->lcd_panel_id =
 361                         LCD_PANEL_ID5_1400X1050;
 362                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 363                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 364                 break;
 365         case 0xF:
 366                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
 367                 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
 368                 viaparinfo->lvds_setting_info->lcd_panel_id =
 369                         LCD_PANEL_ID6_1600X1200;
 370                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 371                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 372                 break;
 373         case 0x10:
 374                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
 375                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 376                 viaparinfo->lvds_setting_info->lcd_panel_id =
 377                         LCD_PANEL_ID7_1366X768;
 378                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 379                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 380                 break;
 381         case 0x11:
 382                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
 383                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
 384                 viaparinfo->lvds_setting_info->lcd_panel_id =
 385                         LCD_PANEL_ID8_1024X600;
 386                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 387                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 388                 break;
 389         case 0x12:
 390                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 391                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 392                 viaparinfo->lvds_setting_info->lcd_panel_id =
 393                         LCD_PANEL_ID3_1280X768;
 394                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 395                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 396                 break;
 397         case 0x13:
 398                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 399                 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
 400                 viaparinfo->lvds_setting_info->lcd_panel_id =
 401                         LCD_PANEL_ID9_1280X800;
 402                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 403                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 404                 break;
 405         case 0x14:
 406                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
 407                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 408                 viaparinfo->lvds_setting_info->lcd_panel_id =
 409                         LCD_PANEL_IDB_1360X768;
 410                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 411                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 412                 break;
 413         case 0x15:
 414                 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
 415                 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
 416                 viaparinfo->lvds_setting_info->lcd_panel_id =
 417                         LCD_PANEL_ID3_1280X768;
 418                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
 419                 viaparinfo->lvds_setting_info->LCDDithering = 0;
 420                 break;
 421         case 0x16:
 422                 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
 423                 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
 424                 viaparinfo->lvds_setting_info->lcd_panel_id =
 425                         LCD_PANEL_IDC_480X640;
 426                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 427                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 428                 break;
 429         default:
 430                 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
 431                 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
 432                 viaparinfo->lvds_setting_info->lcd_panel_id =
 433                         LCD_PANEL_ID1_800X600;
 434                 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
 435                 viaparinfo->lvds_setting_info->LCDDithering = 1;
 436         }
 437 }
 438
 439 static int lvds_register_read(int index)
 440 {
 441         u8 data;
 442
 443         viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
 444         viafb_i2c_readbyte((u8) viaparinfo->chip_info->
 445             lvds_chip_info.lvds_chip_slave_addr,
 446                         (u8) index, &data);
 447         return data;
 448 }
 449
 450 static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
 451                       int panel_vres)
 452 {
 453         int reg_value = 0;
 454         int viafb_load_reg_num;
 455         struct io_register *reg = NULL;
 456
 457         DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
 458
 459         /* LCD Scaling Enable */
 460         viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
 461         if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
 462                 viafb_load_scaling_factor_for_p4m900(set_hres, set_vres,
 463                                                panel_hres, panel_vres);
 464                 return;
 465         }
 466
 467         /* Check if expansion for horizontal */
 468         if (set_hres != panel_hres) {
 469                 /* Load Horizontal Scaling Factor */
 470                 switch (viaparinfo->chip_info->gfx_chip_name) {
 471                 case UNICHROME_CLE266:
 472                 case UNICHROME_K400:
 473                         reg_value =
 474                             CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
 475                         viafb_load_reg_num =
 476                             lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
 477                             reg_num;
 478                         reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
 479                         viafb_load_reg(reg_value,
 480                                 viafb_load_reg_num, reg, VIACR);
 481                         break;
 482                 case UNICHROME_K800:
 483                 case UNICHROME_PM800:
 484                 case UNICHROME_CN700:
 485                 case UNICHROME_CX700:
 486                 case UNICHROME_K8M890:
 487                 case UNICHROME_P4M890:
 488                         reg_value =
 489                             K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
 490                         /* Horizontal scaling enabled */
 491                         viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
 492                         viafb_load_reg_num =
 493                             lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
 494                         reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
 495                         viafb_load_reg(reg_value,
 496                                 viafb_load_reg_num, reg, VIACR);
 497                         break;
 498                 }
 499
 500                 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
 501         } else {
 502                 /* Horizontal scaling disabled */
 503                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
 504         }
 505
 506         /* Check if expansion for vertical */
 507         if (set_vres != panel_vres) {
 508                 /* Load Vertical Scaling Factor */
 509                 switch (viaparinfo->chip_info->gfx_chip_name) {
 510                 case UNICHROME_CLE266:
 511                 case UNICHROME_K400:
 512                         reg_value =
 513                             CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
 514                         viafb_load_reg_num =
 515                             lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
 516                             reg_num;
 517                         reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
 518                         viafb_load_reg(reg_value,
 519                                 viafb_load_reg_num, reg, VIACR);
 520                         break;
 521                 case UNICHROME_K800:
 522                 case UNICHROME_PM800:
 523                 case UNICHROME_CN700:
 524                 case UNICHROME_CX700:
 525                 case UNICHROME_K8M890:
 526                 case UNICHROME_P4M890:
 527                         reg_value =
 528                             K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
 529                         /* Vertical scaling enabled */
 530                         viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
 531                         viafb_load_reg_num =
 532                             lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
 533                         reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
 534                         viafb_load_reg(reg_value,
 535                                 viafb_load_reg_num, reg, VIACR);
 536                         break;
 537                 }
 538
 539                 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
 540         } else {
 541                 /* Vertical scaling disabled */
 542                 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
 543         }
 544 }
 545
 546 static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
 547         int panel_id)
 548 {
 549         u32 compact_mode = viafb_compact_res(set_hres, set_vres);
 550         int reg_num = 0;
 551         struct io_reg *lcd_patch_reg = NULL;
 552
 553         switch (panel_id) {
 554                 /* LCD 800x600 */
 555         case LCD_PANEL_ID1_800X600:
 556                 switch (compact_mode) {
 557                 case viafb_compact_res(640, 400):
 558                 case viafb_compact_res(640, 480):
 559                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
 560                         lcd_patch_reg = K400_LCD_RES_6X4_8X6;
 561                         break;
 562                 case viafb_compact_res(720, 480):
 563                 case viafb_compact_res(720, 576):
 564                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
 565                         lcd_patch_reg = K400_LCD_RES_7X4_8X6;
 566                         break;
 567                 }
 568                 break;
 569
 570                 /* LCD 1024x768 */
 571         case LCD_PANEL_ID2_1024X768:
 572                 switch (compact_mode) {
 573                 case viafb_compact_res(640, 400):
 574                 case viafb_compact_res(640, 480):
 575                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
 576                         lcd_patch_reg = K400_LCD_RES_6X4_10X7;
 577                         break;
 578                 case viafb_compact_res(720, 480):
 579                 case viafb_compact_res(720, 576):
 580                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
 581                         lcd_patch_reg = K400_LCD_RES_7X4_10X7;
 582                         break;
 583                 case viafb_compact_res(800, 600):
 584                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
 585                         lcd_patch_reg = K400_LCD_RES_8X6_10X7;
 586                         break;
 587                 }
 588                 break;
 589
 590                 /* LCD 1280x1024 */
 591         case LCD_PANEL_ID4_1280X1024:
 592                 switch (compact_mode) {
 593                 case viafb_compact_res(640, 400):
 594                 case viafb_compact_res(640, 480):
 595                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
 596                         lcd_patch_reg = K400_LCD_RES_6X4_12X10;
 597                         break;
 598                 case viafb_compact_res(720, 480):
 599                 case viafb_compact_res(720, 576):
 600                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
 601                         lcd_patch_reg = K400_LCD_RES_7X4_12X10;
 602                         break;
 603                 case viafb_compact_res(800, 600):
 604                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
 605                         lcd_patch_reg = K400_LCD_RES_8X6_12X10;
 606                         break;
 607                 case viafb_compact_res(1024, 768):
 608                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
 609                         lcd_patch_reg = K400_LCD_RES_10X7_12X10;
 610                         break;
 611
 612                 }
 613                 break;
 614
 615                 /* LCD 1400x1050 */
 616         case LCD_PANEL_ID5_1400X1050:
 617                 switch (compact_mode) {
 618                 case viafb_compact_res(640, 480):
 619                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
 620                         lcd_patch_reg = K400_LCD_RES_6X4_14X10;
 621                         break;
 622                 case viafb_compact_res(800, 600):
 623                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
 624                         lcd_patch_reg = K400_LCD_RES_8X6_14X10;
 625                         break;
 626                 case viafb_compact_res(1024, 768):
 627                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
 628                         lcd_patch_reg = K400_LCD_RES_10X7_14X10;
 629                         break;
 630                 case viafb_compact_res(1280, 768):
 631                 case viafb_compact_res(1280, 800):
 632                 case viafb_compact_res(1280, 960):
 633                 case viafb_compact_res(1280, 1024):
 634                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
 635                         lcd_patch_reg = K400_LCD_RES_12X10_14X10;
 636                         break;
 637                 }
 638                 break;
 639
 640                 /* LCD 1600x1200 */
 641         case LCD_PANEL_ID6_1600X1200:
 642                 switch (compact_mode) {
 643                 case viafb_compact_res(640, 400):
 644                 case viafb_compact_res(640, 480):
 645                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
 646                         lcd_patch_reg = K400_LCD_RES_6X4_16X12;
 647                         break;
 648                 case viafb_compact_res(720, 480):
 649                 case viafb_compact_res(720, 576):
 650                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
 651                         lcd_patch_reg = K400_LCD_RES_7X4_16X12;
 652                         break;
 653                 case viafb_compact_res(800, 600):
 654                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
 655                         lcd_patch_reg = K400_LCD_RES_8X6_16X12;
 656                         break;
 657                 case viafb_compact_res(1024, 768):
 658                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
 659                         lcd_patch_reg = K400_LCD_RES_10X7_16X12;
 660                         break;
 661                 case viafb_compact_res(1280, 768):
 662                 case viafb_compact_res(1280, 800):
 663                 case viafb_compact_res(1280, 960):
 664                 case viafb_compact_res(1280, 1024):
 665                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
 666                         lcd_patch_reg = K400_LCD_RES_12X10_16X12;
 667                         break;
 668                 }
 669                 break;
 670
 671                 /* LCD 1366x768 */
 672         case LCD_PANEL_ID7_1366X768:
 673                 switch (compact_mode) {
 674                 case viafb_compact_res(640, 480):
 675                         reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
 676                         lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
 677                         break;
 678                 case viafb_compact_res(720, 480):
 679                 case viafb_compact_res(720, 576):
 680                         reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
 681                         lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
 682                         break;
 683                 case viafb_compact_res(800, 600):
 684                         reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
 685                         lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
 686                         break;
 687                 case viafb_compact_res(1024, 768):
 688                         reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
 689                         lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
 690                         break;
 691                 case viafb_compact_res(1280, 768):
 692                 case viafb_compact_res(1280, 800):
 693                 case viafb_compact_res(1280, 960):
 694                 case viafb_compact_res(1280, 1024):
 695                         reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
 696                         lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
 697                         break;
 698                 }
 699                 break;
 700
 701                 /* LCD 1360x768 */
 702         case LCD_PANEL_IDB_1360X768:
 703                 break;
 704         }
 705         if (reg_num != 0) {
 706                 /* H.W. Reset : ON */
 707                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
 708
 709                 viafb_write_regx(lcd_patch_reg, reg_num);
 710
 711                 /* H.W. Reset : OFF */
 712                 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
 713
 714                 /* Reset PLL */
 715                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
 716                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
 717
 718                 /* Fire! */
 719                 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
 720         }
 721 }
 722
 723 static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
 724         int panel_id)
 725 {
 726         u32 compact_mode = viafb_compact_res(set_hres, set_vres);
 727         int reg_num = 0;
 728         struct io_reg *lcd_patch_reg = NULL;
 729
 730         switch (panel_id) {
 731         case LCD_PANEL_ID5_1400X1050:
 732                 switch (compact_mode) {
 733                 case viafb_compact_res(640, 480):
 734                         reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
 735                         lcd_patch_reg = P880_LCD_RES_6X4_14X10;
 736                         break;
 737                 case viafb_compact_res(800, 600):
 738                         reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
 739                         lcd_patch_reg = P880_LCD_RES_8X6_14X10;
 740                         break;
 741                 }
 742                 break;
 743         case LCD_PANEL_ID6_1600X1200:
 744                 switch (compact_mode) {
 745                 case viafb_compact_res(640, 400):
 746                 case viafb_compact_res(640, 480):
 747                         reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
 748                         lcd_patch_reg = P880_LCD_RES_6X4_16X12;
 749                         break;
 750                 case viafb_compact_res(720, 480):
 751                 case viafb_compact_res(720, 576):
 752                         reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
 753                         lcd_patch_reg = P880_LCD_RES_7X4_16X12;
 754                         break;
 755                 case viafb_compact_res(800, 600):
 756                         reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
 757                         lcd_patch_reg = P880_LCD_RES_8X6_16X12;
 758                         break;
 759                 case viafb_compact_res(1024, 768):
 760                         reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
 761                         lcd_patch_reg = P880_LCD_RES_10X7_16X12;
 762                         break;
 763                 case viafb_compact_res(1280, 768):
 764                 case viafb_compact_res(1280, 960):
 765                 case viafb_compact_res(1280, 1024):
 766                         reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
 767                         lcd_patch_reg = P880_LCD_RES_12X10_16X12;
 768                         break;
 769                 }
 770                 break;
 771
 772         }
 773         if (reg_num != 0) {
 774                 /* H.W. Reset : ON */
 775                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
 776
 777                 viafb_write_regx(lcd_patch_reg, reg_num);
 778
 779                 /* H.W. Reset : OFF */
 780                 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
 781
 782                 /* Reset PLL */
 783                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
 784                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
 785
 786                 /* Fire! */
 787                 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
 788         }
 789 }
 790
 791 static void load_lcd_patch_regs(int set_hres, int set_vres,
 792         int panel_id, int set_iga)
 793 {
 794         viafb_unlock_crt();
 795
 796         /* Patch for simultaneous & Expansion */
 797         if ((set_iga == IGA1_IGA2) &&
 798                 (viaparinfo->lvds_setting_info->display_method ==
 799             LCD_EXPANDSION)) {
 800                 switch (viaparinfo->chip_info->gfx_chip_name) {
 801                 case UNICHROME_CLE266:
 802                 case UNICHROME_K400:
 803                         load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
 804                         break;
 805                 case UNICHROME_K800:
 806                         break;
 807                 case UNICHROME_PM800:
 808                 case UNICHROME_CN700:
 809                 case UNICHROME_CX700:
 810                         load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
 811                 }
 812         }
 813
 814         viafb_lock_crt();
 815 }
 816
 817 static void via_pitch_alignment_patch_lcd(
 818         struct lvds_setting_information *plvds_setting_info,
 819                                    struct lvds_chip_information
 820                                    *plvds_chip_info)
 821 {
 822         unsigned char cr13, cr35, cr65, cr66, cr67;
 823         unsigned long dwScreenPitch = 0;
 824         unsigned long dwPitch;
 825
 826         dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
 827         if (dwPitch & 0x1F) {
 828                 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
 829                 if (plvds_setting_info->iga_path == IGA2) {
 830                         if (plvds_setting_info->bpp > 8) {
 831                                 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
 832                                 viafb_write_reg(CR66, VIACR, cr66);
 833                                 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
 834                                 cr67 |=
 835                                     (unsigned
 836                                      char)((dwScreenPitch & 0x300) >> 8);
 837                                 viafb_write_reg(CR67, VIACR, cr67);
 838                         }
 839
 840                         /* Fetch Count */
 841                         cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
 842                         cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
 843                         viafb_write_reg(CR67, VIACR, cr67);
 844                         cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
 845                         cr65 += 2;
 846                         viafb_write_reg(CR65, VIACR, cr65);
 847                 } else {
 848                         if (plvds_setting_info->bpp > 8) {
 849                                 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
 850                                 viafb_write_reg(CR13, VIACR, cr13);
 851                                 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
 852                                 cr35 |=
 853                                     (unsigned
 854                                      char)((dwScreenPitch & 0x700) >> 3);
 855                                 viafb_write_reg(CR35, VIACR, cr35);
 856                         }
 857                 }
 858         }
 859 }
 860 static void lcd_patch_skew_dvp0(struct lvds_setting_information
 861                          *plvds_setting_info,
 862                          struct lvds_chip_information *plvds_chip_info)
 863 {
 864         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
 865                 switch (viaparinfo->chip_info->gfx_chip_name) {
 866                 case UNICHROME_P4M900:
 867                         viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
 868                                                     plvds_chip_info);
 869                         break;
 870                 case UNICHROME_P4M890:
 871                         viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
 872                                                     plvds_chip_info);
 873                         break;
 874                 }
 875         }
 876 }
 877 static void lcd_patch_skew_dvp1(struct lvds_setting_information
 878                          *plvds_setting_info,
 879                          struct lvds_chip_information *plvds_chip_info)
 880 {
 881         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
 882                 switch (viaparinfo->chip_info->gfx_chip_name) {
 883                 case UNICHROME_CX700:
 884                         viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
 885                                                     plvds_chip_info);
 886                         break;
 887                 }
 888         }
 889 }
 890 static void lcd_patch_skew(struct lvds_setting_information
 891         *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
 892 {
 893         DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
 894         switch (plvds_chip_info->output_interface) {
 895         case INTERFACE_DVP0:
 896                 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
 897                 break;
 898         case INTERFACE_DVP1:
 899                 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
 900                 break;
 901         case INTERFACE_DFP_LOW:
 902                 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
 903                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 904                                        BIT0 + BIT1 + BIT2 + BIT3);
 905                 }
 906                 break;
 907         }
 908 }
 909
 910 /* LCD Set Mode */
 911 void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
 912                   struct lvds_setting_information *plvds_setting_info,
 913                   struct lvds_chip_information *plvds_chip_info)
 914 {
 915         int set_iga = plvds_setting_info->iga_path;
 916         int mode_bpp = plvds_setting_info->bpp;
 917         int set_hres = plvds_setting_info->h_active;
 918         int set_vres = plvds_setting_info->v_active;
 919         int panel_hres = plvds_setting_info->lcd_panel_hres;
 920         int panel_vres = plvds_setting_info->lcd_panel_vres;
 921         u32 pll_D_N;
 922         int offset;
 923         struct display_timing mode_crt_reg, panel_crt_reg;
 924         struct crt_mode_table *panel_crt_table = NULL;
 925         struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
 926                 panel_vres);
 927
 928         DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
 929         /* Get mode table */
 930         mode_crt_reg = mode_crt_table->crtc;
 931         /* Get panel table Pointer */
 932         panel_crt_table = vmode_tbl->crtc;
 933         panel_crt_reg = panel_crt_table->crtc;
 934         DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
 935         if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
 936                 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
 937         plvds_setting_info->vclk = panel_crt_table->clk;
 938         if (set_iga == IGA1) {
 939                 /* IGA1 doesn't have LCD scaling, so set it as centering. */
 940                 viafb_load_crtc_timing(lcd_centering_timging
 941                                  (mode_crt_reg, panel_crt_reg), IGA1);
 942         } else {
 943                 /* Expansion */
 944                 if ((plvds_setting_info->display_method ==
 945                      LCD_EXPANDSION) & ((set_hres != panel_hres)
 946                                         || (set_vres != panel_vres))) {
 947                         /* expansion timing IGA2 loaded panel set timing*/
 948                         viafb_load_crtc_timing(panel_crt_reg, IGA2);
 949                         DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
 950                         load_lcd_scaling(set_hres, set_vres, panel_hres,
 951                                          panel_vres);
 952                         DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
 953                 } else {        /* Centering */
 954                         /* centering timing IGA2 always loaded panel
 955                            and mode releative timing */
 956                         viafb_load_crtc_timing(lcd_centering_timging
 957                                          (mode_crt_reg, panel_crt_reg), IGA2);
 958                         viafb_write_reg_mask(CR79, VIACR, 0x00,
 959                                 BIT0 + BIT1 + BIT2);
 960                         /* LCD scaling disabled */
 961                 }
 962         }
 963
 964         if (set_iga == IGA1_IGA2) {
 965                 load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
 966                 /* Fill shadow registers */
 967
 968                 switch (plvds_setting_info->lcd_panel_id) {
 969                 case LCD_PANEL_ID0_640X480:
 970                         offset = 80;
 971                         break;
 972                 case LCD_PANEL_ID1_800X600:
 973                 case LCD_PANEL_IDA_800X480:
 974                         offset = 110;
 975                         break;
 976                 case LCD_PANEL_ID2_1024X768:
 977                         offset = 150;
 978                         break;
 979                 case LCD_PANEL_ID3_1280X768:
 980                 case LCD_PANEL_ID4_1280X1024:
 981                 case LCD_PANEL_ID5_1400X1050:
 982                 case LCD_PANEL_ID9_1280X800:
 983                         offset = 190;
 984                         break;
 985                 case LCD_PANEL_ID6_1600X1200:
 986                         offset = 250;
 987                         break;
 988                 case LCD_PANEL_ID7_1366X768:
 989                 case LCD_PANEL_IDB_1360X768:
 990                         offset = 212;
 991                         break;
 992                 default:
 993                         offset = 140;
 994                         break;
 995                 }
 996
 997                 /* Offset for simultaneous */
 998                 viafb_set_secondary_pitch(offset << 3);
 999                 DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
1000                 viafb_load_fetch_count_reg(set_hres, 4, IGA2);
1001                 /* Fetch count for simultaneous */
1002         } else {                /* SAMM */
1003                 /* Fetch count for IGA2 only */
1004                 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1005
1006                 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1007                     && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1008                         viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1009         }
1010
1011         fill_lcd_format();
1012
1013         pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
1014         DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
1015         viafb_set_vclock(pll_D_N, set_iga);
1016
1017         viafb_set_output_path(DEVICE_LCD, set_iga,
1018                 plvds_chip_info->output_interface);
1019         lcd_patch_skew(plvds_setting_info, plvds_chip_info);
1020
1021         /* If K8M800, enable LCD Prefetch Mode. */
1022         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1023             || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
1024                 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
1025
1026         load_lcd_patch_regs(set_hres, set_vres,
1027                             plvds_setting_info->lcd_panel_id, set_iga);
1028
1029         DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
1030
1031         /* Patch for non 32bit alignment mode */
1032         via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
1033 }
1034
1035 static void integrated_lvds_disable(struct lvds_setting_information
1036                              *plvds_setting_info,
1037                              struct lvds_chip_information *plvds_chip_info)
1038 {
1039         bool turn_off_first_powersequence = false;
1040         bool turn_off_second_powersequence = false;
1041         if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
1042                 turn_off_first_powersequence = true;
1043         if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
1044                 turn_off_first_powersequence = true;
1045         if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
1046                 turn_off_second_powersequence = true;
1047         if (turn_off_second_powersequence) {
1048                 /* Use second power sequence control: */
1049
1050                 /* Turn off power sequence. */
1051                 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
1052
1053                 /* Turn off back light. */
1054                 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
1055         }
1056         if (turn_off_first_powersequence) {
1057                 /* Use first power sequence control: */
1058
1059                 /* Turn off power sequence. */
1060                 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
1061
1062                 /* Turn off back light. */
1063                 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
1064         }
1065
1066         /* Turn DFP High/Low Pad off. */
1067         viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
1068
1069         /* Power off LVDS channel. */
1070         switch (plvds_chip_info->output_interface) {
1071         case INTERFACE_LVDS0:
1072                 {
1073                         viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
1074                         break;
1075                 }
1076
1077         case INTERFACE_LVDS1:
1078                 {
1079                         viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
1080                         break;
1081                 }
1082
1083         case INTERFACE_LVDS0LVDS1:
1084                 {
1085                         viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
1086                         break;
1087                 }
1088         }
1089 }
1090
1091 static void integrated_lvds_enable(struct lvds_setting_information
1092                             *plvds_setting_info,
1093                             struct lvds_chip_information *plvds_chip_info)
1094 {
1095         DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
1096                   plvds_chip_info->output_interface);
1097         if (plvds_setting_info->lcd_mode == LCD_SPWG)
1098                 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
1099         else
1100                 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
1101
1102         switch (plvds_chip_info->output_interface) {
1103         case INTERFACE_LVDS0LVDS1:
1104         case INTERFACE_LVDS0:
1105                 /* Use first power sequence control: */
1106                 /* Use hardware control power sequence. */
1107                 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
1108                 /* Turn on back light. */
1109                 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
1110                 /* Turn on hardware power sequence. */
1111                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
1112                 break;
1113         case INTERFACE_LVDS1:
1114                 /* Use second power sequence control: */
1115                 /* Use hardware control power sequence. */
1116                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
1117                 /* Turn on back light. */
1118                 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
1119                 /* Turn on hardware power sequence. */
1120                 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
1121                 break;
1122         }
1123
1124         /* Turn DFP High/Low pad on. */
1125         viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
1126
1127         /* Power on LVDS channel. */
1128         switch (plvds_chip_info->output_interface) {
1129         case INTERFACE_LVDS0:
1130                 {
1131                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
1132                         break;
1133                 }
1134
1135         case INTERFACE_LVDS1:
1136                 {
1137                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
1138                         break;
1139                 }
1140
1141         case INTERFACE_LVDS0LVDS1:
1142                 {
1143                         viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
1144                         break;
1145                 }
1146         }
1147 }
1148
1149 void viafb_lcd_disable(void)
1150 {
1151
1152         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1153                 lcd_powersequence_off();
1154                 /* DI1 pad off */
1155                 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
1156         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1157                 if (viafb_LCD2_ON
1158                     && (INTEGRATED_LVDS ==
1159                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1160                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
1161                                 &viaparinfo->chip_info->lvds_chip_info2);
1162                 if (INTEGRATED_LVDS ==
1163                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1164                         integrated_lvds_disable(viaparinfo->lvds_setting_info,
1165                                 &viaparinfo->chip_info->lvds_chip_info);
1166                 if (VT1636_LVDS == viaparinfo->chip_info->
1167                         lvds_chip_info.lvds_chip_name)
1168                         viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1169                                 &viaparinfo->chip_info->lvds_chip_info);
1170         } else if (VT1636_LVDS ==
1171         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1172                 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
1173                                     &viaparinfo->chip_info->lvds_chip_info);
1174         } else {
1175                 /* DFP-HL pad off          */
1176                 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
1177                 /* Backlight off           */
1178                 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
1179                 /* 24 bit DI data paht off */
1180                 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
1181                 /* Simultaneout disabled   */
1182                 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1183         }
1184
1185         /* Disable expansion bit   */
1186         viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
1187         /* CRT path set to IGA1    */
1188         viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
1189         /* Simultaneout disabled   */
1190         viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
1191         /* IGA2 path disabled      */
1192         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1193
1194 }
1195
1196 void viafb_lcd_enable(void)
1197 {
1198         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1199                 /* DI1 pad on */
1200                 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
1201                 lcd_powersequence_on();
1202         } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1203                 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
1204                         viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
1205                         integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
1206                                 &viaparinfo->chip_info->lvds_chip_info2);
1207                 if (INTEGRATED_LVDS ==
1208                         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
1209                         integrated_lvds_enable(viaparinfo->lvds_setting_info,
1210                                 &viaparinfo->chip_info->lvds_chip_info);
1211                 if (VT1636_LVDS == viaparinfo->chip_info->
1212                         lvds_chip_info.lvds_chip_name)
1213                         viafb_enable_lvds_vt1636(viaparinfo->
1214                         lvds_setting_info, &viaparinfo->chip_info->
1215                         lvds_chip_info);
1216         } else if (VT1636_LVDS ==
1217         viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
1218                 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
1219                                    &viaparinfo->chip_info->lvds_chip_info);
1220         } else {
1221                 /* DFP-HL pad on           */
1222                 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
1223                 /* Backlight on            */
1224                 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
1225                 /* 24 bit DI data paht on  */
1226                 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
1227
1228                 /* Set data source selection bit by iga path */
1229                 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1230                         /* DFP-H set to IGA1       */
1231                         viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
1232                         /* DFP-L set to IGA1       */
1233                         viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
1234                 } else {
1235                         /* DFP-H set to IGA2       */
1236                         viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
1237                         /* DFP-L set to IGA2       */
1238                         viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
1239                 }
1240                 /* LCD enabled             */
1241                 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
1242         }
1243
1244         if ((viaparinfo->lvds_setting_info->iga_path == IGA1)
1245             || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
1246                 /* CRT path set to IGA2    */
1247                 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
1248                 /* IGA2 path disabled      */
1249                 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
1250                 /* IGA2 path enabled       */
1251         } else {                /* IGA2 */
1252                 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
1253         }
1254
1255 }
1256
1257 static void lcd_powersequence_off(void)
1258 {
1259         int i, mask, data;
1260
1261         /* Software control power sequence */
1262         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1263
1264         for (i = 0; i < 3; i++) {
1265                 mask = PowerSequenceOff[0][i];
1266                 data = PowerSequenceOff[1][i] & mask;
1267                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1268                 udelay(PowerSequenceOff[2][i]);
1269         }
1270
1271         /* Disable LCD */
1272         viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
1273 }
1274
1275 static void lcd_powersequence_on(void)
1276 {
1277         int i, mask, data;
1278
1279         /* Software control power sequence */
1280         viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
1281
1282         /* Enable LCD */
1283         viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
1284
1285         for (i = 0; i < 3; i++) {
1286                 mask = PowerSequenceOn[0][i];
1287                 data = PowerSequenceOn[1][i] & mask;
1288                 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
1289                 udelay(PowerSequenceOn[2][i]);
1290         }
1291
1292         udelay(1);
1293 }
1294
1295 static void fill_lcd_format(void)
1296 {
1297         u8 bdithering = 0, bdual = 0;
1298
1299         if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
1300                 bdual = BIT4;
1301         if (viaparinfo->lvds_setting_info->LCDDithering)
1302                 bdithering = BIT0;
1303         /* Dual & Dithering */
1304         viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
1305 }
1306
1307 static void check_diport_of_integrated_lvds(
1308         struct lvds_chip_information *plvds_chip_info,
1309                                      struct lvds_setting_information
1310                                      *plvds_setting_info)
1311 {
1312         /* Determine LCD DI Port by hardware layout. */
1313         switch (viafb_display_hardware_layout) {
1314         case HW_LAYOUT_LCD_ONLY:
1315                 {
1316                         if (plvds_setting_info->device_lcd_dualedge) {
1317                                 plvds_chip_info->output_interface =
1318                                     INTERFACE_LVDS0LVDS1;
1319                         } else {
1320                                 plvds_chip_info->output_interface =
1321                                     INTERFACE_LVDS0;
1322                         }
1323
1324                         break;
1325                 }
1326
1327         case HW_LAYOUT_DVI_ONLY:
1328                 {
1329                         plvds_chip_info->output_interface = INTERFACE_NONE;
1330                         break;
1331                 }
1332
1333         case HW_LAYOUT_LCD1_LCD2:
1334         case HW_LAYOUT_LCD_EXTERNAL_LCD2:
1335                 {
1336                         plvds_chip_info->output_interface =
1337                             INTERFACE_LVDS0LVDS1;
1338                         break;
1339                 }
1340
1341         case HW_LAYOUT_LCD_DVI:
1342                 {
1343                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1344                         break;
1345                 }
1346
1347         default:
1348                 {
1349                         plvds_chip_info->output_interface = INTERFACE_LVDS1;
1350                         break;
1351                 }
1352         }
1353
1354         DEBUG_MSG(KERN_INFO
1355                   "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1356                   viafb_display_hardware_layout,
1357                   plvds_chip_info->output_interface);
1358 }
1359
1360 void viafb_init_lvds_output_interface(struct lvds_chip_information
1361                                 *plvds_chip_info,
1362                                 struct lvds_setting_information
1363                                 *plvds_setting_info)
1364 {
1365         if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1366                 /*Do nothing, lcd port is specified by module parameter */
1367                 return;
1368         }
1369
1370         switch (plvds_chip_info->lvds_chip_name) {
1371
1372         case VT1636_LVDS:
1373                 switch (viaparinfo->chip_info->gfx_chip_name) {
1374                 case UNICHROME_CX700:
1375                         plvds_chip_info->output_interface = INTERFACE_DVP1;
1376                         break;
1377                 case UNICHROME_CN700:
1378                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1379                         break;
1380                 default:
1381                         plvds_chip_info->output_interface = INTERFACE_DVP0;
1382                         break;
1383                 }
1384                 break;
1385
1386         case INTEGRATED_LVDS:
1387                 check_diport_of_integrated_lvds(plvds_chip_info,
1388                                                 plvds_setting_info);
1389                 break;
1390
1391         default:
1392                 switch (viaparinfo->chip_info->gfx_chip_name) {
1393                 case UNICHROME_K8M890:
1394                 case UNICHROME_P4M900:
1395                 case UNICHROME_P4M890:
1396                         plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1397                         break;
1398                 default:
1399                         plvds_chip_info->output_interface = INTERFACE_DFP;
1400                         break;
1401                 }
1402                 break;
1403         }
1404 }
1405
1406 static struct display_timing lcd_centering_timging(struct display_timing
1407                                             mode_crt_reg,
1408                                             struct display_timing panel_crt_reg)
1409 {
1410         struct display_timing crt_reg;
1411
1412         crt_reg.hor_total = panel_crt_reg.hor_total;
1413         crt_reg.hor_addr = mode_crt_reg.hor_addr;
1414         crt_reg.hor_blank_start =
1415             (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1416             crt_reg.hor_addr;
1417         crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1418         crt_reg.hor_sync_start =
1419             (panel_crt_reg.hor_sync_start -
1420              panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1421         crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1422
1423         crt_reg.ver_total = panel_crt_reg.ver_total;
1424         crt_reg.ver_addr = mode_crt_reg.ver_addr;
1425         crt_reg.ver_blank_start =
1426             (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1427             crt_reg.ver_addr;
1428         crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1429         crt_reg.ver_sync_start =
1430             (panel_crt_reg.ver_sync_start -
1431              panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1432         crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1433
1434         return crt_reg;
1435 }
1436
1437 static void load_crtc_shadow_timing(struct display_timing mode_timing,
1438                              struct display_timing panel_timing)
1439 {
1440         struct io_register *reg = NULL;
1441         int i;
1442         int viafb_load_reg_Num = 0;
1443         int reg_value = 0;
1444
1445         if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
1446                 /* Expansion */
1447                 for (i = 12; i < 20; i++) {
1448                         switch (i) {
1449                         case H_TOTAL_SHADOW_INDEX:
1450                                 reg_value =
1451                                     IGA2_HOR_TOTAL_SHADOW_FORMULA
1452                                     (panel_timing.hor_total);
1453                                 viafb_load_reg_Num =
1454                                     iga2_shadow_crtc_reg.hor_total_shadow.
1455                                     reg_num;
1456                                 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1457                                 break;
1458                         case H_BLANK_END_SHADOW_INDEX:
1459                                 reg_value =
1460                                     IGA2_HOR_BLANK_END_SHADOW_FORMULA
1461                                     (panel_timing.hor_blank_start,
1462                                      panel_timing.hor_blank_end);
1463                                 viafb_load_reg_Num =
1464                                     iga2_shadow_crtc_reg.
1465                                     hor_blank_end_shadow.reg_num;
1466                                 reg =
1467                                     iga2_shadow_crtc_reg.
1468                                     hor_blank_end_shadow.reg;
1469                                 break;
1470                         case V_TOTAL_SHADOW_INDEX:
1471                                 reg_value =
1472                                     IGA2_VER_TOTAL_SHADOW_FORMULA
1473                                     (panel_timing.ver_total);
1474                                 viafb_load_reg_Num =
1475                                     iga2_shadow_crtc_reg.ver_total_shadow.
1476                                     reg_num;
1477                                 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1478                                 break;
1479                         case V_ADDR_SHADOW_INDEX:
1480                                 reg_value =
1481                                     IGA2_VER_ADDR_SHADOW_FORMULA
1482                                     (panel_timing.ver_addr);
1483                                 viafb_load_reg_Num =
1484                                     iga2_shadow_crtc_reg.ver_addr_shadow.
1485                                     reg_num;
1486                                 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1487                                 break;
1488                         case V_BLANK_SATRT_SHADOW_INDEX:
1489                                 reg_value =
1490                                     IGA2_VER_BLANK_START_SHADOW_FORMULA
1491                                     (panel_timing.ver_blank_start);
1492                                 viafb_load_reg_Num =
1493                                     iga2_shadow_crtc_reg.
1494                                     ver_blank_start_shadow.reg_num;
1495                                 reg =
1496                                     iga2_shadow_crtc_reg.
1497                                     ver_blank_start_shadow.reg;
1498                                 break;
1499                         case V_BLANK_END_SHADOW_INDEX:
1500                                 reg_value =
1501                                     IGA2_VER_BLANK_END_SHADOW_FORMULA
1502                                     (panel_timing.ver_blank_start,
1503                                      panel_timing.ver_blank_end);
1504                                 viafb_load_reg_Num =
1505                                     iga2_shadow_crtc_reg.
1506                                     ver_blank_end_shadow.reg_num;
1507                                 reg =
1508                                     iga2_shadow_crtc_reg.
1509                                     ver_blank_end_shadow.reg;
1510                                 break;
1511                         case V_SYNC_SATRT_SHADOW_INDEX:
1512                                 reg_value =
1513                                     IGA2_VER_SYNC_START_SHADOW_FORMULA
1514                                     (panel_timing.ver_sync_start);
1515                                 viafb_load_reg_Num =
1516                                     iga2_shadow_crtc_reg.
1517                                     ver_sync_start_shadow.reg_num;
1518                                 reg =
1519                                     iga2_shadow_crtc_reg.
1520                                     ver_sync_start_shadow.reg;
1521                                 break;
1522                         case V_SYNC_END_SHADOW_INDEX:
1523                                 reg_value =
1524                                     IGA2_VER_SYNC_END_SHADOW_FORMULA
1525                                     (panel_timing.ver_sync_start,
1526                                      panel_timing.ver_sync_end);
1527                                 viafb_load_reg_Num =
1528                                     iga2_shadow_crtc_reg.
1529                                     ver_sync_end_shadow.reg_num;
1530                                 reg =
1531                                     iga2_shadow_crtc_reg.
1532                                     ver_sync_end_shadow.reg;
1533                                 break;
1534                         }
1535                         viafb_load_reg(reg_value,
1536                                 viafb_load_reg_Num, reg, VIACR);
1537                 }
1538         } else {                /* Centering */
1539                 for (i = 12; i < 20; i++) {
1540                         switch (i) {
1541                         case H_TOTAL_SHADOW_INDEX:
1542                                 reg_value =
1543                                     IGA2_HOR_TOTAL_SHADOW_FORMULA
1544                                     (panel_timing.hor_total);
1545                                 viafb_load_reg_Num =
1546                                     iga2_shadow_crtc_reg.hor_total_shadow.
1547                                     reg_num;
1548                                 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1549                                 break;
1550                         case H_BLANK_END_SHADOW_INDEX:
1551                                 reg_value =
1552                                     IGA2_HOR_BLANK_END_SHADOW_FORMULA
1553                                     (panel_timing.hor_blank_start,
1554                                      panel_timing.hor_blank_end);
1555                                 viafb_load_reg_Num =
1556                                     iga2_shadow_crtc_reg.
1557                                     hor_blank_end_shadow.reg_num;
1558                                 reg =
1559                                     iga2_shadow_crtc_reg.
1560                                     hor_blank_end_shadow.reg;
1561                                 break;
1562                         case V_TOTAL_SHADOW_INDEX:
1563                                 reg_value =
1564                                     IGA2_VER_TOTAL_SHADOW_FORMULA
1565                                     (panel_timing.ver_total);
1566                                 viafb_load_reg_Num =
1567                                     iga2_shadow_crtc_reg.ver_total_shadow.
1568                                     reg_num;
1569                                 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1570                                 break;
1571                         case V_ADDR_SHADOW_INDEX:
1572                                 reg_value =
1573                                     IGA2_VER_ADDR_SHADOW_FORMULA
1574                                     (mode_timing.ver_addr);
1575                                 viafb_load_reg_Num =
1576                                     iga2_shadow_crtc_reg.ver_addr_shadow.
1577                                     reg_num;
1578                                 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1579                                 break;
1580                         case V_BLANK_SATRT_SHADOW_INDEX:
1581                                 reg_value =
1582                                     IGA2_VER_BLANK_START_SHADOW_FORMULA
1583                                     (mode_timing.ver_blank_start);
1584                                 viafb_load_reg_Num =
1585                                     iga2_shadow_crtc_reg.
1586                                     ver_blank_start_shadow.reg_num;
1587                                 reg =
1588                                     iga2_shadow_crtc_reg.
1589                                     ver_blank_start_shadow.reg;
1590                                 break;
1591                         case V_BLANK_END_SHADOW_INDEX:
1592                                 reg_value =
1593                                     IGA2_VER_BLANK_END_SHADOW_FORMULA
1594                                     (panel_timing.ver_blank_start,
1595                                      panel_timing.ver_blank_end);
1596                                 viafb_load_reg_Num =
1597                                     iga2_shadow_crtc_reg.
1598                                     ver_blank_end_shadow.reg_num;
1599                                 reg =
1600                                     iga2_shadow_crtc_reg.
1601                                     ver_blank_end_shadow.reg;
1602                                 break;
1603                         case V_SYNC_SATRT_SHADOW_INDEX:
1604                                 reg_value =
1605                                     IGA2_VER_SYNC_START_SHADOW_FORMULA(
1606                                     (panel_timing.ver_sync_start -
1607                                     panel_timing.ver_blank_start) +
1608                                     (panel_timing.ver_addr -
1609                                     mode_timing.ver_addr) / 2 +
1610                                     mode_timing.ver_addr);
1611                                 viafb_load_reg_Num =
1612                                     iga2_shadow_crtc_reg.ver_sync_start_shadow.
1613                                     reg_num;
1614                                 reg =
1615                                     iga2_shadow_crtc_reg.ver_sync_start_shadow.
1616                                     reg;
1617                                 break;
1618                         case V_SYNC_END_SHADOW_INDEX:
1619                                 reg_value =
1620                                     IGA2_VER_SYNC_END_SHADOW_FORMULA(
1621                                     (panel_timing.ver_sync_start -
1622                                     panel_timing.ver_blank_start) +
1623                                     (panel_timing.ver_addr -
1624                                     mode_timing.ver_addr) / 2 +
1625                                     mode_timing.ver_addr,
1626                                     panel_timing.ver_sync_end);
1627                                 viafb_load_reg_Num =
1628                                     iga2_shadow_crtc_reg.ver_sync_end_shadow.
1629                                     reg_num;
1630                                 reg =
1631                                     iga2_shadow_crtc_reg.ver_sync_end_shadow.
1632                                     reg;
1633                                 break;
1634                         }
1635                         viafb_load_reg(reg_value,
1636                                 viafb_load_reg_Num, reg, VIACR);
1637                 }
1638         }
1639 }
1640
1641 bool viafb_lcd_get_mobile_state(bool *mobile)
1642 {
1643         unsigned char *romptr, *tableptr;
1644         u8 core_base;
1645         unsigned char *biosptr;
1646         /* Rom address */
1647         u32 romaddr = 0x000C0000;
1648         u16 start_pattern = 0;
1649
1650         biosptr = ioremap(romaddr, 0x10000);
1651
1652         memcpy(&start_pattern, biosptr, 2);
1653         /* Compare pattern */
1654         if (start_pattern == 0xAA55) {
1655                 /* Get the start of Table */
1656                 /* 0x1B means BIOS offset position */
1657                 romptr = biosptr + 0x1B;
1658                 tableptr = biosptr + *((u16 *) romptr);
1659
1660                 /* Get the start of biosver structure */
1661                 /* 18 means BIOS version position. */
1662                 romptr = tableptr + 18;
1663                 romptr = biosptr + *((u16 *) romptr);
1664
1665                 /* The offset should be 44, but the
1666                    actual image is less three char. */
1667                 /* pRom += 44; */
1668                 romptr += 41;
1669
1670                 core_base = *romptr++;
1671
1672                 if (core_base & 0x8)
1673                         *mobile = false;
1674                 else
1675                         *mobile = true;
1676                 /* release memory */
1677                 iounmap(biosptr);
1678
1679                 return true;
1680         } else {
1681                 iounmap(biosptr);
1682                 return false;
1683         }
1684 }
1685
1686 static void viafb_load_scaling_factor_for_p4m900(int set_hres,
1687         int set_vres, int panel_hres, int panel_vres)
1688 {
1689         int h_scaling_factor;
1690         int v_scaling_factor;
1691         u8 cra2 = 0;
1692         u8 cr77 = 0;
1693         u8 cr78 = 0;
1694         u8 cr79 = 0;
1695         u8 cr9f = 0;
1696         /* Check if expansion for horizontal */
1697         if (set_hres < panel_hres) {
1698                 /* Load Horizontal Scaling Factor */
1699
1700                 /* For VIA_K8M800 or later chipsets. */
1701                 h_scaling_factor =
1702                     K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
1703                 /* HSCaleFactor[1:0] at CR9F[1:0] */
1704                 cr9f = h_scaling_factor & 0x0003;
1705                 /* HSCaleFactor[9:2] at CR77[7:0] */
1706                 cr77 = (h_scaling_factor & 0x03FC) >> 2;
1707                 /* HSCaleFactor[11:10] at CR79[5:4] */
1708                 cr79 = (h_scaling_factor & 0x0C00) >> 10;
1709                 cr79 <<= 4;
1710
1711                 /* Horizontal scaling enabled */
1712                 cra2 = 0xC0;
1713
1714                 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d\n",
1715                           h_scaling_factor);
1716         } else {
1717                 /* Horizontal scaling disabled */
1718                 cra2 = 0x00;
1719         }
1720
1721         /* Check if expansion for vertical */
1722         if (set_vres < panel_vres) {
1723                 /* Load Vertical Scaling Factor */
1724
1725                 /* For VIA_K8M800 or later chipsets. */
1726                 v_scaling_factor =
1727                     K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
1728
1729                 /* Vertical scaling enabled */
1730                 cra2 |= 0x08;
1731                 /* VSCaleFactor[0] at CR79[3] */
1732                 cr79 |= ((v_scaling_factor & 0x0001) << 3);
1733                 /* VSCaleFactor[8:1] at CR78[7:0] */
1734                 cr78 |= (v_scaling_factor & 0x01FE) >> 1;
1735                 /* VSCaleFactor[10:9] at CR79[7:6] */
1736                 cr79 |= ((v_scaling_factor & 0x0600) >> 9) << 6;
1737
1738                 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d\n",
1739                           v_scaling_factor);
1740         } else {
1741                 /* Vertical scaling disabled */
1742                 cra2 |= 0x00;
1743         }
1744
1745         viafb_write_reg_mask(CRA2, VIACR, cra2, BIT3 + BIT6 + BIT7);
1746         viafb_write_reg_mask(CR77, VIACR, cr77, 0xFF);
1747         viafb_write_reg_mask(CR78, VIACR, cr78, 0xFF);
1748         viafb_write_reg_mask(CR79, VIACR, cr79, 0xF8);
1749         viafb_write_reg_mask(CR9F, VIACR, cr9f, BIT0 + BIT1);
1750 }