2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 static const struct pci_device_id_info pciidlist[] = {
25 {PCI_VIA_VENDOR_ID, UNICHROME_CLE266_DID, UNICHROME_CLE266},
26 {PCI_VIA_VENDOR_ID, UNICHROME_PM800_DID, UNICHROME_PM800},
27 {PCI_VIA_VENDOR_ID, UNICHROME_K400_DID, UNICHROME_K400},
28 {PCI_VIA_VENDOR_ID, UNICHROME_K800_DID, UNICHROME_K800},
29 {PCI_VIA_VENDOR_ID, UNICHROME_CN700_DID, UNICHROME_CN700},
30 {PCI_VIA_VENDOR_ID, UNICHROME_P4M890_DID, UNICHROME_P4M890},
31 {PCI_VIA_VENDOR_ID, UNICHROME_K8M890_DID, UNICHROME_K8M890},
32 {PCI_VIA_VENDOR_ID, UNICHROME_CX700_DID, UNICHROME_CX700},
33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
39 struct offset offset_reg = {
40 /* IGA1 Offset Register */
41 {IGA1_OFFSET_REG_NUM, {{CR13, 0, 7}, {CR35, 5, 7} } },
42 /* IGA2 Offset Register */
43 {IGA2_OFFSET_REG_NUM, {{CR66, 0, 7}, {CR67, 0, 1} } }
46 static struct pll_map pll_value[] = {
47 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
48 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
49 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
50 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
51 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
52 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
53 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
54 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
55 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
56 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
57 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
58 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
59 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
60 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
61 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
62 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
63 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
64 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
65 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
66 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
67 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
68 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
69 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
70 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
71 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
72 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
73 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
74 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
75 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
76 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
77 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
78 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
79 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
80 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
81 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
82 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
83 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
84 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
85 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
87 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
89 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
91 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
93 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
95 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
97 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
99 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
101 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
103 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
105 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
107 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
109 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
111 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
113 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
115 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
117 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
119 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
121 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
123 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
125 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
127 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
129 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
131 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
133 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
135 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
136 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
138 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
140 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
141 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
145 static struct fifo_depth_select display_fifo_depth_reg = {
146 /* IGA1 FIFO Depth_Select */
147 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
148 /* IGA2 FIFO Depth_Select */
149 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
150 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
153 static struct fifo_threshold_select fifo_threshold_select_reg = {
154 /* IGA1 FIFO Threshold Select */
155 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
156 /* IGA2 FIFO Threshold Select */
157 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
160 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
161 /* IGA1 FIFO High Threshold Select */
162 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
163 /* IGA2 FIFO High Threshold Select */
164 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
167 static struct display_queue_expire_num display_queue_expire_num_reg = {
168 /* IGA1 Display Queue Expire Num */
169 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
170 /* IGA2 Display Queue Expire Num */
171 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
174 /* Definition Fetch Count Registers*/
175 static struct fetch_count fetch_count_reg = {
176 /* IGA1 Fetch Count Register */
177 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
178 /* IGA2 Fetch Count Register */
179 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
182 static struct iga1_crtc_timing iga1_crtc_reg = {
183 /* IGA1 Horizontal Total */
184 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
185 /* IGA1 Horizontal Addressable Video */
186 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
187 /* IGA1 Horizontal Blank Start */
188 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
189 /* IGA1 Horizontal Blank End */
190 {IGA1_HOR_BLANK_END_REG_NUM,
191 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
192 /* IGA1 Horizontal Sync Start */
193 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
194 /* IGA1 Horizontal Sync End */
195 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
196 /* IGA1 Vertical Total */
197 {IGA1_VER_TOTAL_REG_NUM,
198 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
199 /* IGA1 Vertical Addressable Video */
200 {IGA1_VER_ADDR_REG_NUM,
201 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
202 /* IGA1 Vertical Blank Start */
203 {IGA1_VER_BLANK_START_REG_NUM,
204 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
205 /* IGA1 Vertical Blank End */
206 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
207 /* IGA1 Vertical Sync Start */
208 {IGA1_VER_SYNC_START_REG_NUM,
209 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
210 /* IGA1 Vertical Sync End */
211 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
214 static struct iga2_crtc_timing iga2_crtc_reg = {
215 /* IGA2 Horizontal Total */
216 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
217 /* IGA2 Horizontal Addressable Video */
218 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
219 /* IGA2 Horizontal Blank Start */
220 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
221 /* IGA2 Horizontal Blank End */
222 {IGA2_HOR_BLANK_END_REG_NUM,
223 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
224 /* IGA2 Horizontal Sync Start */
225 {IGA2_HOR_SYNC_START_REG_NUM,
226 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
227 /* IGA2 Horizontal Sync End */
228 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
229 /* IGA2 Vertical Total */
230 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
231 /* IGA2 Vertical Addressable Video */
232 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
233 /* IGA2 Vertical Blank Start */
234 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
235 /* IGA2 Vertical Blank End */
236 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
237 /* IGA2 Vertical Sync Start */
238 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
239 /* IGA2 Vertical Sync End */
240 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
243 static struct rgbLUT palLUT_table[] = {
245 /* Index 0x00~0x03 */
246 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
249 /* Index 0x04~0x07 */
250 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
253 /* Index 0x08~0x0B */
254 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
257 /* Index 0x0C~0x0F */
258 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
261 /* Index 0x10~0x13 */
262 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
265 /* Index 0x14~0x17 */
266 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
269 /* Index 0x18~0x1B */
270 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
273 /* Index 0x1C~0x1F */
274 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
277 /* Index 0x20~0x23 */
278 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
281 /* Index 0x24~0x27 */
282 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
285 /* Index 0x28~0x2B */
286 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
289 /* Index 0x2C~0x2F */
290 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
293 /* Index 0x30~0x33 */
294 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
297 /* Index 0x34~0x37 */
298 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
301 /* Index 0x38~0x3B */
302 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
305 /* Index 0x3C~0x3F */
306 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
309 /* Index 0x40~0x43 */
310 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
313 /* Index 0x44~0x47 */
314 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
317 /* Index 0x48~0x4B */
318 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
321 /* Index 0x4C~0x4F */
322 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
325 /* Index 0x50~0x53 */
326 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
329 /* Index 0x54~0x57 */
330 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
333 /* Index 0x58~0x5B */
334 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
337 /* Index 0x5C~0x5F */
338 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
341 /* Index 0x60~0x63 */
342 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
345 /* Index 0x64~0x67 */
346 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
349 /* Index 0x68~0x6B */
350 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
353 /* Index 0x6C~0x6F */
354 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
357 /* Index 0x70~0x73 */
358 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
361 /* Index 0x74~0x77 */
362 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
365 /* Index 0x78~0x7B */
366 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
369 /* Index 0x7C~0x7F */
370 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
373 /* Index 0x80~0x83 */
374 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
377 /* Index 0x84~0x87 */
378 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
381 /* Index 0x88~0x8B */
382 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
385 /* Index 0x8C~0x8F */
386 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
389 /* Index 0x90~0x93 */
390 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
393 /* Index 0x94~0x97 */
394 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
397 /* Index 0x98~0x9B */
398 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
401 /* Index 0x9C~0x9F */
402 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
405 /* Index 0xA0~0xA3 */
406 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
409 /* Index 0xA4~0xA7 */
410 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
413 /* Index 0xA8~0xAB */
414 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
417 /* Index 0xAC~0xAF */
418 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
421 /* Index 0xB0~0xB3 */
422 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
425 /* Index 0xB4~0xB7 */
426 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
429 /* Index 0xB8~0xBB */
430 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
433 /* Index 0xBC~0xBF */
434 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
437 /* Index 0xC0~0xC3 */
438 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
441 /* Index 0xC4~0xC7 */
442 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
445 /* Index 0xC8~0xCB */
446 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
449 /* Index 0xCC~0xCF */
450 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
453 /* Index 0xD0~0xD3 */
454 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
457 /* Index 0xD4~0xD7 */
458 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
461 /* Index 0xD8~0xDB */
462 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
465 /* Index 0xDC~0xDF */
466 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
469 /* Index 0xE0~0xE3 */
470 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
473 /* Index 0xE4~0xE7 */
474 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
477 /* Index 0xE8~0xEB */
478 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
481 /* Index 0xEC~0xEF */
482 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
485 /* Index 0xF0~0xF3 */
486 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
489 /* Index 0xF4~0xF7 */
490 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
493 /* Index 0xF8~0xFB */
494 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
497 /* Index 0xFC~0xFF */
498 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
503 static void set_crt_output_path(int set_iga);
504 static void dvi_patch_skew_dvp0(void);
505 static void dvi_patch_skew_dvp1(void);
506 static void dvi_patch_skew_dvp_low(void);
507 static void set_dvi_output_path(int set_iga, int output_interface);
508 static void set_lcd_output_path(int set_iga, int output_interface);
509 static int search_mode_setting(int ModeInfoIndex);
510 static void load_fix_bit_crtc_reg(void);
511 static void init_gfx_chip_info(void);
512 static void init_tmds_chip_info(void);
513 static void init_lvds_chip_info(void);
514 static void device_screen_off(void);
515 static void device_screen_on(void);
516 static void set_display_channel(void);
517 static void device_off(void);
518 static void device_on(void);
519 static void enable_second_display_channel(void);
520 static void disable_second_display_channel(void);
521 static int get_fb_size_from_pci(void);
523 void viafb_write_reg(u8 index, u16 io_port, u8 data)
525 outb(index, io_port);
526 outb(data, io_port + 1);
527 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
529 u8 viafb_read_reg(int io_port, u8 index)
531 outb(index, io_port);
532 return inb(io_port + 1);
535 void viafb_lock_crt(void)
537 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
540 void viafb_unlock_crt(void)
542 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
543 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
546 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
550 outb(index, io_port);
551 tmp = inb(io_port + 1);
552 outb((data & mask) | (tmp & (~mask)), io_port + 1);
553 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
556 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
558 outb(index, LUT_INDEX_WRITE);
564 /*Set IGA path for each device*/
565 void viafb_set_iga_path(void)
568 if (viafb_SAMM_ON == 1) {
570 if (viafb_primary_dev == CRT_Device)
571 viaparinfo->crt_setting_info->iga_path = IGA1;
573 viaparinfo->crt_setting_info->iga_path = IGA2;
577 if (viafb_primary_dev == DVI_Device)
578 viaparinfo->tmds_setting_info->iga_path = IGA1;
580 viaparinfo->tmds_setting_info->iga_path = IGA2;
584 if (viafb_primary_dev == LCD_Device) {
586 (viaparinfo->chip_info->gfx_chip_name ==
589 lvds_setting_info->iga_path = IGA2;
591 crt_setting_info->iga_path = IGA1;
593 tmds_setting_info->iga_path = IGA1;
596 lvds_setting_info->iga_path = IGA1;
598 viaparinfo->lvds_setting_info->iga_path = IGA2;
602 if (LCD2_Device == viafb_primary_dev)
603 viaparinfo->lvds_setting_info2->iga_path = IGA1;
605 viaparinfo->lvds_setting_info2->iga_path = IGA2;
610 if (viafb_CRT_ON && viafb_LCD_ON) {
611 viaparinfo->crt_setting_info->iga_path = IGA1;
612 viaparinfo->lvds_setting_info->iga_path = IGA2;
613 } else if (viafb_CRT_ON && viafb_DVI_ON) {
614 viaparinfo->crt_setting_info->iga_path = IGA1;
615 viaparinfo->tmds_setting_info->iga_path = IGA2;
616 } else if (viafb_LCD_ON && viafb_DVI_ON) {
617 viaparinfo->tmds_setting_info->iga_path = IGA1;
618 viaparinfo->lvds_setting_info->iga_path = IGA2;
619 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
620 viaparinfo->lvds_setting_info->iga_path = IGA2;
621 viaparinfo->lvds_setting_info2->iga_path = IGA2;
622 } else if (viafb_CRT_ON) {
623 viaparinfo->crt_setting_info->iga_path = IGA1;
624 } else if (viafb_LCD_ON) {
625 viaparinfo->lvds_setting_info->iga_path = IGA2;
626 } else if (viafb_DVI_ON) {
627 viaparinfo->tmds_setting_info->iga_path = IGA1;
632 void viafb_set_primary_address(u32 addr)
634 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
635 viafb_write_reg(CR0D, VIACR, addr & 0xFF);
636 viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
637 viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
638 viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
641 void viafb_set_secondary_address(u32 addr)
643 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
644 /* secondary display supports only quadword aligned memory */
645 viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
646 viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
647 viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
648 viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
651 void viafb_set_output_path(int device, int set_iga, int output_interface)
655 set_crt_output_path(set_iga);
658 set_dvi_output_path(set_iga, output_interface);
661 set_lcd_output_path(set_iga, output_interface);
666 static void set_crt_output_path(int set_iga)
668 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
672 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
676 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
677 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
678 if (set_iga == IGA1_IGA2)
679 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
684 static void dvi_patch_skew_dvp0(void)
686 /* Reset data driving first: */
687 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
688 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
690 switch (viaparinfo->chip_info->gfx_chip_name) {
691 case UNICHROME_P4M890:
693 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
694 (viaparinfo->tmds_setting_info->v_active ==
696 viafb_write_reg_mask(CR96, VIACR, 0x03,
699 viafb_write_reg_mask(CR96, VIACR, 0x07,
704 case UNICHROME_P4M900:
706 viafb_write_reg_mask(CR96, VIACR, 0x07,
707 BIT0 + BIT1 + BIT2 + BIT3);
708 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
709 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
720 static void dvi_patch_skew_dvp1(void)
722 switch (viaparinfo->chip_info->gfx_chip_name) {
723 case UNICHROME_CX700:
735 static void dvi_patch_skew_dvp_low(void)
737 switch (viaparinfo->chip_info->gfx_chip_name) {
738 case UNICHROME_K8M890:
740 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
744 case UNICHROME_P4M900:
746 viafb_write_reg_mask(CR99, VIACR, 0x08,
747 BIT0 + BIT1 + BIT2 + BIT3);
751 case UNICHROME_P4M890:
753 viafb_write_reg_mask(CR99, VIACR, 0x0F,
754 BIT0 + BIT1 + BIT2 + BIT3);
765 static void set_dvi_output_path(int set_iga, int output_interface)
767 switch (output_interface) {
769 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
771 if (set_iga == IGA1) {
772 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
773 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
776 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
777 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
781 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
783 dvi_patch_skew_dvp0();
787 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
789 viafb_write_reg_mask(CR93, VIACR, 0x21,
792 viafb_write_reg_mask(CR93, VIACR, 0xA1,
796 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
798 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
801 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
802 dvi_patch_skew_dvp1();
804 case INTERFACE_DFP_HIGH:
805 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
806 if (set_iga == IGA1) {
807 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
808 viafb_write_reg_mask(CR97, VIACR, 0x03,
811 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
812 viafb_write_reg_mask(CR97, VIACR, 0x13,
816 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
819 case INTERFACE_DFP_LOW:
820 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
823 if (set_iga == IGA1) {
824 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
825 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
827 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
828 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
831 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
832 dvi_patch_skew_dvp_low();
837 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
839 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
843 if (set_iga == IGA2) {
844 enable_second_display_channel();
845 /* Disable LCD Scaling */
846 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
850 static void set_lcd_output_path(int set_iga, int output_interface)
853 "set_lcd_output_path, iga:%d,out_interface:%d\n",
854 set_iga, output_interface);
857 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
858 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
860 disable_second_display_channel();
864 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
865 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
867 enable_second_display_channel();
871 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
872 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
874 disable_second_display_channel();
878 switch (output_interface) {
880 if (set_iga == IGA1) {
881 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
883 viafb_write_reg(CR91, VIACR, 0x00);
884 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
890 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
892 viafb_write_reg(CR91, VIACR, 0x00);
893 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
897 case INTERFACE_DFP_HIGH:
899 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
901 viafb_write_reg(CR91, VIACR, 0x00);
902 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
903 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
907 case INTERFACE_DFP_LOW:
909 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
911 viafb_write_reg(CR91, VIACR, 0x00);
912 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
913 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
919 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
920 || (UNICHROME_P4M890 ==
921 viaparinfo->chip_info->gfx_chip_name))
922 viafb_write_reg_mask(CR97, VIACR, 0x84,
923 BIT7 + BIT2 + BIT1 + BIT0);
924 if (set_iga == IGA1) {
925 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
926 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
928 viafb_write_reg(CR91, VIACR, 0x00);
929 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
930 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
934 case INTERFACE_LVDS0:
935 case INTERFACE_LVDS0LVDS1:
937 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
939 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
943 case INTERFACE_LVDS1:
945 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
947 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
952 /* Search Mode Index */
953 static int search_mode_setting(int ModeInfoIndex)
957 while ((i < NUM_TOTAL_MODETABLE) &&
958 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
960 if (i >= NUM_TOTAL_MODETABLE)
966 struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
968 struct VideoModeTable *TmpTbl = NULL;
969 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
973 struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
975 struct VideoModeTable *TmpTbl = NULL;
977 while ((i < NUM_TOTAL_CEA_MODES) &&
978 (Index != CEA_HDMI_Modes[i].ModeIndex))
980 if ((i < NUM_TOTAL_CEA_MODES))
981 TmpTbl = &CEA_HDMI_Modes[i];
983 /*Still use general timing if don't find CEA timing */
985 while ((i < NUM_TOTAL_MODETABLE) &&
986 (Index != CLE266Modes[i].ModeIndex))
988 if (i >= NUM_TOTAL_MODETABLE)
990 TmpTbl = &CLE266Modes[i];
995 static void load_fix_bit_crtc_reg(void)
997 /* always set to 1 */
998 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
999 /* line compare should set all bits = 1 (extend modes) */
1000 viafb_write_reg(CR18, VIACR, 0xff);
1001 /* line compare should set all bits = 1 (extend modes) */
1002 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1003 /* line compare should set all bits = 1 (extend modes) */
1004 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1005 /* line compare should set all bits = 1 (extend modes) */
1006 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1007 /* line compare should set all bits = 1 (extend modes) */
1008 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1009 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1010 /* extend mode always set to e3h */
1011 viafb_write_reg(CR17, VIACR, 0xe3);
1012 /* extend mode always set to 0h */
1013 viafb_write_reg(CR08, VIACR, 0x00);
1014 /* extend mode always set to 0h */
1015 viafb_write_reg(CR14, VIACR, 0x00);
1017 /* If K8M800, enable Prefetch Mode. */
1018 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1019 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1020 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1021 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1022 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1023 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1027 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1028 struct io_register *reg,
1036 int start_index, end_index, cr_index;
1039 for (i = 0; i < viafb_load_reg_num; i++) {
1042 start_index = reg[i].start_bit;
1043 end_index = reg[i].end_bit;
1044 cr_index = reg[i].io_addr;
1046 shift_next_reg = bit_num;
1047 for (j = start_index; j <= end_index; j++) {
1048 /*if (bit_num==8) timing_value = timing_value >>8; */
1049 reg_mask = reg_mask | (BIT0 << j);
1050 get_bit = (timing_value & (BIT0 << bit_num));
1052 data | ((get_bit >> shift_next_reg) << start_index);
1055 if (io_type == VIACR)
1056 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1058 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1063 /* Write Registers */
1064 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1067 unsigned char RegTemp;
1069 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1071 for (i = 0; i < ItemNum; i++) {
1072 outb(RegTable[i].index, RegTable[i].port);
1073 RegTemp = inb(RegTable[i].port + 1);
1074 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1075 outb(RegTemp, RegTable[i].port + 1);
1079 void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
1082 int viafb_load_reg_num;
1083 struct io_register *reg;
1088 reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
1089 viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
1090 reg = offset_reg.iga1_offset_reg.reg;
1091 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1092 if (set_iga == IGA1)
1095 reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
1096 viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
1097 reg = offset_reg.iga2_offset_reg.reg;
1098 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1103 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1106 int viafb_load_reg_num;
1107 struct io_register *reg = NULL;
1112 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1113 viafb_load_reg_num = fetch_count_reg.
1114 iga1_fetch_count_reg.reg_num;
1115 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1116 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1117 if (set_iga == IGA1)
1120 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1121 viafb_load_reg_num = fetch_count_reg.
1122 iga2_fetch_count_reg.reg_num;
1123 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1124 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1130 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1133 int viafb_load_reg_num;
1134 struct io_register *reg = NULL;
1135 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1136 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1137 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1138 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1140 if (set_iga == IGA1) {
1141 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1142 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1143 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1144 iga1_fifo_high_threshold =
1145 K800_IGA1_FIFO_HIGH_THRESHOLD;
1146 /* If resolution > 1280x1024, expire length = 64, else
1147 expire length = 128 */
1148 if ((hor_active > 1280) && (ver_active > 1024))
1149 iga1_display_queue_expire_num = 16;
1151 iga1_display_queue_expire_num =
1152 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1156 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1157 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1158 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1159 iga1_fifo_high_threshold =
1160 P880_IGA1_FIFO_HIGH_THRESHOLD;
1161 iga1_display_queue_expire_num =
1162 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1164 /* If resolution > 1280x1024, expire length = 64, else
1165 expire length = 128 */
1166 if ((hor_active > 1280) && (ver_active > 1024))
1167 iga1_display_queue_expire_num = 16;
1169 iga1_display_queue_expire_num =
1170 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1173 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1174 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1175 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1176 iga1_fifo_high_threshold =
1177 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1179 /* If resolution > 1280x1024, expire length = 64,
1180 else expire length = 128 */
1181 if ((hor_active > 1280) && (ver_active > 1024))
1182 iga1_display_queue_expire_num = 16;
1184 iga1_display_queue_expire_num =
1185 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1188 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1189 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1190 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1191 iga1_fifo_high_threshold =
1192 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1193 iga1_display_queue_expire_num =
1194 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1197 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1198 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1199 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1200 iga1_fifo_high_threshold =
1201 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1202 iga1_display_queue_expire_num =
1203 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1206 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1207 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1208 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1209 iga1_fifo_high_threshold =
1210 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1211 iga1_display_queue_expire_num =
1212 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1215 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1216 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1217 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1218 iga1_fifo_high_threshold =
1219 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1220 iga1_display_queue_expire_num =
1221 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1224 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1225 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1226 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1227 iga1_fifo_high_threshold =
1228 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1229 iga1_display_queue_expire_num =
1230 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1233 /* Set Display FIFO Depath Select */
1234 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1235 viafb_load_reg_num =
1236 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1237 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1238 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1240 /* Set Display FIFO Threshold Select */
1241 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1242 viafb_load_reg_num =
1243 fifo_threshold_select_reg.
1244 iga1_fifo_threshold_select_reg.reg_num;
1246 fifo_threshold_select_reg.
1247 iga1_fifo_threshold_select_reg.reg;
1248 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1250 /* Set FIFO High Threshold Select */
1252 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1253 viafb_load_reg_num =
1254 fifo_high_threshold_select_reg.
1255 iga1_fifo_high_threshold_select_reg.reg_num;
1257 fifo_high_threshold_select_reg.
1258 iga1_fifo_high_threshold_select_reg.reg;
1259 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1261 /* Set Display Queue Expire Num */
1263 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1264 (iga1_display_queue_expire_num);
1265 viafb_load_reg_num =
1266 display_queue_expire_num_reg.
1267 iga1_display_queue_expire_num_reg.reg_num;
1269 display_queue_expire_num_reg.
1270 iga1_display_queue_expire_num_reg.reg;
1271 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1274 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1275 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1276 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1277 iga2_fifo_high_threshold =
1278 K800_IGA2_FIFO_HIGH_THRESHOLD;
1280 /* If resolution > 1280x1024, expire length = 64,
1281 else expire length = 128 */
1282 if ((hor_active > 1280) && (ver_active > 1024))
1283 iga2_display_queue_expire_num = 16;
1285 iga2_display_queue_expire_num =
1286 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1289 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1290 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1291 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1292 iga2_fifo_high_threshold =
1293 P880_IGA2_FIFO_HIGH_THRESHOLD;
1295 /* If resolution > 1280x1024, expire length = 64,
1296 else expire length = 128 */
1297 if ((hor_active > 1280) && (ver_active > 1024))
1298 iga2_display_queue_expire_num = 16;
1300 iga2_display_queue_expire_num =
1301 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1304 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1305 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1306 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1307 iga2_fifo_high_threshold =
1308 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1310 /* If resolution > 1280x1024, expire length = 64,
1311 else expire length = 128 */
1312 if ((hor_active > 1280) && (ver_active > 1024))
1313 iga2_display_queue_expire_num = 16;
1315 iga2_display_queue_expire_num =
1316 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1319 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1320 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1321 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1322 iga2_fifo_high_threshold =
1323 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1324 iga2_display_queue_expire_num =
1325 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1328 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1329 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1330 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1331 iga2_fifo_high_threshold =
1332 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1333 iga2_display_queue_expire_num =
1334 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1337 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1338 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1339 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1340 iga2_fifo_high_threshold =
1341 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1342 iga2_display_queue_expire_num =
1343 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1346 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1347 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1348 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1349 iga2_fifo_high_threshold =
1350 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1351 iga2_display_queue_expire_num =
1352 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1355 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1356 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1357 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1358 iga2_fifo_high_threshold =
1359 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1360 iga2_display_queue_expire_num =
1361 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1364 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1365 /* Set Display FIFO Depath Select */
1367 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1369 /* Patch LCD in IGA2 case */
1370 viafb_load_reg_num =
1371 display_fifo_depth_reg.
1372 iga2_fifo_depth_select_reg.reg_num;
1374 display_fifo_depth_reg.
1375 iga2_fifo_depth_select_reg.reg;
1376 viafb_load_reg(reg_value,
1377 viafb_load_reg_num, reg, VIACR);
1380 /* Set Display FIFO Depath Select */
1382 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1383 viafb_load_reg_num =
1384 display_fifo_depth_reg.
1385 iga2_fifo_depth_select_reg.reg_num;
1387 display_fifo_depth_reg.
1388 iga2_fifo_depth_select_reg.reg;
1389 viafb_load_reg(reg_value,
1390 viafb_load_reg_num, reg, VIACR);
1393 /* Set Display FIFO Threshold Select */
1394 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1395 viafb_load_reg_num =
1396 fifo_threshold_select_reg.
1397 iga2_fifo_threshold_select_reg.reg_num;
1399 fifo_threshold_select_reg.
1400 iga2_fifo_threshold_select_reg.reg;
1401 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1403 /* Set FIFO High Threshold Select */
1405 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1406 viafb_load_reg_num =
1407 fifo_high_threshold_select_reg.
1408 iga2_fifo_high_threshold_select_reg.reg_num;
1410 fifo_high_threshold_select_reg.
1411 iga2_fifo_high_threshold_select_reg.reg;
1412 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1414 /* Set Display Queue Expire Num */
1416 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1417 (iga2_display_queue_expire_num);
1418 viafb_load_reg_num =
1419 display_queue_expire_num_reg.
1420 iga2_display_queue_expire_num_reg.reg_num;
1422 display_queue_expire_num_reg.
1423 iga2_display_queue_expire_num_reg.reg;
1424 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1430 u32 viafb_get_clk_value(int clk)
1434 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1435 if (clk == pll_value[i].clk) {
1436 switch (viaparinfo->chip_info->gfx_chip_name) {
1437 case UNICHROME_CLE266:
1438 case UNICHROME_K400:
1439 return pll_value[i].cle266_pll;
1441 case UNICHROME_K800:
1442 case UNICHROME_PM800:
1443 case UNICHROME_CN700:
1444 return pll_value[i].k800_pll;
1446 case UNICHROME_CX700:
1447 case UNICHROME_K8M890:
1448 case UNICHROME_P4M890:
1449 case UNICHROME_P4M900:
1450 case UNICHROME_VX800:
1451 return pll_value[i].cx700_pll;
1456 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1461 void viafb_set_vclock(u32 CLK, int set_iga)
1463 unsigned char RegTemp;
1465 /* H.W. Reset : ON */
1466 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1468 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1469 /* Change D,N FOR VCLK */
1470 switch (viaparinfo->chip_info->gfx_chip_name) {
1471 case UNICHROME_CLE266:
1472 case UNICHROME_K400:
1473 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1474 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1477 case UNICHROME_K800:
1478 case UNICHROME_PM800:
1479 case UNICHROME_CN700:
1480 case UNICHROME_CX700:
1481 case UNICHROME_K8M890:
1482 case UNICHROME_P4M890:
1483 case UNICHROME_P4M900:
1484 case UNICHROME_VX800:
1485 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1486 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1487 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1488 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1489 (CLK & 0xFFFF) / 0x100);
1490 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1491 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1496 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1497 /* Change D,N FOR LCK */
1498 switch (viaparinfo->chip_info->gfx_chip_name) {
1499 case UNICHROME_CLE266:
1500 case UNICHROME_K400:
1501 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1502 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1505 case UNICHROME_K800:
1506 case UNICHROME_PM800:
1507 case UNICHROME_CN700:
1508 case UNICHROME_CX700:
1509 case UNICHROME_K8M890:
1510 case UNICHROME_P4M890:
1511 case UNICHROME_P4M900:
1512 case UNICHROME_VX800:
1513 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1514 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1515 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1520 /* H.W. Reset : OFF */
1521 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1524 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1525 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1526 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1529 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1530 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1531 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1535 RegTemp = inb(VIARMisc);
1536 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1539 void viafb_load_crtc_timing(struct display_timing device_timing,
1543 int viafb_load_reg_num = 0;
1545 struct io_register *reg = NULL;
1549 for (i = 0; i < 12; i++) {
1550 if (set_iga == IGA1) {
1554 IGA1_HOR_TOTAL_FORMULA(device_timing.
1556 viafb_load_reg_num =
1557 iga1_crtc_reg.hor_total.reg_num;
1558 reg = iga1_crtc_reg.hor_total.reg;
1562 IGA1_HOR_ADDR_FORMULA(device_timing.
1564 viafb_load_reg_num =
1565 iga1_crtc_reg.hor_addr.reg_num;
1566 reg = iga1_crtc_reg.hor_addr.reg;
1568 case H_BLANK_START_INDEX:
1570 IGA1_HOR_BLANK_START_FORMULA
1571 (device_timing.hor_blank_start);
1572 viafb_load_reg_num =
1573 iga1_crtc_reg.hor_blank_start.reg_num;
1574 reg = iga1_crtc_reg.hor_blank_start.reg;
1576 case H_BLANK_END_INDEX:
1578 IGA1_HOR_BLANK_END_FORMULA
1579 (device_timing.hor_blank_start,
1580 device_timing.hor_blank_end);
1581 viafb_load_reg_num =
1582 iga1_crtc_reg.hor_blank_end.reg_num;
1583 reg = iga1_crtc_reg.hor_blank_end.reg;
1585 case H_SYNC_START_INDEX:
1587 IGA1_HOR_SYNC_START_FORMULA
1588 (device_timing.hor_sync_start);
1589 viafb_load_reg_num =
1590 iga1_crtc_reg.hor_sync_start.reg_num;
1591 reg = iga1_crtc_reg.hor_sync_start.reg;
1593 case H_SYNC_END_INDEX:
1595 IGA1_HOR_SYNC_END_FORMULA
1596 (device_timing.hor_sync_start,
1597 device_timing.hor_sync_end);
1598 viafb_load_reg_num =
1599 iga1_crtc_reg.hor_sync_end.reg_num;
1600 reg = iga1_crtc_reg.hor_sync_end.reg;
1604 IGA1_VER_TOTAL_FORMULA(device_timing.
1606 viafb_load_reg_num =
1607 iga1_crtc_reg.ver_total.reg_num;
1608 reg = iga1_crtc_reg.ver_total.reg;
1612 IGA1_VER_ADDR_FORMULA(device_timing.
1614 viafb_load_reg_num =
1615 iga1_crtc_reg.ver_addr.reg_num;
1616 reg = iga1_crtc_reg.ver_addr.reg;
1618 case V_BLANK_START_INDEX:
1620 IGA1_VER_BLANK_START_FORMULA
1621 (device_timing.ver_blank_start);
1622 viafb_load_reg_num =
1623 iga1_crtc_reg.ver_blank_start.reg_num;
1624 reg = iga1_crtc_reg.ver_blank_start.reg;
1626 case V_BLANK_END_INDEX:
1628 IGA1_VER_BLANK_END_FORMULA
1629 (device_timing.ver_blank_start,
1630 device_timing.ver_blank_end);
1631 viafb_load_reg_num =
1632 iga1_crtc_reg.ver_blank_end.reg_num;
1633 reg = iga1_crtc_reg.ver_blank_end.reg;
1635 case V_SYNC_START_INDEX:
1637 IGA1_VER_SYNC_START_FORMULA
1638 (device_timing.ver_sync_start);
1639 viafb_load_reg_num =
1640 iga1_crtc_reg.ver_sync_start.reg_num;
1641 reg = iga1_crtc_reg.ver_sync_start.reg;
1643 case V_SYNC_END_INDEX:
1645 IGA1_VER_SYNC_END_FORMULA
1646 (device_timing.ver_sync_start,
1647 device_timing.ver_sync_end);
1648 viafb_load_reg_num =
1649 iga1_crtc_reg.ver_sync_end.reg_num;
1650 reg = iga1_crtc_reg.ver_sync_end.reg;
1656 if (set_iga == IGA2) {
1660 IGA2_HOR_TOTAL_FORMULA(device_timing.
1662 viafb_load_reg_num =
1663 iga2_crtc_reg.hor_total.reg_num;
1664 reg = iga2_crtc_reg.hor_total.reg;
1668 IGA2_HOR_ADDR_FORMULA(device_timing.
1670 viafb_load_reg_num =
1671 iga2_crtc_reg.hor_addr.reg_num;
1672 reg = iga2_crtc_reg.hor_addr.reg;
1674 case H_BLANK_START_INDEX:
1676 IGA2_HOR_BLANK_START_FORMULA
1677 (device_timing.hor_blank_start);
1678 viafb_load_reg_num =
1679 iga2_crtc_reg.hor_blank_start.reg_num;
1680 reg = iga2_crtc_reg.hor_blank_start.reg;
1682 case H_BLANK_END_INDEX:
1684 IGA2_HOR_BLANK_END_FORMULA
1685 (device_timing.hor_blank_start,
1686 device_timing.hor_blank_end);
1687 viafb_load_reg_num =
1688 iga2_crtc_reg.hor_blank_end.reg_num;
1689 reg = iga2_crtc_reg.hor_blank_end.reg;
1691 case H_SYNC_START_INDEX:
1693 IGA2_HOR_SYNC_START_FORMULA
1694 (device_timing.hor_sync_start);
1695 if (UNICHROME_CN700 <=
1696 viaparinfo->chip_info->gfx_chip_name)
1697 viafb_load_reg_num =
1698 iga2_crtc_reg.hor_sync_start.
1701 viafb_load_reg_num = 3;
1702 reg = iga2_crtc_reg.hor_sync_start.reg;
1704 case H_SYNC_END_INDEX:
1706 IGA2_HOR_SYNC_END_FORMULA
1707 (device_timing.hor_sync_start,
1708 device_timing.hor_sync_end);
1709 viafb_load_reg_num =
1710 iga2_crtc_reg.hor_sync_end.reg_num;
1711 reg = iga2_crtc_reg.hor_sync_end.reg;
1715 IGA2_VER_TOTAL_FORMULA(device_timing.
1717 viafb_load_reg_num =
1718 iga2_crtc_reg.ver_total.reg_num;
1719 reg = iga2_crtc_reg.ver_total.reg;
1723 IGA2_VER_ADDR_FORMULA(device_timing.
1725 viafb_load_reg_num =
1726 iga2_crtc_reg.ver_addr.reg_num;
1727 reg = iga2_crtc_reg.ver_addr.reg;
1729 case V_BLANK_START_INDEX:
1731 IGA2_VER_BLANK_START_FORMULA
1732 (device_timing.ver_blank_start);
1733 viafb_load_reg_num =
1734 iga2_crtc_reg.ver_blank_start.reg_num;
1735 reg = iga2_crtc_reg.ver_blank_start.reg;
1737 case V_BLANK_END_INDEX:
1739 IGA2_VER_BLANK_END_FORMULA
1740 (device_timing.ver_blank_start,
1741 device_timing.ver_blank_end);
1742 viafb_load_reg_num =
1743 iga2_crtc_reg.ver_blank_end.reg_num;
1744 reg = iga2_crtc_reg.ver_blank_end.reg;
1746 case V_SYNC_START_INDEX:
1748 IGA2_VER_SYNC_START_FORMULA
1749 (device_timing.ver_sync_start);
1750 viafb_load_reg_num =
1751 iga2_crtc_reg.ver_sync_start.reg_num;
1752 reg = iga2_crtc_reg.ver_sync_start.reg;
1754 case V_SYNC_END_INDEX:
1756 IGA2_VER_SYNC_END_FORMULA
1757 (device_timing.ver_sync_start,
1758 device_timing.ver_sync_end);
1759 viafb_load_reg_num =
1760 iga2_crtc_reg.ver_sync_end.reg_num;
1761 reg = iga2_crtc_reg.ver_sync_end.reg;
1766 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1772 void viafb_set_color_depth(int bpp_byte, int set_iga)
1774 if (set_iga == IGA1) {
1777 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1780 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1783 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1789 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1792 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1795 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1801 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1802 int mode_index, int bpp_byte, int set_iga)
1804 struct VideoModeTable *video_mode;
1805 struct display_timing crt_reg;
1811 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1813 for (i = 0; i < video_mode->mode_array; i++) {
1816 if (crt_table[i].refresh_rate == viaparinfo->
1817 crt_setting_info->refresh_rate)
1821 crt_reg = crt_table[index].crtc;
1823 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1824 /* So we would delete border. */
1825 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480)
1826 && (viaparinfo->crt_setting_info->refresh_rate == 60)) {
1827 /* The border is 8 pixels. */
1828 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1830 /* Blanking time should add left and right borders. */
1831 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1834 h_addr = crt_reg.hor_addr;
1835 v_addr = crt_reg.ver_addr;
1837 /* update polarity for CRT timing */
1838 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1839 if (crt_table[index].v_sync_polarity == NEGATIVE)
1840 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1841 (BIT6 + BIT7), VIAWMisc);
1843 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1846 if (crt_table[index].v_sync_polarity == NEGATIVE)
1847 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1850 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1853 if (set_iga == IGA1) {
1855 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1856 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1857 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1862 viafb_load_crtc_timing(crt_reg, IGA1);
1865 viafb_load_crtc_timing(crt_reg, IGA2);
1869 load_fix_bit_crtc_reg();
1871 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1872 viafb_load_offset_reg(h_addr, bpp_byte, set_iga);
1873 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1876 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1877 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1878 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1880 /* load SR Register About Memory and Color part */
1881 viafb_set_color_depth(bpp_byte, set_iga);
1883 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1884 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1885 viafb_set_vclock(pll_D_N, set_iga);
1889 void viafb_init_chip_info(void)
1891 init_gfx_chip_info();
1892 init_tmds_chip_info();
1893 init_lvds_chip_info();
1895 viaparinfo->crt_setting_info->iga_path = IGA1;
1896 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1898 /*Set IGA path for each device */
1899 viafb_set_iga_path();
1901 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1902 viaparinfo->lvds_setting_info->get_lcd_size_method =
1903 GET_LCD_SIZE_BY_USER_SETTING;
1904 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1905 viaparinfo->lvds_setting_info2->display_method =
1906 viaparinfo->lvds_setting_info->display_method;
1907 viaparinfo->lvds_setting_info2->lcd_mode =
1908 viaparinfo->lvds_setting_info->lcd_mode;
1911 void viafb_update_device_setting(int hres, int vres,
1912 int bpp, int vmode_refresh, int flag)
1915 viaparinfo->crt_setting_info->h_active = hres;
1916 viaparinfo->crt_setting_info->v_active = vres;
1917 viaparinfo->crt_setting_info->bpp = bpp;
1918 viaparinfo->crt_setting_info->refresh_rate =
1921 viaparinfo->tmds_setting_info->h_active = hres;
1922 viaparinfo->tmds_setting_info->v_active = vres;
1923 viaparinfo->tmds_setting_info->bpp = bpp;
1924 viaparinfo->tmds_setting_info->refresh_rate =
1927 viaparinfo->lvds_setting_info->h_active = hres;
1928 viaparinfo->lvds_setting_info->v_active = vres;
1929 viaparinfo->lvds_setting_info->bpp = bpp;
1930 viaparinfo->lvds_setting_info->refresh_rate =
1932 viaparinfo->lvds_setting_info2->h_active = hres;
1933 viaparinfo->lvds_setting_info2->v_active = vres;
1934 viaparinfo->lvds_setting_info2->bpp = bpp;
1935 viaparinfo->lvds_setting_info2->refresh_rate =
1939 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1940 viaparinfo->tmds_setting_info->h_active = hres;
1941 viaparinfo->tmds_setting_info->v_active = vres;
1942 viaparinfo->tmds_setting_info->bpp = bpp;
1943 viaparinfo->tmds_setting_info->refresh_rate =
1947 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1948 viaparinfo->lvds_setting_info->h_active = hres;
1949 viaparinfo->lvds_setting_info->v_active = vres;
1950 viaparinfo->lvds_setting_info->bpp = bpp;
1951 viaparinfo->lvds_setting_info->refresh_rate =
1954 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1955 viaparinfo->lvds_setting_info2->h_active = hres;
1956 viaparinfo->lvds_setting_info2->v_active = vres;
1957 viaparinfo->lvds_setting_info2->bpp = bpp;
1958 viaparinfo->lvds_setting_info2->refresh_rate =
1964 static void init_gfx_chip_info(void)
1966 struct pci_dev *pdev = NULL;
1970 /* Indentify GFX Chip Name */
1971 for (i = 0; pciidlist[i].vendor != 0; i++) {
1972 pdev = pci_get_device(pciidlist[i].vendor,
1973 pciidlist[i].device, 0);
1978 if (!pciidlist[i].vendor)
1981 viaparinfo->chip_info->gfx_chip_name = pciidlist[i].chip_index;
1983 /* Check revision of CLE266 Chip */
1984 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1985 /* CR4F only define in CLE266.CX chip */
1986 tmp = viafb_read_reg(VIACR, CR4F);
1987 viafb_write_reg(CR4F, VIACR, 0x55);
1988 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1989 viaparinfo->chip_info->gfx_chip_revision =
1992 viaparinfo->chip_info->gfx_chip_revision =
1994 /* restore orignal CR4F value */
1995 viafb_write_reg(CR4F, VIACR, tmp);
1998 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1999 tmp = viafb_read_reg(VIASR, SR43);
2000 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
2002 viaparinfo->chip_info->gfx_chip_revision =
2003 CX700_REVISION_700M2;
2004 } else if (tmp & 0x40) {
2005 viaparinfo->chip_info->gfx_chip_revision =
2006 CX700_REVISION_700M;
2008 viaparinfo->chip_info->gfx_chip_revision =
2016 static void init_tmds_chip_info(void)
2018 viafb_tmds_trasmitter_identify();
2020 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2022 switch (viaparinfo->chip_info->gfx_chip_name) {
2023 case UNICHROME_CX700:
2025 /* we should check support by hardware layout.*/
2026 if ((viafb_display_hardware_layout ==
2028 || (viafb_display_hardware_layout ==
2029 HW_LAYOUT_LCD_DVI)) {
2030 viaparinfo->chip_info->tmds_chip_info.
2031 output_interface = INTERFACE_TMDS;
2033 viaparinfo->chip_info->tmds_chip_info.
2039 case UNICHROME_K8M890:
2040 case UNICHROME_P4M900:
2041 case UNICHROME_P4M890:
2042 /* TMDS on PCIE, we set DFPLOW as default. */
2043 viaparinfo->chip_info->tmds_chip_info.output_interface =
2048 /* set DVP1 default for DVI */
2049 viaparinfo->chip_info->tmds_chip_info
2050 .output_interface = INTERFACE_DVP1;
2055 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2056 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2057 viaparinfo->tmds_setting_info->get_dvi_size_method =
2058 GET_DVI_SIZE_BY_VGA_BIOS;
2059 viafb_init_dvi_size();
2062 static void init_lvds_chip_info(void)
2064 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2065 viaparinfo->lvds_setting_info->get_lcd_size_method =
2066 GET_LCD_SIZE_BY_VGA_BIOS;
2068 viaparinfo->lvds_setting_info->get_lcd_size_method =
2069 GET_LCD_SIZE_BY_USER_SETTING;
2071 viafb_lvds_trasmitter_identify();
2072 viafb_init_lcd_size();
2073 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2074 viaparinfo->lvds_setting_info);
2075 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2076 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2077 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2079 /*If CX700,two singel LCD, we need to reassign
2080 LCD interface to different LVDS port */
2081 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2082 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2083 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2084 lvds_chip_name) && (INTEGRATED_LVDS ==
2085 viaparinfo->chip_info->
2086 lvds_chip_info2.lvds_chip_name)) {
2087 viaparinfo->chip_info->lvds_chip_info.output_interface =
2089 viaparinfo->chip_info->lvds_chip_info2.
2095 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2096 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2097 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2098 viaparinfo->chip_info->lvds_chip_info.output_interface);
2099 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2100 viaparinfo->chip_info->lvds_chip_info.output_interface);
2103 void viafb_init_dac(int set_iga)
2108 if (set_iga == IGA1) {
2109 /* access Primary Display's LUT */
2110 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2112 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2113 for (i = 0; i < 256; i++) {
2114 write_dac_reg(i, palLUT_table[i].red,
2115 palLUT_table[i].green,
2116 palLUT_table[i].blue);
2119 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2121 tmp = viafb_read_reg(VIACR, CR6A);
2122 /* access Secondary Display's LUT */
2123 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2124 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2125 for (i = 0; i < 256; i++) {
2126 write_dac_reg(i, palLUT_table[i].red,
2127 palLUT_table[i].green,
2128 palLUT_table[i].blue);
2130 /* set IGA1 DAC for default */
2131 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2132 viafb_write_reg(CR6A, VIACR, tmp);
2136 static void device_screen_off(void)
2138 /* turn off CRT screen (IGA1) */
2139 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2142 static void device_screen_on(void)
2144 /* turn on CRT screen (IGA1) */
2145 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2148 static void set_display_channel(void)
2150 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2151 is keeped on lvds_setting_info2 */
2152 if (viafb_LCD2_ON &&
2153 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2154 /* For dual channel LCD: */
2155 /* Set to Dual LVDS channel. */
2156 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2157 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2159 /* Set to LVDS1 + TMDS channel. */
2160 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2161 } else if (viafb_DVI_ON) {
2162 /* Set to single TMDS channel. */
2163 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2164 } else if (viafb_LCD_ON) {
2165 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2166 /* For dual channel LCD: */
2167 /* Set to Dual LVDS channel. */
2168 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2170 /* Set to LVDS0 + LVDS1 channel. */
2171 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2176 int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2177 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1)
2181 u8 value, index, mask;
2182 struct VideoModeTable *vmode_tbl;
2183 struct crt_mode_table *crt_timing;
2184 struct VideoModeTable *vmode_tbl1 = NULL;
2185 struct crt_mode_table *crt_timing1 = NULL;
2187 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2189 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2190 vmode_index, hor_res, ver_res, video_bpp);
2192 device_screen_off();
2193 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2194 crt_timing = vmode_tbl->crtc;
2196 if (viafb_SAMM_ON == 1) {
2197 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2198 crt_timing1 = vmode_tbl1->crtc;
2204 /* Write Common Setting for Video Mode */
2205 switch (viaparinfo->chip_info->gfx_chip_name) {
2206 case UNICHROME_CLE266:
2207 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2210 case UNICHROME_K400:
2211 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2214 case UNICHROME_K800:
2215 case UNICHROME_PM800:
2216 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2219 case UNICHROME_CN700:
2220 case UNICHROME_K8M890:
2221 case UNICHROME_P4M890:
2222 case UNICHROME_P4M900:
2223 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2226 case UNICHROME_CX700:
2227 case UNICHROME_VX800:
2228 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2234 /* Fill VPIT Parameters */
2235 /* Write Misc Register */
2236 outb(VPIT.Misc, VIAWMisc);
2238 /* Write Sequencer */
2239 for (i = 1; i <= StdSR; i++) {
2241 outb(VPIT.SR[i - 1], VIASR + 1);
2244 viafb_set_primary_address(0);
2245 viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
2246 viafb_set_iga_path();
2249 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1);
2251 /* Write Graphic Controller */
2252 for (i = 0; i < StdGR; i++) {
2254 outb(VPIT.GR[i], VIAGR + 1);
2257 /* Write Attribute Controller */
2258 for (i = 0; i < StdAR; i++) {
2261 outb(VPIT.AR[i], VIAAR);
2267 /* Update Patch Register */
2269 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2270 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) {
2271 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2272 if (res_patch_table[i].mode_index == vmode_index) {
2274 j < res_patch_table[i].table_length; j++) {
2277 io_reg_table[j].index;
2280 io_reg_table[j].port;
2283 io_reg_table[j].value;
2286 io_reg_table[j].mask;
2287 viafb_write_reg_mask(index, port, value,
2294 if (viafb_SAMM_ON == 1) {
2295 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2296 || (viaparinfo->chip_info->gfx_chip_name ==
2298 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2299 if (res_patch_table[i].mode_index ==
2304 table_length; j++) {
2307 io_reg_table[j].index;
2310 io_reg_table[j].port;
2313 io_reg_table[j].value;
2316 io_reg_table[j].mask;
2317 viafb_write_reg_mask(index,
2325 /* Update Refresh Rate Setting */
2327 /* Clear On Screen */
2331 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2333 viafb_fill_crtc_timing(crt_timing1, vmode_index1,
2335 viaparinfo->crt_setting_info->iga_path);
2337 viafb_fill_crtc_timing(crt_timing, vmode_index,
2339 viaparinfo->crt_setting_info->iga_path);
2342 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2344 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2345 to 8 alignment (1368),there is several pixels (2 pixels)
2346 on right side of screen. */
2349 viafb_write_reg(CR02, VIACR,
2350 viafb_read_reg(VIACR, CR02) - 1);
2356 if (viafb_SAMM_ON &&
2357 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2358 viafb_dvi_set_mode(viafb_get_mode_index
2359 (viaparinfo->tmds_setting_info->h_active,
2360 viaparinfo->tmds_setting_info->
2362 video_bpp1, viaparinfo->
2363 tmds_setting_info->iga_path);
2365 viafb_dvi_set_mode(viafb_get_mode_index
2366 (viaparinfo->tmds_setting_info->h_active,
2368 tmds_setting_info->v_active),
2369 video_bpp, viaparinfo->
2370 tmds_setting_info->iga_path);
2375 if (viafb_SAMM_ON &&
2376 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2377 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2378 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2380 &viaparinfo->chip_info->lvds_chip_info);
2382 /* IGA1 doesn't have LCD scaling, so set it center. */
2383 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2384 viaparinfo->lvds_setting_info->display_method =
2387 viaparinfo->lvds_setting_info->bpp = video_bpp;
2388 viafb_lcd_set_mode(crt_timing, viaparinfo->
2390 &viaparinfo->chip_info->lvds_chip_info);
2393 if (viafb_LCD2_ON) {
2394 if (viafb_SAMM_ON &&
2395 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2396 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2397 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2399 &viaparinfo->chip_info->lvds_chip_info2);
2401 /* IGA1 doesn't have LCD scaling, so set it center. */
2402 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2403 viaparinfo->lvds_setting_info2->display_method =
2406 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2407 viafb_lcd_set_mode(crt_timing, viaparinfo->
2409 &viaparinfo->chip_info->lvds_chip_info2);
2413 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2414 && (viafb_LCD_ON || viafb_DVI_ON))
2415 set_display_channel();
2417 /* If set mode normally, save resolution information for hot-plug . */
2418 if (!viafb_hotplug) {
2419 viafb_hotplug_Xres = hor_res;
2420 viafb_hotplug_Yres = ver_res;
2421 viafb_hotplug_bpp = video_bpp;
2422 viafb_hotplug_refresh = viafb_refresh;
2425 viafb_DeviceStatus = DVI_Device;
2427 viafb_DeviceStatus = CRT_Device;
2431 if (viafb_SAMM_ON == 1)
2432 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2438 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2442 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2443 if ((hres == res_map_refresh_tbl[i].hres)
2444 && (vres == res_map_refresh_tbl[i].vres)
2445 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2446 return res_map_refresh_tbl[i].pixclock;
2448 return RES_640X480_60HZ_PIXCLOCK;
2452 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2454 #define REFRESH_TOLERANCE 3
2455 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2456 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2457 if ((hres == res_map_refresh_tbl[i].hres)
2458 && (vres == res_map_refresh_tbl[i].vres)
2459 && (diff > (abs(long_refresh -
2460 res_map_refresh_tbl[i].vmode_refresh)))) {
2461 diff = abs(long_refresh - res_map_refresh_tbl[i].
2466 #undef REFRESH_TOLERANCE
2468 return res_map_refresh_tbl[nearest].vmode_refresh;
2472 static void device_off(void)
2474 viafb_crt_disable();
2475 viafb_dvi_disable();
2476 viafb_lcd_disable();
2479 static void device_on(void)
2481 if (viafb_CRT_ON == 1)
2483 if (viafb_DVI_ON == 1)
2485 if (viafb_LCD_ON == 1)
2489 void viafb_crt_disable(void)
2491 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2494 void viafb_crt_enable(void)
2496 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2499 void viafb_get_mmio_info(unsigned long *mmio_base, u32 *mmio_len)
2501 struct pci_dev *pdev = NULL;
2505 for (i = 0; pciidlist[i].vendor != 0; i++)
2506 if (viaparinfo->chip_info->gfx_chip_name ==
2507 pciidlist[i].chip_index)
2510 if (!pciidlist[i].vendor)
2513 vendor = pciidlist[i].vendor;
2514 device = pciidlist[i].device;
2516 pdev = pci_get_device(vendor, device, NULL);
2524 *mmio_base = pci_resource_start(pdev, 1);
2525 *mmio_len = pci_resource_len(pdev, 1);
2530 static void enable_second_display_channel(void)
2532 /* to enable second display channel. */
2533 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2534 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2535 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2538 static void disable_second_display_channel(void)
2540 /* to disable second display channel. */
2541 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2542 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2543 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2546 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len)
2548 struct pci_dev *pdev = NULL;
2552 for (i = 0; pciidlist[i].vendor != 0; i++)
2553 if (viaparinfo->chip_info->gfx_chip_name ==
2554 pciidlist[i].chip_index)
2557 if (!pciidlist[i].vendor)
2560 vendor = pciidlist[i].vendor;
2561 device = pciidlist[i].device;
2563 pdev = pci_get_device(vendor, device, NULL);
2566 *fb_base = viafb_read_reg(VIASR, SR30) << 24;
2567 *fb_len = viafb_get_memsize();
2568 DEBUG_MSG(KERN_INFO "Get FB info from SR30!\n");
2569 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2570 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2574 *fb_base = (unsigned int)pci_resource_start(pdev, 0);
2575 *fb_len = get_fb_size_from_pci();
2576 DEBUG_MSG(KERN_INFO "Get FB info from PCI system!\n");
2577 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2578 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2583 static int get_fb_size_from_pci(void)
2585 unsigned long configid, deviceid, FBSize = 0;
2587 int DeviceFound = false;
2589 for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2590 outl(configid, (unsigned long)0xCF8);
2591 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2596 outl(configid + 0xE0, (unsigned long)0xCF8);
2597 FBSize = inl((unsigned long)0xCFC);
2598 DeviceFound = true; /* Found device id */
2601 case CN400_FUNCTION3:
2602 case CN700_FUNCTION3:
2603 case CX700_FUNCTION3:
2604 case KM800_FUNCTION3:
2605 case KM890_FUNCTION3:
2606 case P4M890_FUNCTION3:
2607 case P4M900_FUNCTION3:
2608 case VX800_FUNCTION3:
2609 /*case CN750_FUNCTION3: */
2610 outl(configid + 0xA0, (unsigned long)0xCF8);
2611 FBSize = inl((unsigned long)0xCFC);
2612 DeviceFound = true; /* Found device id */
2623 DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2625 FBSize = FBSize & 0x00007000;
2626 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2628 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2631 VideoMemSize = (16 << 20); /*16M */
2635 VideoMemSize = (32 << 20); /*32M */
2639 VideoMemSize = (64 << 20); /*64M */
2643 VideoMemSize = (32 << 20); /*32M */
2649 VideoMemSize = (8 << 20); /*8M */
2653 VideoMemSize = (16 << 20); /*16M */
2657 VideoMemSize = (32 << 20); /*32M */
2661 VideoMemSize = (64 << 20); /*64M */
2665 VideoMemSize = (128 << 20); /*128M */
2669 VideoMemSize = (256 << 20); /*256M */
2673 VideoMemSize = (32 << 20); /*32M */
2678 return VideoMemSize;
2681 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2684 switch (output_interface) {
2685 case INTERFACE_DVP0:
2687 /* DVP0 Clock Polarity and Adjust: */
2688 viafb_write_reg_mask(CR96, VIACR,
2689 p_gfx_dpa_setting->DVP0, 0x0F);
2691 /* DVP0 Clock and Data Pads Driving: */
2692 viafb_write_reg_mask(SR1E, VIASR,
2693 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2694 viafb_write_reg_mask(SR2A, VIASR,
2695 p_gfx_dpa_setting->DVP0ClockDri_S1,
2697 viafb_write_reg_mask(SR1B, VIASR,
2698 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2699 viafb_write_reg_mask(SR2A, VIASR,
2700 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2704 case INTERFACE_DVP1:
2706 /* DVP1 Clock Polarity and Adjust: */
2707 viafb_write_reg_mask(CR9B, VIACR,
2708 p_gfx_dpa_setting->DVP1, 0x0F);
2710 /* DVP1 Clock and Data Pads Driving: */
2711 viafb_write_reg_mask(SR65, VIASR,
2712 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2716 case INTERFACE_DFP_HIGH:
2718 viafb_write_reg_mask(CR97, VIACR,
2719 p_gfx_dpa_setting->DFPHigh, 0x0F);
2723 case INTERFACE_DFP_LOW:
2725 viafb_write_reg_mask(CR99, VIACR,
2726 p_gfx_dpa_setting->DFPLow, 0x0F);
2732 viafb_write_reg_mask(CR97, VIACR,
2733 p_gfx_dpa_setting->DFPHigh, 0x0F);
2734 viafb_write_reg_mask(CR99, VIACR,
2735 p_gfx_dpa_setting->DFPLow, 0x0F);
2741 void viafb_memory_pitch_patch(struct fb_info *info)
2743 if (info->var.xres != info->var.xres_virtual) {
2744 viafb_load_offset_reg(info->var.xres_virtual,
2745 info->var.bits_per_pixel >> 3, IGA1);
2747 if (viafb_SAMM_ON) {
2748 viafb_load_offset_reg(viafb_second_virtual_xres,
2752 viafb_load_offset_reg(info->var.xres_virtual,
2753 info->var.bits_per_pixel >> 3, IGA2);
2759 /*According var's xres, yres fill var's other timing information*/
2760 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2763 struct VideoModeTable *vmode_tbl = NULL;
2764 struct crt_mode_table *crt_timing = NULL;
2765 struct display_timing crt_reg;
2766 int i = 0, index = 0;
2767 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2768 crt_timing = vmode_tbl->crtc;
2769 for (i = 0; i < vmode_tbl->mode_array; i++) {
2771 if (crt_timing[i].refresh_rate == refresh)
2775 crt_reg = crt_timing[index].crtc;
2776 switch (var->bits_per_pixel) {
2778 var->red.offset = 0;
2779 var->green.offset = 0;
2780 var->blue.offset = 0;
2781 var->red.length = 6;
2782 var->green.length = 6;
2783 var->blue.length = 6;
2786 var->red.offset = 11;
2787 var->green.offset = 5;
2788 var->blue.offset = 0;
2789 var->red.length = 5;
2790 var->green.length = 6;
2791 var->blue.length = 5;
2794 var->red.offset = 16;
2795 var->green.offset = 8;
2796 var->blue.offset = 0;
2797 var->red.length = 8;
2798 var->green.length = 8;
2799 var->blue.length = 8;
2802 /* never happed, put here to keep consistent */
2806 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2808 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2809 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2810 var->hsync_len = crt_reg.hor_sync_end;
2812 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2813 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2814 var->vsync_len = crt_reg.ver_sync_end;