SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  66          CX700_60_466M, VX855_60_466M},
  67         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  68          CX700_61_500M, VX855_61_500M},
  69         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  70          CX700_65_000M, VX855_65_000M},
  71         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  72          CX700_65_178M, VX855_65_178M},
  73         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  74          CX700_66_750M, VX855_66_750M},
  75         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  76          CX700_68_179M, VX855_68_179M},
  77         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  78          CX700_69_924M, VX855_69_924M},
  79         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  80          CX700_70_159M, VX855_70_159M},
  81         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  82          CX700_72_000M, VX855_72_000M},
  83         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  84          CX700_78_750M, VX855_78_750M},
  85         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  86          CX700_80_136M, VX855_80_136M},
  87         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  88          CX700_83_375M, VX855_83_375M},
  89         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  90          CX700_83_950M, VX855_83_950M},
  91         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  92          CX700_84_750M, VX855_84_750M},
  93         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  94          CX700_85_860M, VX855_85_860M},
  95         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  96          CX700_88_750M, VX855_88_750M},
  97         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  98          CX700_94_500M, VX855_94_500M},
  99         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 100          CX700_97_750M, VX855_97_750M},
 101         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 102          CX700_101_000M, VX855_101_000M},
 103         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 104          CX700_106_500M, VX855_106_500M},
 105         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 106          CX700_108_000M, VX855_108_000M},
 107         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 108          CX700_113_309M, VX855_113_309M},
 109         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 110          CX700_118_840M, VX855_118_840M},
 111         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 112          CX700_119_000M, VX855_119_000M},
 113         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 114          CX700_121_750M, 0},
 115         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 116          CX700_125_104M, 0},
 117         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 118          CX700_133_308M, 0},
 119         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 120          CX700_135_000M, VX855_135_000M},
 121         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 122          CX700_136_700M, VX855_136_700M},
 123         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 124          CX700_138_400M, VX855_138_400M},
 125         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 126          CX700_146_760M, VX855_146_760M},
 127         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 128          CX700_153_920M, VX855_153_920M},
 129         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 130          CX700_156_000M, VX855_156_000M},
 131         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 132          CX700_157_500M, VX855_157_500M},
 133         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 134          CX700_162_000M, VX855_162_000M},
 135         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 136          CX700_187_000M, VX855_187_000M},
 137         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 138          CX700_193_295M, VX855_193_295M},
 139         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 140          CX700_202_500M, VX855_202_500M},
 141         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 142          CX700_204_000M, VX855_204_000M},
 143         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 144          CX700_218_500M, VX855_218_500M},
 145         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 146          CX700_234_000M, VX855_234_000M},
 147         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 148          CX700_267_250M, VX855_267_250M},
 149         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 150          CX700_297_500M, VX855_297_500M},
 151         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 152          CX700_74_481M, VX855_74_481M},
 153         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 154          CX700_172_798M, VX855_172_798M},
 155         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 156          CX700_122_614M, VX855_122_614M},
 157         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 158          CX700_74_270M, 0},
 159         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 160          CX700_148_500M, VX855_148_500M}
 161 };
 162
 163 static struct fifo_depth_select display_fifo_depth_reg = {
 164         /* IGA1 FIFO Depth_Select */
 165         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 166         /* IGA2 FIFO Depth_Select */
 167         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 168          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 169 };
 170
 171 static struct fifo_threshold_select fifo_threshold_select_reg = {
 172         /* IGA1 FIFO Threshold Select */
 173         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 174         /* IGA2 FIFO Threshold Select */
 175         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 176 };
 177
 178 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 179         /* IGA1 FIFO High Threshold Select */
 180         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 181         /* IGA2 FIFO High Threshold Select */
 182         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 183 };
 184
 185 static struct display_queue_expire_num display_queue_expire_num_reg = {
 186         /* IGA1 Display Queue Expire Num */
 187         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 188         /* IGA2 Display Queue Expire Num */
 189         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 190 };
 191
 192 /* Definition Fetch Count Registers*/
 193 static struct fetch_count fetch_count_reg = {
 194         /* IGA1 Fetch Count Register */
 195         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 196         /* IGA2 Fetch Count Register */
 197         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 198 };
 199
 200 static struct iga1_crtc_timing iga1_crtc_reg = {
 201         /* IGA1 Horizontal Total */
 202         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 203         /* IGA1 Horizontal Addressable Video */
 204         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 205         /* IGA1 Horizontal Blank Start */
 206         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 207         /* IGA1 Horizontal Blank End */
 208         {IGA1_HOR_BLANK_END_REG_NUM,
 209          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 210         /* IGA1 Horizontal Sync Start */
 211         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 212         /* IGA1 Horizontal Sync End */
 213         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 214         /* IGA1 Vertical Total */
 215         {IGA1_VER_TOTAL_REG_NUM,
 216          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 217         /* IGA1 Vertical Addressable Video */
 218         {IGA1_VER_ADDR_REG_NUM,
 219          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 220         /* IGA1 Vertical Blank Start */
 221         {IGA1_VER_BLANK_START_REG_NUM,
 222          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 223         /* IGA1 Vertical Blank End */
 224         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 225         /* IGA1 Vertical Sync Start */
 226         {IGA1_VER_SYNC_START_REG_NUM,
 227          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 228         /* IGA1 Vertical Sync End */
 229         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 230 };
 231
 232 static struct iga2_crtc_timing iga2_crtc_reg = {
 233         /* IGA2 Horizontal Total */
 234         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 235         /* IGA2 Horizontal Addressable Video */
 236         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 237         /* IGA2 Horizontal Blank Start */
 238         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 239         /* IGA2 Horizontal Blank End */
 240         {IGA2_HOR_BLANK_END_REG_NUM,
 241          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 242         /* IGA2 Horizontal Sync Start */
 243         {IGA2_HOR_SYNC_START_REG_NUM,
 244          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 245         /* IGA2 Horizontal Sync End */
 246         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 247         /* IGA2 Vertical Total */
 248         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 249         /* IGA2 Vertical Addressable Video */
 250         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 251         /* IGA2 Vertical Blank Start */
 252         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 253         /* IGA2 Vertical Blank End */
 254         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 255         /* IGA2 Vertical Sync Start */
 256         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 257         /* IGA2 Vertical Sync End */
 258         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 259 };
 260
 261 static struct rgbLUT palLUT_table[] = {
 262         /* {R,G,B} */
 263         /* Index 0x00~0x03 */
 264         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 265                                                                      0x2A,
 266                                                                      0x2A},
 267         /* Index 0x04~0x07 */
 268         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 269                                                                      0x2A,
 270                                                                      0x2A},
 271         /* Index 0x08~0x0B */
 272         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 273                                                                      0x3F,
 274                                                                      0x3F},
 275         /* Index 0x0C~0x0F */
 276         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 277                                                                      0x3F,
 278                                                                      0x3F},
 279         /* Index 0x10~0x13 */
 280         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 281                                                                      0x0B,
 282                                                                      0x0B},
 283         /* Index 0x14~0x17 */
 284         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 285                                                                      0x18,
 286                                                                      0x18},
 287         /* Index 0x18~0x1B */
 288         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 289                                                                      0x28,
 290                                                                      0x28},
 291         /* Index 0x1C~0x1F */
 292         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 293                                                                      0x3F,
 294                                                                      0x3F},
 295         /* Index 0x20~0x23 */
 296         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 297                                                                      0x00,
 298                                                                      0x3F},
 299         /* Index 0x24~0x27 */
 300         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 301                                                                      0x00,
 302                                                                      0x10},
 303         /* Index 0x28~0x2B */
 304         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 305                                                                      0x2F,
 306                                                                      0x00},
 307         /* Index 0x2C~0x2F */
 308         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 309                                                                      0x3F,
 310                                                                      0x00},
 311         /* Index 0x30~0x33 */
 312         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 313                                                                      0x3F,
 314                                                                      0x2F},
 315         /* Index 0x34~0x37 */
 316         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 317                                                                      0x10,
 318                                                                      0x3F},
 319         /* Index 0x38~0x3B */
 320         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 321                                                                      0x1F,
 322                                                                      0x3F},
 323         /* Index 0x3C~0x3F */
 324         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 325                                                                      0x1F,
 326                                                                      0x27},
 327         /* Index 0x40~0x43 */
 328         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 329                                                                      0x3F,
 330                                                                      0x1F},
 331         /* Index 0x44~0x47 */
 332         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 333                                                                      0x3F,
 334                                                                      0x1F},
 335         /* Index 0x48~0x4B */
 336         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 337                                                                      0x3F,
 338                                                                      0x37},
 339         /* Index 0x4C~0x4F */
 340         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 341                                                                      0x27,
 342                                                                      0x3F},
 343         /* Index 0x50~0x53 */
 344         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 345                                                                      0x2D,
 346                                                                      0x3F},
 347         /* Index 0x54~0x57 */
 348         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 349                                                                      0x2D,
 350                                                                      0x31},
 351         /* Index 0x58~0x5B */
 352         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 353                                                                      0x3A,
 354                                                                      0x2D},
 355         /* Index 0x5C~0x5F */
 356         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 357                                                                      0x3F,
 358                                                                      0x2D},
 359         /* Index 0x60~0x63 */
 360         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 361                                                                      0x3F,
 362                                                                      0x3A},
 363         /* Index 0x64~0x67 */
 364         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 365                                                                      0x31,
 366                                                                      0x3F},
 367         /* Index 0x68~0x6B */
 368         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 369                                                                      0x00,
 370                                                                      0x1C},
 371         /* Index 0x6C~0x6F */
 372         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 373                                                                      0x00,
 374                                                                      0x07},
 375         /* Index 0x70~0x73 */
 376         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 377                                                                      0x15,
 378                                                                      0x00},
 379         /* Index 0x74~0x77 */
 380         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 381                                                                      0x1C,
 382                                                                      0x00},
 383         /* Index 0x78~0x7B */
 384         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 385                                                                      0x1C,
 386                                                                      0x15},
 387         /* Index 0x7C~0x7F */
 388         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 389                                                                      0x07,
 390                                                                      0x1C},
 391         /* Index 0x80~0x83 */
 392         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 393                                                                      0x0E,
 394                                                                      0x1C},
 395         /* Index 0x84~0x87 */
 396         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 397                                                                      0x0E,
 398                                                                      0x11},
 399         /* Index 0x88~0x8B */
 400         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 401                                                                      0x18,
 402                                                                      0x0E},
 403         /* Index 0x8C~0x8F */
 404         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 405                                                                      0x1C,
 406                                                                      0x0E},
 407         /* Index 0x90~0x93 */
 408         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 409                                                                      0x1C,
 410                                                                      0x18},
 411         /* Index 0x94~0x97 */
 412         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 413                                                                      0x11,
 414                                                                      0x1C},
 415         /* Index 0x98~0x9B */
 416         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 417                                                                      0x14,
 418                                                                      0x1C},
 419         /* Index 0x9C~0x9F */
 420         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 421                                                                      0x14,
 422                                                                      0x16},
 423         /* Index 0xA0~0xA3 */
 424         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 425                                                                      0x1A,
 426                                                                      0x14},
 427         /* Index 0xA4~0xA7 */
 428         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 429                                                                      0x1C,
 430                                                                      0x14},
 431         /* Index 0xA8~0xAB */
 432         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 433                                                                      0x1C,
 434                                                                      0x1A},
 435         /* Index 0xAC~0xAF */
 436         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 437                                                                      0x16,
 438                                                                      0x1C},
 439         /* Index 0xB0~0xB3 */
 440         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 441                                                                      0x00,
 442                                                                      0x10},
 443         /* Index 0xB4~0xB7 */
 444         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 445                                                                      0x00,
 446                                                                      0x04},
 447         /* Index 0xB8~0xBB */
 448         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 449                                                                      0x0C,
 450                                                                      0x00},
 451         /* Index 0xBC~0xBF */
 452         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 453                                                                      0x10,
 454                                                                      0x00},
 455         /* Index 0xC0~0xC3 */
 456         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 457                                                                      0x10,
 458                                                                      0x0C},
 459         /* Index 0xC4~0xC7 */
 460         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 461                                                                      0x04,
 462                                                                      0x10},
 463         /* Index 0xC8~0xCB */
 464         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 465                                                                      0x08,
 466                                                                      0x10},
 467         /* Index 0xCC~0xCF */
 468         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 469                                                                      0x08,
 470                                                                      0x0A},
 471         /* Index 0xD0~0xD3 */
 472         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 473                                                                      0x0E,
 474                                                                      0x08},
 475         /* Index 0xD4~0xD7 */
 476         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 477                                                                      0x10,
 478                                                                      0x08},
 479         /* Index 0xD8~0xDB */
 480         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 481                                                                      0x10,
 482                                                                      0x0E},
 483         /* Index 0xDC~0xDF */
 484         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 485                                                                      0x0A,
 486                                                                      0x10},
 487         /* Index 0xE0~0xE3 */
 488         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 489                                                                      0x0B,
 490                                                                      0x10},
 491         /* Index 0xE4~0xE7 */
 492         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 493                                                                      0x0B,
 494                                                                      0x0C},
 495         /* Index 0xE8~0xEB */
 496         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 497                                                                      0x0F,
 498                                                                      0x0B},
 499         /* Index 0xEC~0xEF */
 500         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 501                                                                      0x10,
 502                                                                      0x0B},
 503         /* Index 0xF0~0xF3 */
 504         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 505                                                                      0x10,
 506                                                                      0x0F},
 507         /* Index 0xF4~0xF7 */
 508         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 509                                                                      0x0C,
 510                                                                      0x10},
 511         /* Index 0xF8~0xFB */
 512         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 513                                                                      0x00,
 514                                                                      0x00},
 515         /* Index 0xFC~0xFF */
 516         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 517                                                                      0x00,
 518                                                                      0x00}
 519 };
 520
 521 static void set_crt_output_path(int set_iga);
 522 static void dvi_patch_skew_dvp0(void);
 523 static void dvi_patch_skew_dvp1(void);
 524 static void dvi_patch_skew_dvp_low(void);
 525 static void set_dvi_output_path(int set_iga, int output_interface);
 526 static void set_lcd_output_path(int set_iga, int output_interface);
 527 static void load_fix_bit_crtc_reg(void);
 528 static void init_gfx_chip_info(struct pci_dev *pdev,
 529                                 const struct pci_device_id *pdi);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_write_reg(u8 index, u16 io_port, u8 data)
 541 {
 542         outb(index, io_port);
 543         outb(data, io_port + 1);
 544         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
 545 }
 546 u8 viafb_read_reg(int io_port, u8 index)
 547 {
 548         outb(index, io_port);
 549         return inb(io_port + 1);
 550 }
 551
 552 void viafb_lock_crt(void)
 553 {
 554         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 555 }
 556
 557 void viafb_unlock_crt(void)
 558 {
 559         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 560         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 561 }
 562
 563 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
 564 {
 565         u8 tmp;
 566
 567         outb(index, io_port);
 568         tmp = inb(io_port + 1);
 569         outb((data & mask) | (tmp & (~mask)), io_port + 1);
 570         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
 571 }
 572
 573 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 574 {
 575         outb(index, LUT_INDEX_WRITE);
 576         outb(r, LUT_DATA);
 577         outb(g, LUT_DATA);
 578         outb(b, LUT_DATA);
 579 }
 580
 581 /*Set IGA path for each device*/
 582 void viafb_set_iga_path(void)
 583 {
 584
 585         if (viafb_SAMM_ON == 1) {
 586                 if (viafb_CRT_ON) {
 587                         if (viafb_primary_dev == CRT_Device)
 588                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 589                         else
 590                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 591                 }
 592
 593                 if (viafb_DVI_ON) {
 594                         if (viafb_primary_dev == DVI_Device)
 595                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 596                         else
 597                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 598                 }
 599
 600                 if (viafb_LCD_ON) {
 601                         if (viafb_primary_dev == LCD_Device) {
 602                                 if (viafb_dual_fb &&
 603                                         (viaparinfo->chip_info->gfx_chip_name ==
 604                                         UNICHROME_CLE266)) {
 605                                         viaparinfo->
 606                                         lvds_setting_info->iga_path = IGA2;
 607                                         viaparinfo->
 608                                         crt_setting_info->iga_path = IGA1;
 609                                         viaparinfo->
 610                                         tmds_setting_info->iga_path = IGA1;
 611                                 } else
 612                                         viaparinfo->
 613                                         lvds_setting_info->iga_path = IGA1;
 614                         } else {
 615                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         }
 617                 }
 618                 if (viafb_LCD2_ON) {
 619                         if (LCD2_Device == viafb_primary_dev)
 620                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 621                         else
 622                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 623                 }
 624         } else {
 625                 viafb_SAMM_ON = 0;
 626
 627                 if (viafb_CRT_ON && viafb_LCD_ON) {
 628                         viaparinfo->crt_setting_info->iga_path = IGA1;
 629                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 630                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 631                         viaparinfo->crt_setting_info->iga_path = IGA1;
 632                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 633                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 634                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 635                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 636                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 637                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 638                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 639                 } else if (viafb_CRT_ON) {
 640                         viaparinfo->crt_setting_info->iga_path = IGA1;
 641                 } else if (viafb_LCD_ON) {
 642                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 643                 } else if (viafb_DVI_ON) {
 644                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 645                 }
 646         }
 647 }
 648
 649 void viafb_set_primary_address(u32 addr)
 650 {
 651         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
 652         viafb_write_reg(CR0D, VIACR, addr & 0xFF);
 653         viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
 654         viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
 655         viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
 656 }
 657
 658 void viafb_set_secondary_address(u32 addr)
 659 {
 660         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
 661         /* secondary display supports only quadword aligned memory */
 662         viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
 663         viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
 664         viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
 665         viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
 666 }
 667
 668 void viafb_set_primary_pitch(u32 pitch)
 669 {
 670         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
 671         /* spec does not say that first adapter skips 3 bits but old
 672          * code did it and seems to be reasonable in analogy to 2nd adapter
 673          */
 674         pitch = pitch >> 3;
 675         viafb_write_reg(0x13, VIACR, pitch & 0xFF);
 676         viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
 677 }
 678
 679 void viafb_set_secondary_pitch(u32 pitch)
 680 {
 681         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
 682         pitch = pitch >> 3;
 683         viafb_write_reg(0x66, VIACR, pitch & 0xFF);
 684         viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
 685         viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
 686 }
 687
 688 void viafb_set_primary_color_depth(u8 depth)
 689 {
 690         u8 value;
 691
 692         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
 693         switch (depth) {
 694         case 6:
 695                 value = 0x00;
 696                 break;
 697         case 16:
 698                 value = 0x14;
 699                 break;
 700         case 24:
 701                 value = 0x0C;
 702                 break;
 703         default:
 704                 printk(KERN_WARNING "viafb_set_primary_color_depth: "
 705                         "Unsupported depth: %d\n", depth);
 706                 return;
 707         }
 708
 709         viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
 710 }
 711
 712 void viafb_set_secondary_color_depth(u8 depth)
 713 {
 714         u8 value;
 715
 716         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
 717         switch (depth) {
 718         case 6:
 719                 value = 0x00;
 720                 break;
 721         case 16:
 722                 value = 0x40;
 723                 break;
 724         case 24:
 725                 value = 0xC0;
 726                 break;
 727         default:
 728                 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
 729                         "Unsupported depth: %d\n", depth);
 730                 return;
 731         }
 732
 733         viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
 734 }
 735
 736 void viafb_set_output_path(int device, int set_iga, int output_interface)
 737 {
 738         switch (device) {
 739         case DEVICE_CRT:
 740                 set_crt_output_path(set_iga);
 741                 break;
 742         case DEVICE_DVI:
 743                 set_dvi_output_path(set_iga, output_interface);
 744                 break;
 745         case DEVICE_LCD:
 746                 set_lcd_output_path(set_iga, output_interface);
 747                 break;
 748         }
 749 }
 750
 751 static void set_crt_output_path(int set_iga)
 752 {
 753         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 754
 755         switch (set_iga) {
 756         case IGA1:
 757                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 758                 break;
 759         case IGA2:
 760                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 761                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 762                 break;
 763         }
 764 }
 765
 766 static void dvi_patch_skew_dvp0(void)
 767 {
 768         /* Reset data driving first: */
 769         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 770         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 771
 772         switch (viaparinfo->chip_info->gfx_chip_name) {
 773         case UNICHROME_P4M890:
 774                 {
 775                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 776                                 (viaparinfo->tmds_setting_info->v_active ==
 777                                 1200))
 778                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 779                                                BIT0 + BIT1 + BIT2);
 780                         else
 781                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 782                                                BIT0 + BIT1 + BIT2);
 783                         break;
 784                 }
 785
 786         case UNICHROME_P4M900:
 787                 {
 788                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 789                                        BIT0 + BIT1 + BIT2 + BIT3);
 790                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 791                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 792                         break;
 793                 }
 794
 795         default:
 796                 {
 797                         break;
 798                 }
 799         }
 800 }
 801
 802 static void dvi_patch_skew_dvp1(void)
 803 {
 804         switch (viaparinfo->chip_info->gfx_chip_name) {
 805         case UNICHROME_CX700:
 806                 {
 807                         break;
 808                 }
 809
 810         default:
 811                 {
 812                         break;
 813                 }
 814         }
 815 }
 816
 817 static void dvi_patch_skew_dvp_low(void)
 818 {
 819         switch (viaparinfo->chip_info->gfx_chip_name) {
 820         case UNICHROME_K8M890:
 821                 {
 822                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 823                         break;
 824                 }
 825
 826         case UNICHROME_P4M900:
 827                 {
 828                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 829                                        BIT0 + BIT1 + BIT2 + BIT3);
 830                         break;
 831                 }
 832
 833         case UNICHROME_P4M890:
 834                 {
 835                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 836                                        BIT0 + BIT1 + BIT2 + BIT3);
 837                         break;
 838                 }
 839
 840         default:
 841                 {
 842                         break;
 843                 }
 844         }
 845 }
 846
 847 static void set_dvi_output_path(int set_iga, int output_interface)
 848 {
 849         switch (output_interface) {
 850         case INTERFACE_DVP0:
 851                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 852
 853                 if (set_iga == IGA1) {
 854                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 855                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 856                                 BIT5 + BIT7);
 857                 } else {
 858                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 859                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 860                                 BIT5 + BIT7);
 861                 }
 862
 863                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 864
 865                 dvi_patch_skew_dvp0();
 866                 break;
 867
 868         case INTERFACE_DVP1:
 869                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 870                         if (set_iga == IGA1)
 871                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 872                                                BIT0 + BIT5 + BIT7);
 873                         else
 874                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 875                                                BIT0 + BIT5 + BIT7);
 876                 } else {
 877                         if (set_iga == IGA1)
 878                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 879                         else
 880                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 881                 }
 882
 883                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 884                 dvi_patch_skew_dvp1();
 885                 break;
 886         case INTERFACE_DFP_HIGH:
 887                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 888                         if (set_iga == IGA1) {
 889                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 890                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 891                                                BIT0 + BIT1 + BIT4);
 892                         } else {
 893                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 894                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 895                                                BIT0 + BIT1 + BIT4);
 896                         }
 897                 }
 898                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 899                 break;
 900
 901         case INTERFACE_DFP_LOW:
 902                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 903                         break;
 904
 905                 if (set_iga == IGA1) {
 906                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 907                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 908                 } else {
 909                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 910                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 911                 }
 912
 913                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 914                 dvi_patch_skew_dvp_low();
 915                 break;
 916
 917         case INTERFACE_TMDS:
 918                 if (set_iga == IGA1)
 919                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 920                 else
 921                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 922                 break;
 923         }
 924
 925         if (set_iga == IGA2) {
 926                 enable_second_display_channel();
 927                 /* Disable LCD Scaling */
 928                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 929         }
 930 }
 931
 932 static void set_lcd_output_path(int set_iga, int output_interface)
 933 {
 934         DEBUG_MSG(KERN_INFO
 935                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 936                   set_iga, output_interface);
 937         switch (set_iga) {
 938         case IGA1:
 939                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 940                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 941
 942                 disable_second_display_channel();
 943                 break;
 944
 945         case IGA2:
 946                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 947                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 948
 949                 enable_second_display_channel();
 950                 break;
 951         }
 952
 953         switch (output_interface) {
 954         case INTERFACE_DVP0:
 955                 if (set_iga == IGA1) {
 956                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 957                 } else {
 958                         viafb_write_reg(CR91, VIACR, 0x00);
 959                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 960                 }
 961                 break;
 962
 963         case INTERFACE_DVP1:
 964                 if (set_iga == IGA1)
 965                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 966                 else {
 967                         viafb_write_reg(CR91, VIACR, 0x00);
 968                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 969                 }
 970                 break;
 971
 972         case INTERFACE_DFP_HIGH:
 973                 if (set_iga == IGA1)
 974                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 975                 else {
 976                         viafb_write_reg(CR91, VIACR, 0x00);
 977                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 978                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 979                 }
 980                 break;
 981
 982         case INTERFACE_DFP_LOW:
 983                 if (set_iga == IGA1)
 984                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 985                 else {
 986                         viafb_write_reg(CR91, VIACR, 0x00);
 987                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 988                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 989                 }
 990
 991                 break;
 992
 993         case INTERFACE_DFP:
 994                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
 995                     || (UNICHROME_P4M890 ==
 996                     viaparinfo->chip_info->gfx_chip_name))
 997                         viafb_write_reg_mask(CR97, VIACR, 0x84,
 998                                        BIT7 + BIT2 + BIT1 + BIT0);
 999                 if (set_iga == IGA1) {
1000                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1001                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1002                 } else {
1003                         viafb_write_reg(CR91, VIACR, 0x00);
1004                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1005                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1006                 }
1007                 break;
1008
1009         case INTERFACE_LVDS0:
1010         case INTERFACE_LVDS0LVDS1:
1011                 if (set_iga == IGA1)
1012                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
1013                 else
1014                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
1015
1016                 break;
1017
1018         case INTERFACE_LVDS1:
1019                 if (set_iga == IGA1)
1020                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
1021                 else
1022                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
1023                 break;
1024         }
1025 }
1026
1027 static void load_fix_bit_crtc_reg(void)
1028 {
1029         /* always set to 1 */
1030         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1031         /* line compare should set all bits = 1 (extend modes) */
1032         viafb_write_reg(CR18, VIACR, 0xff);
1033         /* line compare should set all bits = 1 (extend modes) */
1034         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1035         /* line compare should set all bits = 1 (extend modes) */
1036         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1037         /* line compare should set all bits = 1 (extend modes) */
1038         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1039         /* line compare should set all bits = 1 (extend modes) */
1040         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1041         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1042         /* extend mode always set to e3h */
1043         viafb_write_reg(CR17, VIACR, 0xe3);
1044         /* extend mode always set to 0h */
1045         viafb_write_reg(CR08, VIACR, 0x00);
1046         /* extend mode always set to 0h */
1047         viafb_write_reg(CR14, VIACR, 0x00);
1048
1049         /* If K8M800, enable Prefetch Mode. */
1050         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1051                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1052                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1053         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1054             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1055                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1056
1057 }
1058
1059 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1060         struct io_register *reg,
1061               int io_type)
1062 {
1063         int reg_mask;
1064         int bit_num = 0;
1065         int data;
1066         int i, j;
1067         int shift_next_reg;
1068         int start_index, end_index, cr_index;
1069         u16 get_bit;
1070
1071         for (i = 0; i < viafb_load_reg_num; i++) {
1072                 reg_mask = 0;
1073                 data = 0;
1074                 start_index = reg[i].start_bit;
1075                 end_index = reg[i].end_bit;
1076                 cr_index = reg[i].io_addr;
1077
1078                 shift_next_reg = bit_num;
1079                 for (j = start_index; j <= end_index; j++) {
1080                         /*if (bit_num==8) timing_value = timing_value >>8; */
1081                         reg_mask = reg_mask | (BIT0 << j);
1082                         get_bit = (timing_value & (BIT0 << bit_num));
1083                         data =
1084                             data | ((get_bit >> shift_next_reg) << start_index);
1085                         bit_num++;
1086                 }
1087                 if (io_type == VIACR)
1088                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1089                 else
1090                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1091         }
1092
1093 }
1094
1095 /* Write Registers */
1096 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1097 {
1098         int i;
1099         unsigned char RegTemp;
1100
1101         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1102
1103         for (i = 0; i < ItemNum; i++) {
1104                 outb(RegTable[i].index, RegTable[i].port);
1105                 RegTemp = inb(RegTable[i].port + 1);
1106                 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1107                 outb(RegTemp, RegTable[i].port + 1);
1108         }
1109 }
1110
1111 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1112 {
1113         int reg_value;
1114         int viafb_load_reg_num;
1115         struct io_register *reg = NULL;
1116
1117         switch (set_iga) {
1118         case IGA1:
1119                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1120                 viafb_load_reg_num = fetch_count_reg.
1121                         iga1_fetch_count_reg.reg_num;
1122                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1123                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1124                 break;
1125         case IGA2:
1126                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1127                 viafb_load_reg_num = fetch_count_reg.
1128                         iga2_fetch_count_reg.reg_num;
1129                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1130                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1131                 break;
1132         }
1133
1134 }
1135
1136 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1137 {
1138         int reg_value;
1139         int viafb_load_reg_num;
1140         struct io_register *reg = NULL;
1141         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1142             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1143         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1144             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1145
1146         if (set_iga == IGA1) {
1147                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1148                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1149                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1150                         iga1_fifo_high_threshold =
1151                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1152                         /* If resolution > 1280x1024, expire length = 64, else
1153                            expire length = 128 */
1154                         if ((hor_active > 1280) && (ver_active > 1024))
1155                                 iga1_display_queue_expire_num = 16;
1156                         else
1157                                 iga1_display_queue_expire_num =
1158                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1159
1160                 }
1161
1162                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1163                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1164                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1165                         iga1_fifo_high_threshold =
1166                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1167                         iga1_display_queue_expire_num =
1168                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1169
1170                         /* If resolution > 1280x1024, expire length = 64, else
1171                            expire length = 128 */
1172                         if ((hor_active > 1280) && (ver_active > 1024))
1173                                 iga1_display_queue_expire_num = 16;
1174                         else
1175                                 iga1_display_queue_expire_num =
1176                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1177                 }
1178
1179                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1180                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1181                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1182                         iga1_fifo_high_threshold =
1183                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1184
1185                         /* If resolution > 1280x1024, expire length = 64,
1186                            else expire length = 128 */
1187                         if ((hor_active > 1280) && (ver_active > 1024))
1188                                 iga1_display_queue_expire_num = 16;
1189                         else
1190                                 iga1_display_queue_expire_num =
1191                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1192                 }
1193
1194                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1195                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1196                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1197                         iga1_fifo_high_threshold =
1198                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1199                         iga1_display_queue_expire_num =
1200                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1201                 }
1202
1203                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1204                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1205                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1206                         iga1_fifo_high_threshold =
1207                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1208                         iga1_display_queue_expire_num =
1209                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1210                 }
1211
1212                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1213                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1214                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1215                         iga1_fifo_high_threshold =
1216                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1217                         iga1_display_queue_expire_num =
1218                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1219                 }
1220
1221                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1222                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1223                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1224                         iga1_fifo_high_threshold =
1225                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1226                         iga1_display_queue_expire_num =
1227                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1228                 }
1229
1230                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1231                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1232                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1233                         iga1_fifo_high_threshold =
1234                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1235                         iga1_display_queue_expire_num =
1236                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1237                 }
1238
1239                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1240                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1241                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1242                         iga1_fifo_high_threshold =
1243                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1244                         iga1_display_queue_expire_num =
1245                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1246                 }
1247
1248                 /* Set Display FIFO Depath Select */
1249                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1250                 viafb_load_reg_num =
1251                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1252                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1253                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1254
1255                 /* Set Display FIFO Threshold Select */
1256                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1257                 viafb_load_reg_num =
1258                     fifo_threshold_select_reg.
1259                     iga1_fifo_threshold_select_reg.reg_num;
1260                 reg =
1261                     fifo_threshold_select_reg.
1262                     iga1_fifo_threshold_select_reg.reg;
1263                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1264
1265                 /* Set FIFO High Threshold Select */
1266                 reg_value =
1267                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1268                 viafb_load_reg_num =
1269                     fifo_high_threshold_select_reg.
1270                     iga1_fifo_high_threshold_select_reg.reg_num;
1271                 reg =
1272                     fifo_high_threshold_select_reg.
1273                     iga1_fifo_high_threshold_select_reg.reg;
1274                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1275
1276                 /* Set Display Queue Expire Num */
1277                 reg_value =
1278                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1279                     (iga1_display_queue_expire_num);
1280                 viafb_load_reg_num =
1281                     display_queue_expire_num_reg.
1282                     iga1_display_queue_expire_num_reg.reg_num;
1283                 reg =
1284                     display_queue_expire_num_reg.
1285                     iga1_display_queue_expire_num_reg.reg;
1286                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1287
1288         } else {
1289                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1290                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1291                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1292                         iga2_fifo_high_threshold =
1293                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1294
1295                         /* If resolution > 1280x1024, expire length = 64,
1296                            else  expire length = 128 */
1297                         if ((hor_active > 1280) && (ver_active > 1024))
1298                                 iga2_display_queue_expire_num = 16;
1299                         else
1300                                 iga2_display_queue_expire_num =
1301                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1302                 }
1303
1304                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1305                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1306                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1307                         iga2_fifo_high_threshold =
1308                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1309
1310                         /* If resolution > 1280x1024, expire length = 64,
1311                            else  expire length = 128 */
1312                         if ((hor_active > 1280) && (ver_active > 1024))
1313                                 iga2_display_queue_expire_num = 16;
1314                         else
1315                                 iga2_display_queue_expire_num =
1316                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1317                 }
1318
1319                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1320                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1321                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1322                         iga2_fifo_high_threshold =
1323                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1324
1325                         /* If resolution > 1280x1024, expire length = 64,
1326                            else expire length = 128 */
1327                         if ((hor_active > 1280) && (ver_active > 1024))
1328                                 iga2_display_queue_expire_num = 16;
1329                         else
1330                                 iga2_display_queue_expire_num =
1331                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1332                 }
1333
1334                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1335                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1336                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1337                         iga2_fifo_high_threshold =
1338                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1339                         iga2_display_queue_expire_num =
1340                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1341                 }
1342
1343                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1344                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1345                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1346                         iga2_fifo_high_threshold =
1347                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1348                         iga2_display_queue_expire_num =
1349                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1350                 }
1351
1352                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1353                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1354                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1355                         iga2_fifo_high_threshold =
1356                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1357                         iga2_display_queue_expire_num =
1358                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1359                 }
1360
1361                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1362                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1363                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1364                         iga2_fifo_high_threshold =
1365                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1366                         iga2_display_queue_expire_num =
1367                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1368                 }
1369
1370                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1371                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1372                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1373                         iga2_fifo_high_threshold =
1374                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1375                         iga2_display_queue_expire_num =
1376                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1377                 }
1378
1379                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1380                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1381                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1382                         iga2_fifo_high_threshold =
1383                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1384                         iga2_display_queue_expire_num =
1385                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1386                 }
1387
1388                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1389                         /* Set Display FIFO Depath Select */
1390                         reg_value =
1391                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1392                             - 1;
1393                         /* Patch LCD in IGA2 case */
1394                         viafb_load_reg_num =
1395                             display_fifo_depth_reg.
1396                             iga2_fifo_depth_select_reg.reg_num;
1397                         reg =
1398                             display_fifo_depth_reg.
1399                             iga2_fifo_depth_select_reg.reg;
1400                         viafb_load_reg(reg_value,
1401                                 viafb_load_reg_num, reg, VIACR);
1402                 } else {
1403
1404                         /* Set Display FIFO Depath Select */
1405                         reg_value =
1406                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1407                         viafb_load_reg_num =
1408                             display_fifo_depth_reg.
1409                             iga2_fifo_depth_select_reg.reg_num;
1410                         reg =
1411                             display_fifo_depth_reg.
1412                             iga2_fifo_depth_select_reg.reg;
1413                         viafb_load_reg(reg_value,
1414                                 viafb_load_reg_num, reg, VIACR);
1415                 }
1416
1417                 /* Set Display FIFO Threshold Select */
1418                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1419                 viafb_load_reg_num =
1420                     fifo_threshold_select_reg.
1421                     iga2_fifo_threshold_select_reg.reg_num;
1422                 reg =
1423                     fifo_threshold_select_reg.
1424                     iga2_fifo_threshold_select_reg.reg;
1425                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1426
1427                 /* Set FIFO High Threshold Select */
1428                 reg_value =
1429                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1430                 viafb_load_reg_num =
1431                     fifo_high_threshold_select_reg.
1432                     iga2_fifo_high_threshold_select_reg.reg_num;
1433                 reg =
1434                     fifo_high_threshold_select_reg.
1435                     iga2_fifo_high_threshold_select_reg.reg;
1436                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1437
1438                 /* Set Display Queue Expire Num */
1439                 reg_value =
1440                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1441                     (iga2_display_queue_expire_num);
1442                 viafb_load_reg_num =
1443                     display_queue_expire_num_reg.
1444                     iga2_display_queue_expire_num_reg.reg_num;
1445                 reg =
1446                     display_queue_expire_num_reg.
1447                     iga2_display_queue_expire_num_reg.reg;
1448                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1449
1450         }
1451
1452 }
1453
1454 u32 viafb_get_clk_value(int clk)
1455 {
1456         int i;
1457
1458         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1459                 if (clk == pll_value[i].clk) {
1460                         switch (viaparinfo->chip_info->gfx_chip_name) {
1461                         case UNICHROME_CLE266:
1462                         case UNICHROME_K400:
1463                                 return pll_value[i].cle266_pll;
1464
1465                         case UNICHROME_K800:
1466                         case UNICHROME_PM800:
1467                         case UNICHROME_CN700:
1468                                 return pll_value[i].k800_pll;
1469
1470                         case UNICHROME_CX700:
1471                         case UNICHROME_K8M890:
1472                         case UNICHROME_P4M890:
1473                         case UNICHROME_P4M900:
1474                         case UNICHROME_VX800:
1475                                 return pll_value[i].cx700_pll;
1476                         case UNICHROME_VX855:
1477                                 return pll_value[i].vx855_pll;
1478                         }
1479                 }
1480         }
1481
1482         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1483         return 0;
1484 }
1485
1486 /* Set VCLK*/
1487 void viafb_set_vclock(u32 CLK, int set_iga)
1488 {
1489         unsigned char RegTemp;
1490
1491         /* H.W. Reset : ON */
1492         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1493
1494         if (set_iga == IGA1) {
1495                 /* Change D,N FOR VCLK */
1496                 switch (viaparinfo->chip_info->gfx_chip_name) {
1497                 case UNICHROME_CLE266:
1498                 case UNICHROME_K400:
1499                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1500                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1501                         break;
1502
1503                 case UNICHROME_K800:
1504                 case UNICHROME_PM800:
1505                 case UNICHROME_CN700:
1506                 case UNICHROME_CX700:
1507                 case UNICHROME_K8M890:
1508                 case UNICHROME_P4M890:
1509                 case UNICHROME_P4M900:
1510                 case UNICHROME_VX800:
1511                 case UNICHROME_VX855:
1512                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1513                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1514                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1515                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1516                                   (CLK & 0xFFFF) / 0x100);
1517                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1518                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1519                         break;
1520                 }
1521         }
1522
1523         if (set_iga == IGA2) {
1524                 /* Change D,N FOR LCK */
1525                 switch (viaparinfo->chip_info->gfx_chip_name) {
1526                 case UNICHROME_CLE266:
1527                 case UNICHROME_K400:
1528                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1529                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1530                         break;
1531
1532                 case UNICHROME_K800:
1533                 case UNICHROME_PM800:
1534                 case UNICHROME_CN700:
1535                 case UNICHROME_CX700:
1536                 case UNICHROME_K8M890:
1537                 case UNICHROME_P4M890:
1538                 case UNICHROME_P4M900:
1539                 case UNICHROME_VX800:
1540                 case UNICHROME_VX855:
1541                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1542                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1543                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1544                         break;
1545                 }
1546         }
1547
1548         /* H.W. Reset : OFF */
1549         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1550
1551         /* Reset PLL */
1552         if (set_iga == IGA1) {
1553                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1554                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1555         }
1556
1557         if (set_iga == IGA2) {
1558                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1559                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1560         }
1561
1562         /* Fire! */
1563         RegTemp = inb(VIARMisc);
1564         outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1565 }
1566
1567 void viafb_load_crtc_timing(struct display_timing device_timing,
1568         int set_iga)
1569 {
1570         int i;
1571         int viafb_load_reg_num = 0;
1572         int reg_value = 0;
1573         struct io_register *reg = NULL;
1574
1575         viafb_unlock_crt();
1576
1577         for (i = 0; i < 12; i++) {
1578                 if (set_iga == IGA1) {
1579                         switch (i) {
1580                         case H_TOTAL_INDEX:
1581                                 reg_value =
1582                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1583                                                            hor_total);
1584                                 viafb_load_reg_num =
1585                                         iga1_crtc_reg.hor_total.reg_num;
1586                                 reg = iga1_crtc_reg.hor_total.reg;
1587                                 break;
1588                         case H_ADDR_INDEX:
1589                                 reg_value =
1590                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1591                                                           hor_addr);
1592                                 viafb_load_reg_num =
1593                                         iga1_crtc_reg.hor_addr.reg_num;
1594                                 reg = iga1_crtc_reg.hor_addr.reg;
1595                                 break;
1596                         case H_BLANK_START_INDEX:
1597                                 reg_value =
1598                                     IGA1_HOR_BLANK_START_FORMULA
1599                                     (device_timing.hor_blank_start);
1600                                 viafb_load_reg_num =
1601                                     iga1_crtc_reg.hor_blank_start.reg_num;
1602                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1603                                 break;
1604                         case H_BLANK_END_INDEX:
1605                                 reg_value =
1606                                     IGA1_HOR_BLANK_END_FORMULA
1607                                     (device_timing.hor_blank_start,
1608                                      device_timing.hor_blank_end);
1609                                 viafb_load_reg_num =
1610                                     iga1_crtc_reg.hor_blank_end.reg_num;
1611                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1612                                 break;
1613                         case H_SYNC_START_INDEX:
1614                                 reg_value =
1615                                     IGA1_HOR_SYNC_START_FORMULA
1616                                     (device_timing.hor_sync_start);
1617                                 viafb_load_reg_num =
1618                                     iga1_crtc_reg.hor_sync_start.reg_num;
1619                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1620                                 break;
1621                         case H_SYNC_END_INDEX:
1622                                 reg_value =
1623                                     IGA1_HOR_SYNC_END_FORMULA
1624                                     (device_timing.hor_sync_start,
1625                                      device_timing.hor_sync_end);
1626                                 viafb_load_reg_num =
1627                                     iga1_crtc_reg.hor_sync_end.reg_num;
1628                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1629                                 break;
1630                         case V_TOTAL_INDEX:
1631                                 reg_value =
1632                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1633                                                            ver_total);
1634                                 viafb_load_reg_num =
1635                                         iga1_crtc_reg.ver_total.reg_num;
1636                                 reg = iga1_crtc_reg.ver_total.reg;
1637                                 break;
1638                         case V_ADDR_INDEX:
1639                                 reg_value =
1640                                     IGA1_VER_ADDR_FORMULA(device_timing.
1641                                                           ver_addr);
1642                                 viafb_load_reg_num =
1643                                         iga1_crtc_reg.ver_addr.reg_num;
1644                                 reg = iga1_crtc_reg.ver_addr.reg;
1645                                 break;
1646                         case V_BLANK_START_INDEX:
1647                                 reg_value =
1648                                     IGA1_VER_BLANK_START_FORMULA
1649                                     (device_timing.ver_blank_start);
1650                                 viafb_load_reg_num =
1651                                     iga1_crtc_reg.ver_blank_start.reg_num;
1652                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1653                                 break;
1654                         case V_BLANK_END_INDEX:
1655                                 reg_value =
1656                                     IGA1_VER_BLANK_END_FORMULA
1657                                     (device_timing.ver_blank_start,
1658                                      device_timing.ver_blank_end);
1659                                 viafb_load_reg_num =
1660                                     iga1_crtc_reg.ver_blank_end.reg_num;
1661                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1662                                 break;
1663                         case V_SYNC_START_INDEX:
1664                                 reg_value =
1665                                     IGA1_VER_SYNC_START_FORMULA
1666                                     (device_timing.ver_sync_start);
1667                                 viafb_load_reg_num =
1668                                     iga1_crtc_reg.ver_sync_start.reg_num;
1669                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1670                                 break;
1671                         case V_SYNC_END_INDEX:
1672                                 reg_value =
1673                                     IGA1_VER_SYNC_END_FORMULA
1674                                     (device_timing.ver_sync_start,
1675                                      device_timing.ver_sync_end);
1676                                 viafb_load_reg_num =
1677                                     iga1_crtc_reg.ver_sync_end.reg_num;
1678                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1679                                 break;
1680
1681                         }
1682                 }
1683
1684                 if (set_iga == IGA2) {
1685                         switch (i) {
1686                         case H_TOTAL_INDEX:
1687                                 reg_value =
1688                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1689                                                            hor_total);
1690                                 viafb_load_reg_num =
1691                                         iga2_crtc_reg.hor_total.reg_num;
1692                                 reg = iga2_crtc_reg.hor_total.reg;
1693                                 break;
1694                         case H_ADDR_INDEX:
1695                                 reg_value =
1696                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1697                                                           hor_addr);
1698                                 viafb_load_reg_num =
1699                                         iga2_crtc_reg.hor_addr.reg_num;
1700                                 reg = iga2_crtc_reg.hor_addr.reg;
1701                                 break;
1702                         case H_BLANK_START_INDEX:
1703                                 reg_value =
1704                                     IGA2_HOR_BLANK_START_FORMULA
1705                                     (device_timing.hor_blank_start);
1706                                 viafb_load_reg_num =
1707                                     iga2_crtc_reg.hor_blank_start.reg_num;
1708                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1709                                 break;
1710                         case H_BLANK_END_INDEX:
1711                                 reg_value =
1712                                     IGA2_HOR_BLANK_END_FORMULA
1713                                     (device_timing.hor_blank_start,
1714                                      device_timing.hor_blank_end);
1715                                 viafb_load_reg_num =
1716                                     iga2_crtc_reg.hor_blank_end.reg_num;
1717                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1718                                 break;
1719                         case H_SYNC_START_INDEX:
1720                                 reg_value =
1721                                     IGA2_HOR_SYNC_START_FORMULA
1722                                     (device_timing.hor_sync_start);
1723                                 if (UNICHROME_CN700 <=
1724                                         viaparinfo->chip_info->gfx_chip_name)
1725                                         viafb_load_reg_num =
1726                                             iga2_crtc_reg.hor_sync_start.
1727                                             reg_num;
1728                                 else
1729                                         viafb_load_reg_num = 3;
1730                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1731                                 break;
1732                         case H_SYNC_END_INDEX:
1733                                 reg_value =
1734                                     IGA2_HOR_SYNC_END_FORMULA
1735                                     (device_timing.hor_sync_start,
1736                                      device_timing.hor_sync_end);
1737                                 viafb_load_reg_num =
1738                                     iga2_crtc_reg.hor_sync_end.reg_num;
1739                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1740                                 break;
1741                         case V_TOTAL_INDEX:
1742                                 reg_value =
1743                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1744                                                            ver_total);
1745                                 viafb_load_reg_num =
1746                                         iga2_crtc_reg.ver_total.reg_num;
1747                                 reg = iga2_crtc_reg.ver_total.reg;
1748                                 break;
1749                         case V_ADDR_INDEX:
1750                                 reg_value =
1751                                     IGA2_VER_ADDR_FORMULA(device_timing.
1752                                                           ver_addr);
1753                                 viafb_load_reg_num =
1754                                         iga2_crtc_reg.ver_addr.reg_num;
1755                                 reg = iga2_crtc_reg.ver_addr.reg;
1756                                 break;
1757                         case V_BLANK_START_INDEX:
1758                                 reg_value =
1759                                     IGA2_VER_BLANK_START_FORMULA
1760                                     (device_timing.ver_blank_start);
1761                                 viafb_load_reg_num =
1762                                     iga2_crtc_reg.ver_blank_start.reg_num;
1763                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1764                                 break;
1765                         case V_BLANK_END_INDEX:
1766                                 reg_value =
1767                                     IGA2_VER_BLANK_END_FORMULA
1768                                     (device_timing.ver_blank_start,
1769                                      device_timing.ver_blank_end);
1770                                 viafb_load_reg_num =
1771                                     iga2_crtc_reg.ver_blank_end.reg_num;
1772                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1773                                 break;
1774                         case V_SYNC_START_INDEX:
1775                                 reg_value =
1776                                     IGA2_VER_SYNC_START_FORMULA
1777                                     (device_timing.ver_sync_start);
1778                                 viafb_load_reg_num =
1779                                     iga2_crtc_reg.ver_sync_start.reg_num;
1780                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1781                                 break;
1782                         case V_SYNC_END_INDEX:
1783                                 reg_value =
1784                                     IGA2_VER_SYNC_END_FORMULA
1785                                     (device_timing.ver_sync_start,
1786                                      device_timing.ver_sync_end);
1787                                 viafb_load_reg_num =
1788                                     iga2_crtc_reg.ver_sync_end.reg_num;
1789                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1790                                 break;
1791
1792                         }
1793                 }
1794                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1795         }
1796
1797         viafb_lock_crt();
1798 }
1799
1800 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1801         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1802 {
1803         struct display_timing crt_reg;
1804         int i;
1805         int index = 0;
1806         int h_addr, v_addr;
1807         u32 pll_D_N;
1808
1809         for (i = 0; i < video_mode->mode_array; i++) {
1810                 index = i;
1811
1812                 if (crt_table[i].refresh_rate == viaparinfo->
1813                         crt_setting_info->refresh_rate)
1814                         break;
1815         }
1816
1817         crt_reg = crt_table[index].crtc;
1818
1819         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1820         /* So we would delete border. */
1821         if ((viafb_LCD_ON | viafb_DVI_ON)
1822             && video_mode->crtc[0].crtc.hor_addr == 640
1823             && video_mode->crtc[0].crtc.ver_addr == 480
1824             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1825                 /* The border is 8 pixels. */
1826                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1827
1828                 /* Blanking time should add left and right borders. */
1829                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1830         }
1831
1832         h_addr = crt_reg.hor_addr;
1833         v_addr = crt_reg.ver_addr;
1834
1835         /* update polarity for CRT timing */
1836         if (crt_table[index].h_sync_polarity == NEGATIVE) {
1837                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1838                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1839                              (BIT6 + BIT7), VIAWMisc);
1840                 else
1841                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1842                              VIAWMisc);
1843         } else {
1844                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1845                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1846                              VIAWMisc);
1847                 else
1848                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1849         }
1850
1851         if (set_iga == IGA1) {
1852                 viafb_unlock_crt();
1853                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1854                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1855                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1856         }
1857
1858         switch (set_iga) {
1859         case IGA1:
1860                 viafb_load_crtc_timing(crt_reg, IGA1);
1861                 break;
1862         case IGA2:
1863                 viafb_load_crtc_timing(crt_reg, IGA2);
1864                 break;
1865         }
1866
1867         load_fix_bit_crtc_reg();
1868         viafb_lock_crt();
1869         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1870         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1871
1872         /* load FIFO */
1873         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1874             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1875                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1876
1877         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1878         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1879         viafb_set_vclock(pll_D_N, set_iga);
1880
1881 }
1882
1883 void viafb_init_chip_info(struct pci_dev *pdev,
1884                           const struct pci_device_id *pdi)
1885 {
1886         init_gfx_chip_info(pdev, pdi);
1887         init_tmds_chip_info();
1888         init_lvds_chip_info();
1889
1890         viaparinfo->crt_setting_info->iga_path = IGA1;
1891         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1892
1893         /*Set IGA path for each device */
1894         viafb_set_iga_path();
1895
1896         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1897         viaparinfo->lvds_setting_info->get_lcd_size_method =
1898                 GET_LCD_SIZE_BY_USER_SETTING;
1899         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1900         viaparinfo->lvds_setting_info2->display_method =
1901                 viaparinfo->lvds_setting_info->display_method;
1902         viaparinfo->lvds_setting_info2->lcd_mode =
1903                 viaparinfo->lvds_setting_info->lcd_mode;
1904 }
1905
1906 void viafb_update_device_setting(int hres, int vres,
1907         int bpp, int vmode_refresh, int flag)
1908 {
1909         if (flag == 0) {
1910                 viaparinfo->crt_setting_info->h_active = hres;
1911                 viaparinfo->crt_setting_info->v_active = vres;
1912                 viaparinfo->crt_setting_info->bpp = bpp;
1913                 viaparinfo->crt_setting_info->refresh_rate =
1914                         vmode_refresh;
1915
1916                 viaparinfo->tmds_setting_info->h_active = hres;
1917                 viaparinfo->tmds_setting_info->v_active = vres;
1918
1919                 viaparinfo->lvds_setting_info->h_active = hres;
1920                 viaparinfo->lvds_setting_info->v_active = vres;
1921                 viaparinfo->lvds_setting_info->bpp = bpp;
1922                 viaparinfo->lvds_setting_info->refresh_rate =
1923                         vmode_refresh;
1924                 viaparinfo->lvds_setting_info2->h_active = hres;
1925                 viaparinfo->lvds_setting_info2->v_active = vres;
1926                 viaparinfo->lvds_setting_info2->bpp = bpp;
1927                 viaparinfo->lvds_setting_info2->refresh_rate =
1928                         vmode_refresh;
1929         } else {
1930
1931                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1932                         viaparinfo->tmds_setting_info->h_active = hres;
1933                         viaparinfo->tmds_setting_info->v_active = vres;
1934                 }
1935
1936                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1937                         viaparinfo->lvds_setting_info->h_active = hres;
1938                         viaparinfo->lvds_setting_info->v_active = vres;
1939                         viaparinfo->lvds_setting_info->bpp = bpp;
1940                         viaparinfo->lvds_setting_info->refresh_rate =
1941                                 vmode_refresh;
1942                 }
1943                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1944                         viaparinfo->lvds_setting_info2->h_active = hres;
1945                         viaparinfo->lvds_setting_info2->v_active = vres;
1946                         viaparinfo->lvds_setting_info2->bpp = bpp;
1947                         viaparinfo->lvds_setting_info2->refresh_rate =
1948                                 vmode_refresh;
1949                 }
1950         }
1951 }
1952
1953 static void init_gfx_chip_info(struct pci_dev *pdev,
1954                                const struct pci_device_id *pdi)
1955 {
1956         u8 tmp;
1957
1958         viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
1959
1960         /* Check revision of CLE266 Chip */
1961         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1962                 /* CR4F only define in CLE266.CX chip */
1963                 tmp = viafb_read_reg(VIACR, CR4F);
1964                 viafb_write_reg(CR4F, VIACR, 0x55);
1965                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1966                         viaparinfo->chip_info->gfx_chip_revision =
1967                         CLE266_REVISION_AX;
1968                 else
1969                         viaparinfo->chip_info->gfx_chip_revision =
1970                         CLE266_REVISION_CX;
1971                 /* restore orignal CR4F value */
1972                 viafb_write_reg(CR4F, VIACR, tmp);
1973         }
1974
1975         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1976                 tmp = viafb_read_reg(VIASR, SR43);
1977                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1978                 if (tmp & 0x02) {
1979                         viaparinfo->chip_info->gfx_chip_revision =
1980                                 CX700_REVISION_700M2;
1981                 } else if (tmp & 0x40) {
1982                         viaparinfo->chip_info->gfx_chip_revision =
1983                                 CX700_REVISION_700M;
1984                 } else {
1985                         viaparinfo->chip_info->gfx_chip_revision =
1986                                 CX700_REVISION_700;
1987                 }
1988         }
1989 }
1990
1991 static void init_tmds_chip_info(void)
1992 {
1993         viafb_tmds_trasmitter_identify();
1994
1995         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1996                 output_interface) {
1997                 switch (viaparinfo->chip_info->gfx_chip_name) {
1998                 case UNICHROME_CX700:
1999                         {
2000                                 /* we should check support by hardware layout.*/
2001                                 if ((viafb_display_hardware_layout ==
2002                                      HW_LAYOUT_DVI_ONLY)
2003                                     || (viafb_display_hardware_layout ==
2004                                         HW_LAYOUT_LCD_DVI)) {
2005                                         viaparinfo->chip_info->tmds_chip_info.
2006                                             output_interface = INTERFACE_TMDS;
2007                                 } else {
2008                                         viaparinfo->chip_info->tmds_chip_info.
2009                                                 output_interface =
2010                                                 INTERFACE_NONE;
2011                                 }
2012                                 break;
2013                         }
2014                 case UNICHROME_K8M890:
2015                 case UNICHROME_P4M900:
2016                 case UNICHROME_P4M890:
2017                         /* TMDS on PCIE, we set DFPLOW as default. */
2018                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2019                             INTERFACE_DFP_LOW;
2020                         break;
2021                 default:
2022                         {
2023                                 /* set DVP1 default for DVI */
2024                                 viaparinfo->chip_info->tmds_chip_info
2025                                 .output_interface = INTERFACE_DVP1;
2026                         }
2027                 }
2028         }
2029
2030         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2031                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2032         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2033                 &viaparinfo->shared->tmds_setting_info);
2034 }
2035
2036 static void init_lvds_chip_info(void)
2037 {
2038         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2039                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2040                     GET_LCD_SIZE_BY_VGA_BIOS;
2041         else
2042                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2043                     GET_LCD_SIZE_BY_USER_SETTING;
2044
2045         viafb_lvds_trasmitter_identify();
2046         viafb_init_lcd_size();
2047         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2048                                    viaparinfo->lvds_setting_info);
2049         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2050                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2051                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2052         }
2053         /*If CX700,two singel LCD, we need to reassign
2054            LCD interface to different LVDS port */
2055         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2056             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2057                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2058                         lvds_chip_name) && (INTEGRATED_LVDS ==
2059                         viaparinfo->chip_info->
2060                         lvds_chip_info2.lvds_chip_name)) {
2061                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2062                                 INTERFACE_LVDS0;
2063                         viaparinfo->chip_info->lvds_chip_info2.
2064                                 output_interface =
2065                             INTERFACE_LVDS1;
2066                 }
2067         }
2068
2069         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2070                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2071         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2072                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2073         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2074                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2075 }
2076
2077 void viafb_init_dac(int set_iga)
2078 {
2079         int i;
2080         u8 tmp;
2081
2082         if (set_iga == IGA1) {
2083                 /* access Primary Display's LUT */
2084                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2085                 /* turn off LCK */
2086                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2087                 for (i = 0; i < 256; i++) {
2088                         write_dac_reg(i, palLUT_table[i].red,
2089                                       palLUT_table[i].green,
2090                                       palLUT_table[i].blue);
2091                 }
2092                 /* turn on LCK */
2093                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2094         } else {
2095                 tmp = viafb_read_reg(VIACR, CR6A);
2096                 /* access Secondary Display's LUT */
2097                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2098                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2099                 for (i = 0; i < 256; i++) {
2100                         write_dac_reg(i, palLUT_table[i].red,
2101                                       palLUT_table[i].green,
2102                                       palLUT_table[i].blue);
2103                 }
2104                 /* set IGA1 DAC for default */
2105                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2106                 viafb_write_reg(CR6A, VIACR, tmp);
2107         }
2108 }
2109
2110 static void device_screen_off(void)
2111 {
2112         /* turn off CRT screen (IGA1) */
2113         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2114 }
2115
2116 static void device_screen_on(void)
2117 {
2118         /* turn on CRT screen (IGA1) */
2119         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2120 }
2121
2122 static void set_display_channel(void)
2123 {
2124         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2125         is keeped on lvds_setting_info2 */
2126         if (viafb_LCD2_ON &&
2127                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2128                 /* For dual channel LCD: */
2129                 /* Set to Dual LVDS channel. */
2130                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2131         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2132                 /* For LCD+DFP: */
2133                 /* Set to LVDS1 + TMDS channel. */
2134                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2135         } else if (viafb_DVI_ON) {
2136                 /* Set to single TMDS channel. */
2137                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2138         } else if (viafb_LCD_ON) {
2139                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2140                         /* For dual channel LCD: */
2141                         /* Set to Dual LVDS channel. */
2142                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2143                 } else {
2144                         /* Set to LVDS0 + LVDS1 channel. */
2145                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2146                 }
2147         }
2148 }
2149
2150 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2151         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2152 {
2153         int i, j;
2154         int port;
2155         u8 value, index, mask;
2156         struct crt_mode_table *crt_timing;
2157         struct crt_mode_table *crt_timing1 = NULL;
2158
2159         device_screen_off();
2160         crt_timing = vmode_tbl->crtc;
2161
2162         if (viafb_SAMM_ON == 1) {
2163                 crt_timing1 = vmode_tbl1->crtc;
2164         }
2165
2166         inb(VIAStatus);
2167         outb(0x00, VIAAR);
2168
2169         /* Write Common Setting for Video Mode */
2170         switch (viaparinfo->chip_info->gfx_chip_name) {
2171         case UNICHROME_CLE266:
2172                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2173                 break;
2174
2175         case UNICHROME_K400:
2176                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2177                 break;
2178
2179         case UNICHROME_K800:
2180         case UNICHROME_PM800:
2181                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2182                 break;
2183
2184         case UNICHROME_CN700:
2185         case UNICHROME_K8M890:
2186         case UNICHROME_P4M890:
2187         case UNICHROME_P4M900:
2188                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2189                 break;
2190
2191         case UNICHROME_CX700:
2192         case UNICHROME_VX800:
2193                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2194                 break;
2195
2196         case UNICHROME_VX855:
2197                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2198                 break;
2199         }
2200
2201         device_off();
2202
2203         /* Fill VPIT Parameters */
2204         /* Write Misc Register */
2205         outb(VPIT.Misc, VIAWMisc);
2206
2207         /* Write Sequencer */
2208         for (i = 1; i <= StdSR; i++) {
2209                 outb(i, VIASR);
2210                 outb(VPIT.SR[i - 1], VIASR + 1);
2211         }
2212
2213         viafb_write_reg_mask(0x15, VIASR, viafbinfo->fix.visual
2214                 == FB_VISUAL_PSEUDOCOLOR ? 0x22 : 0xA2, 0xA2);
2215         viafb_set_iga_path();
2216
2217         /* Write CRTC */
2218         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2219
2220         /* Write Graphic Controller */
2221         for (i = 0; i < StdGR; i++) {
2222                 outb(i, VIAGR);
2223                 outb(VPIT.GR[i], VIAGR + 1);
2224         }
2225
2226         /* Write Attribute Controller */
2227         for (i = 0; i < StdAR; i++) {
2228                 inb(VIAStatus);
2229                 outb(i, VIAAR);
2230                 outb(VPIT.AR[i], VIAAR);
2231         }
2232
2233         inb(VIAStatus);
2234         outb(0x20, VIAAR);
2235
2236         /* Update Patch Register */
2237
2238         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2239             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2240             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2241             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2242                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2243                         index = res_patch_table[0].io_reg_table[j].index;
2244                         port = res_patch_table[0].io_reg_table[j].port;
2245                         value = res_patch_table[0].io_reg_table[j].value;
2246                         mask = res_patch_table[0].io_reg_table[j].mask;
2247                         viafb_write_reg_mask(index, port, value, mask);
2248                 }
2249         }
2250
2251         viafb_set_primary_pitch(viafbinfo->fix.line_length);
2252         viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2253                 : viafbinfo->fix.line_length);
2254         viafb_set_primary_color_depth(viaparinfo->depth);
2255         viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2256                 : viaparinfo->depth);
2257         /* Update Refresh Rate Setting */
2258
2259         /* Clear On Screen */
2260
2261         /* CRT set mode */
2262         if (viafb_CRT_ON) {
2263                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2264                         IGA2)) {
2265                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2266                                 video_bpp1 / 8,
2267                                 viaparinfo->crt_setting_info->iga_path);
2268                 } else {
2269                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2270                                 video_bpp / 8,
2271                                 viaparinfo->crt_setting_info->iga_path);
2272                 }
2273
2274                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2275
2276                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2277                 to 8 alignment (1368),there is several pixels (2 pixels)
2278                 on right side of screen. */
2279                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2280                         viafb_unlock_crt();
2281                         viafb_write_reg(CR02, VIACR,
2282                                 viafb_read_reg(VIACR, CR02) - 1);
2283                         viafb_lock_crt();
2284                 }
2285         }
2286
2287         if (viafb_DVI_ON) {
2288                 if (viafb_SAMM_ON &&
2289                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2290                         viafb_dvi_set_mode(viafb_get_mode
2291                                      (viaparinfo->tmds_setting_info->h_active,
2292                                       viaparinfo->tmds_setting_info->
2293                                       v_active),
2294                                      video_bpp1, viaparinfo->
2295                                      tmds_setting_info->iga_path);
2296                 } else {
2297                         viafb_dvi_set_mode(viafb_get_mode
2298                                      (viaparinfo->tmds_setting_info->h_active,
2299                                       viaparinfo->
2300                                       tmds_setting_info->v_active),
2301                                      video_bpp, viaparinfo->
2302                                      tmds_setting_info->iga_path);
2303                 }
2304         }
2305
2306         if (viafb_LCD_ON) {
2307                 if (viafb_SAMM_ON &&
2308                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2309                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2310                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2311                                 lvds_setting_info,
2312                                      &viaparinfo->chip_info->lvds_chip_info);
2313                 } else {
2314                         /* IGA1 doesn't have LCD scaling, so set it center. */
2315                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2316                                 viaparinfo->lvds_setting_info->display_method =
2317                                     LCD_CENTERING;
2318                         }
2319                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2320                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2321                                 lvds_setting_info,
2322                                      &viaparinfo->chip_info->lvds_chip_info);
2323                 }
2324         }
2325         if (viafb_LCD2_ON) {
2326                 if (viafb_SAMM_ON &&
2327                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2328                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2329                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2330                                 lvds_setting_info2,
2331                                      &viaparinfo->chip_info->lvds_chip_info2);
2332                 } else {
2333                         /* IGA1 doesn't have LCD scaling, so set it center. */
2334                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2335                                 viaparinfo->lvds_setting_info2->display_method =
2336                                     LCD_CENTERING;
2337                         }
2338                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2339                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2340                                 lvds_setting_info2,
2341                                      &viaparinfo->chip_info->lvds_chip_info2);
2342                 }
2343         }
2344
2345         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2346             && (viafb_LCD_ON || viafb_DVI_ON))
2347                 set_display_channel();
2348
2349         /* If set mode normally, save resolution information for hot-plug . */
2350         if (!viafb_hotplug) {
2351                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2352                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2353                 viafb_hotplug_bpp = video_bpp;
2354                 viafb_hotplug_refresh = viafb_refresh;
2355
2356                 if (viafb_DVI_ON)
2357                         viafb_DeviceStatus = DVI_Device;
2358                 else
2359                         viafb_DeviceStatus = CRT_Device;
2360         }
2361         device_on();
2362
2363         if (viafb_SAMM_ON == 1)
2364                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2365
2366         device_screen_on();
2367         return 1;
2368 }
2369
2370 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2371 {
2372         int i;
2373
2374         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2375                 if ((hres == res_map_refresh_tbl[i].hres)
2376                     && (vres == res_map_refresh_tbl[i].vres)
2377                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2378                         return res_map_refresh_tbl[i].pixclock;
2379         }
2380         return RES_640X480_60HZ_PIXCLOCK;
2381
2382 }
2383
2384 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2385 {
2386 #define REFRESH_TOLERANCE 3
2387         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2388         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2389                 if ((hres == res_map_refresh_tbl[i].hres)
2390                     && (vres == res_map_refresh_tbl[i].vres)
2391                     && (diff > (abs(long_refresh -
2392                     res_map_refresh_tbl[i].vmode_refresh)))) {
2393                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2394                                 vmode_refresh);
2395                         nearest = i;
2396                 }
2397         }
2398 #undef REFRESH_TOLERANCE
2399         if (nearest > 0)
2400                 return res_map_refresh_tbl[nearest].vmode_refresh;
2401         return 60;
2402 }
2403
2404 static void device_off(void)
2405 {
2406         viafb_crt_disable();
2407         viafb_dvi_disable();
2408         viafb_lcd_disable();
2409 }
2410
2411 static void device_on(void)
2412 {
2413         if (viafb_CRT_ON == 1)
2414                 viafb_crt_enable();
2415         if (viafb_DVI_ON == 1)
2416                 viafb_dvi_enable();
2417         if (viafb_LCD_ON == 1)
2418                 viafb_lcd_enable();
2419 }
2420
2421 void viafb_crt_disable(void)
2422 {
2423         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2424 }
2425
2426 void viafb_crt_enable(void)
2427 {
2428         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2429 }
2430
2431 static void enable_second_display_channel(void)
2432 {
2433         /* to enable second display channel. */
2434         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2435         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2436         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2437 }
2438
2439 static void disable_second_display_channel(void)
2440 {
2441         /* to disable second display channel. */
2442         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2443         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2444         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2445 }
2446
2447 int viafb_get_fb_size_from_pci(void)
2448 {
2449         unsigned long configid, deviceid, FBSize = 0;
2450         int VideoMemSize;
2451         int DeviceFound = false;
2452
2453         for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2454                 outl(configid, (unsigned long)0xCF8);
2455                 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2456
2457                 switch (deviceid) {
2458                 case CLE266:
2459                 case KM400:
2460                         outl(configid + 0xE0, (unsigned long)0xCF8);
2461                         FBSize = inl((unsigned long)0xCFC);
2462                         DeviceFound = true;     /* Found device id */
2463                         break;
2464
2465                 case CN400_FUNCTION3:
2466                 case CN700_FUNCTION3:
2467                 case CX700_FUNCTION3:
2468                 case KM800_FUNCTION3:
2469                 case KM890_FUNCTION3:
2470                 case P4M890_FUNCTION3:
2471                 case P4M900_FUNCTION3:
2472                 case VX800_FUNCTION3:
2473                 case VX855_FUNCTION3:
2474                         /*case CN750_FUNCTION3: */
2475                         outl(configid + 0xA0, (unsigned long)0xCF8);
2476                         FBSize = inl((unsigned long)0xCFC);
2477                         DeviceFound = true;     /* Found device id */
2478                         break;
2479
2480                 default:
2481                         break;
2482                 }
2483
2484                 if (DeviceFound)
2485                         break;
2486         }
2487
2488         DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2489
2490         FBSize = FBSize & 0x00007000;
2491         DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2492
2493         if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2494                 switch (FBSize) {
2495                 case 0x00004000:
2496                         VideoMemSize = (16 << 20);      /*16M */
2497                         break;
2498
2499                 case 0x00005000:
2500                         VideoMemSize = (32 << 20);      /*32M */
2501                         break;
2502
2503                 case 0x00006000:
2504                         VideoMemSize = (64 << 20);      /*64M */
2505                         break;
2506
2507                 default:
2508                         VideoMemSize = (32 << 20);      /*32M */
2509                         break;
2510                 }
2511         } else {
2512                 switch (FBSize) {
2513                 case 0x00001000:
2514                         VideoMemSize = (8 << 20);       /*8M */
2515                         break;
2516
2517                 case 0x00002000:
2518                         VideoMemSize = (16 << 20);      /*16M */
2519                         break;
2520
2521                 case 0x00003000:
2522                         VideoMemSize = (32 << 20);      /*32M */
2523                         break;
2524
2525                 case 0x00004000:
2526                         VideoMemSize = (64 << 20);      /*64M */
2527                         break;
2528
2529                 case 0x00005000:
2530                         VideoMemSize = (128 << 20);     /*128M */
2531                         break;
2532
2533                 case 0x00006000:
2534                         VideoMemSize = (256 << 20);     /*256M */
2535                         break;
2536
2537                 case 0x00007000:        /* Only on VX855/875 */
2538                         VideoMemSize = (512 << 20);     /*512M */
2539                         break;
2540
2541                 default:
2542                         VideoMemSize = (32 << 20);      /*32M */
2543                         break;
2544                 }
2545         }
2546
2547         return VideoMemSize;
2548 }
2549
2550 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2551                                         *p_gfx_dpa_setting)
2552 {
2553         switch (output_interface) {
2554         case INTERFACE_DVP0:
2555                 {
2556                         /* DVP0 Clock Polarity and Adjust: */
2557                         viafb_write_reg_mask(CR96, VIACR,
2558                                        p_gfx_dpa_setting->DVP0, 0x0F);
2559
2560                         /* DVP0 Clock and Data Pads Driving: */
2561                         viafb_write_reg_mask(SR1E, VIASR,
2562                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2563                         viafb_write_reg_mask(SR2A, VIASR,
2564                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2565                                        BIT4);
2566                         viafb_write_reg_mask(SR1B, VIASR,
2567                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2568                         viafb_write_reg_mask(SR2A, VIASR,
2569                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2570                         break;
2571                 }
2572
2573         case INTERFACE_DVP1:
2574                 {
2575                         /* DVP1 Clock Polarity and Adjust: */
2576                         viafb_write_reg_mask(CR9B, VIACR,
2577                                        p_gfx_dpa_setting->DVP1, 0x0F);
2578
2579                         /* DVP1 Clock and Data Pads Driving: */
2580                         viafb_write_reg_mask(SR65, VIASR,
2581                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2582                         break;
2583                 }
2584
2585         case INTERFACE_DFP_HIGH:
2586                 {
2587                         viafb_write_reg_mask(CR97, VIACR,
2588                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2589                         break;
2590                 }
2591
2592         case INTERFACE_DFP_LOW:
2593                 {
2594                         viafb_write_reg_mask(CR99, VIACR,
2595                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2596                         break;
2597                 }
2598
2599         case INTERFACE_DFP:
2600                 {
2601                         viafb_write_reg_mask(CR97, VIACR,
2602                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2603                         viafb_write_reg_mask(CR99, VIACR,
2604                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2605                         break;
2606                 }
2607         }
2608 }
2609
2610 /*According var's xres, yres fill var's other timing information*/
2611 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2612         struct VideoModeTable *vmode_tbl)
2613 {
2614         struct crt_mode_table *crt_timing = NULL;
2615         struct display_timing crt_reg;
2616         int i = 0, index = 0;
2617         crt_timing = vmode_tbl->crtc;
2618         for (i = 0; i < vmode_tbl->mode_array; i++) {
2619                 index = i;
2620                 if (crt_timing[i].refresh_rate == refresh)
2621                         break;
2622         }
2623
2624         crt_reg = crt_timing[index].crtc;
2625         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2626         var->left_margin =
2627             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2628         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2629         var->hsync_len = crt_reg.hor_sync_end;
2630         var->upper_margin =
2631             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2632         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2633         var->vsync_len = crt_reg.ver_sync_end;
2634 }