SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/via/hw.c

   1 /*
   2  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public
   7  * License as published by the Free Software Foundation;
   8  * either version 2, or (at your option) any later version.
   9
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  12  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  13  * A PARTICULAR PURPOSE.See the GNU General Public License
  14  * for more details.
  15
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc.,
  19  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20  */
  21
  22 #include "global.h"
  23
  24 static struct pll_map pll_value[] = {
  25         {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
  26          CX700_25_175M, VX855_25_175M},
  27         {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
  28          CX700_29_581M, VX855_29_581M},
  29         {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
  30          CX700_26_880M, VX855_26_880M},
  31         {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
  32          CX700_31_490M, VX855_31_490M},
  33         {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
  34          CX700_31_500M, VX855_31_500M},
  35         {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
  36          CX700_31_728M, VX855_31_728M},
  37         {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
  38          CX700_32_668M, VX855_32_668M},
  39         {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
  40          CX700_36_000M, VX855_36_000M},
  41         {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
  42          CX700_40_000M, VX855_40_000M},
  43         {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
  44          CX700_41_291M, VX855_41_291M},
  45         {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
  46          CX700_43_163M, VX855_43_163M},
  47         {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
  48          CX700_45_250M, VX855_45_250M},
  49         {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
  50          CX700_46_000M, VX855_46_000M},
  51         {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
  52          CX700_46_996M, VX855_46_996M},
  53         {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
  54          CX700_48_000M, VX855_48_000M},
  55         {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
  56          CX700_48_875M, VX855_48_875M},
  57         {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
  58          CX700_49_500M, VX855_49_500M},
  59         {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
  60          CX700_52_406M, VX855_52_406M},
  61         {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
  62          CX700_52_977M, VX855_52_977M},
  63         {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
  64          CX700_56_250M, VX855_56_250M},
  65         {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
  66          CX700_60_466M, VX855_60_466M},
  67         {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
  68          CX700_61_500M, VX855_61_500M},
  69         {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
  70          CX700_65_000M, VX855_65_000M},
  71         {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
  72          CX700_65_178M, VX855_65_178M},
  73         {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
  74          CX700_66_750M, VX855_66_750M},
  75         {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
  76          CX700_68_179M, VX855_68_179M},
  77         {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
  78          CX700_69_924M, VX855_69_924M},
  79         {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
  80          CX700_70_159M, VX855_70_159M},
  81         {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
  82          CX700_72_000M, VX855_72_000M},
  83         {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
  84          CX700_78_750M, VX855_78_750M},
  85         {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
  86          CX700_80_136M, VX855_80_136M},
  87         {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
  88          CX700_83_375M, VX855_83_375M},
  89         {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
  90          CX700_83_950M, VX855_83_950M},
  91         {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
  92          CX700_84_750M, VX855_84_750M},
  93         {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
  94          CX700_85_860M, VX855_85_860M},
  95         {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
  96          CX700_88_750M, VX855_88_750M},
  97         {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
  98          CX700_94_500M, VX855_94_500M},
  99         {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
 100          CX700_97_750M, VX855_97_750M},
 101         {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
 102          CX700_101_000M, VX855_101_000M},
 103         {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
 104          CX700_106_500M, VX855_106_500M},
 105         {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
 106          CX700_108_000M, VX855_108_000M},
 107         {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
 108          CX700_113_309M, VX855_113_309M},
 109         {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
 110          CX700_118_840M, VX855_118_840M},
 111         {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
 112          CX700_119_000M, VX855_119_000M},
 113         {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
 114          CX700_121_750M, 0},
 115         {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
 116          CX700_125_104M, 0},
 117         {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
 118          CX700_133_308M, 0},
 119         {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
 120          CX700_135_000M, VX855_135_000M},
 121         {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
 122          CX700_136_700M, VX855_136_700M},
 123         {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
 124          CX700_138_400M, VX855_138_400M},
 125         {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
 126          CX700_146_760M, VX855_146_760M},
 127         {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
 128          CX700_153_920M, VX855_153_920M},
 129         {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
 130          CX700_156_000M, VX855_156_000M},
 131         {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
 132          CX700_157_500M, VX855_157_500M},
 133         {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
 134          CX700_162_000M, VX855_162_000M},
 135         {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
 136          CX700_187_000M, VX855_187_000M},
 137         {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
 138          CX700_193_295M, VX855_193_295M},
 139         {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
 140          CX700_202_500M, VX855_202_500M},
 141         {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
 142          CX700_204_000M, VX855_204_000M},
 143         {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
 144          CX700_218_500M, VX855_218_500M},
 145         {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
 146          CX700_234_000M, VX855_234_000M},
 147         {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
 148          CX700_267_250M, VX855_267_250M},
 149         {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
 150          CX700_297_500M, VX855_297_500M},
 151         {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
 152          CX700_74_481M, VX855_74_481M},
 153         {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
 154          CX700_172_798M, VX855_172_798M},
 155         {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
 156          CX700_122_614M, VX855_122_614M},
 157         {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
 158          CX700_74_270M, 0},
 159         {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
 160          CX700_148_500M, VX855_148_500M}
 161 };
 162
 163 static struct fifo_depth_select display_fifo_depth_reg = {
 164         /* IGA1 FIFO Depth_Select */
 165         {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
 166         /* IGA2 FIFO Depth_Select */
 167         {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
 168          {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
 169 };
 170
 171 static struct fifo_threshold_select fifo_threshold_select_reg = {
 172         /* IGA1 FIFO Threshold Select */
 173         {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
 174         /* IGA2 FIFO Threshold Select */
 175         {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
 176 };
 177
 178 static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
 179         /* IGA1 FIFO High Threshold Select */
 180         {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
 181         /* IGA2 FIFO High Threshold Select */
 182         {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
 183 };
 184
 185 static struct display_queue_expire_num display_queue_expire_num_reg = {
 186         /* IGA1 Display Queue Expire Num */
 187         {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
 188         /* IGA2 Display Queue Expire Num */
 189         {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
 190 };
 191
 192 /* Definition Fetch Count Registers*/
 193 static struct fetch_count fetch_count_reg = {
 194         /* IGA1 Fetch Count Register */
 195         {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
 196         /* IGA2 Fetch Count Register */
 197         {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
 198 };
 199
 200 static struct iga1_crtc_timing iga1_crtc_reg = {
 201         /* IGA1 Horizontal Total */
 202         {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
 203         /* IGA1 Horizontal Addressable Video */
 204         {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
 205         /* IGA1 Horizontal Blank Start */
 206         {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
 207         /* IGA1 Horizontal Blank End */
 208         {IGA1_HOR_BLANK_END_REG_NUM,
 209          {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
 210         /* IGA1 Horizontal Sync Start */
 211         {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
 212         /* IGA1 Horizontal Sync End */
 213         {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
 214         /* IGA1 Vertical Total */
 215         {IGA1_VER_TOTAL_REG_NUM,
 216          {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
 217         /* IGA1 Vertical Addressable Video */
 218         {IGA1_VER_ADDR_REG_NUM,
 219          {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
 220         /* IGA1 Vertical Blank Start */
 221         {IGA1_VER_BLANK_START_REG_NUM,
 222          {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
 223         /* IGA1 Vertical Blank End */
 224         {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
 225         /* IGA1 Vertical Sync Start */
 226         {IGA1_VER_SYNC_START_REG_NUM,
 227          {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
 228         /* IGA1 Vertical Sync End */
 229         {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
 230 };
 231
 232 static struct iga2_crtc_timing iga2_crtc_reg = {
 233         /* IGA2 Horizontal Total */
 234         {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
 235         /* IGA2 Horizontal Addressable Video */
 236         {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
 237         /* IGA2 Horizontal Blank Start */
 238         {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
 239         /* IGA2 Horizontal Blank End */
 240         {IGA2_HOR_BLANK_END_REG_NUM,
 241          {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
 242         /* IGA2 Horizontal Sync Start */
 243         {IGA2_HOR_SYNC_START_REG_NUM,
 244          {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
 245         /* IGA2 Horizontal Sync End */
 246         {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
 247         /* IGA2 Vertical Total */
 248         {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
 249         /* IGA2 Vertical Addressable Video */
 250         {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
 251         /* IGA2 Vertical Blank Start */
 252         {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
 253         /* IGA2 Vertical Blank End */
 254         {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
 255         /* IGA2 Vertical Sync Start */
 256         {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
 257         /* IGA2 Vertical Sync End */
 258         {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
 259 };
 260
 261 static struct rgbLUT palLUT_table[] = {
 262         /* {R,G,B} */
 263         /* Index 0x00~0x03 */
 264         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
 265                                                                      0x2A,
 266                                                                      0x2A},
 267         /* Index 0x04~0x07 */
 268         {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
 269                                                                      0x2A,
 270                                                                      0x2A},
 271         /* Index 0x08~0x0B */
 272         {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
 273                                                                      0x3F,
 274                                                                      0x3F},
 275         /* Index 0x0C~0x0F */
 276         {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
 277                                                                      0x3F,
 278                                                                      0x3F},
 279         /* Index 0x10~0x13 */
 280         {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
 281                                                                      0x0B,
 282                                                                      0x0B},
 283         /* Index 0x14~0x17 */
 284         {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
 285                                                                      0x18,
 286                                                                      0x18},
 287         /* Index 0x18~0x1B */
 288         {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
 289                                                                      0x28,
 290                                                                      0x28},
 291         /* Index 0x1C~0x1F */
 292         {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
 293                                                                      0x3F,
 294                                                                      0x3F},
 295         /* Index 0x20~0x23 */
 296         {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
 297                                                                      0x00,
 298                                                                      0x3F},
 299         /* Index 0x24~0x27 */
 300         {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
 301                                                                      0x00,
 302                                                                      0x10},
 303         /* Index 0x28~0x2B */
 304         {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
 305                                                                      0x2F,
 306                                                                      0x00},
 307         /* Index 0x2C~0x2F */
 308         {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
 309                                                                      0x3F,
 310                                                                      0x00},
 311         /* Index 0x30~0x33 */
 312         {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
 313                                                                      0x3F,
 314                                                                      0x2F},
 315         /* Index 0x34~0x37 */
 316         {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
 317                                                                      0x10,
 318                                                                      0x3F},
 319         /* Index 0x38~0x3B */
 320         {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
 321                                                                      0x1F,
 322                                                                      0x3F},
 323         /* Index 0x3C~0x3F */
 324         {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
 325                                                                      0x1F,
 326                                                                      0x27},
 327         /* Index 0x40~0x43 */
 328         {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
 329                                                                      0x3F,
 330                                                                      0x1F},
 331         /* Index 0x44~0x47 */
 332         {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
 333                                                                      0x3F,
 334                                                                      0x1F},
 335         /* Index 0x48~0x4B */
 336         {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
 337                                                                      0x3F,
 338                                                                      0x37},
 339         /* Index 0x4C~0x4F */
 340         {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
 341                                                                      0x27,
 342                                                                      0x3F},
 343         /* Index 0x50~0x53 */
 344         {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
 345                                                                      0x2D,
 346                                                                      0x3F},
 347         /* Index 0x54~0x57 */
 348         {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
 349                                                                      0x2D,
 350                                                                      0x31},
 351         /* Index 0x58~0x5B */
 352         {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
 353                                                                      0x3A,
 354                                                                      0x2D},
 355         /* Index 0x5C~0x5F */
 356         {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
 357                                                                      0x3F,
 358                                                                      0x2D},
 359         /* Index 0x60~0x63 */
 360         {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
 361                                                                      0x3F,
 362                                                                      0x3A},
 363         /* Index 0x64~0x67 */
 364         {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
 365                                                                      0x31,
 366                                                                      0x3F},
 367         /* Index 0x68~0x6B */
 368         {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
 369                                                                      0x00,
 370                                                                      0x1C},
 371         /* Index 0x6C~0x6F */
 372         {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
 373                                                                      0x00,
 374                                                                      0x07},
 375         /* Index 0x70~0x73 */
 376         {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
 377                                                                      0x15,
 378                                                                      0x00},
 379         /* Index 0x74~0x77 */
 380         {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
 381                                                                      0x1C,
 382                                                                      0x00},
 383         /* Index 0x78~0x7B */
 384         {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
 385                                                                      0x1C,
 386                                                                      0x15},
 387         /* Index 0x7C~0x7F */
 388         {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
 389                                                                      0x07,
 390                                                                      0x1C},
 391         /* Index 0x80~0x83 */
 392         {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
 393                                                                      0x0E,
 394                                                                      0x1C},
 395         /* Index 0x84~0x87 */
 396         {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
 397                                                                      0x0E,
 398                                                                      0x11},
 399         /* Index 0x88~0x8B */
 400         {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
 401                                                                      0x18,
 402                                                                      0x0E},
 403         /* Index 0x8C~0x8F */
 404         {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
 405                                                                      0x1C,
 406                                                                      0x0E},
 407         /* Index 0x90~0x93 */
 408         {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
 409                                                                      0x1C,
 410                                                                      0x18},
 411         /* Index 0x94~0x97 */
 412         {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
 413                                                                      0x11,
 414                                                                      0x1C},
 415         /* Index 0x98~0x9B */
 416         {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
 417                                                                      0x14,
 418                                                                      0x1C},
 419         /* Index 0x9C~0x9F */
 420         {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
 421                                                                      0x14,
 422                                                                      0x16},
 423         /* Index 0xA0~0xA3 */
 424         {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
 425                                                                      0x1A,
 426                                                                      0x14},
 427         /* Index 0xA4~0xA7 */
 428         {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
 429                                                                      0x1C,
 430                                                                      0x14},
 431         /* Index 0xA8~0xAB */
 432         {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
 433                                                                      0x1C,
 434                                                                      0x1A},
 435         /* Index 0xAC~0xAF */
 436         {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
 437                                                                      0x16,
 438                                                                      0x1C},
 439         /* Index 0xB0~0xB3 */
 440         {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
 441                                                                      0x00,
 442                                                                      0x10},
 443         /* Index 0xB4~0xB7 */
 444         {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
 445                                                                      0x00,
 446                                                                      0x04},
 447         /* Index 0xB8~0xBB */
 448         {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
 449                                                                      0x0C,
 450                                                                      0x00},
 451         /* Index 0xBC~0xBF */
 452         {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
 453                                                                      0x10,
 454                                                                      0x00},
 455         /* Index 0xC0~0xC3 */
 456         {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
 457                                                                      0x10,
 458                                                                      0x0C},
 459         /* Index 0xC4~0xC7 */
 460         {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
 461                                                                      0x04,
 462                                                                      0x10},
 463         /* Index 0xC8~0xCB */
 464         {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
 465                                                                      0x08,
 466                                                                      0x10},
 467         /* Index 0xCC~0xCF */
 468         {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
 469                                                                      0x08,
 470                                                                      0x0A},
 471         /* Index 0xD0~0xD3 */
 472         {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
 473                                                                      0x0E,
 474                                                                      0x08},
 475         /* Index 0xD4~0xD7 */
 476         {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
 477                                                                      0x10,
 478                                                                      0x08},
 479         /* Index 0xD8~0xDB */
 480         {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
 481                                                                      0x10,
 482                                                                      0x0E},
 483         /* Index 0xDC~0xDF */
 484         {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
 485                                                                      0x0A,
 486                                                                      0x10},
 487         /* Index 0xE0~0xE3 */
 488         {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
 489                                                                      0x0B,
 490                                                                      0x10},
 491         /* Index 0xE4~0xE7 */
 492         {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
 493                                                                      0x0B,
 494                                                                      0x0C},
 495         /* Index 0xE8~0xEB */
 496         {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
 497                                                                      0x0F,
 498                                                                      0x0B},
 499         /* Index 0xEC~0xEF */
 500         {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
 501                                                                      0x10,
 502                                                                      0x0B},
 503         /* Index 0xF0~0xF3 */
 504         {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
 505                                                                      0x10,
 506                                                                      0x0F},
 507         /* Index 0xF4~0xF7 */
 508         {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
 509                                                                      0x0C,
 510                                                                      0x10},
 511         /* Index 0xF8~0xFB */
 512         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 513                                                                      0x00,
 514                                                                      0x00},
 515         /* Index 0xFC~0xFF */
 516         {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
 517                                                                      0x00,
 518                                                                      0x00}
 519 };
 520
 521 static void set_crt_output_path(int set_iga);
 522 static void dvi_patch_skew_dvp0(void);
 523 static void dvi_patch_skew_dvp1(void);
 524 static void dvi_patch_skew_dvp_low(void);
 525 static void set_dvi_output_path(int set_iga, int output_interface);
 526 static void set_lcd_output_path(int set_iga, int output_interface);
 527 static void load_fix_bit_crtc_reg(void);
 528 static void init_gfx_chip_info(struct pci_dev *pdev,
 529                                 const struct pci_device_id *pdi);
 530 static void init_tmds_chip_info(void);
 531 static void init_lvds_chip_info(void);
 532 static void device_screen_off(void);
 533 static void device_screen_on(void);
 534 static void set_display_channel(void);
 535 static void device_off(void);
 536 static void device_on(void);
 537 static void enable_second_display_channel(void);
 538 static void disable_second_display_channel(void);
 539
 540 void viafb_write_reg(u8 index, u16 io_port, u8 data)
 541 {
 542         outb(index, io_port);
 543         outb(data, io_port + 1);
 544         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
 545 }
 546 u8 viafb_read_reg(int io_port, u8 index)
 547 {
 548         outb(index, io_port);
 549         return inb(io_port + 1);
 550 }
 551
 552 void viafb_lock_crt(void)
 553 {
 554         viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
 555 }
 556
 557 void viafb_unlock_crt(void)
 558 {
 559         viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
 560         viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
 561 }
 562
 563 void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
 564 {
 565         u8 tmp;
 566
 567         outb(index, io_port);
 568         tmp = inb(io_port + 1);
 569         outb((data & mask) | (tmp & (~mask)), io_port + 1);
 570         /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
 571 }
 572
 573 void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
 574 {
 575         outb(index, LUT_INDEX_WRITE);
 576         outb(r, LUT_DATA);
 577         outb(g, LUT_DATA);
 578         outb(b, LUT_DATA);
 579 }
 580
 581 /*Set IGA path for each device*/
 582 void viafb_set_iga_path(void)
 583 {
 584
 585         if (viafb_SAMM_ON == 1) {
 586                 if (viafb_CRT_ON) {
 587                         if (viafb_primary_dev == CRT_Device)
 588                                 viaparinfo->crt_setting_info->iga_path = IGA1;
 589                         else
 590                                 viaparinfo->crt_setting_info->iga_path = IGA2;
 591                 }
 592
 593                 if (viafb_DVI_ON) {
 594                         if (viafb_primary_dev == DVI_Device)
 595                                 viaparinfo->tmds_setting_info->iga_path = IGA1;
 596                         else
 597                                 viaparinfo->tmds_setting_info->iga_path = IGA2;
 598                 }
 599
 600                 if (viafb_LCD_ON) {
 601                         if (viafb_primary_dev == LCD_Device) {
 602                                 if (viafb_dual_fb &&
 603                                         (viaparinfo->chip_info->gfx_chip_name ==
 604                                         UNICHROME_CLE266)) {
 605                                         viaparinfo->
 606                                         lvds_setting_info->iga_path = IGA2;
 607                                         viaparinfo->
 608                                         crt_setting_info->iga_path = IGA1;
 609                                         viaparinfo->
 610                                         tmds_setting_info->iga_path = IGA1;
 611                                 } else
 612                                         viaparinfo->
 613                                         lvds_setting_info->iga_path = IGA1;
 614                         } else {
 615                                 viaparinfo->lvds_setting_info->iga_path = IGA2;
 616                         }
 617                 }
 618                 if (viafb_LCD2_ON) {
 619                         if (LCD2_Device == viafb_primary_dev)
 620                                 viaparinfo->lvds_setting_info2->iga_path = IGA1;
 621                         else
 622                                 viaparinfo->lvds_setting_info2->iga_path = IGA2;
 623                 }
 624         } else {
 625                 viafb_SAMM_ON = 0;
 626
 627                 if (viafb_CRT_ON && viafb_LCD_ON) {
 628                         viaparinfo->crt_setting_info->iga_path = IGA1;
 629                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 630                 } else if (viafb_CRT_ON && viafb_DVI_ON) {
 631                         viaparinfo->crt_setting_info->iga_path = IGA1;
 632                         viaparinfo->tmds_setting_info->iga_path = IGA2;
 633                 } else if (viafb_LCD_ON && viafb_DVI_ON) {
 634                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 635                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 636                 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
 637                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 638                         viaparinfo->lvds_setting_info2->iga_path = IGA2;
 639                 } else if (viafb_CRT_ON) {
 640                         viaparinfo->crt_setting_info->iga_path = IGA1;
 641                 } else if (viafb_LCD_ON) {
 642                         viaparinfo->lvds_setting_info->iga_path = IGA2;
 643                 } else if (viafb_DVI_ON) {
 644                         viaparinfo->tmds_setting_info->iga_path = IGA1;
 645                 }
 646         }
 647 }
 648
 649 void viafb_set_primary_address(u32 addr)
 650 {
 651         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
 652         viafb_write_reg(CR0D, VIACR, addr & 0xFF);
 653         viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
 654         viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
 655         viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
 656 }
 657
 658 void viafb_set_secondary_address(u32 addr)
 659 {
 660         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
 661         /* secondary display supports only quadword aligned memory */
 662         viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
 663         viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
 664         viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
 665         viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
 666 }
 667
 668 void viafb_set_primary_pitch(u32 pitch)
 669 {
 670         DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
 671         /* spec does not say that first adapter skips 3 bits but old
 672          * code did it and seems to be reasonable in analogy to 2nd adapter
 673          */
 674         pitch = pitch >> 3;
 675         viafb_write_reg(0x13, VIACR, pitch & 0xFF);
 676         viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
 677 }
 678
 679 void viafb_set_secondary_pitch(u32 pitch)
 680 {
 681         DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
 682         pitch = pitch >> 3;
 683         viafb_write_reg(0x66, VIACR, pitch & 0xFF);
 684         viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
 685         viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
 686 }
 687
 688 void viafb_set_output_path(int device, int set_iga, int output_interface)
 689 {
 690         switch (device) {
 691         case DEVICE_CRT:
 692                 set_crt_output_path(set_iga);
 693                 break;
 694         case DEVICE_DVI:
 695                 set_dvi_output_path(set_iga, output_interface);
 696                 break;
 697         case DEVICE_LCD:
 698                 set_lcd_output_path(set_iga, output_interface);
 699                 break;
 700         }
 701 }
 702
 703 static void set_crt_output_path(int set_iga)
 704 {
 705         viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
 706
 707         switch (set_iga) {
 708         case IGA1:
 709                 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
 710                 break;
 711         case IGA2:
 712         case IGA1_IGA2:
 713                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
 714                 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
 715                 if (set_iga == IGA1_IGA2)
 716                         viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
 717                 break;
 718         }
 719 }
 720
 721 static void dvi_patch_skew_dvp0(void)
 722 {
 723         /* Reset data driving first: */
 724         viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
 725         viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
 726
 727         switch (viaparinfo->chip_info->gfx_chip_name) {
 728         case UNICHROME_P4M890:
 729                 {
 730                         if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
 731                                 (viaparinfo->tmds_setting_info->v_active ==
 732                                 1200))
 733                                 viafb_write_reg_mask(CR96, VIACR, 0x03,
 734                                                BIT0 + BIT1 + BIT2);
 735                         else
 736                                 viafb_write_reg_mask(CR96, VIACR, 0x07,
 737                                                BIT0 + BIT1 + BIT2);
 738                         break;
 739                 }
 740
 741         case UNICHROME_P4M900:
 742                 {
 743                         viafb_write_reg_mask(CR96, VIACR, 0x07,
 744                                        BIT0 + BIT1 + BIT2 + BIT3);
 745                         viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
 746                         viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
 747                         break;
 748                 }
 749
 750         default:
 751                 {
 752                         break;
 753                 }
 754         }
 755 }
 756
 757 static void dvi_patch_skew_dvp1(void)
 758 {
 759         switch (viaparinfo->chip_info->gfx_chip_name) {
 760         case UNICHROME_CX700:
 761                 {
 762                         break;
 763                 }
 764
 765         default:
 766                 {
 767                         break;
 768                 }
 769         }
 770 }
 771
 772 static void dvi_patch_skew_dvp_low(void)
 773 {
 774         switch (viaparinfo->chip_info->gfx_chip_name) {
 775         case UNICHROME_K8M890:
 776                 {
 777                         viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
 778                         break;
 779                 }
 780
 781         case UNICHROME_P4M900:
 782                 {
 783                         viafb_write_reg_mask(CR99, VIACR, 0x08,
 784                                        BIT0 + BIT1 + BIT2 + BIT3);
 785                         break;
 786                 }
 787
 788         case UNICHROME_P4M890:
 789                 {
 790                         viafb_write_reg_mask(CR99, VIACR, 0x0F,
 791                                        BIT0 + BIT1 + BIT2 + BIT3);
 792                         break;
 793                 }
 794
 795         default:
 796                 {
 797                         break;
 798                 }
 799         }
 800 }
 801
 802 static void set_dvi_output_path(int set_iga, int output_interface)
 803 {
 804         switch (output_interface) {
 805         case INTERFACE_DVP0:
 806                 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
 807
 808                 if (set_iga == IGA1) {
 809                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 810                         viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
 811                                 BIT5 + BIT7);
 812                 } else {
 813                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 814                         viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
 815                                 BIT5 + BIT7);
 816                 }
 817
 818                 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
 819
 820                 dvi_patch_skew_dvp0();
 821                 break;
 822
 823         case INTERFACE_DVP1:
 824                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
 825                         if (set_iga == IGA1)
 826                                 viafb_write_reg_mask(CR93, VIACR, 0x21,
 827                                                BIT0 + BIT5 + BIT7);
 828                         else
 829                                 viafb_write_reg_mask(CR93, VIACR, 0xA1,
 830                                                BIT0 + BIT5 + BIT7);
 831                 } else {
 832                         if (set_iga == IGA1)
 833                                 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 834                         else
 835                                 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 836                 }
 837
 838                 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
 839                 dvi_patch_skew_dvp1();
 840                 break;
 841         case INTERFACE_DFP_HIGH:
 842                 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
 843                         if (set_iga == IGA1) {
 844                                 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 845                                 viafb_write_reg_mask(CR97, VIACR, 0x03,
 846                                                BIT0 + BIT1 + BIT4);
 847                         } else {
 848                                 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 849                                 viafb_write_reg_mask(CR97, VIACR, 0x13,
 850                                                BIT0 + BIT1 + BIT4);
 851                         }
 852                 }
 853                 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
 854                 break;
 855
 856         case INTERFACE_DFP_LOW:
 857                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
 858                         break;
 859
 860                 if (set_iga == IGA1) {
 861                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 862                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 863                 } else {
 864                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 865                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 866                 }
 867
 868                 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
 869                 dvi_patch_skew_dvp_low();
 870                 break;
 871
 872         case INTERFACE_TMDS:
 873                 if (set_iga == IGA1)
 874                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 875                 else
 876                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 877                 break;
 878         }
 879
 880         if (set_iga == IGA2) {
 881                 enable_second_display_channel();
 882                 /* Disable LCD Scaling */
 883                 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
 884         }
 885 }
 886
 887 static void set_lcd_output_path(int set_iga, int output_interface)
 888 {
 889         DEBUG_MSG(KERN_INFO
 890                   "set_lcd_output_path, iga:%d,out_interface:%d\n",
 891                   set_iga, output_interface);
 892         switch (set_iga) {
 893         case IGA1:
 894                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 895                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 896
 897                 disable_second_display_channel();
 898                 break;
 899
 900         case IGA2:
 901                 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
 902                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 903
 904                 enable_second_display_channel();
 905                 break;
 906
 907         case IGA1_IGA2:
 908                 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
 909                 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
 910
 911                 disable_second_display_channel();
 912                 break;
 913         }
 914
 915         switch (output_interface) {
 916         case INTERFACE_DVP0:
 917                 if (set_iga == IGA1) {
 918                         viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
 919                 } else {
 920                         viafb_write_reg(CR91, VIACR, 0x00);
 921                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 922                 }
 923                 break;
 924
 925         case INTERFACE_DVP1:
 926                 if (set_iga == IGA1)
 927                         viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
 928                 else {
 929                         viafb_write_reg(CR91, VIACR, 0x00);
 930                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 931                 }
 932                 break;
 933
 934         case INTERFACE_DFP_HIGH:
 935                 if (set_iga == IGA1)
 936                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 937                 else {
 938                         viafb_write_reg(CR91, VIACR, 0x00);
 939                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 940                         viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
 941                 }
 942                 break;
 943
 944         case INTERFACE_DFP_LOW:
 945                 if (set_iga == IGA1)
 946                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 947                 else {
 948                         viafb_write_reg(CR91, VIACR, 0x00);
 949                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 950                         viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
 951                 }
 952
 953                 break;
 954
 955         case INTERFACE_DFP:
 956                 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
 957                     || (UNICHROME_P4M890 ==
 958                     viaparinfo->chip_info->gfx_chip_name))
 959                         viafb_write_reg_mask(CR97, VIACR, 0x84,
 960                                        BIT7 + BIT2 + BIT1 + BIT0);
 961                 if (set_iga == IGA1) {
 962                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 963                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 964                 } else {
 965                         viafb_write_reg(CR91, VIACR, 0x00);
 966                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 967                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 968                 }
 969                 break;
 970
 971         case INTERFACE_LVDS0:
 972         case INTERFACE_LVDS0LVDS1:
 973                 if (set_iga == IGA1)
 974                         viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
 975                 else
 976                         viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
 977
 978                 break;
 979
 980         case INTERFACE_LVDS1:
 981                 if (set_iga == IGA1)
 982                         viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
 983                 else
 984                         viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
 985                 break;
 986         }
 987 }
 988
 989 static void load_fix_bit_crtc_reg(void)
 990 {
 991         /* always set to 1 */
 992         viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
 993         /* line compare should set all bits = 1 (extend modes) */
 994         viafb_write_reg(CR18, VIACR, 0xff);
 995         /* line compare should set all bits = 1 (extend modes) */
 996         viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
 997         /* line compare should set all bits = 1 (extend modes) */
 998         viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
 999         /* line compare should set all bits = 1 (extend modes) */
1000         viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1001         /* line compare should set all bits = 1 (extend modes) */
1002         viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1003         /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1004         /* extend mode always set to e3h */
1005         viafb_write_reg(CR17, VIACR, 0xe3);
1006         /* extend mode always set to 0h */
1007         viafb_write_reg(CR08, VIACR, 0x00);
1008         /* extend mode always set to 0h */
1009         viafb_write_reg(CR14, VIACR, 0x00);
1010
1011         /* If K8M800, enable Prefetch Mode. */
1012         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1013                 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1014                 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1015         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1016             && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1017                 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1018
1019 }
1020
1021 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1022         struct io_register *reg,
1023               int io_type)
1024 {
1025         int reg_mask;
1026         int bit_num = 0;
1027         int data;
1028         int i, j;
1029         int shift_next_reg;
1030         int start_index, end_index, cr_index;
1031         u16 get_bit;
1032
1033         for (i = 0; i < viafb_load_reg_num; i++) {
1034                 reg_mask = 0;
1035                 data = 0;
1036                 start_index = reg[i].start_bit;
1037                 end_index = reg[i].end_bit;
1038                 cr_index = reg[i].io_addr;
1039
1040                 shift_next_reg = bit_num;
1041                 for (j = start_index; j <= end_index; j++) {
1042                         /*if (bit_num==8) timing_value = timing_value >>8; */
1043                         reg_mask = reg_mask | (BIT0 << j);
1044                         get_bit = (timing_value & (BIT0 << bit_num));
1045                         data =
1046                             data | ((get_bit >> shift_next_reg) << start_index);
1047                         bit_num++;
1048                 }
1049                 if (io_type == VIACR)
1050                         viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1051                 else
1052                         viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1053         }
1054
1055 }
1056
1057 /* Write Registers */
1058 void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1059 {
1060         int i;
1061         unsigned char RegTemp;
1062
1063         /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1064
1065         for (i = 0; i < ItemNum; i++) {
1066                 outb(RegTable[i].index, RegTable[i].port);
1067                 RegTemp = inb(RegTable[i].port + 1);
1068                 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1069                 outb(RegTemp, RegTable[i].port + 1);
1070         }
1071 }
1072
1073 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1074 {
1075         int reg_value;
1076         int viafb_load_reg_num;
1077         struct io_register *reg = NULL;
1078
1079         switch (set_iga) {
1080         case IGA1_IGA2:
1081         case IGA1:
1082                 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1083                 viafb_load_reg_num = fetch_count_reg.
1084                         iga1_fetch_count_reg.reg_num;
1085                 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1086                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1087                 if (set_iga == IGA1)
1088                         break;
1089         case IGA2:
1090                 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1091                 viafb_load_reg_num = fetch_count_reg.
1092                         iga2_fetch_count_reg.reg_num;
1093                 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1094                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1095                 break;
1096         }
1097
1098 }
1099
1100 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1101 {
1102         int reg_value;
1103         int viafb_load_reg_num;
1104         struct io_register *reg = NULL;
1105         int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1106             0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1107         int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1108             0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1109
1110         if (set_iga == IGA1) {
1111                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1112                         iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1113                         iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1114                         iga1_fifo_high_threshold =
1115                             K800_IGA1_FIFO_HIGH_THRESHOLD;
1116                         /* If resolution > 1280x1024, expire length = 64, else
1117                            expire length = 128 */
1118                         if ((hor_active > 1280) && (ver_active > 1024))
1119                                 iga1_display_queue_expire_num = 16;
1120                         else
1121                                 iga1_display_queue_expire_num =
1122                                     K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1123
1124                 }
1125
1126                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1127                         iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1128                         iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1129                         iga1_fifo_high_threshold =
1130                             P880_IGA1_FIFO_HIGH_THRESHOLD;
1131                         iga1_display_queue_expire_num =
1132                             P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1133
1134                         /* If resolution > 1280x1024, expire length = 64, else
1135                            expire length = 128 */
1136                         if ((hor_active > 1280) && (ver_active > 1024))
1137                                 iga1_display_queue_expire_num = 16;
1138                         else
1139                                 iga1_display_queue_expire_num =
1140                                     P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1141                 }
1142
1143                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1144                         iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1145                         iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1146                         iga1_fifo_high_threshold =
1147                             CN700_IGA1_FIFO_HIGH_THRESHOLD;
1148
1149                         /* If resolution > 1280x1024, expire length = 64,
1150                            else expire length = 128 */
1151                         if ((hor_active > 1280) && (ver_active > 1024))
1152                                 iga1_display_queue_expire_num = 16;
1153                         else
1154                                 iga1_display_queue_expire_num =
1155                                     CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1156                 }
1157
1158                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1159                         iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1160                         iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1161                         iga1_fifo_high_threshold =
1162                             CX700_IGA1_FIFO_HIGH_THRESHOLD;
1163                         iga1_display_queue_expire_num =
1164                             CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1165                 }
1166
1167                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1168                         iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1169                         iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1170                         iga1_fifo_high_threshold =
1171                             K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1172                         iga1_display_queue_expire_num =
1173                             K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1174                 }
1175
1176                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1177                         iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1178                         iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1179                         iga1_fifo_high_threshold =
1180                             P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1181                         iga1_display_queue_expire_num =
1182                             P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1183                 }
1184
1185                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1186                         iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1187                         iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1188                         iga1_fifo_high_threshold =
1189                             P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1190                         iga1_display_queue_expire_num =
1191                             P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1192                 }
1193
1194                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1195                         iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1196                         iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1197                         iga1_fifo_high_threshold =
1198                             VX800_IGA1_FIFO_HIGH_THRESHOLD;
1199                         iga1_display_queue_expire_num =
1200                             VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1201                 }
1202
1203                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1204                         iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
1205                         iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
1206                         iga1_fifo_high_threshold =
1207                             VX855_IGA1_FIFO_HIGH_THRESHOLD;
1208                         iga1_display_queue_expire_num =
1209                             VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1210                 }
1211
1212                 /* Set Display FIFO Depath Select */
1213                 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1214                 viafb_load_reg_num =
1215                     display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1216                 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1217                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1218
1219                 /* Set Display FIFO Threshold Select */
1220                 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1221                 viafb_load_reg_num =
1222                     fifo_threshold_select_reg.
1223                     iga1_fifo_threshold_select_reg.reg_num;
1224                 reg =
1225                     fifo_threshold_select_reg.
1226                     iga1_fifo_threshold_select_reg.reg;
1227                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1228
1229                 /* Set FIFO High Threshold Select */
1230                 reg_value =
1231                     IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1232                 viafb_load_reg_num =
1233                     fifo_high_threshold_select_reg.
1234                     iga1_fifo_high_threshold_select_reg.reg_num;
1235                 reg =
1236                     fifo_high_threshold_select_reg.
1237                     iga1_fifo_high_threshold_select_reg.reg;
1238                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1239
1240                 /* Set Display Queue Expire Num */
1241                 reg_value =
1242                     IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1243                     (iga1_display_queue_expire_num);
1244                 viafb_load_reg_num =
1245                     display_queue_expire_num_reg.
1246                     iga1_display_queue_expire_num_reg.reg_num;
1247                 reg =
1248                     display_queue_expire_num_reg.
1249                     iga1_display_queue_expire_num_reg.reg;
1250                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1251
1252         } else {
1253                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1254                         iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1255                         iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1256                         iga2_fifo_high_threshold =
1257                             K800_IGA2_FIFO_HIGH_THRESHOLD;
1258
1259                         /* If resolution > 1280x1024, expire length = 64,
1260                            else  expire length = 128 */
1261                         if ((hor_active > 1280) && (ver_active > 1024))
1262                                 iga2_display_queue_expire_num = 16;
1263                         else
1264                                 iga2_display_queue_expire_num =
1265                                     K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1266                 }
1267
1268                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1269                         iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1270                         iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1271                         iga2_fifo_high_threshold =
1272                             P880_IGA2_FIFO_HIGH_THRESHOLD;
1273
1274                         /* If resolution > 1280x1024, expire length = 64,
1275                            else  expire length = 128 */
1276                         if ((hor_active > 1280) && (ver_active > 1024))
1277                                 iga2_display_queue_expire_num = 16;
1278                         else
1279                                 iga2_display_queue_expire_num =
1280                                     P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1281                 }
1282
1283                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1284                         iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1285                         iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1286                         iga2_fifo_high_threshold =
1287                             CN700_IGA2_FIFO_HIGH_THRESHOLD;
1288
1289                         /* If resolution > 1280x1024, expire length = 64,
1290                            else expire length = 128 */
1291                         if ((hor_active > 1280) && (ver_active > 1024))
1292                                 iga2_display_queue_expire_num = 16;
1293                         else
1294                                 iga2_display_queue_expire_num =
1295                                     CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1296                 }
1297
1298                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1299                         iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1300                         iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1301                         iga2_fifo_high_threshold =
1302                             CX700_IGA2_FIFO_HIGH_THRESHOLD;
1303                         iga2_display_queue_expire_num =
1304                             CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1305                 }
1306
1307                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1308                         iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1309                         iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1310                         iga2_fifo_high_threshold =
1311                             K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1312                         iga2_display_queue_expire_num =
1313                             K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1314                 }
1315
1316                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1317                         iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1318                         iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1319                         iga2_fifo_high_threshold =
1320                             P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1321                         iga2_display_queue_expire_num =
1322                             P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1323                 }
1324
1325                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1326                         iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1327                         iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1328                         iga2_fifo_high_threshold =
1329                             P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1330                         iga2_display_queue_expire_num =
1331                             P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1332                 }
1333
1334                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1335                         iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1336                         iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1337                         iga2_fifo_high_threshold =
1338                             VX800_IGA2_FIFO_HIGH_THRESHOLD;
1339                         iga2_display_queue_expire_num =
1340                             VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1341                 }
1342
1343                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
1344                         iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
1345                         iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
1346                         iga2_fifo_high_threshold =
1347                             VX855_IGA2_FIFO_HIGH_THRESHOLD;
1348                         iga2_display_queue_expire_num =
1349                             VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1350                 }
1351
1352                 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1353                         /* Set Display FIFO Depath Select */
1354                         reg_value =
1355                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1356                             - 1;
1357                         /* Patch LCD in IGA2 case */
1358                         viafb_load_reg_num =
1359                             display_fifo_depth_reg.
1360                             iga2_fifo_depth_select_reg.reg_num;
1361                         reg =
1362                             display_fifo_depth_reg.
1363                             iga2_fifo_depth_select_reg.reg;
1364                         viafb_load_reg(reg_value,
1365                                 viafb_load_reg_num, reg, VIACR);
1366                 } else {
1367
1368                         /* Set Display FIFO Depath Select */
1369                         reg_value =
1370                             IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1371                         viafb_load_reg_num =
1372                             display_fifo_depth_reg.
1373                             iga2_fifo_depth_select_reg.reg_num;
1374                         reg =
1375                             display_fifo_depth_reg.
1376                             iga2_fifo_depth_select_reg.reg;
1377                         viafb_load_reg(reg_value,
1378                                 viafb_load_reg_num, reg, VIACR);
1379                 }
1380
1381                 /* Set Display FIFO Threshold Select */
1382                 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1383                 viafb_load_reg_num =
1384                     fifo_threshold_select_reg.
1385                     iga2_fifo_threshold_select_reg.reg_num;
1386                 reg =
1387                     fifo_threshold_select_reg.
1388                     iga2_fifo_threshold_select_reg.reg;
1389                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1390
1391                 /* Set FIFO High Threshold Select */
1392                 reg_value =
1393                     IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1394                 viafb_load_reg_num =
1395                     fifo_high_threshold_select_reg.
1396                     iga2_fifo_high_threshold_select_reg.reg_num;
1397                 reg =
1398                     fifo_high_threshold_select_reg.
1399                     iga2_fifo_high_threshold_select_reg.reg;
1400                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1401
1402                 /* Set Display Queue Expire Num */
1403                 reg_value =
1404                     IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1405                     (iga2_display_queue_expire_num);
1406                 viafb_load_reg_num =
1407                     display_queue_expire_num_reg.
1408                     iga2_display_queue_expire_num_reg.reg_num;
1409                 reg =
1410                     display_queue_expire_num_reg.
1411                     iga2_display_queue_expire_num_reg.reg;
1412                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1413
1414         }
1415
1416 }
1417
1418 u32 viafb_get_clk_value(int clk)
1419 {
1420         int i;
1421
1422         for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1423                 if (clk == pll_value[i].clk) {
1424                         switch (viaparinfo->chip_info->gfx_chip_name) {
1425                         case UNICHROME_CLE266:
1426                         case UNICHROME_K400:
1427                                 return pll_value[i].cle266_pll;
1428
1429                         case UNICHROME_K800:
1430                         case UNICHROME_PM800:
1431                         case UNICHROME_CN700:
1432                                 return pll_value[i].k800_pll;
1433
1434                         case UNICHROME_CX700:
1435                         case UNICHROME_K8M890:
1436                         case UNICHROME_P4M890:
1437                         case UNICHROME_P4M900:
1438                         case UNICHROME_VX800:
1439                                 return pll_value[i].cx700_pll;
1440                         case UNICHROME_VX855:
1441                                 return pll_value[i].vx855_pll;
1442                         }
1443                 }
1444         }
1445
1446         DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1447         return 0;
1448 }
1449
1450 /* Set VCLK*/
1451 void viafb_set_vclock(u32 CLK, int set_iga)
1452 {
1453         unsigned char RegTemp;
1454
1455         /* H.W. Reset : ON */
1456         viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1457
1458         if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1459                 /* Change D,N FOR VCLK */
1460                 switch (viaparinfo->chip_info->gfx_chip_name) {
1461                 case UNICHROME_CLE266:
1462                 case UNICHROME_K400:
1463                         viafb_write_reg(SR46, VIASR, CLK / 0x100);
1464                         viafb_write_reg(SR47, VIASR, CLK % 0x100);
1465                         break;
1466
1467                 case UNICHROME_K800:
1468                 case UNICHROME_PM800:
1469                 case UNICHROME_CN700:
1470                 case UNICHROME_CX700:
1471                 case UNICHROME_K8M890:
1472                 case UNICHROME_P4M890:
1473                 case UNICHROME_P4M900:
1474                 case UNICHROME_VX800:
1475                 case UNICHROME_VX855:
1476                         viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1477                         DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1478                         viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1479                         DEBUG_MSG(KERN_INFO "\nSR45=%x",
1480                                   (CLK & 0xFFFF) / 0x100);
1481                         viafb_write_reg(SR46, VIASR, CLK % 0x100);
1482                         DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1483                         break;
1484                 }
1485         }
1486
1487         if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1488                 /* Change D,N FOR LCK */
1489                 switch (viaparinfo->chip_info->gfx_chip_name) {
1490                 case UNICHROME_CLE266:
1491                 case UNICHROME_K400:
1492                         viafb_write_reg(SR44, VIASR, CLK / 0x100);
1493                         viafb_write_reg(SR45, VIASR, CLK % 0x100);
1494                         break;
1495
1496                 case UNICHROME_K800:
1497                 case UNICHROME_PM800:
1498                 case UNICHROME_CN700:
1499                 case UNICHROME_CX700:
1500                 case UNICHROME_K8M890:
1501                 case UNICHROME_P4M890:
1502                 case UNICHROME_P4M900:
1503                 case UNICHROME_VX800:
1504                 case UNICHROME_VX855:
1505                         viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1506                         viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1507                         viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1508                         break;
1509                 }
1510         }
1511
1512         /* H.W. Reset : OFF */
1513         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1514
1515         /* Reset PLL */
1516         if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1517                 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1518                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1519         }
1520
1521         if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1522                 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1523                 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1524         }
1525
1526         /* Fire! */
1527         RegTemp = inb(VIARMisc);
1528         outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1529 }
1530
1531 void viafb_load_crtc_timing(struct display_timing device_timing,
1532         int set_iga)
1533 {
1534         int i;
1535         int viafb_load_reg_num = 0;
1536         int reg_value = 0;
1537         struct io_register *reg = NULL;
1538
1539         viafb_unlock_crt();
1540
1541         for (i = 0; i < 12; i++) {
1542                 if (set_iga == IGA1) {
1543                         switch (i) {
1544                         case H_TOTAL_INDEX:
1545                                 reg_value =
1546                                     IGA1_HOR_TOTAL_FORMULA(device_timing.
1547                                                            hor_total);
1548                                 viafb_load_reg_num =
1549                                         iga1_crtc_reg.hor_total.reg_num;
1550                                 reg = iga1_crtc_reg.hor_total.reg;
1551                                 break;
1552                         case H_ADDR_INDEX:
1553                                 reg_value =
1554                                     IGA1_HOR_ADDR_FORMULA(device_timing.
1555                                                           hor_addr);
1556                                 viafb_load_reg_num =
1557                                         iga1_crtc_reg.hor_addr.reg_num;
1558                                 reg = iga1_crtc_reg.hor_addr.reg;
1559                                 break;
1560                         case H_BLANK_START_INDEX:
1561                                 reg_value =
1562                                     IGA1_HOR_BLANK_START_FORMULA
1563                                     (device_timing.hor_blank_start);
1564                                 viafb_load_reg_num =
1565                                     iga1_crtc_reg.hor_blank_start.reg_num;
1566                                 reg = iga1_crtc_reg.hor_blank_start.reg;
1567                                 break;
1568                         case H_BLANK_END_INDEX:
1569                                 reg_value =
1570                                     IGA1_HOR_BLANK_END_FORMULA
1571                                     (device_timing.hor_blank_start,
1572                                      device_timing.hor_blank_end);
1573                                 viafb_load_reg_num =
1574                                     iga1_crtc_reg.hor_blank_end.reg_num;
1575                                 reg = iga1_crtc_reg.hor_blank_end.reg;
1576                                 break;
1577                         case H_SYNC_START_INDEX:
1578                                 reg_value =
1579                                     IGA1_HOR_SYNC_START_FORMULA
1580                                     (device_timing.hor_sync_start);
1581                                 viafb_load_reg_num =
1582                                     iga1_crtc_reg.hor_sync_start.reg_num;
1583                                 reg = iga1_crtc_reg.hor_sync_start.reg;
1584                                 break;
1585                         case H_SYNC_END_INDEX:
1586                                 reg_value =
1587                                     IGA1_HOR_SYNC_END_FORMULA
1588                                     (device_timing.hor_sync_start,
1589                                      device_timing.hor_sync_end);
1590                                 viafb_load_reg_num =
1591                                     iga1_crtc_reg.hor_sync_end.reg_num;
1592                                 reg = iga1_crtc_reg.hor_sync_end.reg;
1593                                 break;
1594                         case V_TOTAL_INDEX:
1595                                 reg_value =
1596                                     IGA1_VER_TOTAL_FORMULA(device_timing.
1597                                                            ver_total);
1598                                 viafb_load_reg_num =
1599                                         iga1_crtc_reg.ver_total.reg_num;
1600                                 reg = iga1_crtc_reg.ver_total.reg;
1601                                 break;
1602                         case V_ADDR_INDEX:
1603                                 reg_value =
1604                                     IGA1_VER_ADDR_FORMULA(device_timing.
1605                                                           ver_addr);
1606                                 viafb_load_reg_num =
1607                                         iga1_crtc_reg.ver_addr.reg_num;
1608                                 reg = iga1_crtc_reg.ver_addr.reg;
1609                                 break;
1610                         case V_BLANK_START_INDEX:
1611                                 reg_value =
1612                                     IGA1_VER_BLANK_START_FORMULA
1613                                     (device_timing.ver_blank_start);
1614                                 viafb_load_reg_num =
1615                                     iga1_crtc_reg.ver_blank_start.reg_num;
1616                                 reg = iga1_crtc_reg.ver_blank_start.reg;
1617                                 break;
1618                         case V_BLANK_END_INDEX:
1619                                 reg_value =
1620                                     IGA1_VER_BLANK_END_FORMULA
1621                                     (device_timing.ver_blank_start,
1622                                      device_timing.ver_blank_end);
1623                                 viafb_load_reg_num =
1624                                     iga1_crtc_reg.ver_blank_end.reg_num;
1625                                 reg = iga1_crtc_reg.ver_blank_end.reg;
1626                                 break;
1627                         case V_SYNC_START_INDEX:
1628                                 reg_value =
1629                                     IGA1_VER_SYNC_START_FORMULA
1630                                     (device_timing.ver_sync_start);
1631                                 viafb_load_reg_num =
1632                                     iga1_crtc_reg.ver_sync_start.reg_num;
1633                                 reg = iga1_crtc_reg.ver_sync_start.reg;
1634                                 break;
1635                         case V_SYNC_END_INDEX:
1636                                 reg_value =
1637                                     IGA1_VER_SYNC_END_FORMULA
1638                                     (device_timing.ver_sync_start,
1639                                      device_timing.ver_sync_end);
1640                                 viafb_load_reg_num =
1641                                     iga1_crtc_reg.ver_sync_end.reg_num;
1642                                 reg = iga1_crtc_reg.ver_sync_end.reg;
1643                                 break;
1644
1645                         }
1646                 }
1647
1648                 if (set_iga == IGA2) {
1649                         switch (i) {
1650                         case H_TOTAL_INDEX:
1651                                 reg_value =
1652                                     IGA2_HOR_TOTAL_FORMULA(device_timing.
1653                                                            hor_total);
1654                                 viafb_load_reg_num =
1655                                         iga2_crtc_reg.hor_total.reg_num;
1656                                 reg = iga2_crtc_reg.hor_total.reg;
1657                                 break;
1658                         case H_ADDR_INDEX:
1659                                 reg_value =
1660                                     IGA2_HOR_ADDR_FORMULA(device_timing.
1661                                                           hor_addr);
1662                                 viafb_load_reg_num =
1663                                         iga2_crtc_reg.hor_addr.reg_num;
1664                                 reg = iga2_crtc_reg.hor_addr.reg;
1665                                 break;
1666                         case H_BLANK_START_INDEX:
1667                                 reg_value =
1668                                     IGA2_HOR_BLANK_START_FORMULA
1669                                     (device_timing.hor_blank_start);
1670                                 viafb_load_reg_num =
1671                                     iga2_crtc_reg.hor_blank_start.reg_num;
1672                                 reg = iga2_crtc_reg.hor_blank_start.reg;
1673                                 break;
1674                         case H_BLANK_END_INDEX:
1675                                 reg_value =
1676                                     IGA2_HOR_BLANK_END_FORMULA
1677                                     (device_timing.hor_blank_start,
1678                                      device_timing.hor_blank_end);
1679                                 viafb_load_reg_num =
1680                                     iga2_crtc_reg.hor_blank_end.reg_num;
1681                                 reg = iga2_crtc_reg.hor_blank_end.reg;
1682                                 break;
1683                         case H_SYNC_START_INDEX:
1684                                 reg_value =
1685                                     IGA2_HOR_SYNC_START_FORMULA
1686                                     (device_timing.hor_sync_start);
1687                                 if (UNICHROME_CN700 <=
1688                                         viaparinfo->chip_info->gfx_chip_name)
1689                                         viafb_load_reg_num =
1690                                             iga2_crtc_reg.hor_sync_start.
1691                                             reg_num;
1692                                 else
1693                                         viafb_load_reg_num = 3;
1694                                 reg = iga2_crtc_reg.hor_sync_start.reg;
1695                                 break;
1696                         case H_SYNC_END_INDEX:
1697                                 reg_value =
1698                                     IGA2_HOR_SYNC_END_FORMULA
1699                                     (device_timing.hor_sync_start,
1700                                      device_timing.hor_sync_end);
1701                                 viafb_load_reg_num =
1702                                     iga2_crtc_reg.hor_sync_end.reg_num;
1703                                 reg = iga2_crtc_reg.hor_sync_end.reg;
1704                                 break;
1705                         case V_TOTAL_INDEX:
1706                                 reg_value =
1707                                     IGA2_VER_TOTAL_FORMULA(device_timing.
1708                                                            ver_total);
1709                                 viafb_load_reg_num =
1710                                         iga2_crtc_reg.ver_total.reg_num;
1711                                 reg = iga2_crtc_reg.ver_total.reg;
1712                                 break;
1713                         case V_ADDR_INDEX:
1714                                 reg_value =
1715                                     IGA2_VER_ADDR_FORMULA(device_timing.
1716                                                           ver_addr);
1717                                 viafb_load_reg_num =
1718                                         iga2_crtc_reg.ver_addr.reg_num;
1719                                 reg = iga2_crtc_reg.ver_addr.reg;
1720                                 break;
1721                         case V_BLANK_START_INDEX:
1722                                 reg_value =
1723                                     IGA2_VER_BLANK_START_FORMULA
1724                                     (device_timing.ver_blank_start);
1725                                 viafb_load_reg_num =
1726                                     iga2_crtc_reg.ver_blank_start.reg_num;
1727                                 reg = iga2_crtc_reg.ver_blank_start.reg;
1728                                 break;
1729                         case V_BLANK_END_INDEX:
1730                                 reg_value =
1731                                     IGA2_VER_BLANK_END_FORMULA
1732                                     (device_timing.ver_blank_start,
1733                                      device_timing.ver_blank_end);
1734                                 viafb_load_reg_num =
1735                                     iga2_crtc_reg.ver_blank_end.reg_num;
1736                                 reg = iga2_crtc_reg.ver_blank_end.reg;
1737                                 break;
1738                         case V_SYNC_START_INDEX:
1739                                 reg_value =
1740                                     IGA2_VER_SYNC_START_FORMULA
1741                                     (device_timing.ver_sync_start);
1742                                 viafb_load_reg_num =
1743                                     iga2_crtc_reg.ver_sync_start.reg_num;
1744                                 reg = iga2_crtc_reg.ver_sync_start.reg;
1745                                 break;
1746                         case V_SYNC_END_INDEX:
1747                                 reg_value =
1748                                     IGA2_VER_SYNC_END_FORMULA
1749                                     (device_timing.ver_sync_start,
1750                                      device_timing.ver_sync_end);
1751                                 viafb_load_reg_num =
1752                                     iga2_crtc_reg.ver_sync_end.reg_num;
1753                                 reg = iga2_crtc_reg.ver_sync_end.reg;
1754                                 break;
1755
1756                         }
1757                 }
1758                 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1759         }
1760
1761         viafb_lock_crt();
1762 }
1763
1764 void viafb_set_color_depth(int bpp_byte, int set_iga)
1765 {
1766         if (set_iga == IGA1) {
1767                 switch (bpp_byte) {
1768                 case MODE_8BPP:
1769                         viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1770                         break;
1771                 case MODE_16BPP:
1772                         viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1773                         break;
1774                 case MODE_32BPP:
1775                         viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1776                         break;
1777                 }
1778         } else {
1779                 switch (bpp_byte) {
1780                 case MODE_8BPP:
1781                         viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1782                         break;
1783                 case MODE_16BPP:
1784                         viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1785                         break;
1786                 case MODE_32BPP:
1787                         viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1788                         break;
1789                 }
1790         }
1791 }
1792
1793 void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1794         struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1795 {
1796         struct display_timing crt_reg;
1797         int i;
1798         int index = 0;
1799         int h_addr, v_addr;
1800         u32 pll_D_N;
1801
1802         for (i = 0; i < video_mode->mode_array; i++) {
1803                 index = i;
1804
1805                 if (crt_table[i].refresh_rate == viaparinfo->
1806                         crt_setting_info->refresh_rate)
1807                         break;
1808         }
1809
1810         crt_reg = crt_table[index].crtc;
1811
1812         /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1813         /* So we would delete border. */
1814         if ((viafb_LCD_ON | viafb_DVI_ON)
1815             && video_mode->crtc[0].crtc.hor_addr == 640
1816             && video_mode->crtc[0].crtc.ver_addr == 480
1817             && viaparinfo->crt_setting_info->refresh_rate == 60) {
1818                 /* The border is 8 pixels. */
1819                 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1820
1821                 /* Blanking time should add left and right borders. */
1822                 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1823         }
1824
1825         h_addr = crt_reg.hor_addr;
1826         v_addr = crt_reg.ver_addr;
1827
1828         /* update polarity for CRT timing */
1829         if (crt_table[index].h_sync_polarity == NEGATIVE) {
1830                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1831                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1832                              (BIT6 + BIT7), VIAWMisc);
1833                 else
1834                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1835                              VIAWMisc);
1836         } else {
1837                 if (crt_table[index].v_sync_polarity == NEGATIVE)
1838                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1839                              VIAWMisc);
1840                 else
1841                         outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1842         }
1843
1844         if (set_iga == IGA1) {
1845                 viafb_unlock_crt();
1846                 viafb_write_reg(CR09, VIACR, 0x00);     /*initial CR09=0 */
1847                 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1848                 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1849         }
1850
1851         switch (set_iga) {
1852         case IGA1:
1853                 viafb_load_crtc_timing(crt_reg, IGA1);
1854                 break;
1855         case IGA2:
1856                 viafb_load_crtc_timing(crt_reg, IGA2);
1857                 break;
1858         }
1859
1860         load_fix_bit_crtc_reg();
1861         viafb_lock_crt();
1862         viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1863         viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1864
1865         /* load FIFO */
1866         if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1867             && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1868                 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1869
1870         /* load SR Register About Memory and Color part */
1871         viafb_set_color_depth(bpp_byte, set_iga);
1872
1873         pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1874         DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1875         viafb_set_vclock(pll_D_N, set_iga);
1876
1877 }
1878
1879 void viafb_init_chip_info(struct pci_dev *pdev,
1880                           const struct pci_device_id *pdi)
1881 {
1882         init_gfx_chip_info(pdev, pdi);
1883         init_tmds_chip_info();
1884         init_lvds_chip_info();
1885
1886         viaparinfo->crt_setting_info->iga_path = IGA1;
1887         viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1888
1889         /*Set IGA path for each device */
1890         viafb_set_iga_path();
1891
1892         viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1893         viaparinfo->lvds_setting_info->get_lcd_size_method =
1894                 GET_LCD_SIZE_BY_USER_SETTING;
1895         viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1896         viaparinfo->lvds_setting_info2->display_method =
1897                 viaparinfo->lvds_setting_info->display_method;
1898         viaparinfo->lvds_setting_info2->lcd_mode =
1899                 viaparinfo->lvds_setting_info->lcd_mode;
1900 }
1901
1902 void viafb_update_device_setting(int hres, int vres,
1903         int bpp, int vmode_refresh, int flag)
1904 {
1905         if (flag == 0) {
1906                 viaparinfo->crt_setting_info->h_active = hres;
1907                 viaparinfo->crt_setting_info->v_active = vres;
1908                 viaparinfo->crt_setting_info->bpp = bpp;
1909                 viaparinfo->crt_setting_info->refresh_rate =
1910                         vmode_refresh;
1911
1912                 viaparinfo->tmds_setting_info->h_active = hres;
1913                 viaparinfo->tmds_setting_info->v_active = vres;
1914
1915                 viaparinfo->lvds_setting_info->h_active = hres;
1916                 viaparinfo->lvds_setting_info->v_active = vres;
1917                 viaparinfo->lvds_setting_info->bpp = bpp;
1918                 viaparinfo->lvds_setting_info->refresh_rate =
1919                         vmode_refresh;
1920                 viaparinfo->lvds_setting_info2->h_active = hres;
1921                 viaparinfo->lvds_setting_info2->v_active = vres;
1922                 viaparinfo->lvds_setting_info2->bpp = bpp;
1923                 viaparinfo->lvds_setting_info2->refresh_rate =
1924                         vmode_refresh;
1925         } else {
1926
1927                 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1928                         viaparinfo->tmds_setting_info->h_active = hres;
1929                         viaparinfo->tmds_setting_info->v_active = vres;
1930                 }
1931
1932                 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1933                         viaparinfo->lvds_setting_info->h_active = hres;
1934                         viaparinfo->lvds_setting_info->v_active = vres;
1935                         viaparinfo->lvds_setting_info->bpp = bpp;
1936                         viaparinfo->lvds_setting_info->refresh_rate =
1937                                 vmode_refresh;
1938                 }
1939                 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1940                         viaparinfo->lvds_setting_info2->h_active = hres;
1941                         viaparinfo->lvds_setting_info2->v_active = vres;
1942                         viaparinfo->lvds_setting_info2->bpp = bpp;
1943                         viaparinfo->lvds_setting_info2->refresh_rate =
1944                                 vmode_refresh;
1945                 }
1946         }
1947 }
1948
1949 static void init_gfx_chip_info(struct pci_dev *pdev,
1950                                const struct pci_device_id *pdi)
1951 {
1952         u8 tmp;
1953
1954         viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
1955
1956         /* Check revision of CLE266 Chip */
1957         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1958                 /* CR4F only define in CLE266.CX chip */
1959                 tmp = viafb_read_reg(VIACR, CR4F);
1960                 viafb_write_reg(CR4F, VIACR, 0x55);
1961                 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1962                         viaparinfo->chip_info->gfx_chip_revision =
1963                         CLE266_REVISION_AX;
1964                 else
1965                         viaparinfo->chip_info->gfx_chip_revision =
1966                         CLE266_REVISION_CX;
1967                 /* restore orignal CR4F value */
1968                 viafb_write_reg(CR4F, VIACR, tmp);
1969         }
1970
1971         if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1972                 tmp = viafb_read_reg(VIASR, SR43);
1973                 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1974                 if (tmp & 0x02) {
1975                         viaparinfo->chip_info->gfx_chip_revision =
1976                                 CX700_REVISION_700M2;
1977                 } else if (tmp & 0x40) {
1978                         viaparinfo->chip_info->gfx_chip_revision =
1979                                 CX700_REVISION_700M;
1980                 } else {
1981                         viaparinfo->chip_info->gfx_chip_revision =
1982                                 CX700_REVISION_700;
1983                 }
1984         }
1985 }
1986
1987 static void init_tmds_chip_info(void)
1988 {
1989         viafb_tmds_trasmitter_identify();
1990
1991         if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
1992                 output_interface) {
1993                 switch (viaparinfo->chip_info->gfx_chip_name) {
1994                 case UNICHROME_CX700:
1995                         {
1996                                 /* we should check support by hardware layout.*/
1997                                 if ((viafb_display_hardware_layout ==
1998                                      HW_LAYOUT_DVI_ONLY)
1999                                     || (viafb_display_hardware_layout ==
2000                                         HW_LAYOUT_LCD_DVI)) {
2001                                         viaparinfo->chip_info->tmds_chip_info.
2002                                             output_interface = INTERFACE_TMDS;
2003                                 } else {
2004                                         viaparinfo->chip_info->tmds_chip_info.
2005                                                 output_interface =
2006                                                 INTERFACE_NONE;
2007                                 }
2008                                 break;
2009                         }
2010                 case UNICHROME_K8M890:
2011                 case UNICHROME_P4M900:
2012                 case UNICHROME_P4M890:
2013                         /* TMDS on PCIE, we set DFPLOW as default. */
2014                         viaparinfo->chip_info->tmds_chip_info.output_interface =
2015                             INTERFACE_DFP_LOW;
2016                         break;
2017                 default:
2018                         {
2019                                 /* set DVP1 default for DVI */
2020                                 viaparinfo->chip_info->tmds_chip_info
2021                                 .output_interface = INTERFACE_DVP1;
2022                         }
2023                 }
2024         }
2025
2026         DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2027                   viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2028         viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2029                 &viaparinfo->shared->tmds_setting_info);
2030 }
2031
2032 static void init_lvds_chip_info(void)
2033 {
2034         if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2035                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2036                     GET_LCD_SIZE_BY_VGA_BIOS;
2037         else
2038                 viaparinfo->lvds_setting_info->get_lcd_size_method =
2039                     GET_LCD_SIZE_BY_USER_SETTING;
2040
2041         viafb_lvds_trasmitter_identify();
2042         viafb_init_lcd_size();
2043         viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2044                                    viaparinfo->lvds_setting_info);
2045         if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2046                 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2047                         lvds_chip_info2, viaparinfo->lvds_setting_info2);
2048         }
2049         /*If CX700,two singel LCD, we need to reassign
2050            LCD interface to different LVDS port */
2051         if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2052             && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2053                 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2054                         lvds_chip_name) && (INTEGRATED_LVDS ==
2055                         viaparinfo->chip_info->
2056                         lvds_chip_info2.lvds_chip_name)) {
2057                         viaparinfo->chip_info->lvds_chip_info.output_interface =
2058                                 INTERFACE_LVDS0;
2059                         viaparinfo->chip_info->lvds_chip_info2.
2060                                 output_interface =
2061                             INTERFACE_LVDS1;
2062                 }
2063         }
2064
2065         DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2066                   viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2067         DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2068                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2069         DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2070                   viaparinfo->chip_info->lvds_chip_info.output_interface);
2071 }
2072
2073 void viafb_init_dac(int set_iga)
2074 {
2075         int i;
2076         u8 tmp;
2077
2078         if (set_iga == IGA1) {
2079                 /* access Primary Display's LUT */
2080                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2081                 /* turn off LCK */
2082                 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2083                 for (i = 0; i < 256; i++) {
2084                         write_dac_reg(i, palLUT_table[i].red,
2085                                       palLUT_table[i].green,
2086                                       palLUT_table[i].blue);
2087                 }
2088                 /* turn on LCK */
2089                 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2090         } else {
2091                 tmp = viafb_read_reg(VIACR, CR6A);
2092                 /* access Secondary Display's LUT */
2093                 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2094                 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2095                 for (i = 0; i < 256; i++) {
2096                         write_dac_reg(i, palLUT_table[i].red,
2097                                       palLUT_table[i].green,
2098                                       palLUT_table[i].blue);
2099                 }
2100                 /* set IGA1 DAC for default */
2101                 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2102                 viafb_write_reg(CR6A, VIACR, tmp);
2103         }
2104 }
2105
2106 static void device_screen_off(void)
2107 {
2108         /* turn off CRT screen (IGA1) */
2109         viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2110 }
2111
2112 static void device_screen_on(void)
2113 {
2114         /* turn on CRT screen (IGA1) */
2115         viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2116 }
2117
2118 static void set_display_channel(void)
2119 {
2120         /*If viafb_LCD2_ON, on cx700, internal lvds's information
2121         is keeped on lvds_setting_info2 */
2122         if (viafb_LCD2_ON &&
2123                 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2124                 /* For dual channel LCD: */
2125                 /* Set to Dual LVDS channel. */
2126                 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2127         } else if (viafb_LCD_ON && viafb_DVI_ON) {
2128                 /* For LCD+DFP: */
2129                 /* Set to LVDS1 + TMDS channel. */
2130                 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2131         } else if (viafb_DVI_ON) {
2132                 /* Set to single TMDS channel. */
2133                 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2134         } else if (viafb_LCD_ON) {
2135                 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2136                         /* For dual channel LCD: */
2137                         /* Set to Dual LVDS channel. */
2138                         viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2139                 } else {
2140                         /* Set to LVDS0 + LVDS1 channel. */
2141                         viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2142                 }
2143         }
2144 }
2145
2146 int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2147         struct VideoModeTable *vmode_tbl1, int video_bpp1)
2148 {
2149         int i, j;
2150         int port;
2151         u8 value, index, mask;
2152         struct crt_mode_table *crt_timing;
2153         struct crt_mode_table *crt_timing1 = NULL;
2154
2155         device_screen_off();
2156         crt_timing = vmode_tbl->crtc;
2157
2158         if (viafb_SAMM_ON == 1) {
2159                 crt_timing1 = vmode_tbl1->crtc;
2160         }
2161
2162         inb(VIAStatus);
2163         outb(0x00, VIAAR);
2164
2165         /* Write Common Setting for Video Mode */
2166         switch (viaparinfo->chip_info->gfx_chip_name) {
2167         case UNICHROME_CLE266:
2168                 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2169                 break;
2170
2171         case UNICHROME_K400:
2172                 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2173                 break;
2174
2175         case UNICHROME_K800:
2176         case UNICHROME_PM800:
2177                 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2178                 break;
2179
2180         case UNICHROME_CN700:
2181         case UNICHROME_K8M890:
2182         case UNICHROME_P4M890:
2183         case UNICHROME_P4M900:
2184                 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2185                 break;
2186
2187         case UNICHROME_CX700:
2188         case UNICHROME_VX800:
2189                 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
2190                 break;
2191
2192         case UNICHROME_VX855:
2193                 viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
2194                 break;
2195         }
2196
2197         device_off();
2198
2199         /* Fill VPIT Parameters */
2200         /* Write Misc Register */
2201         outb(VPIT.Misc, VIAWMisc);
2202
2203         /* Write Sequencer */
2204         for (i = 1; i <= StdSR; i++) {
2205                 outb(i, VIASR);
2206                 outb(VPIT.SR[i - 1], VIASR + 1);
2207         }
2208
2209         viafb_set_iga_path();
2210
2211         /* Write CRTC */
2212         viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2213
2214         /* Write Graphic Controller */
2215         for (i = 0; i < StdGR; i++) {
2216                 outb(i, VIAGR);
2217                 outb(VPIT.GR[i], VIAGR + 1);
2218         }
2219
2220         /* Write Attribute Controller */
2221         for (i = 0; i < StdAR; i++) {
2222                 inb(VIAStatus);
2223                 outb(i, VIAAR);
2224                 outb(VPIT.AR[i], VIAAR);
2225         }
2226
2227         inb(VIAStatus);
2228         outb(0x20, VIAAR);
2229
2230         /* Update Patch Register */
2231
2232         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2233             || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2234             && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2235             && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2236                 for (j = 0; j < res_patch_table[0].table_length; j++) {
2237                         index = res_patch_table[0].io_reg_table[j].index;
2238                         port = res_patch_table[0].io_reg_table[j].port;
2239                         value = res_patch_table[0].io_reg_table[j].value;
2240                         mask = res_patch_table[0].io_reg_table[j].mask;
2241                         viafb_write_reg_mask(index, port, value, mask);
2242                 }
2243         }
2244
2245         viafb_set_primary_pitch(viafbinfo->fix.line_length);
2246         viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2247                 : viafbinfo->fix.line_length);
2248         /* Update Refresh Rate Setting */
2249
2250         /* Clear On Screen */
2251
2252         /* CRT set mode */
2253         if (viafb_CRT_ON) {
2254                 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2255                         IGA2)) {
2256                         viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2257                                 video_bpp1 / 8,
2258                                 viaparinfo->crt_setting_info->iga_path);
2259                 } else {
2260                         viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2261                                 video_bpp / 8,
2262                                 viaparinfo->crt_setting_info->iga_path);
2263                 }
2264
2265                 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2266
2267                 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2268                 to 8 alignment (1368),there is several pixels (2 pixels)
2269                 on right side of screen. */
2270                 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2271                         viafb_unlock_crt();
2272                         viafb_write_reg(CR02, VIACR,
2273                                 viafb_read_reg(VIACR, CR02) - 1);
2274                         viafb_lock_crt();
2275                 }
2276         }
2277
2278         if (viafb_DVI_ON) {
2279                 if (viafb_SAMM_ON &&
2280                         (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2281                         viafb_dvi_set_mode(viafb_get_mode
2282                                      (viaparinfo->tmds_setting_info->h_active,
2283                                       viaparinfo->tmds_setting_info->
2284                                       v_active),
2285                                      video_bpp1, viaparinfo->
2286                                      tmds_setting_info->iga_path);
2287                 } else {
2288                         viafb_dvi_set_mode(viafb_get_mode
2289                                      (viaparinfo->tmds_setting_info->h_active,
2290                                       viaparinfo->
2291                                       tmds_setting_info->v_active),
2292                                      video_bpp, viaparinfo->
2293                                      tmds_setting_info->iga_path);
2294                 }
2295         }
2296
2297         if (viafb_LCD_ON) {
2298                 if (viafb_SAMM_ON &&
2299                         (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2300                         viaparinfo->lvds_setting_info->bpp = video_bpp1;
2301                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2302                                 lvds_setting_info,
2303                                      &viaparinfo->chip_info->lvds_chip_info);
2304                 } else {
2305                         /* IGA1 doesn't have LCD scaling, so set it center. */
2306                         if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2307                                 viaparinfo->lvds_setting_info->display_method =
2308                                     LCD_CENTERING;
2309                         }
2310                         viaparinfo->lvds_setting_info->bpp = video_bpp;
2311                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2312                                 lvds_setting_info,
2313                                      &viaparinfo->chip_info->lvds_chip_info);
2314                 }
2315         }
2316         if (viafb_LCD2_ON) {
2317                 if (viafb_SAMM_ON &&
2318                         (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2319                         viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2320                         viafb_lcd_set_mode(crt_timing1, viaparinfo->
2321                                 lvds_setting_info2,
2322                                      &viaparinfo->chip_info->lvds_chip_info2);
2323                 } else {
2324                         /* IGA1 doesn't have LCD scaling, so set it center. */
2325                         if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2326                                 viaparinfo->lvds_setting_info2->display_method =
2327                                     LCD_CENTERING;
2328                         }
2329                         viaparinfo->lvds_setting_info2->bpp = video_bpp;
2330                         viafb_lcd_set_mode(crt_timing, viaparinfo->
2331                                 lvds_setting_info2,
2332                                      &viaparinfo->chip_info->lvds_chip_info2);
2333                 }
2334         }
2335
2336         if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2337             && (viafb_LCD_ON || viafb_DVI_ON))
2338                 set_display_channel();
2339
2340         /* If set mode normally, save resolution information for hot-plug . */
2341         if (!viafb_hotplug) {
2342                 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2343                 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2344                 viafb_hotplug_bpp = video_bpp;
2345                 viafb_hotplug_refresh = viafb_refresh;
2346
2347                 if (viafb_DVI_ON)
2348                         viafb_DeviceStatus = DVI_Device;
2349                 else
2350                         viafb_DeviceStatus = CRT_Device;
2351         }
2352         device_on();
2353
2354         if (viafb_SAMM_ON == 1)
2355                 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2356
2357         device_screen_on();
2358         return 1;
2359 }
2360
2361 int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2362 {
2363         int i;
2364
2365         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2366                 if ((hres == res_map_refresh_tbl[i].hres)
2367                     && (vres == res_map_refresh_tbl[i].vres)
2368                     && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2369                         return res_map_refresh_tbl[i].pixclock;
2370         }
2371         return RES_640X480_60HZ_PIXCLOCK;
2372
2373 }
2374
2375 int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2376 {
2377 #define REFRESH_TOLERANCE 3
2378         int i, nearest = -1, diff = REFRESH_TOLERANCE;
2379         for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2380                 if ((hres == res_map_refresh_tbl[i].hres)
2381                     && (vres == res_map_refresh_tbl[i].vres)
2382                     && (diff > (abs(long_refresh -
2383                     res_map_refresh_tbl[i].vmode_refresh)))) {
2384                         diff = abs(long_refresh - res_map_refresh_tbl[i].
2385                                 vmode_refresh);
2386                         nearest = i;
2387                 }
2388         }
2389 #undef REFRESH_TOLERANCE
2390         if (nearest > 0)
2391                 return res_map_refresh_tbl[nearest].vmode_refresh;
2392         return 60;
2393 }
2394
2395 static void device_off(void)
2396 {
2397         viafb_crt_disable();
2398         viafb_dvi_disable();
2399         viafb_lcd_disable();
2400 }
2401
2402 static void device_on(void)
2403 {
2404         if (viafb_CRT_ON == 1)
2405                 viafb_crt_enable();
2406         if (viafb_DVI_ON == 1)
2407                 viafb_dvi_enable();
2408         if (viafb_LCD_ON == 1)
2409                 viafb_lcd_enable();
2410 }
2411
2412 void viafb_crt_disable(void)
2413 {
2414         viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2415 }
2416
2417 void viafb_crt_enable(void)
2418 {
2419         viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2420 }
2421
2422 static void enable_second_display_channel(void)
2423 {
2424         /* to enable second display channel. */
2425         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2426         viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2427         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2428 }
2429
2430 static void disable_second_display_channel(void)
2431 {
2432         /* to disable second display channel. */
2433         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2434         viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2435         viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2436 }
2437
2438 int viafb_get_fb_size_from_pci(void)
2439 {
2440         unsigned long configid, deviceid, FBSize = 0;
2441         int VideoMemSize;
2442         int DeviceFound = false;
2443
2444         for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2445                 outl(configid, (unsigned long)0xCF8);
2446                 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2447
2448                 switch (deviceid) {
2449                 case CLE266:
2450                 case KM400:
2451                         outl(configid + 0xE0, (unsigned long)0xCF8);
2452                         FBSize = inl((unsigned long)0xCFC);
2453                         DeviceFound = true;     /* Found device id */
2454                         break;
2455
2456                 case CN400_FUNCTION3:
2457                 case CN700_FUNCTION3:
2458                 case CX700_FUNCTION3:
2459                 case KM800_FUNCTION3:
2460                 case KM890_FUNCTION3:
2461                 case P4M890_FUNCTION3:
2462                 case P4M900_FUNCTION3:
2463                 case VX800_FUNCTION3:
2464                 case VX855_FUNCTION3:
2465                         /*case CN750_FUNCTION3: */
2466                         outl(configid + 0xA0, (unsigned long)0xCF8);
2467                         FBSize = inl((unsigned long)0xCFC);
2468                         DeviceFound = true;     /* Found device id */
2469                         break;
2470
2471                 default:
2472                         break;
2473                 }
2474
2475                 if (DeviceFound)
2476                         break;
2477         }
2478
2479         DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2480
2481         FBSize = FBSize & 0x00007000;
2482         DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2483
2484         if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2485                 switch (FBSize) {
2486                 case 0x00004000:
2487                         VideoMemSize = (16 << 20);      /*16M */
2488                         break;
2489
2490                 case 0x00005000:
2491                         VideoMemSize = (32 << 20);      /*32M */
2492                         break;
2493
2494                 case 0x00006000:
2495                         VideoMemSize = (64 << 20);      /*64M */
2496                         break;
2497
2498                 default:
2499                         VideoMemSize = (32 << 20);      /*32M */
2500                         break;
2501                 }
2502         } else {
2503                 switch (FBSize) {
2504                 case 0x00001000:
2505                         VideoMemSize = (8 << 20);       /*8M */
2506                         break;
2507
2508                 case 0x00002000:
2509                         VideoMemSize = (16 << 20);      /*16M */
2510                         break;
2511
2512                 case 0x00003000:
2513                         VideoMemSize = (32 << 20);      /*32M */
2514                         break;
2515
2516                 case 0x00004000:
2517                         VideoMemSize = (64 << 20);      /*64M */
2518                         break;
2519
2520                 case 0x00005000:
2521                         VideoMemSize = (128 << 20);     /*128M */
2522                         break;
2523
2524                 case 0x00006000:
2525                         VideoMemSize = (256 << 20);     /*256M */
2526                         break;
2527
2528                 case 0x00007000:        /* Only on VX855/875 */
2529                         VideoMemSize = (512 << 20);     /*512M */
2530                         break;
2531
2532                 default:
2533                         VideoMemSize = (32 << 20);      /*32M */
2534                         break;
2535                 }
2536         }
2537
2538         return VideoMemSize;
2539 }
2540
2541 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2542                                         *p_gfx_dpa_setting)
2543 {
2544         switch (output_interface) {
2545         case INTERFACE_DVP0:
2546                 {
2547                         /* DVP0 Clock Polarity and Adjust: */
2548                         viafb_write_reg_mask(CR96, VIACR,
2549                                        p_gfx_dpa_setting->DVP0, 0x0F);
2550
2551                         /* DVP0 Clock and Data Pads Driving: */
2552                         viafb_write_reg_mask(SR1E, VIASR,
2553                                        p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2554                         viafb_write_reg_mask(SR2A, VIASR,
2555                                        p_gfx_dpa_setting->DVP0ClockDri_S1,
2556                                        BIT4);
2557                         viafb_write_reg_mask(SR1B, VIASR,
2558                                        p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2559                         viafb_write_reg_mask(SR2A, VIASR,
2560                                        p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2561                         break;
2562                 }
2563
2564         case INTERFACE_DVP1:
2565                 {
2566                         /* DVP1 Clock Polarity and Adjust: */
2567                         viafb_write_reg_mask(CR9B, VIACR,
2568                                        p_gfx_dpa_setting->DVP1, 0x0F);
2569
2570                         /* DVP1 Clock and Data Pads Driving: */
2571                         viafb_write_reg_mask(SR65, VIASR,
2572                                        p_gfx_dpa_setting->DVP1Driving, 0x0F);
2573                         break;
2574                 }
2575
2576         case INTERFACE_DFP_HIGH:
2577                 {
2578                         viafb_write_reg_mask(CR97, VIACR,
2579                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2580                         break;
2581                 }
2582
2583         case INTERFACE_DFP_LOW:
2584                 {
2585                         viafb_write_reg_mask(CR99, VIACR,
2586                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2587                         break;
2588                 }
2589
2590         case INTERFACE_DFP:
2591                 {
2592                         viafb_write_reg_mask(CR97, VIACR,
2593                                        p_gfx_dpa_setting->DFPHigh, 0x0F);
2594                         viafb_write_reg_mask(CR99, VIACR,
2595                                        p_gfx_dpa_setting->DFPLow, 0x0F);
2596                         break;
2597                 }
2598         }
2599 }
2600
2601 /*According var's xres, yres fill var's other timing information*/
2602 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2603         struct VideoModeTable *vmode_tbl)
2604 {
2605         struct crt_mode_table *crt_timing = NULL;
2606         struct display_timing crt_reg;
2607         int i = 0, index = 0;
2608         crt_timing = vmode_tbl->crtc;
2609         for (i = 0; i < vmode_tbl->mode_array; i++) {
2610                 index = i;
2611                 if (crt_timing[i].refresh_rate == refresh)
2612                         break;
2613         }
2614
2615         crt_reg = crt_timing[index].crtc;
2616         switch (var->bits_per_pixel) {
2617         case 8:
2618                 var->red.offset = 0;
2619                 var->green.offset = 0;
2620                 var->blue.offset = 0;
2621                 var->red.length = 6;
2622                 var->green.length = 6;
2623                 var->blue.length = 6;
2624                 break;
2625         case 16:
2626                 var->red.offset = 11;
2627                 var->green.offset = 5;
2628                 var->blue.offset = 0;
2629                 var->red.length = 5;
2630                 var->green.length = 6;
2631                 var->blue.length = 5;
2632                 break;
2633         case 32:
2634                 var->red.offset = 16;
2635                 var->green.offset = 8;
2636                 var->blue.offset = 0;
2637                 var->red.length = 8;
2638                 var->green.length = 8;
2639                 var->blue.length = 8;
2640                 break;
2641         default:
2642                 /* never happed, put here to keep consistent */
2643                 break;
2644         }
2645
2646         var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2647         var->left_margin =
2648             crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2649         var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2650         var->hsync_len = crt_reg.hor_sync_end;
2651         var->upper_margin =
2652             crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2653         var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2654         var->vsync_len = crt_reg.ver_sync_end;
2655 }