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   1 /*
   2  * SuperH Mobile LCDC Framebuffer
   3  *
   4  * Copyright (c) 2008 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/mm.h>
  15 #include <linux/fb.h>
  16 #include <linux/clk.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/vmalloc.h>
  21 #include <video/sh_mobile_lcdc.h>
  22 #include <asm/atomic.h>
  23
  24 #define PALETTE_NR 16
  25
  26 struct sh_mobile_lcdc_priv;
  27 struct sh_mobile_lcdc_chan {
  28         struct sh_mobile_lcdc_priv *lcdc;
  29         unsigned long *reg_offs;
  30         unsigned long ldmt1r_value;
  31         unsigned long enabled; /* ME and SE in LDCNT2R */
  32         struct sh_mobile_lcdc_chan_cfg cfg;
  33         u32 pseudo_palette[PALETTE_NR];
  34         struct fb_info *info;
  35         dma_addr_t dma_handle;
  36         struct fb_deferred_io defio;
  37         struct scatterlist *sglist;
  38         unsigned long frame_end;
  39         wait_queue_head_t frame_end_wait;
  40 };
  41
  42 struct sh_mobile_lcdc_priv {
  43         void __iomem *base;
  44         int irq;
  45         atomic_t clk_usecnt;
  46         struct clk *dot_clk;
  47         struct clk *clk;
  48         unsigned long lddckr;
  49         struct sh_mobile_lcdc_chan ch[2];
  50         int started;
  51 };
  52
  53 /* shared registers */
  54 #define _LDDCKR 0x410
  55 #define _LDDCKSTPR 0x414
  56 #define _LDINTR 0x468
  57 #define _LDSR 0x46c
  58 #define _LDCNT1R 0x470
  59 #define _LDCNT2R 0x474
  60 #define _LDDDSR 0x47c
  61 #define _LDDWD0R 0x800
  62 #define _LDDRDR 0x840
  63 #define _LDDWAR 0x900
  64 #define _LDDRAR 0x904
  65
  66 /* per-channel registers */
  67 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
  68        LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
  69
  70 static unsigned long lcdc_offs_mainlcd[] = {
  71         [LDDCKPAT1R] = 0x400,
  72         [LDDCKPAT2R] = 0x404,
  73         [LDMT1R] = 0x418,
  74         [LDMT2R] = 0x41c,
  75         [LDMT3R] = 0x420,
  76         [LDDFR] = 0x424,
  77         [LDSM1R] = 0x428,
  78         [LDSM2R] = 0x42c,
  79         [LDSA1R] = 0x430,
  80         [LDMLSR] = 0x438,
  81         [LDHCNR] = 0x448,
  82         [LDHSYNR] = 0x44c,
  83         [LDVLNR] = 0x450,
  84         [LDVSYNR] = 0x454,
  85         [LDPMR] = 0x460,
  86 };
  87
  88 static unsigned long lcdc_offs_sublcd[] = {
  89         [LDDCKPAT1R] = 0x408,
  90         [LDDCKPAT2R] = 0x40c,
  91         [LDMT1R] = 0x600,
  92         [LDMT2R] = 0x604,
  93         [LDMT3R] = 0x608,
  94         [LDDFR] = 0x60c,
  95         [LDSM1R] = 0x610,
  96         [LDSM2R] = 0x614,
  97         [LDSA1R] = 0x618,
  98         [LDMLSR] = 0x620,
  99         [LDHCNR] = 0x624,
 100         [LDHSYNR] = 0x628,
 101         [LDVLNR] = 0x62c,
 102         [LDVSYNR] = 0x630,
 103         [LDPMR] = 0x63c,
 104 };
 105
 106 #define START_LCDC      0x00000001
 107 #define LCDC_RESET      0x00000100
 108 #define DISPLAY_BEU     0x00000008
 109 #define LCDC_ENABLE     0x00000001
 110 #define LDINTR_FE       0x00000400
 111 #define LDINTR_FS       0x00000004
 112
 113 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
 114                             int reg_nr, unsigned long data)
 115 {
 116         iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
 117 }
 118
 119 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
 120                                     int reg_nr)
 121 {
 122         return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
 123 }
 124
 125 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
 126                        unsigned long reg_offs, unsigned long data)
 127 {
 128         iowrite32(data, priv->base + reg_offs);
 129 }
 130
 131 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
 132                                unsigned long reg_offs)
 133 {
 134         return ioread32(priv->base + reg_offs);
 135 }
 136
 137 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
 138                           unsigned long reg_offs,
 139                           unsigned long mask, unsigned long until)
 140 {
 141         while ((lcdc_read(priv, reg_offs) & mask) != until)
 142                 cpu_relax();
 143 }
 144
 145 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
 146 {
 147         return chan->cfg.chan == LCDC_CHAN_SUBLCD;
 148 }
 149
 150 static void lcdc_sys_write_index(void *handle, unsigned long data)
 151 {
 152         struct sh_mobile_lcdc_chan *ch = handle;
 153
 154         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
 155         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 156         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 157 }
 158
 159 static void lcdc_sys_write_data(void *handle, unsigned long data)
 160 {
 161         struct sh_mobile_lcdc_chan *ch = handle;
 162
 163         lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
 164         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 165         lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 166 }
 167
 168 static unsigned long lcdc_sys_read_data(void *handle)
 169 {
 170         struct sh_mobile_lcdc_chan *ch = handle;
 171
 172         lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
 173         lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
 174         lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
 175         udelay(1);
 176
 177         return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
 178 }
 179
 180 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
 181         lcdc_sys_write_index,
 182         lcdc_sys_write_data,
 183         lcdc_sys_read_data,
 184 };
 185
 186 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
 187 {
 188         if (atomic_inc_and_test(&priv->clk_usecnt)) {
 189                 clk_enable(priv->clk);
 190                 if (priv->dot_clk)
 191                         clk_enable(priv->dot_clk);
 192         }
 193 }
 194
 195 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
 196 {
 197         if (atomic_sub_return(1, &priv->clk_usecnt) == -1) {
 198                 if (priv->dot_clk)
 199                         clk_disable(priv->dot_clk);
 200                 clk_disable(priv->clk);
 201         }
 202 }
 203
 204 static int sh_mobile_lcdc_sginit(struct fb_info *info,
 205                                   struct list_head *pagelist)
 206 {
 207         struct sh_mobile_lcdc_chan *ch = info->par;
 208         unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
 209         struct page *page;
 210         int nr_pages = 0;
 211
 212         sg_init_table(ch->sglist, nr_pages_max);
 213
 214         list_for_each_entry(page, pagelist, lru)
 215                 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
 216
 217         return nr_pages;
 218 }
 219
 220 static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
 221                                        struct list_head *pagelist)
 222 {
 223         struct sh_mobile_lcdc_chan *ch = info->par;
 224         unsigned int nr_pages;
 225
 226         /* enable clocks before accessing hardware */
 227         sh_mobile_lcdc_clk_on(ch->lcdc);
 228
 229         nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
 230         dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 231
 232         /* trigger panel update */
 233         lcdc_write_chan(ch, LDSM2R, 1);
 234
 235         dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
 236 }
 237
 238 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
 239 {
 240         struct fb_deferred_io *fbdefio = info->fbdefio;
 241
 242         if (fbdefio)
 243                 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
 244 }
 245
 246 static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
 247 {
 248         struct sh_mobile_lcdc_priv *priv = data;
 249         struct sh_mobile_lcdc_chan *ch;
 250         unsigned long tmp;
 251         int is_sub;
 252         int k;
 253
 254         /* acknowledge interrupt */
 255         tmp = lcdc_read(priv, _LDINTR);
 256         tmp &= 0xffffff00; /* mask in high 24 bits */
 257         tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */
 258         lcdc_write(priv, _LDINTR, tmp);
 259
 260         /* figure out if this interrupt is for main or sub lcd */
 261         is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
 262
 263         /* wake up channel and disable clocks*/
 264         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 265                 ch = &priv->ch[k];
 266
 267                 if (!ch->enabled)
 268                         continue;
 269
 270                 if (is_sub == lcdc_chan_is_sublcd(ch)) {
 271                         ch->frame_end = 1;
 272                         wake_up(&ch->frame_end_wait);
 273
 274                         sh_mobile_lcdc_clk_off(priv);
 275                 }
 276         }
 277
 278         return IRQ_HANDLED;
 279 }
 280
 281 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
 282                                       int start)
 283 {
 284         unsigned long tmp = lcdc_read(priv, _LDCNT2R);
 285         int k;
 286
 287         /* start or stop the lcdc */
 288         if (start)
 289                 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
 290         else
 291                 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
 292
 293         /* wait until power is applied/stopped on all channels */
 294         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 295                 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
 296                         while (1) {
 297                                 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
 298                                 if (start && tmp == 3)
 299                                         break;
 300                                 if (!start && tmp == 0)
 301                                         break;
 302                                 cpu_relax();
 303                         }
 304
 305         if (!start)
 306                 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
 307 }
 308
 309 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
 310 {
 311         struct sh_mobile_lcdc_chan *ch;
 312         struct fb_videomode *lcd_cfg;
 313         struct sh_mobile_lcdc_board_cfg *board_cfg;
 314         unsigned long tmp;
 315         int k, m;
 316         int ret = 0;
 317
 318         /* enable clocks before accessing the hardware */
 319         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 320                 if (priv->ch[k].enabled)
 321                         sh_mobile_lcdc_clk_on(priv);
 322
 323         /* reset */
 324         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
 325         lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
 326
 327         /* enable LCDC channels */
 328         tmp = lcdc_read(priv, _LDCNT2R);
 329         tmp |= priv->ch[0].enabled;
 330         tmp |= priv->ch[1].enabled;
 331         lcdc_write(priv, _LDCNT2R, tmp);
 332
 333         /* read data from external memory, avoid using the BEU for now */
 334         lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
 335
 336         /* stop the lcdc first */
 337         sh_mobile_lcdc_start_stop(priv, 0);
 338
 339         /* configure clocks */
 340         tmp = priv->lddckr;
 341         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 342                 ch = &priv->ch[k];
 343
 344                 if (!priv->ch[k].enabled)
 345                         continue;
 346
 347                 m = ch->cfg.clock_divider;
 348                 if (!m)
 349                         continue;
 350
 351                 if (m == 1)
 352                         m = 1 << 6;
 353                 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
 354
 355                 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
 356                 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
 357         }
 358
 359         lcdc_write(priv, _LDDCKR, tmp);
 360
 361         /* start dotclock again */
 362         lcdc_write(priv, _LDDCKSTPR, 0);
 363         lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
 364
 365         /* interrupts are disabled to begin with */
 366         lcdc_write(priv, _LDINTR, 0);
 367
 368         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 369                 ch = &priv->ch[k];
 370                 lcd_cfg = &ch->cfg.lcd_cfg;
 371
 372                 if (!ch->enabled)
 373                         continue;
 374
 375                 tmp = ch->ldmt1r_value;
 376                 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
 377                 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
 378                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
 379                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
 380                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
 381                 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
 382                 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
 383                 lcdc_write_chan(ch, LDMT1R, tmp);
 384
 385                 /* setup SYS bus */
 386                 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
 387                 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
 388
 389                 /* horizontal configuration */
 390                 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
 391                 tmp += lcd_cfg->left_margin;
 392                 tmp += lcd_cfg->right_margin;
 393                 tmp /= 8; /* HTCN */
 394                 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
 395                 lcdc_write_chan(ch, LDHCNR, tmp);
 396
 397                 tmp = lcd_cfg->xres;
 398                 tmp += lcd_cfg->right_margin;
 399                 tmp /= 8; /* HSYNP */
 400                 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
 401                 lcdc_write_chan(ch, LDHSYNR, tmp);
 402
 403                 /* power supply */
 404                 lcdc_write_chan(ch, LDPMR, 0);
 405
 406                 /* vertical configuration */
 407                 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
 408                 tmp += lcd_cfg->upper_margin;
 409                 tmp += lcd_cfg->lower_margin; /* VTLN */
 410                 tmp |= lcd_cfg->yres << 16; /* VDLN */
 411                 lcdc_write_chan(ch, LDVLNR, tmp);
 412
 413                 tmp = lcd_cfg->yres;
 414                 tmp += lcd_cfg->lower_margin; /* VSYNP */
 415                 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
 416                 lcdc_write_chan(ch, LDVSYNR, tmp);
 417
 418                 board_cfg = &ch->cfg.board_cfg;
 419                 if (board_cfg->setup_sys)
 420                         ret = board_cfg->setup_sys(board_cfg->board_data, ch,
 421                                                    &sh_mobile_lcdc_sys_bus_ops);
 422                 if (ret)
 423                         return ret;
 424         }
 425
 426         /* word and long word swap */
 427         lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
 428
 429         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 430                 ch = &priv->ch[k];
 431
 432                 if (!priv->ch[k].enabled)
 433                         continue;
 434
 435                 /* set bpp format in PKF[4:0] */
 436                 tmp = lcdc_read_chan(ch, LDDFR);
 437                 tmp &= ~(0x0001001f);
 438                 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
 439                 lcdc_write_chan(ch, LDDFR, tmp);
 440
 441                 /* point out our frame buffer */
 442                 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
 443
 444                 /* set line size */
 445                 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
 446
 447                 /* setup deferred io if SYS bus */
 448                 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
 449                 if (ch->ldmt1r_value & (1 << 12) && tmp) {
 450                         ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
 451                         ch->defio.delay = msecs_to_jiffies(tmp);
 452                         ch->info->fbdefio = &ch->defio;
 453                         fb_deferred_io_init(ch->info);
 454
 455                         /* one-shot mode */
 456                         lcdc_write_chan(ch, LDSM1R, 1);
 457
 458                         /* enable "Frame End Interrupt Enable" bit */
 459                         lcdc_write(priv, _LDINTR, LDINTR_FE);
 460
 461                 } else {
 462                         /* continuous read mode */
 463                         lcdc_write_chan(ch, LDSM1R, 0);
 464                 }
 465         }
 466
 467         /* display output */
 468         lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
 469
 470         /* start the lcdc */
 471         sh_mobile_lcdc_start_stop(priv, 1);
 472         priv->started = 1;
 473
 474         /* tell the board code to enable the panel */
 475         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 476                 ch = &priv->ch[k];
 477                 board_cfg = &ch->cfg.board_cfg;
 478                 if (board_cfg->display_on)
 479                         board_cfg->display_on(board_cfg->board_data);
 480         }
 481
 482         return 0;
 483 }
 484
 485 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
 486 {
 487         struct sh_mobile_lcdc_chan *ch;
 488         struct sh_mobile_lcdc_board_cfg *board_cfg;
 489         int k;
 490
 491         /* clean up deferred io and ask board code to disable panel */
 492         for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
 493                 ch = &priv->ch[k];
 494
 495                 /* deferred io mode:
 496                  * flush frame, and wait for frame end interrupt
 497                  * clean up deferred io and enable clock
 498                  */
 499                 if (ch->info->fbdefio) {
 500                         ch->frame_end = 0;
 501                         schedule_delayed_work(&ch->info->deferred_work, 0);
 502                         wait_event(ch->frame_end_wait, ch->frame_end);
 503                         fb_deferred_io_cleanup(ch->info);
 504                         ch->info->fbdefio = NULL;
 505                         sh_mobile_lcdc_clk_on(priv);
 506                 }
 507
 508                 board_cfg = &ch->cfg.board_cfg;
 509                 if (board_cfg->display_off)
 510                         board_cfg->display_off(board_cfg->board_data);
 511         }
 512
 513         /* stop the lcdc */
 514         if (priv->started) {
 515                 sh_mobile_lcdc_start_stop(priv, 0);
 516                 priv->started = 0;
 517         }
 518
 519         /* stop clocks */
 520         for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
 521                 if (priv->ch[k].enabled)
 522                         sh_mobile_lcdc_clk_off(priv);
 523 }
 524
 525 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
 526 {
 527         int ifm, miftyp;
 528
 529         switch (ch->cfg.interface_type) {
 530         case RGB8: ifm = 0; miftyp = 0; break;
 531         case RGB9: ifm = 0; miftyp = 4; break;
 532         case RGB12A: ifm = 0; miftyp = 5; break;
 533         case RGB12B: ifm = 0; miftyp = 6; break;
 534         case RGB16: ifm = 0; miftyp = 7; break;
 535         case RGB18: ifm = 0; miftyp = 10; break;
 536         case RGB24: ifm = 0; miftyp = 11; break;
 537         case SYS8A: ifm = 1; miftyp = 0; break;
 538         case SYS8B: ifm = 1; miftyp = 1; break;
 539         case SYS8C: ifm = 1; miftyp = 2; break;
 540         case SYS8D: ifm = 1; miftyp = 3; break;
 541         case SYS9: ifm = 1; miftyp = 4; break;
 542         case SYS12: ifm = 1; miftyp = 5; break;
 543         case SYS16A: ifm = 1; miftyp = 7; break;
 544         case SYS16B: ifm = 1; miftyp = 8; break;
 545         case SYS16C: ifm = 1; miftyp = 9; break;
 546         case SYS18: ifm = 1; miftyp = 10; break;
 547         case SYS24: ifm = 1; miftyp = 11; break;
 548         default: goto bad;
 549         }
 550
 551         /* SUBLCD only supports SYS interface */
 552         if (lcdc_chan_is_sublcd(ch)) {
 553                 if (ifm == 0)
 554                         goto bad;
 555                 else
 556                         ifm = 0;
 557         }
 558
 559         ch->ldmt1r_value = (ifm << 12) | miftyp;
 560         return 0;
 561  bad:
 562         return -EINVAL;
 563 }
 564
 565 static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
 566                                        int clock_source,
 567                                        struct sh_mobile_lcdc_priv *priv)
 568 {
 569         char clk_name[8];
 570         char *str;
 571         int icksel;
 572
 573         switch (clock_source) {
 574         case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
 575         case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
 576         case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
 577         default:
 578                 return -EINVAL;
 579         }
 580
 581         priv->lddckr = icksel << 16;
 582
 583         atomic_set(&priv->clk_usecnt, -1);
 584         snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
 585         priv->clk = clk_get(&pdev->dev, clk_name);
 586         if (IS_ERR(priv->clk)) {
 587                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 588                 return PTR_ERR(priv->clk);
 589         }
 590
 591         if (str) {
 592                 priv->dot_clk = clk_get(&pdev->dev, str);
 593                 if (IS_ERR(priv->dot_clk)) {
 594                         dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
 595                         clk_put(priv->clk);
 596                         return PTR_ERR(priv->dot_clk);
 597                 }
 598         }
 599
 600         return 0;
 601 }
 602
 603 static int sh_mobile_lcdc_setcolreg(u_int regno,
 604                                     u_int red, u_int green, u_int blue,
 605                                     u_int transp, struct fb_info *info)
 606 {
 607         u32 *palette = info->pseudo_palette;
 608
 609         if (regno >= PALETTE_NR)
 610                 return -EINVAL;
 611
 612         /* only FB_VISUAL_TRUECOLOR supported */
 613
 614         red >>= 16 - info->var.red.length;
 615         green >>= 16 - info->var.green.length;
 616         blue >>= 16 - info->var.blue.length;
 617         transp >>= 16 - info->var.transp.length;
 618
 619         palette[regno] = (red << info->var.red.offset) |
 620           (green << info->var.green.offset) |
 621           (blue << info->var.blue.offset) |
 622           (transp << info->var.transp.offset);
 623
 624         return 0;
 625 }
 626
 627 static struct fb_fix_screeninfo sh_mobile_lcdc_fix  = {
 628         .id =           "SH Mobile LCDC",
 629         .type =         FB_TYPE_PACKED_PIXELS,
 630         .visual =       FB_VISUAL_TRUECOLOR,
 631         .accel =        FB_ACCEL_NONE,
 632 };
 633
 634 static void sh_mobile_lcdc_fillrect(struct fb_info *info,
 635                                     const struct fb_fillrect *rect)
 636 {
 637         sys_fillrect(info, rect);
 638         sh_mobile_lcdc_deferred_io_touch(info);
 639 }
 640
 641 static void sh_mobile_lcdc_copyarea(struct fb_info *info,
 642                                     const struct fb_copyarea *area)
 643 {
 644         sys_copyarea(info, area);
 645         sh_mobile_lcdc_deferred_io_touch(info);
 646 }
 647
 648 static void sh_mobile_lcdc_imageblit(struct fb_info *info,
 649                                      const struct fb_image *image)
 650 {
 651         sys_imageblit(info, image);
 652         sh_mobile_lcdc_deferred_io_touch(info);
 653 }
 654
 655 static struct fb_ops sh_mobile_lcdc_ops = {
 656         .fb_setcolreg   = sh_mobile_lcdc_setcolreg,
 657         .fb_read        = fb_sys_read,
 658         .fb_write       = fb_sys_write,
 659         .fb_fillrect    = sh_mobile_lcdc_fillrect,
 660         .fb_copyarea    = sh_mobile_lcdc_copyarea,
 661         .fb_imageblit   = sh_mobile_lcdc_imageblit,
 662 };
 663
 664 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
 665 {
 666         switch (bpp) {
 667         case 16: /* PKF[4:0] = 00011 - RGB 565 */
 668                 var->red.offset = 11;
 669                 var->red.length = 5;
 670                 var->green.offset = 5;
 671                 var->green.length = 6;
 672                 var->blue.offset = 0;
 673                 var->blue.length = 5;
 674                 var->transp.offset = 0;
 675                 var->transp.length = 0;
 676                 break;
 677
 678         case 32: /* PKF[4:0] = 00000 - RGB 888
 679                   * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
 680                   * this may be because LDDDSR has word swap enabled..
 681                   */
 682                 var->red.offset = 0;
 683                 var->red.length = 8;
 684                 var->green.offset = 24;
 685                 var->green.length = 8;
 686                 var->blue.offset = 16;
 687                 var->blue.length = 8;
 688                 var->transp.offset = 0;
 689                 var->transp.length = 0;
 690                 break;
 691         default:
 692                 return -EINVAL;
 693         }
 694         var->bits_per_pixel = bpp;
 695         var->red.msb_right = 0;
 696         var->green.msb_right = 0;
 697         var->blue.msb_right = 0;
 698         var->transp.msb_right = 0;
 699         return 0;
 700 }
 701
 702 static int sh_mobile_lcdc_suspend(struct device *dev)
 703 {
 704         struct platform_device *pdev = to_platform_device(dev);
 705
 706         sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
 707         return 0;
 708 }
 709
 710 static int sh_mobile_lcdc_resume(struct device *dev)
 711 {
 712         struct platform_device *pdev = to_platform_device(dev);
 713
 714         return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
 715 }
 716
 717 static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
 718         .suspend = sh_mobile_lcdc_suspend,
 719         .resume = sh_mobile_lcdc_resume,
 720 };
 721
 722 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
 723
 724 static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
 725 {
 726         struct fb_info *info;
 727         struct sh_mobile_lcdc_priv *priv;
 728         struct sh_mobile_lcdc_info *pdata;
 729         struct sh_mobile_lcdc_chan_cfg *cfg;
 730         struct resource *res;
 731         int error;
 732         void *buf;
 733         int i, j;
 734
 735         if (!pdev->dev.platform_data) {
 736                 dev_err(&pdev->dev, "no platform data defined\n");
 737                 error = -EINVAL;
 738                 goto err0;
 739         }
 740
 741         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 742         i = platform_get_irq(pdev, 0);
 743         if (!res || i < 0) {
 744                 dev_err(&pdev->dev, "cannot get platform resources\n");
 745                 error = -ENOENT;
 746                 goto err0;
 747         }
 748
 749         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 750         if (!priv) {
 751                 dev_err(&pdev->dev, "cannot allocate device data\n");
 752                 error = -ENOMEM;
 753                 goto err0;
 754         }
 755
 756         error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
 757                             dev_name(&pdev->dev), priv);
 758         if (error) {
 759                 dev_err(&pdev->dev, "unable to request irq\n");
 760                 goto err1;
 761         }
 762
 763         priv->irq = i;
 764         platform_set_drvdata(pdev, priv);
 765         pdata = pdev->dev.platform_data;
 766
 767         j = 0;
 768         for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
 769                 priv->ch[j].lcdc = priv;
 770                 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
 771
 772                 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
 773                 if (error) {
 774                         dev_err(&pdev->dev, "unsupported interface type\n");
 775                         goto err1;
 776                 }
 777                 init_waitqueue_head(&priv->ch[i].frame_end_wait);
 778
 779                 switch (pdata->ch[i].chan) {
 780                 case LCDC_CHAN_MAINLCD:
 781                         priv->ch[j].enabled = 1 << 1;
 782                         priv->ch[j].reg_offs = lcdc_offs_mainlcd;
 783                         j++;
 784                         break;
 785                 case LCDC_CHAN_SUBLCD:
 786                         priv->ch[j].enabled = 1 << 2;
 787                         priv->ch[j].reg_offs = lcdc_offs_sublcd;
 788                         j++;
 789                         break;
 790                 }
 791         }
 792
 793         if (!j) {
 794                 dev_err(&pdev->dev, "no channels defined\n");
 795                 error = -EINVAL;
 796                 goto err1;
 797         }
 798
 799         error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
 800         if (error) {
 801                 dev_err(&pdev->dev, "unable to setup clocks\n");
 802                 goto err1;
 803         }
 804
 805         priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
 806
 807         for (i = 0; i < j; i++) {
 808                 cfg = &priv->ch[i].cfg;
 809
 810                 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
 811                 if (!priv->ch[i].info) {
 812                         dev_err(&pdev->dev, "unable to allocate fb_info\n");
 813                         error = -ENOMEM;
 814                         break;
 815                 }
 816
 817                 info = priv->ch[i].info;
 818                 info->fbops = &sh_mobile_lcdc_ops;
 819                 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
 820                 info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
 821                 info->var.width = cfg->lcd_size_cfg.width;
 822                 info->var.height = cfg->lcd_size_cfg.height;
 823                 info->var.activate = FB_ACTIVATE_NOW;
 824                 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
 825                 if (error)
 826                         break;
 827
 828                 info->fix = sh_mobile_lcdc_fix;
 829                 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
 830                 info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
 831
 832                 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
 833                                          &priv->ch[i].dma_handle, GFP_KERNEL);
 834                 if (!buf) {
 835                         dev_err(&pdev->dev, "unable to allocate buffer\n");
 836                         error = -ENOMEM;
 837                         break;
 838                 }
 839
 840                 info->pseudo_palette = &priv->ch[i].pseudo_palette;
 841                 info->flags = FBINFO_FLAG_DEFAULT;
 842
 843                 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
 844                 if (error < 0) {
 845                         dev_err(&pdev->dev, "unable to allocate cmap\n");
 846                         dma_free_coherent(&pdev->dev, info->fix.smem_len,
 847                                           buf, priv->ch[i].dma_handle);
 848                         break;
 849                 }
 850
 851                 memset(buf, 0, info->fix.smem_len);
 852                 info->fix.smem_start = priv->ch[i].dma_handle;
 853                 info->screen_base = buf;
 854                 info->device = &pdev->dev;
 855                 info->par = &priv->ch[i];
 856         }
 857
 858         if (error)
 859                 goto err1;
 860
 861         error = sh_mobile_lcdc_start(priv);
 862         if (error) {
 863                 dev_err(&pdev->dev, "unable to start hardware\n");
 864                 goto err1;
 865         }
 866
 867         for (i = 0; i < j; i++) {
 868                 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
 869
 870                 info = ch->info;
 871
 872                 if (info->fbdefio) {
 873                         priv->ch->sglist = vmalloc(sizeof(struct scatterlist) *
 874                                         info->fix.smem_len >> PAGE_SHIFT);
 875                         if (!priv->ch->sglist) {
 876                                 dev_err(&pdev->dev, "cannot allocate sglist\n");
 877                                 goto err1;
 878                         }
 879                 }
 880
 881                 error = register_framebuffer(info);
 882                 if (error < 0)
 883                         goto err1;
 884
 885                 dev_info(info->dev,
 886                          "registered %s/%s as %dx%d %dbpp.\n",
 887                          pdev->name,
 888                          (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
 889                          "mainlcd" : "sublcd",
 890                          (int) ch->cfg.lcd_cfg.xres,
 891                          (int) ch->cfg.lcd_cfg.yres,
 892                          ch->cfg.bpp);
 893
 894                 /* deferred io mode: disable clock to save power */
 895                 if (info->fbdefio)
 896                         sh_mobile_lcdc_clk_off(priv);
 897         }
 898
 899         return 0;
 900  err1:
 901         sh_mobile_lcdc_remove(pdev);
 902  err0:
 903         return error;
 904 }
 905
 906 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
 907 {
 908         struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
 909         struct fb_info *info;
 910         int i;
 911
 912         for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
 913                 if (priv->ch[i].info->dev)
 914                         unregister_framebuffer(priv->ch[i].info);
 915
 916         sh_mobile_lcdc_stop(priv);
 917
 918         for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
 919                 info = priv->ch[i].info;
 920
 921                 if (!info || !info->device)
 922                         continue;
 923
 924                 if (priv->ch[i].sglist)
 925                         vfree(priv->ch[i].sglist);
 926
 927                 dma_free_coherent(&pdev->dev, info->fix.smem_len,
 928                                   info->screen_base, priv->ch[i].dma_handle);
 929                 fb_dealloc_cmap(&info->cmap);
 930                 framebuffer_release(info);
 931         }
 932
 933         if (priv->dot_clk)
 934                 clk_put(priv->dot_clk);
 935         clk_put(priv->clk);
 936
 937         if (priv->base)
 938                 iounmap(priv->base);
 939
 940         if (priv->irq)
 941                 free_irq(priv->irq, priv);
 942         kfree(priv);
 943         return 0;
 944 }
 945
 946 static struct platform_driver sh_mobile_lcdc_driver = {
 947         .driver         = {
 948                 .name           = "sh_mobile_lcdc_fb",
 949                 .owner          = THIS_MODULE,
 950                 .pm             = &sh_mobile_lcdc_dev_pm_ops,
 951         },
 952         .probe          = sh_mobile_lcdc_probe,
 953         .remove         = sh_mobile_lcdc_remove,
 954 };
 955
 956 static int __init sh_mobile_lcdc_init(void)
 957 {
 958         return platform_driver_register(&sh_mobile_lcdc_driver);
 959 }
 960
 961 static void __exit sh_mobile_lcdc_exit(void)
 962 {
 963         platform_driver_unregister(&sh_mobile_lcdc_driver);
 964 }
 965
 966 module_init(sh_mobile_lcdc_init);
 967 module_exit(sh_mobile_lcdc_exit);
 968
 969 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
 970 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
 971 MODULE_LICENSE("GPL v2");