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   1 #ifndef __PXAFB_H__
   2 #define __PXAFB_H__
   3
   4 /*
   5  * linux/drivers/video/pxafb.h
   6  *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
   7  *
   8  *  Copyright (C) 1999 Eric A. Thomas.
   9  *  Copyright (C) 2004 Jean-Frederic Clere.
  10  *  Copyright (C) 2004 Ian Campbell.
  11  *  Copyright (C) 2004 Jeff Lackey.
  12  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
  13  *  which in turn is
  14  *   Based on acornfb.c Copyright (C) Russell King.
  15  *
  16  *  2001-08-03: Cliff Brake <cbrake@acclent.com>
  17  *       - ported SA1100 code to PXA
  18  *
  19  * This file is subject to the terms and conditions of the GNU General Public
  20  * License.  See the file COPYING in the main directory of this archive
  21  * for more details.
  22  */
  23
  24 /* Shadows for LCD controller registers */
  25 struct pxafb_lcd_reg {
  26         unsigned int lccr0;
  27         unsigned int lccr1;
  28         unsigned int lccr2;
  29         unsigned int lccr3;
  30 };
  31
  32 /* PXA LCD DMA descriptor */
  33 struct pxafb_dma_descriptor {
  34         unsigned int fdadr;
  35         unsigned int fsadr;
  36         unsigned int fidr;
  37         unsigned int ldcmd;
  38 };
  39
  40 struct pxafb_info {
  41         struct fb_info          fb;
  42         struct device           *dev;
  43         struct clk              *clk;
  44
  45         void __iomem            *mmio_base;
  46
  47         /*
  48          * These are the addresses we mapped
  49          * the framebuffer memory region to.
  50          */
  51         /* raw memory addresses */
  52         dma_addr_t              map_dma;        /* physical */
  53         u_char *                map_cpu;        /* virtual */
  54         u_int                   map_size;
  55
  56         /* addresses of pieces placed in raw buffer */
  57         u_char *                screen_cpu;     /* virtual address of frame buffer */
  58         dma_addr_t              screen_dma;     /* physical address of frame buffer */
  59         u16 *                   palette_cpu;    /* virtual address of palette memory */
  60         dma_addr_t              palette_dma;    /* physical address of palette memory */
  61         u_int                   palette_size;
  62
  63         /* DMA descriptors */
  64         struct pxafb_dma_descriptor *   dmadesc_fblow_cpu;
  65         dma_addr_t              dmadesc_fblow_dma;
  66         struct pxafb_dma_descriptor *   dmadesc_fbhigh_cpu;
  67         dma_addr_t              dmadesc_fbhigh_dma;
  68         struct pxafb_dma_descriptor *   dmadesc_palette_cpu;
  69         dma_addr_t              dmadesc_palette_dma;
  70
  71         dma_addr_t              fdadr0;
  72         dma_addr_t              fdadr1;
  73
  74         u_int                   lccr0;
  75         u_int                   lccr3;
  76         u_int                   lccr4;
  77         u_int                   cmap_inverse:1,
  78                                 cmap_static:1,
  79                                 unused:30;
  80
  81         u_int                   reg_lccr0;
  82         u_int                   reg_lccr1;
  83         u_int                   reg_lccr2;
  84         u_int                   reg_lccr3;
  85         u_int                   reg_lccr4;
  86
  87         unsigned long   hsync_time;
  88
  89         volatile u_char         state;
  90         volatile u_char         task_state;
  91         struct semaphore        ctrlr_sem;
  92         wait_queue_head_t       ctrlr_wait;
  93         struct work_struct      task;
  94
  95 #ifdef CONFIG_CPU_FREQ
  96         struct notifier_block   freq_transition;
  97         struct notifier_block   freq_policy;
  98 #endif
  99 };
 100
 101 #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
 102
 103 /*
 104  * These are the actions for set_ctrlr_state
 105  */
 106 #define C_DISABLE               (0)
 107 #define C_ENABLE                (1)
 108 #define C_DISABLE_CLKCHANGE     (2)
 109 #define C_ENABLE_CLKCHANGE      (3)
 110 #define C_REENABLE              (4)
 111 #define C_DISABLE_PM            (5)
 112 #define C_ENABLE_PM             (6)
 113 #define C_STARTUP               (7)
 114
 115 #define PXA_NAME        "PXA"
 116
 117 /*
 118  * Minimum X and Y resolutions
 119  */
 120 #define MIN_XRES        64
 121 #define MIN_YRES        64
 122
 123 #endif /* __PXAFB_H__ */