2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
48 #include <mach/hardware.h>
51 #include <asm/div64.h>
52 #include <mach/pxa-regs.h>
53 #include <mach/bitfield.h>
54 #include <mach/pxafb.h>
57 * Complain if VAR is out of range.
63 /* Bits which should not be set in machine configuration structures */
64 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP)
71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
75 static unsigned long video_mem_size = 0;
77 static inline unsigned long
78 lcd_readl(struct pxafb_info *fbi, unsigned int off)
80 return __raw_readl(fbi->mmio_base + off);
84 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
86 __raw_writel(val, fbi->mmio_base + off);
89 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
93 local_irq_save(flags);
95 * We need to handle two requests being made at the same time.
96 * There are two important cases:
97 * 1. When we are changing VT (C_REENABLE) while unblanking
98 * (C_ENABLE) We must perform the unblanking, which will
99 * do our REENABLE for us.
100 * 2. When we are blanking, but immediately unblank before
101 * we have blanked. We do the "REENABLE" thing here as
102 * well, just to be sure.
104 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
106 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
109 if (state != (u_int)-1) {
110 fbi->task_state = state;
111 schedule_work(&fbi->task);
113 local_irq_restore(flags);
116 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
119 chan >>= 16 - bf->length;
120 return chan << bf->offset;
124 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
125 u_int trans, struct fb_info *info)
127 struct pxafb_info *fbi = (struct pxafb_info *)info;
130 if (regno >= fbi->palette_size)
133 if (fbi->fb.var.grayscale) {
134 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
138 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
139 case LCCR4_PAL_FOR_0:
140 val = ((red >> 0) & 0xf800);
141 val |= ((green >> 5) & 0x07e0);
142 val |= ((blue >> 11) & 0x001f);
143 fbi->palette_cpu[regno] = val;
145 case LCCR4_PAL_FOR_1:
146 val = ((red << 8) & 0x00f80000);
147 val |= ((green >> 0) & 0x0000fc00);
148 val |= ((blue >> 8) & 0x000000f8);
149 ((u32 *)(fbi->palette_cpu))[regno] = val;
151 case LCCR4_PAL_FOR_2:
152 val = ((red << 8) & 0x00fc0000);
153 val |= ((green >> 0) & 0x0000fc00);
154 val |= ((blue >> 8) & 0x000000fc);
155 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
164 u_int trans, struct fb_info *info)
166 struct pxafb_info *fbi = (struct pxafb_info *)info;
171 * If inverse mode was selected, invert all the colours
172 * rather than the register number. The register number
173 * is what you poke into the framebuffer to produce the
174 * colour you requested.
176 if (fbi->cmap_inverse) {
178 green = 0xffff - green;
179 blue = 0xffff - blue;
183 * If greyscale is true, then we convert the RGB value
184 * to greyscale no matter what visual we are using.
186 if (fbi->fb.var.grayscale)
187 red = green = blue = (19595 * red + 38470 * green +
190 switch (fbi->fb.fix.visual) {
191 case FB_VISUAL_TRUECOLOR:
193 * 16-bit True Colour. We encode the RGB value
194 * according to the RGB bitfield information.
197 u32 *pal = fbi->fb.pseudo_palette;
199 val = chan_to_field(red, &fbi->fb.var.red);
200 val |= chan_to_field(green, &fbi->fb.var.green);
201 val |= chan_to_field(blue, &fbi->fb.var.blue);
208 case FB_VISUAL_STATIC_PSEUDOCOLOR:
209 case FB_VISUAL_PSEUDOCOLOR:
210 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
218 * pxafb_bpp_to_lccr3():
219 * Convert a bits per pixel value to the correct bit pattern for LCCR3
221 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
224 switch (var->bits_per_pixel) {
225 case 1: ret = LCCR3_1BPP; break;
226 case 2: ret = LCCR3_2BPP; break;
227 case 4: ret = LCCR3_4BPP; break;
228 case 8: ret = LCCR3_8BPP; break;
229 case 16: ret = LCCR3_16BPP; break;
231 switch (var->red.length + var->green.length +
232 var->blue.length + var->transp.length) {
233 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
234 case 19: ret = LCCR3_19BPP_P; break;
238 switch (var->red.length + var->green.length +
239 var->blue.length + var->transp.length) {
240 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
241 case 19: ret = LCCR3_19BPP; break;
242 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
243 case 25: ret = LCCR3_25BPP; break;
250 #ifdef CONFIG_CPU_FREQ
252 * pxafb_display_dma_period()
253 * Calculate the minimum period (in picoseconds) between two DMA
254 * requests for the LCD controller. If we hit this, it means we're
255 * doing nothing but LCD DMA.
257 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
260 * Period = pixclock * bits_per_byte * bytes_per_transfer
261 * / memory_bits_per_pixel;
263 return var->pixclock * 8 * 16 / var->bits_per_pixel;
268 * Select the smallest mode that allows the desired resolution to be
269 * displayed. If desired parameters can be rounded up.
271 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
272 struct fb_var_screeninfo *var)
274 struct pxafb_mode_info *mode = NULL;
275 struct pxafb_mode_info *modelist = mach->modes;
276 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
279 for (i = 0; i < mach->num_modes; i++) {
280 if (modelist[i].xres >= var->xres &&
281 modelist[i].yres >= var->yres &&
282 modelist[i].xres < best_x &&
283 modelist[i].yres < best_y &&
284 modelist[i].bpp >= var->bits_per_pixel) {
285 best_x = modelist[i].xres;
286 best_y = modelist[i].yres;
294 static void pxafb_setmode(struct fb_var_screeninfo *var,
295 struct pxafb_mode_info *mode)
297 var->xres = mode->xres;
298 var->yres = mode->yres;
299 var->bits_per_pixel = mode->bpp;
300 var->pixclock = mode->pixclock;
301 var->hsync_len = mode->hsync_len;
302 var->left_margin = mode->left_margin;
303 var->right_margin = mode->right_margin;
304 var->vsync_len = mode->vsync_len;
305 var->upper_margin = mode->upper_margin;
306 var->lower_margin = mode->lower_margin;
307 var->sync = mode->sync;
308 var->grayscale = mode->cmap_greyscale;
313 * Get the video params out of 'var'. If a value doesn't fit, round it up,
314 * if it's too big, return -EINVAL.
316 * Round up in the following order: bits_per_pixel, xres,
317 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
318 * bitfields, horizontal timing, vertical timing.
320 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
322 struct pxafb_info *fbi = (struct pxafb_info *)info;
323 struct pxafb_mach_info *inf = fbi->dev->platform_data;
325 if (var->xres < MIN_XRES)
326 var->xres = MIN_XRES;
327 if (var->yres < MIN_YRES)
328 var->yres = MIN_YRES;
330 if (inf->fixed_modes) {
331 struct pxafb_mode_info *mode;
333 mode = pxafb_getmode(inf, var);
336 pxafb_setmode(var, mode);
338 if (var->xres > inf->modes->xres)
340 if (var->yres > inf->modes->yres)
342 if (var->bits_per_pixel > inf->modes->bpp)
346 /* we don't support xpan, force xres_virtual to be equal to xres */
347 var->xres_virtual = var->xres;
349 if (var->accel_flags & FB_ACCELF_TEXT)
350 var->yres_virtual = fbi->fb.fix.smem_len /
351 (var->xres_virtual * var->bits_per_pixel / 8);
353 var->yres_virtual = max(var->yres_virtual, var->yres);
356 * Setup the RGB parameters for this display.
358 * The pixel packing format is described on page 7-11 of the
359 * PXA2XX Developer's Manual.
361 if (var->bits_per_pixel == 16) {
362 var->red.offset = 11; var->red.length = 5;
363 var->green.offset = 5; var->green.length = 6;
364 var->blue.offset = 0; var->blue.length = 5;
365 var->transp.offset = var->transp.length = 0;
366 } else if (var->bits_per_pixel > 16) {
367 struct pxafb_mode_info *mode;
369 mode = pxafb_getmode(inf, var);
373 switch (mode->depth) {
374 case 18: /* RGB666 */
375 var->transp.offset = var->transp.length = 0;
376 var->red.offset = 12; var->red.length = 6;
377 var->green.offset = 6; var->green.length = 6;
378 var->blue.offset = 0; var->blue.length = 6;
380 case 19: /* RGBT666 */
381 var->transp.offset = 18; var->transp.length = 1;
382 var->red.offset = 12; var->red.length = 6;
383 var->green.offset = 6; var->green.length = 6;
384 var->blue.offset = 0; var->blue.length = 6;
386 case 24: /* RGB888 */
387 var->transp.offset = var->transp.length = 0;
388 var->red.offset = 16; var->red.length = 8;
389 var->green.offset = 8; var->green.length = 8;
390 var->blue.offset = 0; var->blue.length = 8;
392 case 25: /* RGBT888 */
393 var->transp.offset = 24; var->transp.length = 1;
394 var->red.offset = 16; var->red.length = 8;
395 var->green.offset = 8; var->green.length = 8;
396 var->blue.offset = 0; var->blue.length = 8;
402 var->red.offset = var->green.offset = 0;
403 var->blue.offset = var->transp.offset = 0;
405 var->green.length = 8;
406 var->blue.length = 8;
407 var->transp.length = 0;
410 #ifdef CONFIG_CPU_FREQ
411 pr_debug("pxafb: dma period = %d ps\n",
412 pxafb_display_dma_period(var));
418 static inline void pxafb_set_truecolor(u_int is_true_color)
420 /* do your machine-specific setup if needed */
425 * Set the user defined part of the display for the specified console
427 static int pxafb_set_par(struct fb_info *info)
429 struct pxafb_info *fbi = (struct pxafb_info *)info;
430 struct fb_var_screeninfo *var = &info->var;
432 if (var->bits_per_pixel >= 16)
433 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
434 else if (!fbi->cmap_static)
435 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
438 * Some people have weird ideas about wanting static
439 * pseudocolor maps. I suspect their user space
440 * applications are broken.
442 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
445 fbi->fb.fix.line_length = var->xres_virtual *
446 var->bits_per_pixel / 8;
447 if (var->bits_per_pixel >= 16)
448 fbi->palette_size = 0;
450 fbi->palette_size = var->bits_per_pixel == 1 ?
451 4 : 1 << var->bits_per_pixel;
453 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
456 * Set (any) board control register to handle new color depth
458 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
460 if (fbi->fb.var.bits_per_pixel >= 16)
461 fb_dealloc_cmap(&fbi->fb.cmap);
463 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
465 pxafb_activate_var(var, fbi);
472 * Blank the display by setting all palette values to zero. Note, the
473 * 16 bpp mode does not really use the palette, so this will not
474 * blank the display in all modes.
476 static int pxafb_blank(int blank, struct fb_info *info)
478 struct pxafb_info *fbi = (struct pxafb_info *)info;
482 case FB_BLANK_POWERDOWN:
483 case FB_BLANK_VSYNC_SUSPEND:
484 case FB_BLANK_HSYNC_SUSPEND:
485 case FB_BLANK_NORMAL:
486 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
487 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
488 for (i = 0; i < fbi->palette_size; i++)
489 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
491 pxafb_schedule_work(fbi, C_DISABLE);
492 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
495 case FB_BLANK_UNBLANK:
496 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
497 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
498 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
499 fb_set_cmap(&fbi->fb.cmap, info);
500 pxafb_schedule_work(fbi, C_ENABLE);
505 static struct fb_ops pxafb_ops = {
506 .owner = THIS_MODULE,
507 .fb_check_var = pxafb_check_var,
508 .fb_set_par = pxafb_set_par,
509 .fb_setcolreg = pxafb_setcolreg,
510 .fb_fillrect = cfb_fillrect,
511 .fb_copyarea = cfb_copyarea,
512 .fb_imageblit = cfb_imageblit,
513 .fb_blank = pxafb_blank,
517 * Calculate the PCD value from the clock rate (in picoseconds).
518 * We take account of the PPCR clock setting.
519 * From PXA Developer's Manual:
530 * LCLK = LCD/Memory Clock
533 * PixelClock here is in Hz while the pixclock argument given is the
534 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
536 * The function get_lclk_frequency_10khz returns LCLK in units of
537 * 10khz. Calling the result of this function lclk gives us the
540 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
541 * -------------------------------------- - 1
544 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
546 static inline unsigned int get_pcd(struct pxafb_info *fbi,
547 unsigned int pixclock)
549 unsigned long long pcd;
551 /* FIXME: Need to take into account Double Pixel Clock mode
552 * (DPC) bit? or perhaps set it based on the various clock
554 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
556 do_div(pcd, 100000000 * 2);
557 /* no need for this, since we should subtract 1 anyway. they cancel */
558 /* pcd += 1; */ /* make up for integer math truncations */
559 return (unsigned int)pcd;
563 * Some touchscreens need hsync information from the video driver to
564 * function correctly. We export it here. Note that 'hsync_time' and
565 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
566 * of the hsync period in seconds.
568 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
572 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
577 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
579 fbi->hsync_time = htime;
582 unsigned long pxafb_get_hsync_time(struct device *dev)
584 struct pxafb_info *fbi = dev_get_drvdata(dev);
586 /* If display is blanked/suspended, hsync isn't active */
587 if (!fbi || (fbi->state != C_ENABLE))
590 return fbi->hsync_time;
592 EXPORT_SYMBOL(pxafb_get_hsync_time);
594 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
595 unsigned int offset, size_t size)
597 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
598 unsigned int dma_desc_off, pal_desc_off;
600 if (dma < 0 || dma >= DMA_MAX)
603 dma_desc = &fbi->dma_buff->dma_desc[dma];
604 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
606 dma_desc->fsadr = fbi->video_mem_phys + offset;
608 dma_desc->ldcmd = size;
610 if (pal < 0 || pal >= PAL_MAX) {
611 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
612 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
614 pal_desc = &fbi->dma_buff->pal_desc[pal];
615 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
617 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
620 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
621 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
623 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
625 pal_desc->ldcmd |= LDCMD_PAL;
627 /* flip back and forth between palette and frame buffer */
628 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
629 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
630 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
636 #ifdef CONFIG_FB_PXA_SMARTPANEL
637 static int setup_smart_dma(struct pxafb_info *fbi)
639 struct pxafb_dma_descriptor *dma_desc;
640 unsigned long dma_desc_off, cmd_buff_off;
642 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
643 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
644 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
646 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
647 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
649 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
651 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
655 int pxafb_smart_flush(struct fb_info *info)
657 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
661 /* disable controller until all registers are set up */
662 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
664 /* 1. make it an even number of commands to align on 32-bit boundary
665 * 2. add the interrupt command to the end of the chain so we can
666 * keep track of the end of the transfer
669 while (fbi->n_smart_cmds & 1)
670 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
672 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
673 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
674 setup_smart_dma(fbi);
676 /* continue to execute next command */
677 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
678 lcd_writel(fbi, PRSR, prsr);
680 /* stop the processor in case it executed "wait for sync" cmd */
681 lcd_writel(fbi, CMDCR, 0x0001);
683 /* don't send interrupts for fifo underruns on channel 6 */
684 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
686 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
687 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
688 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
689 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
690 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
693 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
695 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
696 pr_warning("%s: timeout waiting for command done\n",
702 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
703 lcd_writel(fbi, PRSR, prsr);
704 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
705 lcd_writel(fbi, FDADR6, 0);
706 fbi->n_smart_cmds = 0;
710 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
713 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
715 for (i = 0; i < n_cmds; i++, cmds++) {
716 /* if it is a software delay, flush and delay */
717 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
718 pxafb_smart_flush(info);
719 mdelay(*cmds & 0xff);
723 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
724 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
725 pxafb_smart_flush(info);
727 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
733 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
735 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
736 return (t == 0) ? 1 : t;
739 static void setup_smart_timing(struct pxafb_info *fbi,
740 struct fb_var_screeninfo *var)
742 struct pxafb_mach_info *inf = fbi->dev->platform_data;
743 struct pxafb_mode_info *mode = &inf->modes[0];
744 unsigned long lclk = clk_get_rate(fbi->clk);
745 unsigned t1, t2, t3, t4;
747 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
748 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
749 t3 = mode->op_hold_time;
750 t4 = mode->cmd_inh_time;
753 LCCR1_DisWdth(var->xres) |
754 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
755 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
756 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
758 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
759 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
760 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
761 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
763 /* FIXME: make this configurable */
767 static int pxafb_smart_thread(void *arg)
769 struct pxafb_info *fbi = arg;
770 struct pxafb_mach_info *inf = fbi->dev->platform_data;
772 if (!fbi || !inf->smart_update) {
773 pr_err("%s: not properly initialized, thread terminated\n",
778 pr_debug("%s(): task starting\n", __func__);
781 while (!kthread_should_stop()) {
786 mutex_lock(&fbi->ctrlr_lock);
788 if (fbi->state == C_ENABLE) {
789 inf->smart_update(&fbi->fb);
790 complete(&fbi->refresh_done);
793 mutex_unlock(&fbi->ctrlr_lock);
795 set_current_state(TASK_INTERRUPTIBLE);
796 schedule_timeout(30 * HZ / 1000);
799 pr_debug("%s(): task ending\n", __func__);
803 static int pxafb_smart_init(struct pxafb_info *fbi)
805 if (!(fbi->lccr0 & LCCR0_LCDT))
808 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
809 fbi->n_smart_cmds = 0;
811 init_completion(&fbi->command_done);
812 init_completion(&fbi->refresh_done);
814 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
816 if (IS_ERR(fbi->smart_thread)) {
817 pr_err("%s: unable to create kernel thread\n", __func__);
818 return PTR_ERR(fbi->smart_thread);
824 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
829 int pxafb_smart_flush(struct fb_info *info)
834 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
835 #endif /* CONFIG_FB_PXA_SMARTPANEL */
837 static void setup_parallel_timing(struct pxafb_info *fbi,
838 struct fb_var_screeninfo *var)
840 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
843 LCCR1_DisWdth(var->xres) +
844 LCCR1_HorSnchWdth(var->hsync_len) +
845 LCCR1_BegLnDel(var->left_margin) +
846 LCCR1_EndLnDel(var->right_margin);
849 * If we have a dual scan LCD, we need to halve
850 * the YRES parameter.
852 lines_per_panel = var->yres;
853 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
854 lines_per_panel /= 2;
857 LCCR2_DisHght(lines_per_panel) +
858 LCCR2_VrtSnchWdth(var->vsync_len) +
859 LCCR2_BegFrmDel(var->upper_margin) +
860 LCCR2_EndFrmDel(var->lower_margin);
862 fbi->reg_lccr3 = fbi->lccr3 |
863 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
864 LCCR3_HorSnchH : LCCR3_HorSnchL) |
865 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
866 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
869 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
870 set_hsync_time(fbi, pcd);
875 * pxafb_activate_var():
876 * Configures LCD Controller based on entries in var parameter.
877 * Settings are only written to the controller if changes were made.
879 static int pxafb_activate_var(struct fb_var_screeninfo *var,
880 struct pxafb_info *fbi)
883 size_t nbytes, offset;
886 if (!(fbi->lccr0 & LCCR0_LCDT)) {
887 if (var->xres < 16 || var->xres > 1024)
888 printk(KERN_ERR "%s: invalid xres %d\n",
889 fbi->fb.fix.id, var->xres);
890 switch (var->bits_per_pixel) {
900 printk(KERN_ERR "%s: invalid bit depth %d\n",
901 fbi->fb.fix.id, var->bits_per_pixel);
905 if (var->hsync_len < 1 || var->hsync_len > 64)
906 printk(KERN_ERR "%s: invalid hsync_len %d\n",
907 fbi->fb.fix.id, var->hsync_len);
908 if (var->left_margin < 1 || var->left_margin > 255)
909 printk(KERN_ERR "%s: invalid left_margin %d\n",
910 fbi->fb.fix.id, var->left_margin);
911 if (var->right_margin < 1 || var->right_margin > 255)
912 printk(KERN_ERR "%s: invalid right_margin %d\n",
913 fbi->fb.fix.id, var->right_margin);
914 if (var->yres < 1 || var->yres > 1024)
915 printk(KERN_ERR "%s: invalid yres %d\n",
916 fbi->fb.fix.id, var->yres);
917 if (var->vsync_len < 1 || var->vsync_len > 64)
918 printk(KERN_ERR "%s: invalid vsync_len %d\n",
919 fbi->fb.fix.id, var->vsync_len);
920 if (var->upper_margin < 0 || var->upper_margin > 255)
921 printk(KERN_ERR "%s: invalid upper_margin %d\n",
922 fbi->fb.fix.id, var->upper_margin);
923 if (var->lower_margin < 0 || var->lower_margin > 255)
924 printk(KERN_ERR "%s: invalid lower_margin %d\n",
925 fbi->fb.fix.id, var->lower_margin);
928 /* Update shadow copy atomically */
929 local_irq_save(flags);
931 #ifdef CONFIG_FB_PXA_SMARTPANEL
932 if (fbi->lccr0 & LCCR0_LCDT)
933 setup_smart_timing(fbi, var);
936 setup_parallel_timing(fbi, var);
938 fbi->reg_lccr0 = fbi->lccr0 |
939 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
940 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
942 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
944 nbytes = fbi->fb.fix.line_length * var->yres;
945 offset = fbi->fb.fix.line_length * var->yoffset;
947 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
949 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, offset + nbytes, nbytes);
952 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
953 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, offset, nbytes);
955 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, offset, nbytes);
957 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
958 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
959 local_irq_restore(flags);
962 * Only update the registers if the controller is enabled
963 * and something has changed.
965 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
966 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
967 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
968 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
969 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
970 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
971 pxafb_schedule_work(fbi, C_REENABLE);
977 * NOTE! The following functions are purely helpers for set_ctrlr_state.
978 * Do not call them directly; set_ctrlr_state does the correct serialisation
979 * to ensure that things happen in the right way 100% of time time.
982 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
984 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
986 if (fbi->backlight_power)
987 fbi->backlight_power(on);
990 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
992 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
995 fbi->lcd_power(on, &fbi->fb.var);
998 static void pxafb_enable_controller(struct pxafb_info *fbi)
1000 pr_debug("pxafb: Enabling LCD controller\n");
1001 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1002 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1003 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1004 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1005 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1006 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1008 /* enable LCD controller clock */
1009 clk_enable(fbi->clk);
1011 if (fbi->lccr0 & LCCR0_LCDT)
1014 /* Sequence from 11.7.10 */
1015 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1016 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1017 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1018 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1020 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1021 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1022 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1025 static void pxafb_disable_controller(struct pxafb_info *fbi)
1029 #ifdef CONFIG_FB_PXA_SMARTPANEL
1030 if (fbi->lccr0 & LCCR0_LCDT) {
1031 wait_for_completion_timeout(&fbi->refresh_done,
1037 /* Clear LCD Status Register */
1038 lcd_writel(fbi, LCSR, 0xffffffff);
1040 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1041 lcd_writel(fbi, LCCR0, lccr0);
1042 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1044 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1046 /* disable LCD controller clock */
1047 clk_disable(fbi->clk);
1051 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1053 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1055 struct pxafb_info *fbi = dev_id;
1056 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1058 if (lcsr & LCSR_LDD) {
1059 lccr0 = lcd_readl(fbi, LCCR0);
1060 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1061 complete(&fbi->disable_done);
1064 #ifdef CONFIG_FB_PXA_SMARTPANEL
1065 if (lcsr & LCSR_CMD_INT)
1066 complete(&fbi->command_done);
1069 lcd_writel(fbi, LCSR, lcsr);
1074 * This function must be called from task context only, since it will
1075 * sleep when disabling the LCD controller, or if we get two contending
1076 * processes trying to alter state.
1078 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1082 mutex_lock(&fbi->ctrlr_lock);
1084 old_state = fbi->state;
1087 * Hack around fbcon initialisation.
1089 if (old_state == C_STARTUP && state == C_REENABLE)
1093 case C_DISABLE_CLKCHANGE:
1095 * Disable controller for clock change. If the
1096 * controller is already disabled, then do nothing.
1098 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1100 /* TODO __pxafb_lcd_power(fbi, 0); */
1101 pxafb_disable_controller(fbi);
1108 * Disable controller
1110 if (old_state != C_DISABLE) {
1112 __pxafb_backlight_power(fbi, 0);
1113 __pxafb_lcd_power(fbi, 0);
1114 if (old_state != C_DISABLE_CLKCHANGE)
1115 pxafb_disable_controller(fbi);
1119 case C_ENABLE_CLKCHANGE:
1121 * Enable the controller after clock change. Only
1122 * do this if we were disabled for the clock change.
1124 if (old_state == C_DISABLE_CLKCHANGE) {
1125 fbi->state = C_ENABLE;
1126 pxafb_enable_controller(fbi);
1127 /* TODO __pxafb_lcd_power(fbi, 1); */
1133 * Re-enable the controller only if it was already
1134 * enabled. This is so we reprogram the control
1137 if (old_state == C_ENABLE) {
1138 __pxafb_lcd_power(fbi, 0);
1139 pxafb_disable_controller(fbi);
1140 pxafb_enable_controller(fbi);
1141 __pxafb_lcd_power(fbi, 1);
1147 * Re-enable the controller after PM. This is not
1148 * perfect - think about the case where we were doing
1149 * a clock change, and we suspended half-way through.
1151 if (old_state != C_DISABLE_PM)
1157 * Power up the LCD screen, enable controller, and
1158 * turn on the backlight.
1160 if (old_state != C_ENABLE) {
1161 fbi->state = C_ENABLE;
1162 pxafb_enable_controller(fbi);
1163 __pxafb_lcd_power(fbi, 1);
1164 __pxafb_backlight_power(fbi, 1);
1168 mutex_unlock(&fbi->ctrlr_lock);
1172 * Our LCD controller task (which is called when we blank or unblank)
1175 static void pxafb_task(struct work_struct *work)
1177 struct pxafb_info *fbi =
1178 container_of(work, struct pxafb_info, task);
1179 u_int state = xchg(&fbi->task_state, -1);
1181 set_ctrlr_state(fbi, state);
1184 #ifdef CONFIG_CPU_FREQ
1186 * CPU clock speed change handler. We need to adjust the LCD timing
1187 * parameters when the CPU clock is adjusted by the power management
1190 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1193 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1195 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1196 /* TODO struct cpufreq_freqs *f = data; */
1200 case CPUFREQ_PRECHANGE:
1201 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1204 case CPUFREQ_POSTCHANGE:
1205 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1206 set_hsync_time(fbi, pcd);
1207 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1208 LCCR3_PixClkDiv(pcd);
1209 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1216 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1218 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1219 struct fb_var_screeninfo *var = &fbi->fb.var;
1220 struct cpufreq_policy *policy = data;
1223 case CPUFREQ_ADJUST:
1224 case CPUFREQ_INCOMPATIBLE:
1225 pr_debug("min dma period: %d ps, "
1226 "new clock %d kHz\n", pxafb_display_dma_period(var),
1228 /* TODO: fill in min/max values */
1237 * Power management hooks. Note that we won't be called from IRQ context,
1238 * unlike the blank functions above, so we may sleep.
1240 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1242 struct pxafb_info *fbi = platform_get_drvdata(dev);
1244 set_ctrlr_state(fbi, C_DISABLE_PM);
1248 static int pxafb_resume(struct platform_device *dev)
1250 struct pxafb_info *fbi = platform_get_drvdata(dev);
1252 set_ctrlr_state(fbi, C_ENABLE_PM);
1256 #define pxafb_suspend NULL
1257 #define pxafb_resume NULL
1260 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1262 int size = PAGE_ALIGN(fbi->video_mem_size);
1264 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1265 if (fbi->video_mem == NULL)
1268 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1269 fbi->video_mem_size = size;
1271 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1272 fbi->fb.fix.smem_len = fbi->video_mem_size;
1273 fbi->fb.screen_base = fbi->video_mem;
1275 return fbi->video_mem ? 0 : -ENOMEM;
1278 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1279 struct pxafb_mach_info *inf)
1281 unsigned int lcd_conn = inf->lcd_conn;
1282 struct pxafb_mode_info *m;
1285 fbi->cmap_inverse = inf->cmap_inverse;
1286 fbi->cmap_static = inf->cmap_static;
1288 switch (lcd_conn & LCD_TYPE_MASK) {
1289 case LCD_TYPE_MONO_STN:
1290 fbi->lccr0 = LCCR0_CMS;
1292 case LCD_TYPE_MONO_DSTN:
1293 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1295 case LCD_TYPE_COLOR_STN:
1298 case LCD_TYPE_COLOR_DSTN:
1299 fbi->lccr0 = LCCR0_SDS;
1301 case LCD_TYPE_COLOR_TFT:
1302 fbi->lccr0 = LCCR0_PAS;
1304 case LCD_TYPE_SMART_PANEL:
1305 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1308 /* fall back to backward compatibility way */
1309 fbi->lccr0 = inf->lccr0;
1310 fbi->lccr3 = inf->lccr3;
1311 fbi->lccr4 = inf->lccr4;
1315 if (lcd_conn == LCD_MONO_STN_8BPP)
1316 fbi->lccr0 |= LCCR0_DPD;
1318 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1320 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1321 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1322 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1325 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1327 /* decide video memory size as follows:
1328 * 1. default to mode of maximum resolution
1329 * 2. allow platform to override
1330 * 3. allow module parameter to override
1332 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1333 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1334 m->xres * m->yres * m->bpp / 8);
1336 if (inf->video_mem_size > fbi->video_mem_size)
1337 fbi->video_mem_size = inf->video_mem_size;
1339 if (video_mem_size > fbi->video_mem_size)
1340 fbi->video_mem_size = video_mem_size;
1343 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1345 struct pxafb_info *fbi;
1347 struct pxafb_mach_info *inf = dev->platform_data;
1349 /* Alloc the pxafb_info and pseudo_palette in one step */
1350 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1354 memset(fbi, 0, sizeof(struct pxafb_info));
1357 fbi->clk = clk_get(dev, "LCDCLK");
1358 if (IS_ERR(fbi->clk)) {
1363 strcpy(fbi->fb.fix.id, PXA_NAME);
1365 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1366 fbi->fb.fix.type_aux = 0;
1367 fbi->fb.fix.xpanstep = 0;
1368 fbi->fb.fix.ypanstep = 1;
1369 fbi->fb.fix.ywrapstep = 0;
1370 fbi->fb.fix.accel = FB_ACCEL_NONE;
1372 fbi->fb.var.nonstd = 0;
1373 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1374 fbi->fb.var.height = -1;
1375 fbi->fb.var.width = -1;
1376 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1377 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1379 fbi->fb.fbops = &pxafb_ops;
1380 fbi->fb.flags = FBINFO_DEFAULT;
1384 addr = addr + sizeof(struct pxafb_info);
1385 fbi->fb.pseudo_palette = addr;
1387 fbi->state = C_STARTUP;
1388 fbi->task_state = (u_char)-1;
1390 pxafb_decode_mach_info(fbi, inf);
1392 init_waitqueue_head(&fbi->ctrlr_wait);
1393 INIT_WORK(&fbi->task, pxafb_task);
1394 mutex_init(&fbi->ctrlr_lock);
1395 init_completion(&fbi->disable_done);
1400 #ifdef CONFIG_FB_PXA_PARAMETERS
1401 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1403 struct pxafb_mach_info *inf = dev->platform_data;
1405 const char *name = this_opt+5;
1406 unsigned int namelen = strlen(name);
1407 int res_specified = 0, bpp_specified = 0;
1408 unsigned int xres = 0, yres = 0, bpp = 0;
1409 int yres_specified = 0;
1411 for (i = namelen-1; i >= 0; i--) {
1415 if (!bpp_specified && !yres_specified) {
1416 bpp = simple_strtoul(&name[i+1], NULL, 0);
1422 if (!yres_specified) {
1423 yres = simple_strtoul(&name[i+1], NULL, 0);
1434 if (i < 0 && yres_specified) {
1435 xres = simple_strtoul(name, NULL, 0);
1439 if (res_specified) {
1440 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1441 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1450 inf->modes[0].bpp = bpp;
1451 dev_info(dev, "overriding bit depth: %d\n", bpp);
1454 dev_err(dev, "Depth %d is not valid\n", bpp);
1460 static int __devinit parse_opt(struct device *dev, char *this_opt)
1462 struct pxafb_mach_info *inf = dev->platform_data;
1463 struct pxafb_mode_info *mode = &inf->modes[0];
1468 if (!strncmp(this_opt, "vmem:", 5)) {
1469 video_mem_size = memparse(this_opt + 5, NULL);
1470 } else if (!strncmp(this_opt, "mode:", 5)) {
1471 return parse_opt_mode(dev, this_opt);
1472 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1473 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1474 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1475 } else if (!strncmp(this_opt, "left:", 5)) {
1476 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1477 sprintf(s, "left: %u\n", mode->left_margin);
1478 } else if (!strncmp(this_opt, "right:", 6)) {
1479 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1480 sprintf(s, "right: %u\n", mode->right_margin);
1481 } else if (!strncmp(this_opt, "upper:", 6)) {
1482 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1483 sprintf(s, "upper: %u\n", mode->upper_margin);
1484 } else if (!strncmp(this_opt, "lower:", 6)) {
1485 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1486 sprintf(s, "lower: %u\n", mode->lower_margin);
1487 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1488 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1489 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1490 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1491 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1492 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1493 } else if (!strncmp(this_opt, "hsync:", 6)) {
1494 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1495 sprintf(s, "hsync: Active Low\n");
1496 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1498 sprintf(s, "hsync: Active High\n");
1499 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1501 } else if (!strncmp(this_opt, "vsync:", 6)) {
1502 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1503 sprintf(s, "vsync: Active Low\n");
1504 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1506 sprintf(s, "vsync: Active High\n");
1507 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1509 } else if (!strncmp(this_opt, "dpc:", 4)) {
1510 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1511 sprintf(s, "double pixel clock: false\n");
1512 inf->lccr3 &= ~LCCR3_DPC;
1514 sprintf(s, "double pixel clock: true\n");
1515 inf->lccr3 |= LCCR3_DPC;
1517 } else if (!strncmp(this_opt, "outputen:", 9)) {
1518 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1519 sprintf(s, "output enable: active low\n");
1520 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1522 sprintf(s, "output enable: active high\n");
1523 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1525 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1526 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1527 sprintf(s, "pixel clock polarity: falling edge\n");
1528 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1530 sprintf(s, "pixel clock polarity: rising edge\n");
1531 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1533 } else if (!strncmp(this_opt, "color", 5)) {
1534 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1535 } else if (!strncmp(this_opt, "mono", 4)) {
1536 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1537 } else if (!strncmp(this_opt, "active", 6)) {
1538 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1539 } else if (!strncmp(this_opt, "passive", 7)) {
1540 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1541 } else if (!strncmp(this_opt, "single", 6)) {
1542 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1543 } else if (!strncmp(this_opt, "dual", 4)) {
1544 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1545 } else if (!strncmp(this_opt, "4pix", 4)) {
1546 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1547 } else if (!strncmp(this_opt, "8pix", 4)) {
1548 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1550 dev_err(dev, "unknown option: %s\n", this_opt);
1555 dev_info(dev, "override %s", s);
1560 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1565 if (!options || !*options)
1568 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1570 /* could be made table driven or similar?... */
1571 while ((this_opt = strsep(&options, ",")) != NULL) {
1572 ret = parse_opt(dev, this_opt);
1579 static char g_options[256] __devinitdata = "";
1582 static int __init pxafb_setup_options(void)
1584 char *options = NULL;
1586 if (fb_get_options("pxafb", &options))
1590 strlcpy(g_options, options, sizeof(g_options));
1595 #define pxafb_setup_options() (0)
1597 module_param_string(options, g_options, sizeof(g_options), 0);
1598 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1602 #define pxafb_parse_options(...) (0)
1603 #define pxafb_setup_options() (0)
1607 /* Check for various illegal bit-combinations. Currently only
1608 * a warning is given. */
1609 static void __devinit pxafb_check_options(struct device *dev,
1610 struct pxafb_mach_info *inf)
1615 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1616 dev_warn(dev, "machine LCCR0 setting contains "
1617 "illegal bits: %08x\n",
1618 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1619 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1620 dev_warn(dev, "machine LCCR3 setting contains "
1621 "illegal bits: %08x\n",
1622 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1623 if (inf->lccr0 & LCCR0_DPD &&
1624 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1625 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1626 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1627 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1628 "only valid in passive mono"
1629 " single panel mode\n");
1630 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1631 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1632 dev_warn(dev, "Dual panel only valid in passive mode\n");
1633 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1634 (inf->modes->upper_margin || inf->modes->lower_margin))
1635 dev_warn(dev, "Upper and lower margins must be 0 in "
1639 #define pxafb_check_options(...) do {} while (0)
1642 static int __devinit pxafb_probe(struct platform_device *dev)
1644 struct pxafb_info *fbi;
1645 struct pxafb_mach_info *inf;
1649 dev_dbg(&dev->dev, "pxafb_probe\n");
1651 inf = dev->dev.platform_data;
1657 ret = pxafb_parse_options(&dev->dev, g_options);
1661 pxafb_check_options(&dev->dev, inf);
1663 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1667 if (inf->modes->xres == 0 ||
1668 inf->modes->yres == 0 ||
1669 inf->modes->bpp == 0) {
1670 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1675 fbi = pxafb_init_fbinfo(&dev->dev);
1677 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1678 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1683 fbi->backlight_power = inf->pxafb_backlight_power;
1684 fbi->lcd_power = inf->pxafb_lcd_power;
1686 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1688 dev_err(&dev->dev, "no I/O memory resource defined\n");
1693 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1695 dev_err(&dev->dev, "failed to request I/O memory\n");
1700 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1701 if (fbi->mmio_base == NULL) {
1702 dev_err(&dev->dev, "failed to map I/O memory\n");
1704 goto failed_free_res;
1707 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1708 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1709 &fbi->dma_buff_phys, GFP_KERNEL);
1710 if (fbi->dma_buff == NULL) {
1711 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1713 goto failed_free_io;
1716 ret = pxafb_init_video_memory(fbi);
1718 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1720 goto failed_free_dma;
1723 irq = platform_get_irq(dev, 0);
1725 dev_err(&dev->dev, "no IRQ defined\n");
1727 goto failed_free_mem;
1730 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1732 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1734 goto failed_free_mem;
1737 ret = pxafb_smart_init(fbi);
1739 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1740 goto failed_free_irq;
1744 * This makes sure that our colour bitfield
1745 * descriptors are correctly initialised.
1747 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1749 dev_err(&dev->dev, "failed to get suitable mode\n");
1750 goto failed_free_irq;
1753 ret = pxafb_set_par(&fbi->fb);
1755 dev_err(&dev->dev, "Failed to set parameters\n");
1756 goto failed_free_irq;
1759 platform_set_drvdata(dev, fbi);
1761 ret = register_framebuffer(&fbi->fb);
1764 "Failed to register framebuffer device: %d\n", ret);
1765 goto failed_free_cmap;
1768 #ifdef CONFIG_CPU_FREQ
1769 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1770 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1771 cpufreq_register_notifier(&fbi->freq_transition,
1772 CPUFREQ_TRANSITION_NOTIFIER);
1773 cpufreq_register_notifier(&fbi->freq_policy,
1774 CPUFREQ_POLICY_NOTIFIER);
1778 * Ok, now enable the LCD controller
1780 set_ctrlr_state(fbi, C_ENABLE);
1785 if (fbi->fb.cmap.len)
1786 fb_dealloc_cmap(&fbi->fb.cmap);
1790 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1792 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1793 fbi->dma_buff, fbi->dma_buff_phys);
1795 iounmap(fbi->mmio_base);
1797 release_mem_region(r->start, r->end - r->start + 1);
1800 platform_set_drvdata(dev, NULL);
1806 static int __devexit pxafb_remove(struct platform_device *dev)
1808 struct pxafb_info *fbi = platform_get_drvdata(dev);
1811 struct fb_info *info;
1818 unregister_framebuffer(info);
1820 pxafb_disable_controller(fbi);
1822 if (fbi->fb.cmap.len)
1823 fb_dealloc_cmap(&fbi->fb.cmap);
1825 irq = platform_get_irq(dev, 0);
1828 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1830 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1831 fbi->dma_buff, fbi->dma_buff_phys);
1833 iounmap(fbi->mmio_base);
1835 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1836 release_mem_region(r->start, r->end - r->start + 1);
1844 static struct platform_driver pxafb_driver = {
1845 .probe = pxafb_probe,
1846 .remove = pxafb_remove,
1847 .suspend = pxafb_suspend,
1848 .resume = pxafb_resume,
1850 .owner = THIS_MODULE,
1851 .name = "pxa2xx-fb",
1855 static int __init pxafb_init(void)
1857 if (pxafb_setup_options())
1860 return platform_driver_register(&pxafb_driver);
1863 static void __exit pxafb_exit(void)
1865 platform_driver_unregister(&pxafb_driver);
1868 module_init(pxafb_init);
1869 module_exit(pxafb_exit);
1871 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1872 MODULE_LICENSE("GPL");