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   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/kernel.h>
  28 #include <linux/sched.h>
  29 #include <linux/errno.h>
  30 #include <linux/string.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/slab.h>
  33 #include <linux/fb.h>
  34 #include <linux/delay.h>
  35 #include <linux/init.h>
  36 #include <linux/ioport.h>
  37 #include <linux/cpufreq.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/clk.h>
  41 #include <linux/err.h>
  42
  43 #include <asm/hardware.h>
  44 #include <asm/io.h>
  45 #include <asm/irq.h>
  46 #include <asm/uaccess.h>
  47 #include <asm/div64.h>
  48 #include <asm/arch/pxa-regs.h>
  49 #include <asm/arch/bitfield.h>
  50 #include <asm/arch/pxafb.h>
  51
  52 /*
  53  * Complain if VAR is out of range.
  54  */
  55 #define DEBUG_VAR 1
  56
  57 #include "pxafb.h"
  58
  59 /* Bits which should not be set in machine configuration structures */
  60 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
  61 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
  62
  63 static void (*pxafb_backlight_power)(int);
  64 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
  65
  66 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
  67 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  68
  69 #ifdef CONFIG_FB_PXA_PARAMETERS
  70 #define PXAFB_OPTIONS_SIZE 256
  71 static char g_options[PXAFB_OPTIONS_SIZE] __devinitdata = "";
  72 #endif
  73
  74 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  75 {
  76         unsigned long flags;
  77
  78         local_irq_save(flags);
  79         /*
  80          * We need to handle two requests being made at the same time.
  81          * There are two important cases:
  82          *  1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  83          *     We must perform the unblanking, which will do our REENABLE for us.
  84          *  2. When we are blanking, but immediately unblank before we have
  85          *     blanked.  We do the "REENABLE" thing here as well, just to be sure.
  86          */
  87         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  88                 state = (u_int) -1;
  89         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  90                 state = C_REENABLE;
  91
  92         if (state != (u_int)-1) {
  93                 fbi->task_state = state;
  94                 schedule_work(&fbi->task);
  95         }
  96         local_irq_restore(flags);
  97 }
  98
  99 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 100 {
 101         chan &= 0xffff;
 102         chan >>= 16 - bf->length;
 103         return chan << bf->offset;
 104 }
 105
 106 static int
 107 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 108                        u_int trans, struct fb_info *info)
 109 {
 110         struct pxafb_info *fbi = (struct pxafb_info *)info;
 111         u_int val, ret = 1;
 112
 113         if (regno < fbi->palette_size) {
 114                 if (fbi->fb.var.grayscale) {
 115                         val = ((blue >> 8) & 0x00ff);
 116                 } else {
 117                         val  = ((red   >>  0) & 0xf800);
 118                         val |= ((green >>  5) & 0x07e0);
 119                         val |= ((blue  >> 11) & 0x001f);
 120                 }
 121                 fbi->palette_cpu[regno] = val;
 122                 ret = 0;
 123         }
 124         return ret;
 125 }
 126
 127 static int
 128 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 129                    u_int trans, struct fb_info *info)
 130 {
 131         struct pxafb_info *fbi = (struct pxafb_info *)info;
 132         unsigned int val;
 133         int ret = 1;
 134
 135         /*
 136          * If inverse mode was selected, invert all the colours
 137          * rather than the register number.  The register number
 138          * is what you poke into the framebuffer to produce the
 139          * colour you requested.
 140          */
 141         if (fbi->cmap_inverse) {
 142                 red   = 0xffff - red;
 143                 green = 0xffff - green;
 144                 blue  = 0xffff - blue;
 145         }
 146
 147         /*
 148          * If greyscale is true, then we convert the RGB value
 149          * to greyscale no matter what visual we are using.
 150          */
 151         if (fbi->fb.var.grayscale)
 152                 red = green = blue = (19595 * red + 38470 * green +
 153                                         7471 * blue) >> 16;
 154
 155         switch (fbi->fb.fix.visual) {
 156         case FB_VISUAL_TRUECOLOR:
 157                 /*
 158                  * 16-bit True Colour.  We encode the RGB value
 159                  * according to the RGB bitfield information.
 160                  */
 161                 if (regno < 16) {
 162                         u32 *pal = fbi->fb.pseudo_palette;
 163
 164                         val  = chan_to_field(red, &fbi->fb.var.red);
 165                         val |= chan_to_field(green, &fbi->fb.var.green);
 166                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 167
 168                         pal[regno] = val;
 169                         ret = 0;
 170                 }
 171                 break;
 172
 173         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 174         case FB_VISUAL_PSEUDOCOLOR:
 175                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 176                 break;
 177         }
 178
 179         return ret;
 180 }
 181
 182 /*
 183  *  pxafb_bpp_to_lccr3():
 184  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 185  */
 186 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
 187 {
 188         int ret = 0;
 189         switch (var->bits_per_pixel) {
 190         case 1:  ret = LCCR3_1BPP; break;
 191         case 2:  ret = LCCR3_2BPP; break;
 192         case 4:  ret = LCCR3_4BPP; break;
 193         case 8:  ret = LCCR3_8BPP; break;
 194         case 16: ret = LCCR3_16BPP; break;
 195         }
 196         return ret;
 197 }
 198
 199 #ifdef CONFIG_CPU_FREQ
 200 /*
 201  *  pxafb_display_dma_period()
 202  *    Calculate the minimum period (in picoseconds) between two DMA
 203  *    requests for the LCD controller.  If we hit this, it means we're
 204  *    doing nothing but LCD DMA.
 205  */
 206 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 207 {
 208        /*
 209         * Period = pixclock * bits_per_byte * bytes_per_transfer
 210         *              / memory_bits_per_pixel;
 211         */
 212        return var->pixclock * 8 * 16 / var->bits_per_pixel;
 213 }
 214
 215 extern unsigned int get_clk_frequency_khz(int info);
 216 #endif
 217
 218 /*
 219  * Select the smallest mode that allows the desired resolution to be
 220  * displayed. If desired parameters can be rounded up.
 221  */
 222 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, struct fb_var_screeninfo *var)
 223 {
 224         struct pxafb_mode_info *mode = NULL;
 225         struct pxafb_mode_info *modelist = mach->modes;
 226         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
 227         unsigned int i;
 228
 229         for (i = 0 ; i < mach->num_modes ; i++) {
 230                 if (modelist[i].xres >= var->xres && modelist[i].yres >= var->yres &&
 231                                 modelist[i].xres < best_x && modelist[i].yres < best_y &&
 232                                 modelist[i].bpp >= var->bits_per_pixel ) {
 233                         best_x = modelist[i].xres;
 234                         best_y = modelist[i].yres;
 235                         mode = &modelist[i];
 236                 }
 237         }
 238
 239         return mode;
 240 }
 241
 242 static void pxafb_setmode(struct fb_var_screeninfo *var, struct pxafb_mode_info *mode)
 243 {
 244         var->xres               = mode->xres;
 245         var->yres               = mode->yres;
 246         var->bits_per_pixel     = mode->bpp;
 247         var->pixclock           = mode->pixclock;
 248         var->hsync_len          = mode->hsync_len;
 249         var->left_margin        = mode->left_margin;
 250         var->right_margin       = mode->right_margin;
 251         var->vsync_len          = mode->vsync_len;
 252         var->upper_margin       = mode->upper_margin;
 253         var->lower_margin       = mode->lower_margin;
 254         var->sync               = mode->sync;
 255         var->grayscale          = mode->cmap_greyscale;
 256         var->xres_virtual       = var->xres;
 257         var->yres_virtual       = var->yres;
 258 }
 259
 260 /*
 261  *  pxafb_check_var():
 262  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 263  *    if it's too big, return -EINVAL.
 264  *
 265  *    Round up in the following order: bits_per_pixel, xres,
 266  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 267  *    bitfields, horizontal timing, vertical timing.
 268  */
 269 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 270 {
 271         struct pxafb_info *fbi = (struct pxafb_info *)info;
 272         struct pxafb_mach_info *inf = fbi->dev->platform_data;
 273
 274         if (var->xres < MIN_XRES)
 275                 var->xres = MIN_XRES;
 276         if (var->yres < MIN_YRES)
 277                 var->yres = MIN_YRES;
 278
 279         if (inf->fixed_modes) {
 280                 struct pxafb_mode_info *mode;
 281
 282                 mode = pxafb_getmode(inf, var);
 283                 if (!mode)
 284                         return -EINVAL;
 285                 pxafb_setmode(var, mode);
 286         } else {
 287                 if (var->xres > inf->modes->xres)
 288                         return -EINVAL;
 289                 if (var->yres > inf->modes->yres)
 290                         return -EINVAL;
 291                 if (var->bits_per_pixel > inf->modes->bpp)
 292                         return -EINVAL;
 293         }
 294
 295         var->xres_virtual =
 296                 max(var->xres_virtual, var->xres);
 297         var->yres_virtual =
 298                 max(var->yres_virtual, var->yres);
 299
 300         /*
 301          * Setup the RGB parameters for this display.
 302          *
 303          * The pixel packing format is described on page 7-11 of the
 304          * PXA2XX Developer's Manual.
 305          */
 306         if (var->bits_per_pixel == 16) {
 307                 var->red.offset   = 11; var->red.length   = 5;
 308                 var->green.offset = 5;  var->green.length = 6;
 309                 var->blue.offset  = 0;  var->blue.length  = 5;
 310                 var->transp.offset = var->transp.length = 0;
 311         } else {
 312                 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
 313                 var->red.length   = 8;
 314                 var->green.length = 8;
 315                 var->blue.length  = 8;
 316                 var->transp.length = 0;
 317         }
 318
 319 #ifdef CONFIG_CPU_FREQ
 320         pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
 321                  pxafb_display_dma_period(var),
 322                  get_clk_frequency_khz(0));
 323 #endif
 324
 325         return 0;
 326 }
 327
 328 static inline void pxafb_set_truecolor(u_int is_true_color)
 329 {
 330         pr_debug("pxafb: true_color = %d\n", is_true_color);
 331         // do your machine-specific setup if needed
 332 }
 333
 334 /*
 335  * pxafb_set_par():
 336  *      Set the user defined part of the display for the specified console
 337  */
 338 static int pxafb_set_par(struct fb_info *info)
 339 {
 340         struct pxafb_info *fbi = (struct pxafb_info *)info;
 341         struct fb_var_screeninfo *var = &info->var;
 342         unsigned long palette_mem_size;
 343
 344         pr_debug("pxafb: set_par\n");
 345
 346         if (var->bits_per_pixel == 16)
 347                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 348         else if (!fbi->cmap_static)
 349                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 350         else {
 351                 /*
 352                  * Some people have weird ideas about wanting static
 353                  * pseudocolor maps.  I suspect their user space
 354                  * applications are broken.
 355                  */
 356                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 357         }
 358
 359         fbi->fb.fix.line_length = var->xres_virtual *
 360                                   var->bits_per_pixel / 8;
 361         if (var->bits_per_pixel == 16)
 362                 fbi->palette_size = 0;
 363         else
 364                 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
 365
 366         palette_mem_size = fbi->palette_size * sizeof(u16);
 367
 368         pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
 369
 370         fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
 371         fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
 372
 373         /*
 374          * Set (any) board control register to handle new color depth
 375          */
 376         pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
 377
 378         if (fbi->fb.var.bits_per_pixel == 16)
 379                 fb_dealloc_cmap(&fbi->fb.cmap);
 380         else
 381                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 382
 383         pxafb_activate_var(var, fbi);
 384
 385         return 0;
 386 }
 387
 388 /*
 389  * Formal definition of the VESA spec:
 390  *  On
 391  *      This refers to the state of the display when it is in full operation
 392  *  Stand-By
 393  *      This defines an optional operating state of minimal power reduction with
 394  *      the shortest recovery time
 395  *  Suspend
 396  *      This refers to a level of power management in which substantial power
 397  *      reduction is achieved by the display.  The display can have a longer
 398  *      recovery time from this state than from the Stand-by state
 399  *  Off
 400  *      This indicates that the display is consuming the lowest level of power
 401  *      and is non-operational. Recovery from this state may optionally require
 402  *      the user to manually power on the monitor
 403  *
 404  *  Now, the fbdev driver adds an additional state, (blank), where they
 405  *  turn off the video (maybe by colormap tricks), but don't mess with the
 406  *  video itself: think of it semantically between on and Stand-By.
 407  *
 408  *  So here's what we should do in our fbdev blank routine:
 409  *
 410  *      VESA_NO_BLANKING (mode 0)       Video on,  front/back light on
 411  *      VESA_VSYNC_SUSPEND (mode 1)     Video on,  front/back light off
 412  *      VESA_HSYNC_SUSPEND (mode 2)     Video on,  front/back light off
 413  *      VESA_POWERDOWN (mode 3)         Video off, front/back light off
 414  *
 415  *  This will match the matrox implementation.
 416  */
 417
 418 /*
 419  * pxafb_blank():
 420  *      Blank the display by setting all palette values to zero.  Note, the
 421  *      16 bpp mode does not really use the palette, so this will not
 422  *      blank the display in all modes.
 423  */
 424 static int pxafb_blank(int blank, struct fb_info *info)
 425 {
 426         struct pxafb_info *fbi = (struct pxafb_info *)info;
 427         int i;
 428
 429         pr_debug("pxafb: blank=%d\n", blank);
 430
 431         switch (blank) {
 432         case FB_BLANK_POWERDOWN:
 433         case FB_BLANK_VSYNC_SUSPEND:
 434         case FB_BLANK_HSYNC_SUSPEND:
 435         case FB_BLANK_NORMAL:
 436                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 437                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 438                         for (i = 0; i < fbi->palette_size; i++)
 439                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 440
 441                 pxafb_schedule_work(fbi, C_DISABLE);
 442                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 443                 break;
 444
 445         case FB_BLANK_UNBLANK:
 446                 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
 447                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 448                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 449                         fb_set_cmap(&fbi->fb.cmap, info);
 450                 pxafb_schedule_work(fbi, C_ENABLE);
 451         }
 452         return 0;
 453 }
 454
 455 static int pxafb_mmap(struct fb_info *info,
 456                       struct vm_area_struct *vma)
 457 {
 458         struct pxafb_info *fbi = (struct pxafb_info *)info;
 459         unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
 460
 461         if (off < info->fix.smem_len) {
 462                 vma->vm_pgoff += 1;
 463                 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
 464                                              fbi->map_dma, fbi->map_size);
 465         }
 466         return -EINVAL;
 467 }
 468
 469 static struct fb_ops pxafb_ops = {
 470         .owner          = THIS_MODULE,
 471         .fb_check_var   = pxafb_check_var,
 472         .fb_set_par     = pxafb_set_par,
 473         .fb_setcolreg   = pxafb_setcolreg,
 474         .fb_fillrect    = cfb_fillrect,
 475         .fb_copyarea    = cfb_copyarea,
 476         .fb_imageblit   = cfb_imageblit,
 477         .fb_blank       = pxafb_blank,
 478         .fb_mmap        = pxafb_mmap,
 479 };
 480
 481 /*
 482  * Calculate the PCD value from the clock rate (in picoseconds).
 483  * We take account of the PPCR clock setting.
 484  * From PXA Developer's Manual:
 485  *
 486  *   PixelClock =      LCLK
 487  *                -------------
 488  *                2 ( PCD + 1 )
 489  *
 490  *   PCD =      LCLK
 491  *         ------------- - 1
 492  *         2(PixelClock)
 493  *
 494  * Where:
 495  *   LCLK = LCD/Memory Clock
 496  *   PCD = LCCR3[7:0]
 497  *
 498  * PixelClock here is in Hz while the pixclock argument given is the
 499  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 500  *
 501  * The function get_lclk_frequency_10khz returns LCLK in units of
 502  * 10khz. Calling the result of this function lclk gives us the
 503  * following
 504  *
 505  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 506  *          -------------------------------------- - 1
 507  *                          2
 508  *
 509  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 510  */
 511 static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock)
 512 {
 513         unsigned long long pcd;
 514
 515         /* FIXME: Need to take into account Double Pixel Clock mode
 516          * (DPC) bit? or perhaps set it based on the various clock
 517          * speeds */
 518         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
 519         pcd *= pixclock;
 520         do_div(pcd, 100000000 * 2);
 521         /* no need for this, since we should subtract 1 anyway. they cancel */
 522         /* pcd += 1; */ /* make up for integer math truncations */
 523         return (unsigned int)pcd;
 524 }
 525
 526 /*
 527  * Some touchscreens need hsync information from the video driver to
 528  * function correctly. We export it here.  Note that 'hsync_time' and
 529  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
 530  * of the hsync period in seconds.
 531  */
 532 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
 533 {
 534         unsigned long htime;
 535
 536         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
 537                 fbi->hsync_time=0;
 538                 return;
 539         }
 540
 541         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
 542
 543         fbi->hsync_time = htime;
 544 }
 545
 546 unsigned long pxafb_get_hsync_time(struct device *dev)
 547 {
 548         struct pxafb_info *fbi = dev_get_drvdata(dev);
 549
 550         /* If display is blanked/suspended, hsync isn't active */
 551         if (!fbi || (fbi->state != C_ENABLE))
 552                 return 0;
 553
 554         return fbi->hsync_time;
 555 }
 556 EXPORT_SYMBOL(pxafb_get_hsync_time);
 557
 558 /*
 559  * pxafb_activate_var():
 560  *      Configures LCD Controller based on entries in var parameter.  Settings are
 561  *      only written to the controller if changes were made.
 562  */
 563 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
 564 {
 565         struct pxafb_lcd_reg new_regs;
 566         u_long flags;
 567         u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
 568
 569         pr_debug("pxafb: Configuring PXA LCD\n");
 570
 571         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
 572                  var->xres, var->hsync_len,
 573                  var->left_margin, var->right_margin);
 574         pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
 575                  var->yres, var->vsync_len,
 576                  var->upper_margin, var->lower_margin);
 577         pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
 578
 579 #if DEBUG_VAR
 580         if (var->xres < 16        || var->xres > 1024)
 581                 printk(KERN_ERR "%s: invalid xres %d\n",
 582                         fbi->fb.fix.id, var->xres);
 583         switch(var->bits_per_pixel) {
 584         case 1:
 585         case 2:
 586         case 4:
 587         case 8:
 588         case 16:
 589                 break;
 590         default:
 591                 printk(KERN_ERR "%s: invalid bit depth %d\n",
 592                        fbi->fb.fix.id, var->bits_per_pixel);
 593                 break;
 594         }
 595         if (var->hsync_len < 1    || var->hsync_len > 64)
 596                 printk(KERN_ERR "%s: invalid hsync_len %d\n",
 597                         fbi->fb.fix.id, var->hsync_len);
 598         if (var->left_margin < 1  || var->left_margin > 255)
 599                 printk(KERN_ERR "%s: invalid left_margin %d\n",
 600                         fbi->fb.fix.id, var->left_margin);
 601         if (var->right_margin < 1 || var->right_margin > 255)
 602                 printk(KERN_ERR "%s: invalid right_margin %d\n",
 603                         fbi->fb.fix.id, var->right_margin);
 604         if (var->yres < 1         || var->yres > 1024)
 605                 printk(KERN_ERR "%s: invalid yres %d\n",
 606                         fbi->fb.fix.id, var->yres);
 607         if (var->vsync_len < 1    || var->vsync_len > 64)
 608                 printk(KERN_ERR "%s: invalid vsync_len %d\n",
 609                         fbi->fb.fix.id, var->vsync_len);
 610         if (var->upper_margin < 0 || var->upper_margin > 255)
 611                 printk(KERN_ERR "%s: invalid upper_margin %d\n",
 612                         fbi->fb.fix.id, var->upper_margin);
 613         if (var->lower_margin < 0 || var->lower_margin > 255)
 614                 printk(KERN_ERR "%s: invalid lower_margin %d\n",
 615                         fbi->fb.fix.id, var->lower_margin);
 616 #endif
 617
 618         new_regs.lccr0 = fbi->lccr0 |
 619                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
 620                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 621
 622         new_regs.lccr1 =
 623                 LCCR1_DisWdth(var->xres) +
 624                 LCCR1_HorSnchWdth(var->hsync_len) +
 625                 LCCR1_BegLnDel(var->left_margin) +
 626                 LCCR1_EndLnDel(var->right_margin);
 627
 628         /*
 629          * If we have a dual scan LCD, we need to halve
 630          * the YRES parameter.
 631          */
 632         lines_per_panel = var->yres;
 633         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
 634                 lines_per_panel /= 2;
 635
 636         new_regs.lccr2 =
 637                 LCCR2_DisHght(lines_per_panel) +
 638                 LCCR2_VrtSnchWdth(var->vsync_len) +
 639                 LCCR2_BegFrmDel(var->upper_margin) +
 640                 LCCR2_EndFrmDel(var->lower_margin);
 641
 642         new_regs.lccr3 = fbi->lccr3 |
 643                 pxafb_bpp_to_lccr3(var) |
 644                 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
 645                 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
 646
 647         if (pcd)
 648                 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
 649
 650         pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
 651         pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
 652         pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
 653         pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
 654
 655         /* Update shadow copy atomically */
 656         local_irq_save(flags);
 657
 658         /* setup dma descriptors */
 659         fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
 660         fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
 661         fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
 662
 663         fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
 664         fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
 665         fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
 666
 667 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
 668
 669         /* populate descriptors */
 670         fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
 671         fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
 672         fbi->dmadesc_fblow_cpu->fidr  = 0;
 673         fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
 674
 675         fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
 676
 677         fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
 678         fbi->dmadesc_fbhigh_cpu->fidr = 0;
 679         fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
 680
 681         fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
 682         fbi->dmadesc_palette_cpu->fidr  = 0;
 683         fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 684
 685         if (var->bits_per_pixel == 16) {
 686                 /* palette shouldn't be loaded in true-color mode */
 687                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 688                 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
 689                 /* init it to something, even though we won't be using it */
 690                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
 691         } else {
 692                 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
 693                 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
 694                 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
 695         }
 696
 697 #if 0
 698         pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
 699         pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
 700         pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
 701         pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
 702         pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
 703         pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
 704
 705         pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
 706         pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
 707         pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
 708
 709         pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
 710         pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
 711         pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
 712
 713         pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
 714         pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
 715         pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
 716 #endif
 717
 718         fbi->reg_lccr0 = new_regs.lccr0;
 719         fbi->reg_lccr1 = new_regs.lccr1;
 720         fbi->reg_lccr2 = new_regs.lccr2;
 721         fbi->reg_lccr3 = new_regs.lccr3;
 722         set_hsync_time(fbi, pcd);
 723         local_irq_restore(flags);
 724
 725         /*
 726          * Only update the registers if the controller is enabled
 727          * and something has changed.
 728          */
 729         if ((LCCR0  != fbi->reg_lccr0) || (LCCR1  != fbi->reg_lccr1) ||
 730             (LCCR2  != fbi->reg_lccr2) || (LCCR3  != fbi->reg_lccr3) ||
 731             (FDADR0 != fbi->fdadr0)    || (FDADR1 != fbi->fdadr1))
 732                 pxafb_schedule_work(fbi, C_REENABLE);
 733
 734         return 0;
 735 }
 736
 737 /*
 738  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
 739  * Do not call them directly; set_ctrlr_state does the correct serialisation
 740  * to ensure that things happen in the right way 100% of time time.
 741  *      -- rmk
 742  */
 743 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
 744 {
 745         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
 746
 747         if (pxafb_backlight_power)
 748                 pxafb_backlight_power(on);
 749 }
 750
 751 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
 752 {
 753         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
 754
 755         if (pxafb_lcd_power)
 756                 pxafb_lcd_power(on, &fbi->fb.var);
 757 }
 758
 759 static void pxafb_setup_gpio(struct pxafb_info *fbi)
 760 {
 761         int gpio, ldd_bits;
 762         unsigned int lccr0 = fbi->lccr0;
 763
 764         /*
 765          * setup is based on type of panel supported
 766         */
 767
 768         /* 4 bit interface */
 769         if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 770             (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
 771             (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
 772                 ldd_bits = 4;
 773
 774         /* 8 bit interface */
 775         else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
 776                   ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
 777                  ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 778                   (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
 779                 ldd_bits = 8;
 780
 781         /* 16 bit interface */
 782         else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
 783                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
 784                 ldd_bits = 16;
 785
 786         else {
 787                 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
 788                 return;
 789         }
 790
 791         for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
 792                 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
 793         pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
 794         pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
 795         pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
 796         pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
 797 }
 798
 799 static void pxafb_enable_controller(struct pxafb_info *fbi)
 800 {
 801         pr_debug("pxafb: Enabling LCD controller\n");
 802         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
 803         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
 804         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
 805         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
 806         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
 807         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
 808
 809         /* enable LCD controller clock */
 810         clk_enable(fbi->clk);
 811
 812         /* Sequence from 11.7.10 */
 813         LCCR3 = fbi->reg_lccr3;
 814         LCCR2 = fbi->reg_lccr2;
 815         LCCR1 = fbi->reg_lccr1;
 816         LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
 817
 818         FDADR0 = fbi->fdadr0;
 819         FDADR1 = fbi->fdadr1;
 820         LCCR0 |= LCCR0_ENB;
 821
 822         pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
 823         pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
 824         pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
 825         pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
 826         pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
 827         pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
 828 }
 829
 830 static void pxafb_disable_controller(struct pxafb_info *fbi)
 831 {
 832         DECLARE_WAITQUEUE(wait, current);
 833
 834         pr_debug("pxafb: disabling LCD controller\n");
 835
 836         set_current_state(TASK_UNINTERRUPTIBLE);
 837         add_wait_queue(&fbi->ctrlr_wait, &wait);
 838
 839         LCSR = 0xffffffff;      /* Clear LCD Status Register */
 840         LCCR0 &= ~LCCR0_LDM;    /* Enable LCD Disable Done Interrupt */
 841         LCCR0 |= LCCR0_DIS;     /* Disable LCD Controller */
 842
 843         schedule_timeout(200 * HZ / 1000);
 844         remove_wait_queue(&fbi->ctrlr_wait, &wait);
 845
 846         /* disable LCD controller clock */
 847         clk_disable(fbi->clk);
 848 }
 849
 850 /*
 851  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
 852  */
 853 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
 854 {
 855         struct pxafb_info *fbi = dev_id;
 856         unsigned int lcsr = LCSR;
 857
 858         if (lcsr & LCSR_LDD) {
 859                 LCCR0 |= LCCR0_LDM;
 860                 wake_up(&fbi->ctrlr_wait);
 861         }
 862
 863         LCSR = lcsr;
 864         return IRQ_HANDLED;
 865 }
 866
 867 /*
 868  * This function must be called from task context only, since it will
 869  * sleep when disabling the LCD controller, or if we get two contending
 870  * processes trying to alter state.
 871  */
 872 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
 873 {
 874         u_int old_state;
 875
 876         down(&fbi->ctrlr_sem);
 877
 878         old_state = fbi->state;
 879
 880         /*
 881          * Hack around fbcon initialisation.
 882          */
 883         if (old_state == C_STARTUP && state == C_REENABLE)
 884                 state = C_ENABLE;
 885
 886         switch (state) {
 887         case C_DISABLE_CLKCHANGE:
 888                 /*
 889                  * Disable controller for clock change.  If the
 890                  * controller is already disabled, then do nothing.
 891                  */
 892                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
 893                         fbi->state = state;
 894                         //TODO __pxafb_lcd_power(fbi, 0);
 895                         pxafb_disable_controller(fbi);
 896                 }
 897                 break;
 898
 899         case C_DISABLE_PM:
 900         case C_DISABLE:
 901                 /*
 902                  * Disable controller
 903                  */
 904                 if (old_state != C_DISABLE) {
 905                         fbi->state = state;
 906                         __pxafb_backlight_power(fbi, 0);
 907                         __pxafb_lcd_power(fbi, 0);
 908                         if (old_state != C_DISABLE_CLKCHANGE)
 909                                 pxafb_disable_controller(fbi);
 910                 }
 911                 break;
 912
 913         case C_ENABLE_CLKCHANGE:
 914                 /*
 915                  * Enable the controller after clock change.  Only
 916                  * do this if we were disabled for the clock change.
 917                  */
 918                 if (old_state == C_DISABLE_CLKCHANGE) {
 919                         fbi->state = C_ENABLE;
 920                         pxafb_enable_controller(fbi);
 921                         //TODO __pxafb_lcd_power(fbi, 1);
 922                 }
 923                 break;
 924
 925         case C_REENABLE:
 926                 /*
 927                  * Re-enable the controller only if it was already
 928                  * enabled.  This is so we reprogram the control
 929                  * registers.
 930                  */
 931                 if (old_state == C_ENABLE) {
 932                         __pxafb_lcd_power(fbi, 0);
 933                         pxafb_disable_controller(fbi);
 934                         pxafb_setup_gpio(fbi);
 935                         pxafb_enable_controller(fbi);
 936                         __pxafb_lcd_power(fbi, 1);
 937                 }
 938                 break;
 939
 940         case C_ENABLE_PM:
 941                 /*
 942                  * Re-enable the controller after PM.  This is not
 943                  * perfect - think about the case where we were doing
 944                  * a clock change, and we suspended half-way through.
 945                  */
 946                 if (old_state != C_DISABLE_PM)
 947                         break;
 948                 /* fall through */
 949
 950         case C_ENABLE:
 951                 /*
 952                  * Power up the LCD screen, enable controller, and
 953                  * turn on the backlight.
 954                  */
 955                 if (old_state != C_ENABLE) {
 956                         fbi->state = C_ENABLE;
 957                         pxafb_setup_gpio(fbi);
 958                         pxafb_enable_controller(fbi);
 959                         __pxafb_lcd_power(fbi, 1);
 960                         __pxafb_backlight_power(fbi, 1);
 961                 }
 962                 break;
 963         }
 964         up(&fbi->ctrlr_sem);
 965 }
 966
 967 /*
 968  * Our LCD controller task (which is called when we blank or unblank)
 969  * via keventd.
 970  */
 971 static void pxafb_task(struct work_struct *work)
 972 {
 973         struct pxafb_info *fbi =
 974                 container_of(work, struct pxafb_info, task);
 975         u_int state = xchg(&fbi->task_state, -1);
 976
 977         set_ctrlr_state(fbi, state);
 978 }
 979
 980 #ifdef CONFIG_CPU_FREQ
 981 /*
 982  * CPU clock speed change handler.  We need to adjust the LCD timing
 983  * parameters when the CPU clock is adjusted by the power management
 984  * subsystem.
 985  *
 986  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
 987  */
 988 static int
 989 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
 990 {
 991         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
 992         //TODO struct cpufreq_freqs *f = data;
 993         u_int pcd;
 994
 995         switch (val) {
 996         case CPUFREQ_PRECHANGE:
 997                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
 998                 break;
 999
1000         case CPUFREQ_POSTCHANGE:
1001                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1002                 set_hsync_time(fbi, pcd);
1003                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1004                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1005                 break;
1006         }
1007         return 0;
1008 }
1009
1010 static int
1011 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1012 {
1013         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1014         struct fb_var_screeninfo *var = &fbi->fb.var;
1015         struct cpufreq_policy *policy = data;
1016
1017         switch (val) {
1018         case CPUFREQ_ADJUST:
1019         case CPUFREQ_INCOMPATIBLE:
1020                 printk(KERN_DEBUG "min dma period: %d ps, "
1021                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1022                         policy->max);
1023                 // TODO: fill in min/max values
1024                 break;
1025 #if 0
1026         case CPUFREQ_NOTIFY:
1027                 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
1028                 do {} while(0);
1029                 /* todo: panic if min/max values aren't fulfilled
1030                  * [can't really happen unless there's a bug in the
1031                  * CPU policy verification process *
1032                  */
1033                 break;
1034 #endif
1035         }
1036         return 0;
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_PM
1041 /*
1042  * Power management hooks.  Note that we won't be called from IRQ context,
1043  * unlike the blank functions above, so we may sleep.
1044  */
1045 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1046 {
1047         struct pxafb_info *fbi = platform_get_drvdata(dev);
1048
1049         set_ctrlr_state(fbi, C_DISABLE_PM);
1050         return 0;
1051 }
1052
1053 static int pxafb_resume(struct platform_device *dev)
1054 {
1055         struct pxafb_info *fbi = platform_get_drvdata(dev);
1056
1057         set_ctrlr_state(fbi, C_ENABLE_PM);
1058         return 0;
1059 }
1060 #else
1061 #define pxafb_suspend   NULL
1062 #define pxafb_resume    NULL
1063 #endif
1064
1065 /*
1066  * pxafb_map_video_memory():
1067  *      Allocates the DRAM memory for the frame buffer.  This buffer is
1068  *      remapped into a non-cached, non-buffered, memory region to
1069  *      allow palette and pixel writes to occur without flushing the
1070  *      cache.  Once this area is remapped, all virtual memory
1071  *      access to the video memory should occur at the new region.
1072  */
1073 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1074 {
1075         u_long palette_mem_size;
1076
1077         /*
1078          * We reserve one page for the palette, plus the size
1079          * of the framebuffer.
1080          */
1081         fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1082         fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1083                                               &fbi->map_dma, GFP_KERNEL);
1084
1085         if (fbi->map_cpu) {
1086                 /* prevent initial garbage on screen */
1087                 memset(fbi->map_cpu, 0, fbi->map_size);
1088                 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1089                 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1090                 /*
1091                  * FIXME: this is actually the wrong thing to place in
1092                  * smem_start.  But fbdev suffers from the problem that
1093                  * it needs an API which doesn't exist (in this case,
1094                  * dma_writecombine_mmap)
1095                  */
1096                 fbi->fb.fix.smem_start = fbi->screen_dma;
1097
1098                 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1099
1100                 palette_mem_size = fbi->palette_size * sizeof(u16);
1101                 pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
1102
1103                 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1104                 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1105         }
1106
1107         return fbi->map_cpu ? 0 : -ENOMEM;
1108 }
1109
1110 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1111 {
1112         struct pxafb_info *fbi;
1113         void *addr;
1114         struct pxafb_mach_info *inf = dev->platform_data;
1115         struct pxafb_mode_info *mode = inf->modes;
1116         int i, smemlen;
1117
1118         /* Alloc the pxafb_info and pseudo_palette in one step */
1119         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1120         if (!fbi)
1121                 return NULL;
1122
1123         memset(fbi, 0, sizeof(struct pxafb_info));
1124         fbi->dev = dev;
1125
1126         fbi->clk = clk_get(dev, "LCDCLK");
1127         if (IS_ERR(fbi->clk)) {
1128                 kfree(fbi);
1129                 return NULL;
1130         }
1131
1132         strcpy(fbi->fb.fix.id, PXA_NAME);
1133
1134         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1135         fbi->fb.fix.type_aux    = 0;
1136         fbi->fb.fix.xpanstep    = 0;
1137         fbi->fb.fix.ypanstep    = 0;
1138         fbi->fb.fix.ywrapstep   = 0;
1139         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1140
1141         fbi->fb.var.nonstd      = 0;
1142         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1143         fbi->fb.var.height      = -1;
1144         fbi->fb.var.width       = -1;
1145         fbi->fb.var.accel_flags = 0;
1146         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1147
1148         fbi->fb.fbops           = &pxafb_ops;
1149         fbi->fb.flags           = FBINFO_DEFAULT;
1150         fbi->fb.node            = -1;
1151
1152         addr = fbi;
1153         addr = addr + sizeof(struct pxafb_info);
1154         fbi->fb.pseudo_palette  = addr;
1155
1156         pxafb_setmode(&fbi->fb.var, mode);
1157
1158         fbi->cmap_inverse               = inf->cmap_inverse;
1159         fbi->cmap_static                = inf->cmap_static;
1160
1161         fbi->lccr0                      = inf->lccr0;
1162         fbi->lccr3                      = inf->lccr3;
1163         fbi->state                      = C_STARTUP;
1164         fbi->task_state                 = (u_char)-1;
1165
1166         for (i = 0; i < inf->num_modes; i++) {
1167                 smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8;
1168                 if (smemlen > fbi->fb.fix.smem_len)
1169                         fbi->fb.fix.smem_len = smemlen;
1170         }
1171
1172         init_waitqueue_head(&fbi->ctrlr_wait);
1173         INIT_WORK(&fbi->task, pxafb_task);
1174         init_MUTEX(&fbi->ctrlr_sem);
1175
1176         return fbi;
1177 }
1178
1179 #ifdef CONFIG_FB_PXA_PARAMETERS
1180 static int __init pxafb_parse_options(struct device *dev, char *options)
1181 {
1182         struct pxafb_mach_info *inf = dev->platform_data;
1183         char *this_opt;
1184
1185         if (!options || !*options)
1186                 return 0;
1187
1188         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1189
1190         /* could be made table driven or similar?... */
1191         while ((this_opt = strsep(&options, ",")) != NULL) {
1192                 if (!strncmp(this_opt, "mode:", 5)) {
1193                         const char *name = this_opt+5;
1194                         unsigned int namelen = strlen(name);
1195                         int res_specified = 0, bpp_specified = 0;
1196                         unsigned int xres = 0, yres = 0, bpp = 0;
1197                         int yres_specified = 0;
1198                         int i;
1199                         for (i = namelen-1; i >= 0; i--) {
1200                                 switch (name[i]) {
1201                                 case '-':
1202                                         namelen = i;
1203                                         if (!bpp_specified && !yres_specified) {
1204                                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1205                                                 bpp_specified = 1;
1206                                         } else
1207                                                 goto done;
1208                                         break;
1209                                 case 'x':
1210                                         if (!yres_specified) {
1211                                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1212                                                 yres_specified = 1;
1213                                         } else
1214                                                 goto done;
1215                                         break;
1216                                 case '0' ... '9':
1217                                         break;
1218                                 default:
1219                                         goto done;
1220                                 }
1221                         }
1222                         if (i < 0 && yres_specified) {
1223                                 xres = simple_strtoul(name, NULL, 0);
1224                                 res_specified = 1;
1225                         }
1226                 done:
1227                         if (res_specified) {
1228                                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1229                                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1230                         }
1231                         if (bpp_specified)
1232                                 switch (bpp) {
1233                                 case 1:
1234                                 case 2:
1235                                 case 4:
1236                                 case 8:
1237                                 case 16:
1238                                         inf->modes[0].bpp = bpp;
1239                                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1240                                         break;
1241                                 default:
1242                                         dev_err(dev, "Depth %d is not valid\n", bpp);
1243                                 }
1244                 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1245                         inf->modes[0].pixclock = simple_strtoul(this_opt+9, NULL, 0);
1246                         dev_info(dev, "override pixclock: %ld\n", inf->modes[0].pixclock);
1247                 } else if (!strncmp(this_opt, "left:", 5)) {
1248                         inf->modes[0].left_margin = simple_strtoul(this_opt+5, NULL, 0);
1249                         dev_info(dev, "override left: %u\n", inf->modes[0].left_margin);
1250                 } else if (!strncmp(this_opt, "right:", 6)) {
1251                         inf->modes[0].right_margin = simple_strtoul(this_opt+6, NULL, 0);
1252                         dev_info(dev, "override right: %u\n", inf->modes[0].right_margin);
1253                 } else if (!strncmp(this_opt, "upper:", 6)) {
1254                         inf->modes[0].upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1255                         dev_info(dev, "override upper: %u\n", inf->modes[0].upper_margin);
1256                 } else if (!strncmp(this_opt, "lower:", 6)) {
1257                         inf->modes[0].lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1258                         dev_info(dev, "override lower: %u\n", inf->modes[0].lower_margin);
1259                 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1260                         inf->modes[0].hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1261                         dev_info(dev, "override hsynclen: %u\n", inf->modes[0].hsync_len);
1262                 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1263                         inf->modes[0].vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1264                         dev_info(dev, "override vsynclen: %u\n", inf->modes[0].vsync_len);
1265                 } else if (!strncmp(this_opt, "hsync:", 6)) {
1266                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1267                                 dev_info(dev, "override hsync: Active Low\n");
1268                                 inf->modes[0].sync &= ~FB_SYNC_HOR_HIGH_ACT;
1269                         } else {
1270                                 dev_info(dev, "override hsync: Active High\n");
1271                                 inf->modes[0].sync |= FB_SYNC_HOR_HIGH_ACT;
1272                         }
1273                 } else if (!strncmp(this_opt, "vsync:", 6)) {
1274                         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1275                                 dev_info(dev, "override vsync: Active Low\n");
1276                                 inf->modes[0].sync &= ~FB_SYNC_VERT_HIGH_ACT;
1277                         } else {
1278                                 dev_info(dev, "override vsync: Active High\n");
1279                                 inf->modes[0].sync |= FB_SYNC_VERT_HIGH_ACT;
1280                         }
1281                 } else if (!strncmp(this_opt, "dpc:", 4)) {
1282                         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1283                                 dev_info(dev, "override double pixel clock: false\n");
1284                                 inf->lccr3 &= ~LCCR3_DPC;
1285                         } else {
1286                                 dev_info(dev, "override double pixel clock: true\n");
1287                                 inf->lccr3 |= LCCR3_DPC;
1288                         }
1289                 } else if (!strncmp(this_opt, "outputen:", 9)) {
1290                         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1291                                 dev_info(dev, "override output enable: active low\n");
1292                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1293                         } else {
1294                                 dev_info(dev, "override output enable: active high\n");
1295                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1296                         }
1297                 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1298                         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1299                                 dev_info(dev, "override pixel clock polarity: falling edge\n");
1300                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1301                         } else {
1302                                 dev_info(dev, "override pixel clock polarity: rising edge\n");
1303                                 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1304                         }
1305                 } else if (!strncmp(this_opt, "color", 5)) {
1306                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1307                 } else if (!strncmp(this_opt, "mono", 4)) {
1308                         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1309                 } else if (!strncmp(this_opt, "active", 6)) {
1310                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1311                 } else if (!strncmp(this_opt, "passive", 7)) {
1312                         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1313                 } else if (!strncmp(this_opt, "single", 6)) {
1314                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1315                 } else if (!strncmp(this_opt, "dual", 4)) {
1316                         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1317                 } else if (!strncmp(this_opt, "4pix", 4)) {
1318                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1319                 } else if (!strncmp(this_opt, "8pix", 4)) {
1320                         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1321                 } else {
1322                         dev_err(dev, "unknown option: %s\n", this_opt);
1323                         return -EINVAL;
1324                 }
1325         }
1326         return 0;
1327
1328 }
1329 #endif
1330
1331 int __init pxafb_probe(struct platform_device *dev)
1332 {
1333         struct pxafb_info *fbi;
1334         struct pxafb_mach_info *inf;
1335         int ret;
1336
1337         dev_dbg(&dev->dev, "pxafb_probe\n");
1338
1339         inf = dev->dev.platform_data;
1340         ret = -ENOMEM;
1341         fbi = NULL;
1342         if (!inf)
1343                 goto failed;
1344
1345 #ifdef CONFIG_FB_PXA_PARAMETERS
1346         ret = pxafb_parse_options(&dev->dev, g_options);
1347         if (ret < 0)
1348                 goto failed;
1349 #endif
1350
1351 #ifdef DEBUG_VAR
1352         /* Check for various illegal bit-combinations. Currently only
1353          * a warning is given. */
1354
1355         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1356                 dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1357                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1358         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1359                 dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1360                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1361         if (inf->lccr0 & LCCR0_DPD &&
1362             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1363              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1364              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1365                 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1366                          " single panel mode\n");
1367         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1368             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1369                 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1370         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1371              (inf->modes->upper_margin || inf->modes->lower_margin))
1372                 dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
1373 #endif
1374
1375         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp);
1376         if (inf->modes->xres == 0 || inf->modes->yres == 0 || inf->modes->bpp == 0) {
1377                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1378                 ret = -EINVAL;
1379                 goto failed;
1380         }
1381         pxafb_backlight_power = inf->pxafb_backlight_power;
1382         pxafb_lcd_power = inf->pxafb_lcd_power;
1383         fbi = pxafb_init_fbinfo(&dev->dev);
1384         if (!fbi) {
1385                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1386                 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1387                 goto failed;
1388         }
1389
1390         /* Initialize video memory */
1391         ret = pxafb_map_video_memory(fbi);
1392         if (ret) {
1393                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1394                 ret = -ENOMEM;
1395                 goto failed;
1396         }
1397
1398         ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1399         if (ret) {
1400                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1401                 ret = -EBUSY;
1402                 goto failed;
1403         }
1404
1405         /*
1406          * This makes sure that our colour bitfield
1407          * descriptors are correctly initialised.
1408          */
1409         pxafb_check_var(&fbi->fb.var, &fbi->fb);
1410         pxafb_set_par(&fbi->fb);
1411
1412         platform_set_drvdata(dev, fbi);
1413
1414         ret = register_framebuffer(&fbi->fb);
1415         if (ret < 0) {
1416                 dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
1417                 goto failed;
1418         }
1419
1420 #ifdef CONFIG_PM
1421         // TODO
1422 #endif
1423
1424 #ifdef CONFIG_CPU_FREQ
1425         fbi->freq_transition.notifier_call = pxafb_freq_transition;
1426         fbi->freq_policy.notifier_call = pxafb_freq_policy;
1427         cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1428         cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1429 #endif
1430
1431         /*
1432          * Ok, now enable the LCD controller
1433          */
1434         set_ctrlr_state(fbi, C_ENABLE);
1435
1436         return 0;
1437
1438 failed:
1439         platform_set_drvdata(dev, NULL);
1440         kfree(fbi);
1441         return ret;
1442 }
1443
1444 static struct platform_driver pxafb_driver = {
1445         .probe          = pxafb_probe,
1446 #ifdef CONFIG_PM
1447         .suspend        = pxafb_suspend,
1448         .resume         = pxafb_resume,
1449 #endif
1450         .driver         = {
1451                 .name   = "pxa2xx-fb",
1452         },
1453 };
1454
1455 #ifndef MODULE
1456 int __devinit pxafb_setup(char *options)
1457 {
1458 # ifdef CONFIG_FB_PXA_PARAMETERS
1459         if (options)
1460                 strlcpy(g_options, options, sizeof(g_options));
1461 # endif
1462         return 0;
1463 }
1464 #else
1465 # ifdef CONFIG_FB_PXA_PARAMETERS
1466 module_param_string(options, g_options, sizeof(g_options), 0);
1467 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1468 # endif
1469 #endif
1470
1471 int __devinit pxafb_init(void)
1472 {
1473 #ifndef MODULE
1474         char *option = NULL;
1475
1476         if (fb_get_options("pxafb", &option))
1477                 return -ENODEV;
1478         pxafb_setup(option);
1479 #endif
1480         return platform_driver_register(&pxafb_driver);
1481 }
1482
1483 module_init(pxafb_init);
1484
1485 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1486 MODULE_LICENSE("GPL");