2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
48 #include <mach/hardware.h>
51 #include <asm/div64.h>
52 #include <mach/pxa-regs.h>
53 #include <mach/bitfield.h>
54 #include <mach/pxafb.h>
57 * Complain if VAR is out of range.
63 /* Bits which should not be set in machine configuration structures */
64 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
65 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
66 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
68 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
69 LCCR3_PCD | LCCR3_BPP(0xf))
71 static int pxafb_activate_var(struct fb_var_screeninfo *var,
73 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
74 static void setup_base_frame(struct pxafb_info *fbi, int branch);
76 static unsigned long video_mem_size = 0;
78 static inline unsigned long
79 lcd_readl(struct pxafb_info *fbi, unsigned int off)
81 return __raw_readl(fbi->mmio_base + off);
85 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
87 __raw_writel(val, fbi->mmio_base + off);
90 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
94 local_irq_save(flags);
96 * We need to handle two requests being made at the same time.
97 * There are two important cases:
98 * 1. When we are changing VT (C_REENABLE) while unblanking
99 * (C_ENABLE) We must perform the unblanking, which will
100 * do our REENABLE for us.
101 * 2. When we are blanking, but immediately unblank before
102 * we have blanked. We do the "REENABLE" thing here as
103 * well, just to be sure.
105 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
107 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
110 if (state != (u_int)-1) {
111 fbi->task_state = state;
112 schedule_work(&fbi->task);
114 local_irq_restore(flags);
117 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
120 chan >>= 16 - bf->length;
121 return chan << bf->offset;
125 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
126 u_int trans, struct fb_info *info)
128 struct pxafb_info *fbi = (struct pxafb_info *)info;
131 if (regno >= fbi->palette_size)
134 if (fbi->fb.var.grayscale) {
135 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
139 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
140 case LCCR4_PAL_FOR_0:
141 val = ((red >> 0) & 0xf800);
142 val |= ((green >> 5) & 0x07e0);
143 val |= ((blue >> 11) & 0x001f);
144 fbi->palette_cpu[regno] = val;
146 case LCCR4_PAL_FOR_1:
147 val = ((red << 8) & 0x00f80000);
148 val |= ((green >> 0) & 0x0000fc00);
149 val |= ((blue >> 8) & 0x000000f8);
150 ((u32 *)(fbi->palette_cpu))[regno] = val;
152 case LCCR4_PAL_FOR_2:
153 val = ((red << 8) & 0x00fc0000);
154 val |= ((green >> 0) & 0x0000fc00);
155 val |= ((blue >> 8) & 0x000000fc);
156 ((u32 *)(fbi->palette_cpu))[regno] = val;
158 case LCCR4_PAL_FOR_3:
159 val = ((red << 8) & 0x00ff0000);
160 val |= ((green >> 0) & 0x0000ff00);
161 val |= ((blue >> 8) & 0x000000ff);
162 ((u32 *)(fbi->palette_cpu))[regno] = val;
170 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
171 u_int trans, struct fb_info *info)
173 struct pxafb_info *fbi = (struct pxafb_info *)info;
178 * If inverse mode was selected, invert all the colours
179 * rather than the register number. The register number
180 * is what you poke into the framebuffer to produce the
181 * colour you requested.
183 if (fbi->cmap_inverse) {
185 green = 0xffff - green;
186 blue = 0xffff - blue;
190 * If greyscale is true, then we convert the RGB value
191 * to greyscale no matter what visual we are using.
193 if (fbi->fb.var.grayscale)
194 red = green = blue = (19595 * red + 38470 * green +
197 switch (fbi->fb.fix.visual) {
198 case FB_VISUAL_TRUECOLOR:
200 * 16-bit True Colour. We encode the RGB value
201 * according to the RGB bitfield information.
204 u32 *pal = fbi->fb.pseudo_palette;
206 val = chan_to_field(red, &fbi->fb.var.red);
207 val |= chan_to_field(green, &fbi->fb.var.green);
208 val |= chan_to_field(blue, &fbi->fb.var.blue);
215 case FB_VISUAL_STATIC_PSEUDOCOLOR:
216 case FB_VISUAL_PSEUDOCOLOR:
217 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
224 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
225 static inline int var_to_depth(struct fb_var_screeninfo *var)
227 return var->red.length + var->green.length +
228 var->blue.length + var->transp.length;
231 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
232 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
236 switch (var->bits_per_pixel) {
237 case 1: bpp = 0; break;
238 case 2: bpp = 1; break;
239 case 4: bpp = 2; break;
240 case 8: bpp = 3; break;
241 case 16: bpp = 4; break;
243 switch (var_to_depth(var)) {
244 case 18: bpp = 6; break; /* 18-bits/pixel packed */
245 case 19: bpp = 8; break; /* 19-bits/pixel packed */
246 case 24: bpp = 9; break;
250 switch (var_to_depth(var)) {
251 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
252 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
253 case 25: bpp = 10; break;
261 * pxafb_var_to_lccr3():
262 * Convert a bits per pixel value to the correct bit pattern for LCCR3
264 * NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
265 * implication of the acutal use of transparency bit, which we handle it
266 * here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
267 * Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
269 * Transparency for palette pixel formats is not supported at the moment.
271 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
273 int bpp = pxafb_var_to_bpp(var);
279 lccr3 = LCCR3_BPP(bpp);
281 switch (var_to_depth(var)) {
282 case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
283 case 18: lccr3 |= LCCR3_PDFOR_3; break;
284 case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
287 case 25: lccr3 |= LCCR3_PDFOR_0; break;
292 #define SET_PIXFMT(v, r, g, b, t) \
294 (v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
295 (v)->transp.length = (t) ? (t) : 0; \
296 (v)->blue.length = (b); (v)->blue.offset = 0; \
297 (v)->green.length = (g); (v)->green.offset = (b); \
298 (v)->red.length = (r); (v)->red.offset = (b) + (g); \
301 /* set the RGBT bitfields of fb_var_screeninf according to
302 * var->bits_per_pixel and given depth
304 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
307 depth = var->bits_per_pixel;
309 if (var->bits_per_pixel < 16) {
310 /* indexed pixel formats */
311 var->red.offset = 0; var->red.length = 8;
312 var->green.offset = 0; var->green.length = 8;
313 var->blue.offset = 0; var->blue.length = 8;
314 var->transp.offset = 0; var->transp.length = 8;
318 case 16: var->transp.length ?
319 SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
320 SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
321 case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
322 case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
323 case 24: var->transp.length ?
324 SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
325 SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
326 case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
330 #ifdef CONFIG_CPU_FREQ
332 * pxafb_display_dma_period()
333 * Calculate the minimum period (in picoseconds) between two DMA
334 * requests for the LCD controller. If we hit this, it means we're
335 * doing nothing but LCD DMA.
337 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
340 * Period = pixclock * bits_per_byte * bytes_per_transfer
341 * / memory_bits_per_pixel;
343 return var->pixclock * 8 * 16 / var->bits_per_pixel;
348 * Select the smallest mode that allows the desired resolution to be
349 * displayed. If desired parameters can be rounded up.
351 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
352 struct fb_var_screeninfo *var)
354 struct pxafb_mode_info *mode = NULL;
355 struct pxafb_mode_info *modelist = mach->modes;
356 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
359 for (i = 0; i < mach->num_modes; i++) {
360 if (modelist[i].xres >= var->xres &&
361 modelist[i].yres >= var->yres &&
362 modelist[i].xres < best_x &&
363 modelist[i].yres < best_y &&
364 modelist[i].bpp >= var->bits_per_pixel) {
365 best_x = modelist[i].xres;
366 best_y = modelist[i].yres;
374 static void pxafb_setmode(struct fb_var_screeninfo *var,
375 struct pxafb_mode_info *mode)
377 var->xres = mode->xres;
378 var->yres = mode->yres;
379 var->bits_per_pixel = mode->bpp;
380 var->pixclock = mode->pixclock;
381 var->hsync_len = mode->hsync_len;
382 var->left_margin = mode->left_margin;
383 var->right_margin = mode->right_margin;
384 var->vsync_len = mode->vsync_len;
385 var->upper_margin = mode->upper_margin;
386 var->lower_margin = mode->lower_margin;
387 var->sync = mode->sync;
388 var->grayscale = mode->cmap_greyscale;
390 /* set the initial RGBA bitfields */
391 pxafb_set_pixfmt(var, mode->depth);
394 static int pxafb_adjust_timing(struct pxafb_info *fbi,
395 struct fb_var_screeninfo *var)
399 var->xres = max_t(int, var->xres, MIN_XRES);
400 var->yres = max_t(int, var->yres, MIN_YRES);
402 if (!(fbi->lccr0 & LCCR0_LCDT)) {
403 clamp_val(var->hsync_len, 1, 64);
404 clamp_val(var->vsync_len, 1, 64);
405 clamp_val(var->left_margin, 1, 255);
406 clamp_val(var->right_margin, 1, 255);
407 clamp_val(var->upper_margin, 1, 255);
408 clamp_val(var->lower_margin, 1, 255);
411 /* make sure each line is aligned on word boundary */
412 line_length = var->xres * var->bits_per_pixel / 8;
413 line_length = ALIGN(line_length, 4);
414 var->xres = line_length * 8 / var->bits_per_pixel;
416 /* we don't support xpan, force xres_virtual to be equal to xres */
417 var->xres_virtual = var->xres;
419 if (var->accel_flags & FB_ACCELF_TEXT)
420 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
422 var->yres_virtual = max(var->yres_virtual, var->yres);
424 /* check for limits */
425 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
428 if (var->yres > var->yres_virtual)
436 * Get the video params out of 'var'. If a value doesn't fit, round it up,
437 * if it's too big, return -EINVAL.
439 * Round up in the following order: bits_per_pixel, xres,
440 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
441 * bitfields, horizontal timing, vertical timing.
443 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
445 struct pxafb_info *fbi = (struct pxafb_info *)info;
446 struct pxafb_mach_info *inf = fbi->dev->platform_data;
449 if (inf->fixed_modes) {
450 struct pxafb_mode_info *mode;
452 mode = pxafb_getmode(inf, var);
455 pxafb_setmode(var, mode);
458 /* do a test conversion to BPP fields to check the color formats */
459 err = pxafb_var_to_bpp(var);
463 pxafb_set_pixfmt(var, var_to_depth(var));
465 err = pxafb_adjust_timing(fbi, var);
469 #ifdef CONFIG_CPU_FREQ
470 pr_debug("pxafb: dma period = %d ps\n",
471 pxafb_display_dma_period(var));
479 * Set the user defined part of the display for the specified console
481 static int pxafb_set_par(struct fb_info *info)
483 struct pxafb_info *fbi = (struct pxafb_info *)info;
484 struct fb_var_screeninfo *var = &info->var;
486 if (var->bits_per_pixel >= 16)
487 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
488 else if (!fbi->cmap_static)
489 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
492 * Some people have weird ideas about wanting static
493 * pseudocolor maps. I suspect their user space
494 * applications are broken.
496 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
499 fbi->fb.fix.line_length = var->xres_virtual *
500 var->bits_per_pixel / 8;
501 if (var->bits_per_pixel >= 16)
502 fbi->palette_size = 0;
504 fbi->palette_size = var->bits_per_pixel == 1 ?
505 4 : 1 << var->bits_per_pixel;
507 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
509 if (fbi->fb.var.bits_per_pixel >= 16)
510 fb_dealloc_cmap(&fbi->fb.cmap);
512 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
514 pxafb_activate_var(var, fbi);
519 static int pxafb_pan_display(struct fb_var_screeninfo *var,
520 struct fb_info *info)
522 struct pxafb_info *fbi = (struct pxafb_info *)info;
523 int dma = DMA_MAX + DMA_BASE;
525 if (fbi->state != C_ENABLE)
528 setup_base_frame(fbi, 1);
530 if (fbi->lccr0 & LCCR0_SDS)
531 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
533 lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
539 * Blank the display by setting all palette values to zero. Note, the
540 * 16 bpp mode does not really use the palette, so this will not
541 * blank the display in all modes.
543 static int pxafb_blank(int blank, struct fb_info *info)
545 struct pxafb_info *fbi = (struct pxafb_info *)info;
549 case FB_BLANK_POWERDOWN:
550 case FB_BLANK_VSYNC_SUSPEND:
551 case FB_BLANK_HSYNC_SUSPEND:
552 case FB_BLANK_NORMAL:
553 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
554 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
555 for (i = 0; i < fbi->palette_size; i++)
556 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
558 pxafb_schedule_work(fbi, C_DISABLE);
559 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
562 case FB_BLANK_UNBLANK:
563 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
564 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
565 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
566 fb_set_cmap(&fbi->fb.cmap, info);
567 pxafb_schedule_work(fbi, C_ENABLE);
572 static struct fb_ops pxafb_ops = {
573 .owner = THIS_MODULE,
574 .fb_check_var = pxafb_check_var,
575 .fb_set_par = pxafb_set_par,
576 .fb_pan_display = pxafb_pan_display,
577 .fb_setcolreg = pxafb_setcolreg,
578 .fb_fillrect = cfb_fillrect,
579 .fb_copyarea = cfb_copyarea,
580 .fb_imageblit = cfb_imageblit,
581 .fb_blank = pxafb_blank,
585 * Calculate the PCD value from the clock rate (in picoseconds).
586 * We take account of the PPCR clock setting.
587 * From PXA Developer's Manual:
598 * LCLK = LCD/Memory Clock
601 * PixelClock here is in Hz while the pixclock argument given is the
602 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
604 * The function get_lclk_frequency_10khz returns LCLK in units of
605 * 10khz. Calling the result of this function lclk gives us the
608 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
609 * -------------------------------------- - 1
612 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
614 static inline unsigned int get_pcd(struct pxafb_info *fbi,
615 unsigned int pixclock)
617 unsigned long long pcd;
619 /* FIXME: Need to take into account Double Pixel Clock mode
620 * (DPC) bit? or perhaps set it based on the various clock
622 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
624 do_div(pcd, 100000000 * 2);
625 /* no need for this, since we should subtract 1 anyway. they cancel */
626 /* pcd += 1; */ /* make up for integer math truncations */
627 return (unsigned int)pcd;
631 * Some touchscreens need hsync information from the video driver to
632 * function correctly. We export it here. Note that 'hsync_time' and
633 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
634 * of the hsync period in seconds.
636 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
640 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
645 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
647 fbi->hsync_time = htime;
650 unsigned long pxafb_get_hsync_time(struct device *dev)
652 struct pxafb_info *fbi = dev_get_drvdata(dev);
654 /* If display is blanked/suspended, hsync isn't active */
655 if (!fbi || (fbi->state != C_ENABLE))
658 return fbi->hsync_time;
660 EXPORT_SYMBOL(pxafb_get_hsync_time);
662 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
663 unsigned int offset, size_t size)
665 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
666 unsigned int dma_desc_off, pal_desc_off;
668 if (dma < 0 || dma >= DMA_MAX * 2)
671 dma_desc = &fbi->dma_buff->dma_desc[dma];
672 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
674 dma_desc->fsadr = fbi->video_mem_phys + offset;
676 dma_desc->ldcmd = size;
678 if (pal < 0 || pal >= PAL_MAX * 2) {
679 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
680 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
682 pal_desc = &fbi->dma_buff->pal_desc[pal];
683 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
685 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
688 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
689 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
691 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
693 pal_desc->ldcmd |= LDCMD_PAL;
695 /* flip back and forth between palette and frame buffer */
696 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
697 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
698 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
704 static void setup_base_frame(struct pxafb_info *fbi, int branch)
706 struct fb_var_screeninfo *var = &fbi->fb.var;
707 struct fb_fix_screeninfo *fix = &fbi->fb.fix;
708 unsigned int nbytes, offset;
709 int dma, pal, bpp = var->bits_per_pixel;
711 dma = DMA_BASE + (branch ? DMA_MAX : 0);
712 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
714 nbytes = fix->line_length * var->yres;
715 offset = fix->line_length * var->yoffset;
717 if (fbi->lccr0 & LCCR0_SDS) {
719 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
722 setup_frame_dma(fbi, dma, pal, offset, nbytes);
725 #ifdef CONFIG_FB_PXA_SMARTPANEL
726 static int setup_smart_dma(struct pxafb_info *fbi)
728 struct pxafb_dma_descriptor *dma_desc;
729 unsigned long dma_desc_off, cmd_buff_off;
731 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
732 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
733 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
735 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
736 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
738 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
740 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
744 int pxafb_smart_flush(struct fb_info *info)
746 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
750 /* disable controller until all registers are set up */
751 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
753 /* 1. make it an even number of commands to align on 32-bit boundary
754 * 2. add the interrupt command to the end of the chain so we can
755 * keep track of the end of the transfer
758 while (fbi->n_smart_cmds & 1)
759 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
761 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
762 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
763 setup_smart_dma(fbi);
765 /* continue to execute next command */
766 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
767 lcd_writel(fbi, PRSR, prsr);
769 /* stop the processor in case it executed "wait for sync" cmd */
770 lcd_writel(fbi, CMDCR, 0x0001);
772 /* don't send interrupts for fifo underruns on channel 6 */
773 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
775 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
776 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
777 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
778 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
779 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
780 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
783 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
785 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
786 pr_warning("%s: timeout waiting for command done\n",
792 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
793 lcd_writel(fbi, PRSR, prsr);
794 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
795 lcd_writel(fbi, FDADR6, 0);
796 fbi->n_smart_cmds = 0;
800 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
803 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
805 for (i = 0; i < n_cmds; i++, cmds++) {
806 /* if it is a software delay, flush and delay */
807 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
808 pxafb_smart_flush(info);
809 mdelay(*cmds & 0xff);
813 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
814 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
815 pxafb_smart_flush(info);
817 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
823 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
825 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
826 return (t == 0) ? 1 : t;
829 static void setup_smart_timing(struct pxafb_info *fbi,
830 struct fb_var_screeninfo *var)
832 struct pxafb_mach_info *inf = fbi->dev->platform_data;
833 struct pxafb_mode_info *mode = &inf->modes[0];
834 unsigned long lclk = clk_get_rate(fbi->clk);
835 unsigned t1, t2, t3, t4;
837 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
838 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
839 t3 = mode->op_hold_time;
840 t4 = mode->cmd_inh_time;
843 LCCR1_DisWdth(var->xres) |
844 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
845 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
846 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
848 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
849 fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
850 fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
851 fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
853 /* FIXME: make this configurable */
857 static int pxafb_smart_thread(void *arg)
859 struct pxafb_info *fbi = arg;
860 struct pxafb_mach_info *inf = fbi->dev->platform_data;
862 if (!fbi || !inf->smart_update) {
863 pr_err("%s: not properly initialized, thread terminated\n",
868 pr_debug("%s(): task starting\n", __func__);
871 while (!kthread_should_stop()) {
876 mutex_lock(&fbi->ctrlr_lock);
878 if (fbi->state == C_ENABLE) {
879 inf->smart_update(&fbi->fb);
880 complete(&fbi->refresh_done);
883 mutex_unlock(&fbi->ctrlr_lock);
885 set_current_state(TASK_INTERRUPTIBLE);
886 schedule_timeout(30 * HZ / 1000);
889 pr_debug("%s(): task ending\n", __func__);
893 static int pxafb_smart_init(struct pxafb_info *fbi)
895 if (!(fbi->lccr0 & LCCR0_LCDT))
898 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
899 fbi->n_smart_cmds = 0;
901 init_completion(&fbi->command_done);
902 init_completion(&fbi->refresh_done);
904 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
906 if (IS_ERR(fbi->smart_thread)) {
907 pr_err("%s: unable to create kernel thread\n", __func__);
908 return PTR_ERR(fbi->smart_thread);
914 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
919 int pxafb_smart_flush(struct fb_info *info)
924 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
925 #endif /* CONFIG_FB_PXA_SMARTPANEL */
927 static void setup_parallel_timing(struct pxafb_info *fbi,
928 struct fb_var_screeninfo *var)
930 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
933 LCCR1_DisWdth(var->xres) +
934 LCCR1_HorSnchWdth(var->hsync_len) +
935 LCCR1_BegLnDel(var->left_margin) +
936 LCCR1_EndLnDel(var->right_margin);
939 * If we have a dual scan LCD, we need to halve
940 * the YRES parameter.
942 lines_per_panel = var->yres;
943 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
944 lines_per_panel /= 2;
947 LCCR2_DisHght(lines_per_panel) +
948 LCCR2_VrtSnchWdth(var->vsync_len) +
949 LCCR2_BegFrmDel(var->upper_margin) +
950 LCCR2_EndFrmDel(var->lower_margin);
952 fbi->reg_lccr3 = fbi->lccr3 |
953 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
954 LCCR3_HorSnchH : LCCR3_HorSnchL) |
955 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
956 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
959 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
960 set_hsync_time(fbi, pcd);
965 * pxafb_activate_var():
966 * Configures LCD Controller based on entries in var parameter.
967 * Settings are only written to the controller if changes were made.
969 static int pxafb_activate_var(struct fb_var_screeninfo *var,
970 struct pxafb_info *fbi)
974 /* Update shadow copy atomically */
975 local_irq_save(flags);
977 #ifdef CONFIG_FB_PXA_SMARTPANEL
978 if (fbi->lccr0 & LCCR0_LCDT)
979 setup_smart_timing(fbi, var);
982 setup_parallel_timing(fbi, var);
984 setup_base_frame(fbi, 0);
986 fbi->reg_lccr0 = fbi->lccr0 |
987 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
988 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
990 fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
992 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
993 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
994 local_irq_restore(flags);
997 * Only update the registers if the controller is enabled
998 * and something has changed.
1000 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1001 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1002 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1003 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1004 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1005 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1006 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1007 pxafb_schedule_work(fbi, C_REENABLE);
1013 * NOTE! The following functions are purely helpers for set_ctrlr_state.
1014 * Do not call them directly; set_ctrlr_state does the correct serialisation
1015 * to ensure that things happen in the right way 100% of time time.
1018 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1020 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1022 if (fbi->backlight_power)
1023 fbi->backlight_power(on);
1026 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1028 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1031 fbi->lcd_power(on, &fbi->fb.var);
1034 static void pxafb_enable_controller(struct pxafb_info *fbi)
1036 pr_debug("pxafb: Enabling LCD controller\n");
1037 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1038 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1039 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1040 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1041 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1042 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1044 /* enable LCD controller clock */
1045 clk_enable(fbi->clk);
1047 if (fbi->lccr0 & LCCR0_LCDT)
1050 /* Sequence from 11.7.10 */
1051 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1052 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1053 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1054 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1055 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1057 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1058 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1059 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1062 static void pxafb_disable_controller(struct pxafb_info *fbi)
1066 #ifdef CONFIG_FB_PXA_SMARTPANEL
1067 if (fbi->lccr0 & LCCR0_LCDT) {
1068 wait_for_completion_timeout(&fbi->refresh_done,
1074 /* Clear LCD Status Register */
1075 lcd_writel(fbi, LCSR, 0xffffffff);
1077 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1078 lcd_writel(fbi, LCCR0, lccr0);
1079 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1081 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1083 /* disable LCD controller clock */
1084 clk_disable(fbi->clk);
1088 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1090 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1092 struct pxafb_info *fbi = dev_id;
1093 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1095 if (lcsr & LCSR_LDD) {
1096 lccr0 = lcd_readl(fbi, LCCR0);
1097 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1098 complete(&fbi->disable_done);
1101 #ifdef CONFIG_FB_PXA_SMARTPANEL
1102 if (lcsr & LCSR_CMD_INT)
1103 complete(&fbi->command_done);
1106 lcd_writel(fbi, LCSR, lcsr);
1111 * This function must be called from task context only, since it will
1112 * sleep when disabling the LCD controller, or if we get two contending
1113 * processes trying to alter state.
1115 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1119 mutex_lock(&fbi->ctrlr_lock);
1121 old_state = fbi->state;
1124 * Hack around fbcon initialisation.
1126 if (old_state == C_STARTUP && state == C_REENABLE)
1130 case C_DISABLE_CLKCHANGE:
1132 * Disable controller for clock change. If the
1133 * controller is already disabled, then do nothing.
1135 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1137 /* TODO __pxafb_lcd_power(fbi, 0); */
1138 pxafb_disable_controller(fbi);
1145 * Disable controller
1147 if (old_state != C_DISABLE) {
1149 __pxafb_backlight_power(fbi, 0);
1150 __pxafb_lcd_power(fbi, 0);
1151 if (old_state != C_DISABLE_CLKCHANGE)
1152 pxafb_disable_controller(fbi);
1156 case C_ENABLE_CLKCHANGE:
1158 * Enable the controller after clock change. Only
1159 * do this if we were disabled for the clock change.
1161 if (old_state == C_DISABLE_CLKCHANGE) {
1162 fbi->state = C_ENABLE;
1163 pxafb_enable_controller(fbi);
1164 /* TODO __pxafb_lcd_power(fbi, 1); */
1170 * Re-enable the controller only if it was already
1171 * enabled. This is so we reprogram the control
1174 if (old_state == C_ENABLE) {
1175 __pxafb_lcd_power(fbi, 0);
1176 pxafb_disable_controller(fbi);
1177 pxafb_enable_controller(fbi);
1178 __pxafb_lcd_power(fbi, 1);
1184 * Re-enable the controller after PM. This is not
1185 * perfect - think about the case where we were doing
1186 * a clock change, and we suspended half-way through.
1188 if (old_state != C_DISABLE_PM)
1194 * Power up the LCD screen, enable controller, and
1195 * turn on the backlight.
1197 if (old_state != C_ENABLE) {
1198 fbi->state = C_ENABLE;
1199 pxafb_enable_controller(fbi);
1200 __pxafb_lcd_power(fbi, 1);
1201 __pxafb_backlight_power(fbi, 1);
1205 mutex_unlock(&fbi->ctrlr_lock);
1209 * Our LCD controller task (which is called when we blank or unblank)
1212 static void pxafb_task(struct work_struct *work)
1214 struct pxafb_info *fbi =
1215 container_of(work, struct pxafb_info, task);
1216 u_int state = xchg(&fbi->task_state, -1);
1218 set_ctrlr_state(fbi, state);
1221 #ifdef CONFIG_CPU_FREQ
1223 * CPU clock speed change handler. We need to adjust the LCD timing
1224 * parameters when the CPU clock is adjusted by the power management
1227 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1230 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1232 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1233 /* TODO struct cpufreq_freqs *f = data; */
1237 case CPUFREQ_PRECHANGE:
1238 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1241 case CPUFREQ_POSTCHANGE:
1242 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1243 set_hsync_time(fbi, pcd);
1244 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1245 LCCR3_PixClkDiv(pcd);
1246 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1253 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1255 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1256 struct fb_var_screeninfo *var = &fbi->fb.var;
1257 struct cpufreq_policy *policy = data;
1260 case CPUFREQ_ADJUST:
1261 case CPUFREQ_INCOMPATIBLE:
1262 pr_debug("min dma period: %d ps, "
1263 "new clock %d kHz\n", pxafb_display_dma_period(var),
1265 /* TODO: fill in min/max values */
1274 * Power management hooks. Note that we won't be called from IRQ context,
1275 * unlike the blank functions above, so we may sleep.
1277 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1279 struct pxafb_info *fbi = platform_get_drvdata(dev);
1281 set_ctrlr_state(fbi, C_DISABLE_PM);
1285 static int pxafb_resume(struct platform_device *dev)
1287 struct pxafb_info *fbi = platform_get_drvdata(dev);
1289 set_ctrlr_state(fbi, C_ENABLE_PM);
1293 #define pxafb_suspend NULL
1294 #define pxafb_resume NULL
1297 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1299 int size = PAGE_ALIGN(fbi->video_mem_size);
1301 fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1302 if (fbi->video_mem == NULL)
1305 fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1306 fbi->video_mem_size = size;
1308 fbi->fb.fix.smem_start = fbi->video_mem_phys;
1309 fbi->fb.fix.smem_len = fbi->video_mem_size;
1310 fbi->fb.screen_base = fbi->video_mem;
1312 return fbi->video_mem ? 0 : -ENOMEM;
1315 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1316 struct pxafb_mach_info *inf)
1318 unsigned int lcd_conn = inf->lcd_conn;
1319 struct pxafb_mode_info *m;
1322 fbi->cmap_inverse = inf->cmap_inverse;
1323 fbi->cmap_static = inf->cmap_static;
1324 fbi->lccr4 = inf->lccr4;
1326 switch (lcd_conn & LCD_TYPE_MASK) {
1327 case LCD_TYPE_MONO_STN:
1328 fbi->lccr0 = LCCR0_CMS;
1330 case LCD_TYPE_MONO_DSTN:
1331 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1333 case LCD_TYPE_COLOR_STN:
1336 case LCD_TYPE_COLOR_DSTN:
1337 fbi->lccr0 = LCCR0_SDS;
1339 case LCD_TYPE_COLOR_TFT:
1340 fbi->lccr0 = LCCR0_PAS;
1342 case LCD_TYPE_SMART_PANEL:
1343 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1346 /* fall back to backward compatibility way */
1347 fbi->lccr0 = inf->lccr0;
1348 fbi->lccr3 = inf->lccr3;
1352 if (lcd_conn == LCD_MONO_STN_8BPP)
1353 fbi->lccr0 |= LCCR0_DPD;
1355 fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1357 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1358 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1359 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1362 pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1364 /* decide video memory size as follows:
1365 * 1. default to mode of maximum resolution
1366 * 2. allow platform to override
1367 * 3. allow module parameter to override
1369 for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1370 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1371 m->xres * m->yres * m->bpp / 8);
1373 if (inf->video_mem_size > fbi->video_mem_size)
1374 fbi->video_mem_size = inf->video_mem_size;
1376 if (video_mem_size > fbi->video_mem_size)
1377 fbi->video_mem_size = video_mem_size;
1380 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1382 struct pxafb_info *fbi;
1384 struct pxafb_mach_info *inf = dev->platform_data;
1386 /* Alloc the pxafb_info and pseudo_palette in one step */
1387 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1391 memset(fbi, 0, sizeof(struct pxafb_info));
1394 fbi->clk = clk_get(dev, "LCDCLK");
1395 if (IS_ERR(fbi->clk)) {
1400 strcpy(fbi->fb.fix.id, PXA_NAME);
1402 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1403 fbi->fb.fix.type_aux = 0;
1404 fbi->fb.fix.xpanstep = 0;
1405 fbi->fb.fix.ypanstep = 1;
1406 fbi->fb.fix.ywrapstep = 0;
1407 fbi->fb.fix.accel = FB_ACCEL_NONE;
1409 fbi->fb.var.nonstd = 0;
1410 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1411 fbi->fb.var.height = -1;
1412 fbi->fb.var.width = -1;
1413 fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1414 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1416 fbi->fb.fbops = &pxafb_ops;
1417 fbi->fb.flags = FBINFO_DEFAULT;
1421 addr = addr + sizeof(struct pxafb_info);
1422 fbi->fb.pseudo_palette = addr;
1424 fbi->state = C_STARTUP;
1425 fbi->task_state = (u_char)-1;
1427 pxafb_decode_mach_info(fbi, inf);
1429 init_waitqueue_head(&fbi->ctrlr_wait);
1430 INIT_WORK(&fbi->task, pxafb_task);
1431 mutex_init(&fbi->ctrlr_lock);
1432 init_completion(&fbi->disable_done);
1437 #ifdef CONFIG_FB_PXA_PARAMETERS
1438 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1440 struct pxafb_mach_info *inf = dev->platform_data;
1442 const char *name = this_opt+5;
1443 unsigned int namelen = strlen(name);
1444 int res_specified = 0, bpp_specified = 0;
1445 unsigned int xres = 0, yres = 0, bpp = 0;
1446 int yres_specified = 0;
1448 for (i = namelen-1; i >= 0; i--) {
1452 if (!bpp_specified && !yres_specified) {
1453 bpp = simple_strtoul(&name[i+1], NULL, 0);
1459 if (!yres_specified) {
1460 yres = simple_strtoul(&name[i+1], NULL, 0);
1471 if (i < 0 && yres_specified) {
1472 xres = simple_strtoul(name, NULL, 0);
1476 if (res_specified) {
1477 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1478 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1487 inf->modes[0].bpp = bpp;
1488 dev_info(dev, "overriding bit depth: %d\n", bpp);
1491 dev_err(dev, "Depth %d is not valid\n", bpp);
1497 static int __devinit parse_opt(struct device *dev, char *this_opt)
1499 struct pxafb_mach_info *inf = dev->platform_data;
1500 struct pxafb_mode_info *mode = &inf->modes[0];
1505 if (!strncmp(this_opt, "vmem:", 5)) {
1506 video_mem_size = memparse(this_opt + 5, NULL);
1507 } else if (!strncmp(this_opt, "mode:", 5)) {
1508 return parse_opt_mode(dev, this_opt);
1509 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1510 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1511 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1512 } else if (!strncmp(this_opt, "left:", 5)) {
1513 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1514 sprintf(s, "left: %u\n", mode->left_margin);
1515 } else if (!strncmp(this_opt, "right:", 6)) {
1516 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1517 sprintf(s, "right: %u\n", mode->right_margin);
1518 } else if (!strncmp(this_opt, "upper:", 6)) {
1519 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1520 sprintf(s, "upper: %u\n", mode->upper_margin);
1521 } else if (!strncmp(this_opt, "lower:", 6)) {
1522 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1523 sprintf(s, "lower: %u\n", mode->lower_margin);
1524 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1525 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1526 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1527 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1528 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1529 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1530 } else if (!strncmp(this_opt, "hsync:", 6)) {
1531 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1532 sprintf(s, "hsync: Active Low\n");
1533 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1535 sprintf(s, "hsync: Active High\n");
1536 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1538 } else if (!strncmp(this_opt, "vsync:", 6)) {
1539 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1540 sprintf(s, "vsync: Active Low\n");
1541 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1543 sprintf(s, "vsync: Active High\n");
1544 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1546 } else if (!strncmp(this_opt, "dpc:", 4)) {
1547 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1548 sprintf(s, "double pixel clock: false\n");
1549 inf->lccr3 &= ~LCCR3_DPC;
1551 sprintf(s, "double pixel clock: true\n");
1552 inf->lccr3 |= LCCR3_DPC;
1554 } else if (!strncmp(this_opt, "outputen:", 9)) {
1555 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1556 sprintf(s, "output enable: active low\n");
1557 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1559 sprintf(s, "output enable: active high\n");
1560 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1562 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1563 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1564 sprintf(s, "pixel clock polarity: falling edge\n");
1565 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1567 sprintf(s, "pixel clock polarity: rising edge\n");
1568 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1570 } else if (!strncmp(this_opt, "color", 5)) {
1571 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1572 } else if (!strncmp(this_opt, "mono", 4)) {
1573 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1574 } else if (!strncmp(this_opt, "active", 6)) {
1575 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1576 } else if (!strncmp(this_opt, "passive", 7)) {
1577 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1578 } else if (!strncmp(this_opt, "single", 6)) {
1579 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1580 } else if (!strncmp(this_opt, "dual", 4)) {
1581 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1582 } else if (!strncmp(this_opt, "4pix", 4)) {
1583 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1584 } else if (!strncmp(this_opt, "8pix", 4)) {
1585 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1587 dev_err(dev, "unknown option: %s\n", this_opt);
1592 dev_info(dev, "override %s", s);
1597 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1602 if (!options || !*options)
1605 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1607 /* could be made table driven or similar?... */
1608 while ((this_opt = strsep(&options, ",")) != NULL) {
1609 ret = parse_opt(dev, this_opt);
1616 static char g_options[256] __devinitdata = "";
1619 static int __init pxafb_setup_options(void)
1621 char *options = NULL;
1623 if (fb_get_options("pxafb", &options))
1627 strlcpy(g_options, options, sizeof(g_options));
1632 #define pxafb_setup_options() (0)
1634 module_param_string(options, g_options, sizeof(g_options), 0);
1635 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1639 #define pxafb_parse_options(...) (0)
1640 #define pxafb_setup_options() (0)
1644 /* Check for various illegal bit-combinations. Currently only
1645 * a warning is given. */
1646 static void __devinit pxafb_check_options(struct device *dev,
1647 struct pxafb_mach_info *inf)
1652 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1653 dev_warn(dev, "machine LCCR0 setting contains "
1654 "illegal bits: %08x\n",
1655 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1656 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1657 dev_warn(dev, "machine LCCR3 setting contains "
1658 "illegal bits: %08x\n",
1659 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1660 if (inf->lccr0 & LCCR0_DPD &&
1661 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1662 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1663 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1664 dev_warn(dev, "Double Pixel Data (DPD) mode is "
1665 "only valid in passive mono"
1666 " single panel mode\n");
1667 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1668 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1669 dev_warn(dev, "Dual panel only valid in passive mode\n");
1670 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1671 (inf->modes->upper_margin || inf->modes->lower_margin))
1672 dev_warn(dev, "Upper and lower margins must be 0 in "
1676 #define pxafb_check_options(...) do {} while (0)
1679 static int __devinit pxafb_probe(struct platform_device *dev)
1681 struct pxafb_info *fbi;
1682 struct pxafb_mach_info *inf;
1686 dev_dbg(&dev->dev, "pxafb_probe\n");
1688 inf = dev->dev.platform_data;
1694 ret = pxafb_parse_options(&dev->dev, g_options);
1698 pxafb_check_options(&dev->dev, inf);
1700 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1704 if (inf->modes->xres == 0 ||
1705 inf->modes->yres == 0 ||
1706 inf->modes->bpp == 0) {
1707 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1712 fbi = pxafb_init_fbinfo(&dev->dev);
1714 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1715 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1720 fbi->backlight_power = inf->pxafb_backlight_power;
1721 fbi->lcd_power = inf->pxafb_lcd_power;
1723 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1725 dev_err(&dev->dev, "no I/O memory resource defined\n");
1730 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1732 dev_err(&dev->dev, "failed to request I/O memory\n");
1737 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1738 if (fbi->mmio_base == NULL) {
1739 dev_err(&dev->dev, "failed to map I/O memory\n");
1741 goto failed_free_res;
1744 fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1745 fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
1746 &fbi->dma_buff_phys, GFP_KERNEL);
1747 if (fbi->dma_buff == NULL) {
1748 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
1750 goto failed_free_io;
1753 ret = pxafb_init_video_memory(fbi);
1755 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1757 goto failed_free_dma;
1760 irq = platform_get_irq(dev, 0);
1762 dev_err(&dev->dev, "no IRQ defined\n");
1764 goto failed_free_mem;
1767 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1769 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1771 goto failed_free_mem;
1774 ret = pxafb_smart_init(fbi);
1776 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1777 goto failed_free_irq;
1781 * This makes sure that our colour bitfield
1782 * descriptors are correctly initialised.
1784 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1786 dev_err(&dev->dev, "failed to get suitable mode\n");
1787 goto failed_free_irq;
1790 ret = pxafb_set_par(&fbi->fb);
1792 dev_err(&dev->dev, "Failed to set parameters\n");
1793 goto failed_free_irq;
1796 platform_set_drvdata(dev, fbi);
1798 ret = register_framebuffer(&fbi->fb);
1801 "Failed to register framebuffer device: %d\n", ret);
1802 goto failed_free_cmap;
1805 #ifdef CONFIG_CPU_FREQ
1806 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1807 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1808 cpufreq_register_notifier(&fbi->freq_transition,
1809 CPUFREQ_TRANSITION_NOTIFIER);
1810 cpufreq_register_notifier(&fbi->freq_policy,
1811 CPUFREQ_POLICY_NOTIFIER);
1815 * Ok, now enable the LCD controller
1817 set_ctrlr_state(fbi, C_ENABLE);
1822 if (fbi->fb.cmap.len)
1823 fb_dealloc_cmap(&fbi->fb.cmap);
1827 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1829 dma_free_coherent(&dev->dev, fbi->dma_buff_size,
1830 fbi->dma_buff, fbi->dma_buff_phys);
1832 iounmap(fbi->mmio_base);
1834 release_mem_region(r->start, r->end - r->start + 1);
1837 platform_set_drvdata(dev, NULL);
1843 static int __devexit pxafb_remove(struct platform_device *dev)
1845 struct pxafb_info *fbi = platform_get_drvdata(dev);
1848 struct fb_info *info;
1855 unregister_framebuffer(info);
1857 pxafb_disable_controller(fbi);
1859 if (fbi->fb.cmap.len)
1860 fb_dealloc_cmap(&fbi->fb.cmap);
1862 irq = platform_get_irq(dev, 0);
1865 free_pages_exact(fbi->video_mem, fbi->video_mem_size);
1867 dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
1868 fbi->dma_buff, fbi->dma_buff_phys);
1870 iounmap(fbi->mmio_base);
1872 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1873 release_mem_region(r->start, r->end - r->start + 1);
1881 static struct platform_driver pxafb_driver = {
1882 .probe = pxafb_probe,
1883 .remove = pxafb_remove,
1884 .suspend = pxafb_suspend,
1885 .resume = pxafb_resume,
1887 .owner = THIS_MODULE,
1888 .name = "pxa2xx-fb",
1892 static int __init pxafb_init(void)
1894 if (pxafb_setup_options())
1897 return platform_driver_register(&pxafb_driver);
1900 static void __exit pxafb_exit(void)
1902 platform_driver_unregister(&pxafb_driver);
1905 module_init(pxafb_init);
1906 module_exit(pxafb_exit);
1908 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1909 MODULE_LICENSE("GPL");