2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/ioport.h>
37 #include <linux/cpufreq.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/err.h>
43 #include <asm/hardware.h>
46 #include <asm/div64.h>
47 #include <asm/arch/pxa-regs.h>
48 #include <asm/arch/pxa2xx-gpio.h>
49 #include <asm/arch/bitfield.h>
50 #include <asm/arch/pxafb.h>
53 * Complain if VAR is out of range.
59 /* Bits which should not be set in machine configuration structures */
60 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
61 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
62 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
64 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
65 LCCR3_PCD | LCCR3_BPP)
67 static void (*pxafb_backlight_power)(int);
68 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
70 static int pxafb_activate_var(struct fb_var_screeninfo *var,
72 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
74 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
78 local_irq_save(flags);
80 * We need to handle two requests being made at the same time.
81 * There are two important cases:
82 * 1. When we are changing VT (C_REENABLE) while unblanking
83 * (C_ENABLE) We must perform the unblanking, which will
84 * do our REENABLE for us.
85 * 2. When we are blanking, but immediately unblank before
86 * we have blanked. We do the "REENABLE" thing here as
87 * well, just to be sure.
89 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
91 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
94 if (state != (u_int)-1) {
95 fbi->task_state = state;
96 schedule_work(&fbi->task);
98 local_irq_restore(flags);
101 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
104 chan >>= 16 - bf->length;
105 return chan << bf->offset;
109 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
110 u_int trans, struct fb_info *info)
112 struct pxafb_info *fbi = (struct pxafb_info *)info;
115 if (regno >= fbi->palette_size)
118 if (fbi->fb.var.grayscale) {
119 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
123 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
124 case LCCR4_PAL_FOR_0:
125 val = ((red >> 0) & 0xf800);
126 val |= ((green >> 5) & 0x07e0);
127 val |= ((blue >> 11) & 0x001f);
128 fbi->palette_cpu[regno] = val;
130 case LCCR4_PAL_FOR_1:
131 val = ((red << 8) & 0x00f80000);
132 val |= ((green >> 0) & 0x0000fc00);
133 val |= ((blue >> 8) & 0x000000f8);
134 ((u32 *)(fbi->palette_cpu))[regno] = val;
136 case LCCR4_PAL_FOR_2:
137 val = ((red << 8) & 0x00fc0000);
138 val |= ((green >> 0) & 0x0000fc00);
139 val |= ((blue >> 8) & 0x000000fc);
140 ((u32 *)(fbi->palette_cpu))[regno] = val;
148 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
149 u_int trans, struct fb_info *info)
151 struct pxafb_info *fbi = (struct pxafb_info *)info;
156 * If inverse mode was selected, invert all the colours
157 * rather than the register number. The register number
158 * is what you poke into the framebuffer to produce the
159 * colour you requested.
161 if (fbi->cmap_inverse) {
163 green = 0xffff - green;
164 blue = 0xffff - blue;
168 * If greyscale is true, then we convert the RGB value
169 * to greyscale no matter what visual we are using.
171 if (fbi->fb.var.grayscale)
172 red = green = blue = (19595 * red + 38470 * green +
175 switch (fbi->fb.fix.visual) {
176 case FB_VISUAL_TRUECOLOR:
178 * 16-bit True Colour. We encode the RGB value
179 * according to the RGB bitfield information.
182 u32 *pal = fbi->fb.pseudo_palette;
184 val = chan_to_field(red, &fbi->fb.var.red);
185 val |= chan_to_field(green, &fbi->fb.var.green);
186 val |= chan_to_field(blue, &fbi->fb.var.blue);
193 case FB_VISUAL_STATIC_PSEUDOCOLOR:
194 case FB_VISUAL_PSEUDOCOLOR:
195 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
203 * pxafb_bpp_to_lccr3():
204 * Convert a bits per pixel value to the correct bit pattern for LCCR3
206 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
209 switch (var->bits_per_pixel) {
210 case 1: ret = LCCR3_1BPP; break;
211 case 2: ret = LCCR3_2BPP; break;
212 case 4: ret = LCCR3_4BPP; break;
213 case 8: ret = LCCR3_8BPP; break;
214 case 16: ret = LCCR3_16BPP; break;
219 #ifdef CONFIG_CPU_FREQ
221 * pxafb_display_dma_period()
222 * Calculate the minimum period (in picoseconds) between two DMA
223 * requests for the LCD controller. If we hit this, it means we're
224 * doing nothing but LCD DMA.
226 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
229 * Period = pixclock * bits_per_byte * bytes_per_transfer
230 * / memory_bits_per_pixel;
232 return var->pixclock * 8 * 16 / var->bits_per_pixel;
237 * Select the smallest mode that allows the desired resolution to be
238 * displayed. If desired parameters can be rounded up.
240 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
241 struct fb_var_screeninfo *var)
243 struct pxafb_mode_info *mode = NULL;
244 struct pxafb_mode_info *modelist = mach->modes;
245 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
248 for (i = 0; i < mach->num_modes; i++) {
249 if (modelist[i].xres >= var->xres &&
250 modelist[i].yres >= var->yres &&
251 modelist[i].xres < best_x &&
252 modelist[i].yres < best_y &&
253 modelist[i].bpp >= var->bits_per_pixel) {
254 best_x = modelist[i].xres;
255 best_y = modelist[i].yres;
263 static void pxafb_setmode(struct fb_var_screeninfo *var,
264 struct pxafb_mode_info *mode)
266 var->xres = mode->xres;
267 var->yres = mode->yres;
268 var->bits_per_pixel = mode->bpp;
269 var->pixclock = mode->pixclock;
270 var->hsync_len = mode->hsync_len;
271 var->left_margin = mode->left_margin;
272 var->right_margin = mode->right_margin;
273 var->vsync_len = mode->vsync_len;
274 var->upper_margin = mode->upper_margin;
275 var->lower_margin = mode->lower_margin;
276 var->sync = mode->sync;
277 var->grayscale = mode->cmap_greyscale;
278 var->xres_virtual = var->xres;
279 var->yres_virtual = var->yres;
284 * Get the video params out of 'var'. If a value doesn't fit, round it up,
285 * if it's too big, return -EINVAL.
287 * Round up in the following order: bits_per_pixel, xres,
288 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
289 * bitfields, horizontal timing, vertical timing.
291 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
293 struct pxafb_info *fbi = (struct pxafb_info *)info;
294 struct pxafb_mach_info *inf = fbi->dev->platform_data;
296 if (var->xres < MIN_XRES)
297 var->xres = MIN_XRES;
298 if (var->yres < MIN_YRES)
299 var->yres = MIN_YRES;
301 if (inf->fixed_modes) {
302 struct pxafb_mode_info *mode;
304 mode = pxafb_getmode(inf, var);
307 pxafb_setmode(var, mode);
309 if (var->xres > inf->modes->xres)
311 if (var->yres > inf->modes->yres)
313 if (var->bits_per_pixel > inf->modes->bpp)
318 max(var->xres_virtual, var->xres);
320 max(var->yres_virtual, var->yres);
323 * Setup the RGB parameters for this display.
325 * The pixel packing format is described on page 7-11 of the
326 * PXA2XX Developer's Manual.
328 if (var->bits_per_pixel == 16) {
329 var->red.offset = 11; var->red.length = 5;
330 var->green.offset = 5; var->green.length = 6;
331 var->blue.offset = 0; var->blue.length = 5;
332 var->transp.offset = var->transp.length = 0;
334 var->red.offset = var->green.offset = 0;
335 var->blue.offset = var->transp.offset = 0;
337 var->green.length = 8;
338 var->blue.length = 8;
339 var->transp.length = 0;
342 #ifdef CONFIG_CPU_FREQ
343 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
344 pxafb_display_dma_period(var),
345 get_clk_frequency_khz(0));
351 static inline void pxafb_set_truecolor(u_int is_true_color)
353 /* do your machine-specific setup if needed */
358 * Set the user defined part of the display for the specified console
360 static int pxafb_set_par(struct fb_info *info)
362 struct pxafb_info *fbi = (struct pxafb_info *)info;
363 struct fb_var_screeninfo *var = &info->var;
364 unsigned long palette_mem_size;
366 if (var->bits_per_pixel == 16)
367 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
368 else if (!fbi->cmap_static)
369 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
372 * Some people have weird ideas about wanting static
373 * pseudocolor maps. I suspect their user space
374 * applications are broken.
376 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
379 fbi->fb.fix.line_length = var->xres_virtual *
380 var->bits_per_pixel / 8;
381 if (var->bits_per_pixel == 16)
382 fbi->palette_size = 0;
384 fbi->palette_size = var->bits_per_pixel == 1 ?
385 4 : 1 << var->bits_per_pixel;
387 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
388 palette_mem_size = fbi->palette_size * sizeof(u16);
390 palette_mem_size = fbi->palette_size * sizeof(u32);
392 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
393 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
396 * Set (any) board control register to handle new color depth
398 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
400 if (fbi->fb.var.bits_per_pixel == 16)
401 fb_dealloc_cmap(&fbi->fb.cmap);
403 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
405 pxafb_activate_var(var, fbi);
412 * Blank the display by setting all palette values to zero. Note, the
413 * 16 bpp mode does not really use the palette, so this will not
414 * blank the display in all modes.
416 static int pxafb_blank(int blank, struct fb_info *info)
418 struct pxafb_info *fbi = (struct pxafb_info *)info;
422 case FB_BLANK_POWERDOWN:
423 case FB_BLANK_VSYNC_SUSPEND:
424 case FB_BLANK_HSYNC_SUSPEND:
425 case FB_BLANK_NORMAL:
426 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
427 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
428 for (i = 0; i < fbi->palette_size; i++)
429 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
431 pxafb_schedule_work(fbi, C_DISABLE);
432 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
435 case FB_BLANK_UNBLANK:
436 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
437 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
438 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
439 fb_set_cmap(&fbi->fb.cmap, info);
440 pxafb_schedule_work(fbi, C_ENABLE);
445 static int pxafb_mmap(struct fb_info *info,
446 struct vm_area_struct *vma)
448 struct pxafb_info *fbi = (struct pxafb_info *)info;
449 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
451 if (off < info->fix.smem_len) {
453 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
454 fbi->map_dma, fbi->map_size);
459 static struct fb_ops pxafb_ops = {
460 .owner = THIS_MODULE,
461 .fb_check_var = pxafb_check_var,
462 .fb_set_par = pxafb_set_par,
463 .fb_setcolreg = pxafb_setcolreg,
464 .fb_fillrect = cfb_fillrect,
465 .fb_copyarea = cfb_copyarea,
466 .fb_imageblit = cfb_imageblit,
467 .fb_blank = pxafb_blank,
468 .fb_mmap = pxafb_mmap,
472 * Calculate the PCD value from the clock rate (in picoseconds).
473 * We take account of the PPCR clock setting.
474 * From PXA Developer's Manual:
485 * LCLK = LCD/Memory Clock
488 * PixelClock here is in Hz while the pixclock argument given is the
489 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
491 * The function get_lclk_frequency_10khz returns LCLK in units of
492 * 10khz. Calling the result of this function lclk gives us the
495 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
496 * -------------------------------------- - 1
499 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
501 static inline unsigned int get_pcd(struct pxafb_info *fbi,
502 unsigned int pixclock)
504 unsigned long long pcd;
506 /* FIXME: Need to take into account Double Pixel Clock mode
507 * (DPC) bit? or perhaps set it based on the various clock
509 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
511 do_div(pcd, 100000000 * 2);
512 /* no need for this, since we should subtract 1 anyway. they cancel */
513 /* pcd += 1; */ /* make up for integer math truncations */
514 return (unsigned int)pcd;
518 * Some touchscreens need hsync information from the video driver to
519 * function correctly. We export it here. Note that 'hsync_time' and
520 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
521 * of the hsync period in seconds.
523 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
527 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
532 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
534 fbi->hsync_time = htime;
537 unsigned long pxafb_get_hsync_time(struct device *dev)
539 struct pxafb_info *fbi = dev_get_drvdata(dev);
541 /* If display is blanked/suspended, hsync isn't active */
542 if (!fbi || (fbi->state != C_ENABLE))
545 return fbi->hsync_time;
547 EXPORT_SYMBOL(pxafb_get_hsync_time);
550 * pxafb_activate_var():
551 * Configures LCD Controller based on entries in var parameter.
552 * Settings are only written to the controller if changes were made.
554 static int pxafb_activate_var(struct fb_var_screeninfo *var,
555 struct pxafb_info *fbi)
557 struct pxafb_lcd_reg new_regs;
559 u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
562 if (var->xres < 16 || var->xres > 1024)
563 printk(KERN_ERR "%s: invalid xres %d\n",
564 fbi->fb.fix.id, var->xres);
565 switch (var->bits_per_pixel) {
573 printk(KERN_ERR "%s: invalid bit depth %d\n",
574 fbi->fb.fix.id, var->bits_per_pixel);
577 if (var->hsync_len < 1 || var->hsync_len > 64)
578 printk(KERN_ERR "%s: invalid hsync_len %d\n",
579 fbi->fb.fix.id, var->hsync_len);
580 if (var->left_margin < 1 || var->left_margin > 255)
581 printk(KERN_ERR "%s: invalid left_margin %d\n",
582 fbi->fb.fix.id, var->left_margin);
583 if (var->right_margin < 1 || var->right_margin > 255)
584 printk(KERN_ERR "%s: invalid right_margin %d\n",
585 fbi->fb.fix.id, var->right_margin);
586 if (var->yres < 1 || var->yres > 1024)
587 printk(KERN_ERR "%s: invalid yres %d\n",
588 fbi->fb.fix.id, var->yres);
589 if (var->vsync_len < 1 || var->vsync_len > 64)
590 printk(KERN_ERR "%s: invalid vsync_len %d\n",
591 fbi->fb.fix.id, var->vsync_len);
592 if (var->upper_margin < 0 || var->upper_margin > 255)
593 printk(KERN_ERR "%s: invalid upper_margin %d\n",
594 fbi->fb.fix.id, var->upper_margin);
595 if (var->lower_margin < 0 || var->lower_margin > 255)
596 printk(KERN_ERR "%s: invalid lower_margin %d\n",
597 fbi->fb.fix.id, var->lower_margin);
600 new_regs.lccr0 = fbi->lccr0 |
601 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
602 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
605 LCCR1_DisWdth(var->xres) +
606 LCCR1_HorSnchWdth(var->hsync_len) +
607 LCCR1_BegLnDel(var->left_margin) +
608 LCCR1_EndLnDel(var->right_margin);
611 * If we have a dual scan LCD, we need to halve
612 * the YRES parameter.
614 lines_per_panel = var->yres;
615 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
616 lines_per_panel /= 2;
619 LCCR2_DisHght(lines_per_panel) +
620 LCCR2_VrtSnchWdth(var->vsync_len) +
621 LCCR2_BegFrmDel(var->upper_margin) +
622 LCCR2_EndFrmDel(var->lower_margin);
624 new_regs.lccr3 = fbi->lccr3 |
625 pxafb_bpp_to_lccr3(var) |
626 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
627 LCCR3_HorSnchH : LCCR3_HorSnchL) |
628 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
629 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
632 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
634 /* Update shadow copy atomically */
635 local_irq_save(flags);
637 /* setup dma descriptors */
638 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)
639 ((unsigned int)fbi->palette_cpu - 3*16);
640 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)
641 ((unsigned int)fbi->palette_cpu - 2*16);
642 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)
643 ((unsigned int)fbi->palette_cpu - 1*16);
645 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
646 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
647 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
649 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
651 /* populate descriptors */
652 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
653 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
654 fbi->dmadesc_fblow_cpu->fidr = 0;
655 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
657 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
659 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
660 fbi->dmadesc_fbhigh_cpu->fidr = 0;
661 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
663 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
664 fbi->dmadesc_palette_cpu->fidr = 0;
665 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
666 fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
669 fbi->dmadesc_palette_cpu->ldcmd = fbi->palette_size *
671 fbi->dmadesc_palette_cpu->ldcmd |= LDCMD_PAL;
673 if (var->bits_per_pixel == 16) {
674 /* palette shouldn't be loaded in true-color mode */
675 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
676 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
677 /* init it to something, even though we won't be using it */
678 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
680 /* flips back and forth between pal and fbhigh */
681 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
682 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
683 fbi->fdadr0 = fbi->dmadesc_palette_dma;
686 fbi->reg_lccr0 = new_regs.lccr0;
687 fbi->reg_lccr1 = new_regs.lccr1;
688 fbi->reg_lccr2 = new_regs.lccr2;
689 fbi->reg_lccr3 = new_regs.lccr3;
690 fbi->reg_lccr4 = LCCR4 & (~LCCR4_PAL_FOR_MASK);
691 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
692 set_hsync_time(fbi, pcd);
693 local_irq_restore(flags);
696 * Only update the registers if the controller is enabled
697 * and something has changed.
699 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
700 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
701 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
702 pxafb_schedule_work(fbi, C_REENABLE);
708 * NOTE! The following functions are purely helpers for set_ctrlr_state.
709 * Do not call them directly; set_ctrlr_state does the correct serialisation
710 * to ensure that things happen in the right way 100% of time time.
713 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
715 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
717 if (pxafb_backlight_power)
718 pxafb_backlight_power(on);
721 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
723 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
726 pxafb_lcd_power(on, &fbi->fb.var);
729 static void pxafb_setup_gpio(struct pxafb_info *fbi)
732 unsigned int lccr0 = fbi->lccr0;
735 * setup is based on type of panel supported
738 /* 4 bit interface */
739 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
740 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
741 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
744 /* 8 bit interface */
745 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
746 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
747 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
748 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
749 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
750 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
753 /* 16 bit interface */
754 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
755 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
756 (lccr0 & LCCR0_PAS) == LCCR0_Act))
760 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
765 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
766 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
767 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
768 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
769 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
770 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
773 static void pxafb_enable_controller(struct pxafb_info *fbi)
775 pr_debug("pxafb: Enabling LCD controller\n");
776 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
777 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
778 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
779 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
780 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
781 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
783 /* enable LCD controller clock */
784 clk_enable(fbi->clk);
786 /* Sequence from 11.7.10 */
787 LCCR3 = fbi->reg_lccr3;
788 LCCR2 = fbi->reg_lccr2;
789 LCCR1 = fbi->reg_lccr1;
790 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
792 FDADR0 = fbi->fdadr0;
793 FDADR1 = fbi->fdadr1;
797 static void pxafb_disable_controller(struct pxafb_info *fbi)
799 DECLARE_WAITQUEUE(wait, current);
801 set_current_state(TASK_UNINTERRUPTIBLE);
802 add_wait_queue(&fbi->ctrlr_wait, &wait);
804 LCSR = 0xffffffff; /* Clear LCD Status Register */
805 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
806 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
808 schedule_timeout(200 * HZ / 1000);
809 remove_wait_queue(&fbi->ctrlr_wait, &wait);
811 /* disable LCD controller clock */
812 clk_disable(fbi->clk);
816 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
818 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
820 struct pxafb_info *fbi = dev_id;
821 unsigned int lcsr = LCSR;
823 if (lcsr & LCSR_LDD) {
825 wake_up(&fbi->ctrlr_wait);
833 * This function must be called from task context only, since it will
834 * sleep when disabling the LCD controller, or if we get two contending
835 * processes trying to alter state.
837 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
841 down(&fbi->ctrlr_sem);
843 old_state = fbi->state;
846 * Hack around fbcon initialisation.
848 if (old_state == C_STARTUP && state == C_REENABLE)
852 case C_DISABLE_CLKCHANGE:
854 * Disable controller for clock change. If the
855 * controller is already disabled, then do nothing.
857 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
859 /* TODO __pxafb_lcd_power(fbi, 0); */
860 pxafb_disable_controller(fbi);
869 if (old_state != C_DISABLE) {
871 __pxafb_backlight_power(fbi, 0);
872 __pxafb_lcd_power(fbi, 0);
873 if (old_state != C_DISABLE_CLKCHANGE)
874 pxafb_disable_controller(fbi);
878 case C_ENABLE_CLKCHANGE:
880 * Enable the controller after clock change. Only
881 * do this if we were disabled for the clock change.
883 if (old_state == C_DISABLE_CLKCHANGE) {
884 fbi->state = C_ENABLE;
885 pxafb_enable_controller(fbi);
886 /* TODO __pxafb_lcd_power(fbi, 1); */
892 * Re-enable the controller only if it was already
893 * enabled. This is so we reprogram the control
896 if (old_state == C_ENABLE) {
897 __pxafb_lcd_power(fbi, 0);
898 pxafb_disable_controller(fbi);
899 pxafb_setup_gpio(fbi);
900 pxafb_enable_controller(fbi);
901 __pxafb_lcd_power(fbi, 1);
907 * Re-enable the controller after PM. This is not
908 * perfect - think about the case where we were doing
909 * a clock change, and we suspended half-way through.
911 if (old_state != C_DISABLE_PM)
917 * Power up the LCD screen, enable controller, and
918 * turn on the backlight.
920 if (old_state != C_ENABLE) {
921 fbi->state = C_ENABLE;
922 pxafb_setup_gpio(fbi);
923 pxafb_enable_controller(fbi);
924 __pxafb_lcd_power(fbi, 1);
925 __pxafb_backlight_power(fbi, 1);
933 * Our LCD controller task (which is called when we blank or unblank)
936 static void pxafb_task(struct work_struct *work)
938 struct pxafb_info *fbi =
939 container_of(work, struct pxafb_info, task);
940 u_int state = xchg(&fbi->task_state, -1);
942 set_ctrlr_state(fbi, state);
945 #ifdef CONFIG_CPU_FREQ
947 * CPU clock speed change handler. We need to adjust the LCD timing
948 * parameters when the CPU clock is adjusted by the power management
951 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
954 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
956 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
957 /* TODO struct cpufreq_freqs *f = data; */
961 case CPUFREQ_PRECHANGE:
962 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
965 case CPUFREQ_POSTCHANGE:
966 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
967 set_hsync_time(fbi, pcd);
968 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
969 LCCR3_PixClkDiv(pcd);
970 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
977 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
979 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
980 struct fb_var_screeninfo *var = &fbi->fb.var;
981 struct cpufreq_policy *policy = data;
985 case CPUFREQ_INCOMPATIBLE:
986 pr_debug("min dma period: %d ps, "
987 "new clock %d kHz\n", pxafb_display_dma_period(var),
989 /* TODO: fill in min/max values */
998 * Power management hooks. Note that we won't be called from IRQ context,
999 * unlike the blank functions above, so we may sleep.
1001 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1003 struct pxafb_info *fbi = platform_get_drvdata(dev);
1005 set_ctrlr_state(fbi, C_DISABLE_PM);
1009 static int pxafb_resume(struct platform_device *dev)
1011 struct pxafb_info *fbi = platform_get_drvdata(dev);
1013 set_ctrlr_state(fbi, C_ENABLE_PM);
1017 #define pxafb_suspend NULL
1018 #define pxafb_resume NULL
1022 * pxafb_map_video_memory():
1023 * Allocates the DRAM memory for the frame buffer. This buffer is
1024 * remapped into a non-cached, non-buffered, memory region to
1025 * allow palette and pixel writes to occur without flushing the
1026 * cache. Once this area is remapped, all virtual memory
1027 * access to the video memory should occur at the new region.
1029 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1031 u_long palette_mem_size;
1034 * We reserve one page for the palette, plus the size
1035 * of the framebuffer.
1037 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
1038 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1039 &fbi->map_dma, GFP_KERNEL);
1042 /* prevent initial garbage on screen */
1043 memset(fbi->map_cpu, 0, fbi->map_size);
1044 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
1045 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
1047 * FIXME: this is actually the wrong thing to place in
1048 * smem_start. But fbdev suffers from the problem that
1049 * it needs an API which doesn't exist (in this case,
1050 * dma_writecombine_mmap)
1052 fbi->fb.fix.smem_start = fbi->screen_dma;
1053 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1055 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1056 palette_mem_size = fbi->palette_size * sizeof(u16);
1058 palette_mem_size = fbi->palette_size * sizeof(u32);
1060 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE
1061 - palette_mem_size);
1062 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1065 return fbi->map_cpu ? 0 : -ENOMEM;
1068 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1070 struct pxafb_info *fbi;
1072 struct pxafb_mach_info *inf = dev->platform_data;
1073 struct pxafb_mode_info *mode = inf->modes;
1076 /* Alloc the pxafb_info and pseudo_palette in one step */
1077 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1081 memset(fbi, 0, sizeof(struct pxafb_info));
1084 fbi->clk = clk_get(dev, "LCDCLK");
1085 if (IS_ERR(fbi->clk)) {
1090 strcpy(fbi->fb.fix.id, PXA_NAME);
1092 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1093 fbi->fb.fix.type_aux = 0;
1094 fbi->fb.fix.xpanstep = 0;
1095 fbi->fb.fix.ypanstep = 0;
1096 fbi->fb.fix.ywrapstep = 0;
1097 fbi->fb.fix.accel = FB_ACCEL_NONE;
1099 fbi->fb.var.nonstd = 0;
1100 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1101 fbi->fb.var.height = -1;
1102 fbi->fb.var.width = -1;
1103 fbi->fb.var.accel_flags = 0;
1104 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1106 fbi->fb.fbops = &pxafb_ops;
1107 fbi->fb.flags = FBINFO_DEFAULT;
1111 addr = addr + sizeof(struct pxafb_info);
1112 fbi->fb.pseudo_palette = addr;
1114 pxafb_setmode(&fbi->fb.var, mode);
1116 fbi->cmap_inverse = inf->cmap_inverse;
1117 fbi->cmap_static = inf->cmap_static;
1119 fbi->lccr0 = inf->lccr0;
1120 fbi->lccr3 = inf->lccr3;
1121 fbi->lccr4 = inf->lccr4;
1122 fbi->state = C_STARTUP;
1123 fbi->task_state = (u_char)-1;
1125 for (i = 0; i < inf->num_modes; i++) {
1126 smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8;
1127 if (smemlen > fbi->fb.fix.smem_len)
1128 fbi->fb.fix.smem_len = smemlen;
1131 init_waitqueue_head(&fbi->ctrlr_wait);
1132 INIT_WORK(&fbi->task, pxafb_task);
1133 init_MUTEX(&fbi->ctrlr_sem);
1138 #ifdef CONFIG_FB_PXA_PARAMETERS
1139 static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1141 struct pxafb_mach_info *inf = dev->platform_data;
1143 const char *name = this_opt+5;
1144 unsigned int namelen = strlen(name);
1145 int res_specified = 0, bpp_specified = 0;
1146 unsigned int xres = 0, yres = 0, bpp = 0;
1147 int yres_specified = 0;
1149 for (i = namelen-1; i >= 0; i--) {
1153 if (!bpp_specified && !yres_specified) {
1154 bpp = simple_strtoul(&name[i+1], NULL, 0);
1160 if (!yres_specified) {
1161 yres = simple_strtoul(&name[i+1], NULL, 0);
1172 if (i < 0 && yres_specified) {
1173 xres = simple_strtoul(name, NULL, 0);
1177 if (res_specified) {
1178 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1179 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1188 inf->modes[0].bpp = bpp;
1189 dev_info(dev, "overriding bit depth: %d\n", bpp);
1192 dev_err(dev, "Depth %d is not valid\n", bpp);
1198 static int __init parse_opt(struct device *dev, char *this_opt)
1200 struct pxafb_mach_info *inf = dev->platform_data;
1201 struct pxafb_mode_info *mode = &inf->modes[0];
1206 if (!strncmp(this_opt, "mode:", 5)) {
1207 return parse_opt_mode(dev, this_opt);
1208 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1209 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1210 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1211 } else if (!strncmp(this_opt, "left:", 5)) {
1212 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1213 sprintf(s, "left: %u\n", mode->left_margin);
1214 } else if (!strncmp(this_opt, "right:", 6)) {
1215 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1216 sprintf(s, "right: %u\n", mode->right_margin);
1217 } else if (!strncmp(this_opt, "upper:", 6)) {
1218 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1219 sprintf(s, "upper: %u\n", mode->upper_margin);
1220 } else if (!strncmp(this_opt, "lower:", 6)) {
1221 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1222 sprintf(s, "lower: %u\n", mode->lower_margin);
1223 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1224 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1225 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1226 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1227 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1228 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1229 } else if (!strncmp(this_opt, "hsync:", 6)) {
1230 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1231 sprintf(s, "hsync: Active Low\n");
1232 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1234 sprintf(s, "hsync: Active High\n");
1235 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1237 } else if (!strncmp(this_opt, "vsync:", 6)) {
1238 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1239 sprintf(s, "vsync: Active Low\n");
1240 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1242 sprintf(s, "vsync: Active High\n");
1243 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1245 } else if (!strncmp(this_opt, "dpc:", 4)) {
1246 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1247 sprintf(s, "double pixel clock: false\n");
1248 inf->lccr3 &= ~LCCR3_DPC;
1250 sprintf(s, "double pixel clock: true\n");
1251 inf->lccr3 |= LCCR3_DPC;
1253 } else if (!strncmp(this_opt, "outputen:", 9)) {
1254 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1255 sprintf(s, "output enable: active low\n");
1256 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1258 sprintf(s, "output enable: active high\n");
1259 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1261 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1262 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1263 sprintf(s, "pixel clock polarity: falling edge\n");
1264 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1266 sprintf(s, "pixel clock polarity: rising edge\n");
1267 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1269 } else if (!strncmp(this_opt, "color", 5)) {
1270 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1271 } else if (!strncmp(this_opt, "mono", 4)) {
1272 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1273 } else if (!strncmp(this_opt, "active", 6)) {
1274 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1275 } else if (!strncmp(this_opt, "passive", 7)) {
1276 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1277 } else if (!strncmp(this_opt, "single", 6)) {
1278 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1279 } else if (!strncmp(this_opt, "dual", 4)) {
1280 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1281 } else if (!strncmp(this_opt, "4pix", 4)) {
1282 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1283 } else if (!strncmp(this_opt, "8pix", 4)) {
1284 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1286 dev_err(dev, "unknown option: %s\n", this_opt);
1291 dev_info(dev, "override %s", s);
1296 static int __init pxafb_parse_options(struct device *dev, char *options)
1301 if (!options || !*options)
1304 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1306 /* could be made table driven or similar?... */
1307 while ((this_opt = strsep(&options, ",")) != NULL) {
1308 ret = parse_opt(dev, this_opt);
1315 static char g_options[256] __devinitdata = "";
1317 #ifndef CONFIG_MODULES
1318 static int __devinit pxafb_setup_options(void)
1320 char *options = NULL;
1322 if (fb_get_options("pxafb", &options))
1326 strlcpy(g_options, options, sizeof(g_options));
1331 #define pxafb_setup_options() (0)
1333 module_param_string(options, g_options, sizeof(g_options), 0);
1334 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1338 #define pxafb_parse_options(...) (0)
1339 #define pxafb_setup_options() (0)
1342 static int __init pxafb_probe(struct platform_device *dev)
1344 struct pxafb_info *fbi;
1345 struct pxafb_mach_info *inf;
1348 dev_dbg(&dev->dev, "pxafb_probe\n");
1350 inf = dev->dev.platform_data;
1356 ret = pxafb_parse_options(&dev->dev, g_options);
1361 /* Check for various illegal bit-combinations. Currently only
1362 * a warning is given. */
1364 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1365 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1366 "illegal bits: %08x\n",
1367 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1368 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1369 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1370 "illegal bits: %08x\n",
1371 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1372 if (inf->lccr0 & LCCR0_DPD &&
1373 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1374 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1375 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1376 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1377 "only valid in passive mono"
1378 " single panel mode\n");
1379 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1380 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1381 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1382 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1383 (inf->modes->upper_margin || inf->modes->lower_margin))
1384 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1388 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1392 if (inf->modes->xres == 0 ||
1393 inf->modes->yres == 0 ||
1394 inf->modes->bpp == 0) {
1395 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1399 pxafb_backlight_power = inf->pxafb_backlight_power;
1400 pxafb_lcd_power = inf->pxafb_lcd_power;
1401 fbi = pxafb_init_fbinfo(&dev->dev);
1403 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1404 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1409 /* Initialize video memory */
1410 ret = pxafb_map_video_memory(fbi);
1412 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1417 ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1419 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1425 * This makes sure that our colour bitfield
1426 * descriptors are correctly initialised.
1428 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1429 pxafb_set_par(&fbi->fb);
1431 platform_set_drvdata(dev, fbi);
1433 ret = register_framebuffer(&fbi->fb);
1436 "Failed to register framebuffer device: %d\n", ret);
1440 #ifdef CONFIG_CPU_FREQ
1441 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1442 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1443 cpufreq_register_notifier(&fbi->freq_transition,
1444 CPUFREQ_TRANSITION_NOTIFIER);
1445 cpufreq_register_notifier(&fbi->freq_policy,
1446 CPUFREQ_POLICY_NOTIFIER);
1450 * Ok, now enable the LCD controller
1452 set_ctrlr_state(fbi, C_ENABLE);
1457 platform_set_drvdata(dev, NULL);
1462 static struct platform_driver pxafb_driver = {
1463 .probe = pxafb_probe,
1464 .suspend = pxafb_suspend,
1465 .resume = pxafb_resume,
1467 .name = "pxa2xx-fb",
1471 static int __devinit pxafb_init(void)
1473 if (pxafb_setup_options())
1476 return platform_driver_register(&pxafb_driver);
1479 module_init(pxafb_init);
1481 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1482 MODULE_LICENSE("GPL");