SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/pm3fb.c

   1 /*
   2  *  linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
   3  *
   4  *  Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
   5  *
   6  *  Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
   7  *      based on pm2fb.c
   8  *
   9  *  Based on code written by:
  10  *         Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11  *         Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12  *         Russell King, <rmk@arm.linux.org.uk>
  13  *  Based on linux/drivers/video/skeletonfb.c:
  14  *      Copyright (C) 1997 Geert Uytterhoeven
  15  *  Based on linux/driver/video/pm2fb.c:
  16  *      Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17  *      Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License. See the file COPYING in the main directory of this archive for
  21  *  more details.
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/fb.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35
  36 #include <video/pm3fb.h>
  37
  38 #if !defined(CONFIG_PCI)
  39 #error "Only generic PCI cards supported."
  40 #endif
  41
  42 #undef PM3FB_MASTER_DEBUG
  43 #ifdef PM3FB_MASTER_DEBUG
  44 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
  45 #else
  46 #define DPRINTK(a,b...)
  47 #endif
  48
  49 /*
  50  * Driver data
  51  */
  52 static char *mode_option __devinitdata;
  53
  54 /*
  55  * This structure defines the hardware state of the graphics card. Normally
  56  * you place this in a header file in linux/include/video. This file usually
  57  * also includes register information. That allows other driver subsystems
  58  * and userland applications the ability to use the same header file to
  59  * avoid duplicate work and easy porting of software.
  60  */
  61 struct pm3_par {
  62         unsigned char   __iomem *v_regs;/* virtual address of p_regs */
  63         u32             video;          /* video flags before blanking */
  64         u32             base;           /* screen base (xoffset+yoffset) in 128 bits unit */
  65         u32             palette[16];
  66 };
  67
  68 /*
  69  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  70  * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  71  * to get a fb_var_screeninfo. Otherwise define a default var as well.
  72  */
  73 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
  74         .id =           "Permedia3",
  75         .type =         FB_TYPE_PACKED_PIXELS,
  76         .visual =       FB_VISUAL_PSEUDOCOLOR,
  77         .xpanstep =     1,
  78         .ypanstep =     1,
  79         .ywrapstep =    0,
  80         .accel =        FB_ACCEL_3DLABS_PERMEDIA3,
  81 };
  82
  83 /*
  84  * Utility functions
  85  */
  86
  87 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
  88 {
  89         return fb_readl(par->v_regs + off);
  90 }
  91
  92 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
  93 {
  94         fb_writel(v, par->v_regs + off);
  95 }
  96
  97 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
  98 {
  99         while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
 100 }
 101
 102 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
 103 {
 104         PM3_WAIT(par, 3);
 105         PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
 106         PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
 107         wmb();
 108         PM3_WRITE_REG(par, PM3RD_IndexedData, v);
 109         wmb();
 110 }
 111
 112 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
 113                         unsigned char r, unsigned char g, unsigned char b)
 114 {
 115         PM3_WAIT(par, 4);
 116         PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
 117         wmb();
 118         PM3_WRITE_REG(par, PM3RD_PaletteData, r);
 119         wmb();
 120         PM3_WRITE_REG(par, PM3RD_PaletteData, g);
 121         wmb();
 122         PM3_WRITE_REG(par, PM3RD_PaletteData, b);
 123         wmb();
 124 }
 125
 126 static void pm3fb_clear_colormap(struct pm3_par *par,
 127                         unsigned char r, unsigned char g, unsigned char b)
 128 {
 129         int i;
 130
 131         for (i = 0; i < 256 ; i++)
 132                 pm3fb_set_color(par, i, r, g, b);
 133
 134 }
 135
 136 /* Calculating various clock parameter */
 137 static void pm3fb_calculate_clock(unsigned long reqclock,
 138                                 unsigned char *prescale,
 139                                 unsigned char *feedback,
 140                                 unsigned char *postscale)
 141 {
 142         int f, pre, post;
 143         unsigned long freq;
 144         long freqerr = 1000;
 145         long currerr;
 146
 147         for (f = 1; f < 256; f++) {
 148                 for (pre = 1; pre < 256; pre++) {
 149                         for (post = 0; post < 5; post++) {
 150                                 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
 151                                 currerr = (reqclock > freq)
 152                                         ? reqclock - freq
 153                                         : freq - reqclock;
 154                                 if (currerr < freqerr) {
 155                                         freqerr = currerr;
 156                                         *feedback = f;
 157                                         *prescale = pre;
 158                                         *postscale = post;
 159                                 }
 160                         }
 161                 }
 162         }
 163 }
 164
 165 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
 166 {
 167         if ( var->bits_per_pixel == 16 )
 168                 return var->red.length + var->green.length
 169                         + var->blue.length;
 170
 171         return var->bits_per_pixel;
 172 }
 173
 174 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
 175 {
 176         switch (bpp) {
 177         case 8:
 178                 return (v >> 4);
 179         case 16:
 180                 return (v >> 3);
 181         case 32:
 182                 return (v >> 2);
 183         }
 184         DPRINTK("Unsupported depth %u\n", bpp);
 185         return 0;
 186 }
 187
 188 /* acceleration */
 189 static int pm3fb_sync(struct fb_info *info)
 190 {
 191         struct pm3_par *par = info->par;
 192
 193         PM3_WAIT(par, 2);
 194         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 195         PM3_WRITE_REG(par, PM3Sync, 0);
 196         mb();
 197         do {
 198                 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
 199                 rmb();
 200         } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
 201
 202         return 0;
 203 }
 204
 205 static void pm3fb_init_engine(struct fb_info *info)
 206 {
 207         struct pm3_par *par = info->par;
 208         const u32 width = (info->var.xres_virtual + 7) & ~7;
 209
 210         PM3_WAIT(par, 50);
 211         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 212         PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
 213         PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
 214         PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
 215         PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
 216         PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
 217         PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
 218         PM3_WRITE_REG(par, PM3GIDMode, 0x0);
 219         PM3_WRITE_REG(par, PM3DepthMode, 0x0);
 220         PM3_WRITE_REG(par, PM3StencilMode, 0x0);
 221         PM3_WRITE_REG(par, PM3StencilData, 0x0);
 222         PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
 223         PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
 224         PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
 225         PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
 226         PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
 227         PM3_WRITE_REG(par, PM3LUTMode, 0x0);
 228         PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
 229         PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
 230         PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
 231         PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
 232         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
 233         PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
 234         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
 235         PM3_WRITE_REG(par, PM3FogMode, 0x0);
 236         PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
 237         PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
 238         PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
 239         PM3_WRITE_REG(par, PM3YUVMode, 0x0);
 240         PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
 241         PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
 242         PM3_WRITE_REG(par, PM3DitherMode, 0x0);
 243         PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
 244         PM3_WRITE_REG(par, PM3RouterMode, 0x0);
 245         PM3_WRITE_REG(par, PM3Window, 0x0);
 246
 247         PM3_WRITE_REG(par, PM3Config2D, 0x0);
 248
 249         PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
 250
 251         PM3_WRITE_REG(par, PM3XBias, 0x0);
 252         PM3_WRITE_REG(par, PM3YBias, 0x0);
 253         PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
 254
 255         PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
 256
 257         PM3_WRITE_REG(par, PM3FBDestReadEnables,
 258                            PM3FBDestReadEnables_E(0xff) |
 259                            PM3FBDestReadEnables_R(0xff) |
 260                            PM3FBDestReadEnables_ReferenceAlpha(0xff));
 261         PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
 262         PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
 263         PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
 264                            PM3FBDestReadBufferWidth_Width(width));
 265
 266         PM3_WRITE_REG(par, PM3FBDestReadMode,
 267                            PM3FBDestReadMode_ReadEnable |
 268                            PM3FBDestReadMode_Enable0);
 269         PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
 270         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
 271         PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
 272                            PM3FBSourceReadBufferWidth_Width(width));
 273         PM3_WRITE_REG(par, PM3FBSourceReadMode,
 274                            PM3FBSourceReadMode_Blocking |
 275                            PM3FBSourceReadMode_ReadEnable);
 276
 277         PM3_WAIT(par, 2);
 278         {
 279                 unsigned long rm = 1;
 280                 switch (info->var.bits_per_pixel) {
 281                 case 8:
 282                         PM3_WRITE_REG(par, PM3PixelSize,
 283                                            PM3PixelSize_GLOBAL_8BIT);
 284                         break;
 285                 case 16:
 286                         PM3_WRITE_REG(par, PM3PixelSize,
 287                                            PM3PixelSize_GLOBAL_16BIT);
 288                         break;
 289                 case 32:
 290                         PM3_WRITE_REG(par, PM3PixelSize,
 291                                            PM3PixelSize_GLOBAL_32BIT);
 292                         break;
 293                 default:
 294                         DPRINTK(1, "Unsupported depth %d\n",
 295                                 info->var.bits_per_pixel);
 296                         break;
 297                 }
 298                 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
 299         }
 300
 301         PM3_WAIT(par, 20);
 302         PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
 303         PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
 304         PM3_WRITE_REG(par, PM3FBWriteMode,
 305                            PM3FBWriteMode_WriteEnable |
 306                            PM3FBWriteMode_OpaqueSpan |
 307                            PM3FBWriteMode_Enable0);
 308         PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
 309         PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
 310         PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
 311                            PM3FBWriteBufferWidth_Width(width));
 312
 313         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
 314         {
 315                 /* size in lines of FB */
 316                 unsigned long sofb = info->screen_size /
 317                         info->fix.line_length;
 318                 if (sofb > 4095)
 319                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
 320                 else
 321                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
 322
 323                 switch (info->var.bits_per_pixel) {
 324                 case 8:
 325                         PM3_WRITE_REG(par, PM3DitherMode,
 326                                            (1 << 10) | (2 << 3));
 327                         break;
 328                 case 16:
 329                         PM3_WRITE_REG(par, PM3DitherMode,
 330                                            (1 << 10) | (1 << 3));
 331                         break;
 332                 case 32:
 333                         PM3_WRITE_REG(par, PM3DitherMode,
 334                                            (1 << 10) | (0 << 3));
 335                         break;
 336                 default:
 337                         DPRINTK(1, "Unsupported depth %d\n",
 338                                 info->current_par->depth);
 339                         break;
 340                 }
 341         }
 342
 343         PM3_WRITE_REG(par, PM3dXDom, 0x0);
 344         PM3_WRITE_REG(par, PM3dXSub, 0x0);
 345         PM3_WRITE_REG(par, PM3dY, (1 << 16));
 346         PM3_WRITE_REG(par, PM3StartXDom, 0x0);
 347         PM3_WRITE_REG(par, PM3StartXSub, 0x0);
 348         PM3_WRITE_REG(par, PM3StartY, 0x0);
 349         PM3_WRITE_REG(par, PM3Count, 0x0);
 350
 351 /* Disable LocalBuffer. better safe than sorry */
 352         PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
 353         PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
 354         PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
 355         PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
 356
 357         pm3fb_sync(info);
 358 }
 359
 360 static void pm3fb_fillrect (struct fb_info *info,
 361                                 const struct fb_fillrect *region)
 362 {
 363         struct pm3_par *par = info->par;
 364         struct fb_fillrect modded;
 365         int vxres, vyres;
 366         u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
 367                 ((u32*)info->pseudo_palette)[region->color] : region->color;
 368
 369         if (info->state != FBINFO_STATE_RUNNING)
 370                 return;
 371         if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
 372                 region->rop != ROP_COPY ) {
 373                 cfb_fillrect(info, region);
 374                 return;
 375         }
 376
 377         vxres = info->var.xres_virtual;
 378         vyres = info->var.yres_virtual;
 379
 380         memcpy(&modded, region, sizeof(struct fb_fillrect));
 381
 382         if(!modded.width || !modded.height ||
 383            modded.dx >= vxres || modded.dy >= vyres)
 384                 return;
 385
 386         if(modded.dx + modded.width  > vxres)
 387                 modded.width  = vxres - modded.dx;
 388         if(modded.dy + modded.height > vyres)
 389                 modded.height = vyres - modded.dy;
 390
 391         if(info->var.bits_per_pixel == 8)
 392                 color |= color << 8;
 393         if(info->var.bits_per_pixel <= 16)
 394                 color |= color << 16;
 395
 396         PM3_WAIT(par, 4);
 397
 398         PM3_WRITE_REG(par, PM3Config2D,
 399                                   PM3Config2D_UseConstantSource |
 400                                   PM3Config2D_ForegroundROPEnable |
 401                                   (PM3Config2D_ForegroundROP(0x3)) |    /* Ox3 is GXcopy */
 402                                   PM3Config2D_FBWriteEnable);
 403
 404         PM3_WRITE_REG(par, PM3ForegroundColor, color);
 405
 406         PM3_WRITE_REG(par, PM3RectanglePosition,
 407                       (PM3RectanglePosition_XOffset(modded.dx)) |
 408                       (PM3RectanglePosition_YOffset(modded.dy)));
 409
 410         PM3_WRITE_REG(par, PM3Render2D,
 411                       PM3Render2D_XPositive |
 412                       PM3Render2D_YPositive |
 413                       PM3Render2D_Operation_Normal |
 414                       PM3Render2D_SpanOperation |
 415                       (PM3Render2D_Width(modded.width)) |
 416                       (PM3Render2D_Height(modded.height)));
 417 }
 418 /* end of acceleration functions */
 419
 420 /* write the mode to registers */
 421 static void pm3fb_write_mode(struct fb_info *info)
 422 {
 423         struct pm3_par *par = info->par;
 424         char tempsync = 0x00, tempmisc = 0x00;
 425         const u32 hsstart = info->var.right_margin;
 426         const u32 hsend = hsstart + info->var.hsync_len;
 427         const u32 hbend = hsend + info->var.left_margin;
 428         const u32 xres = (info->var.xres + 31) & ~31;
 429         const u32 htotal = xres + hbend;
 430         const u32 vsstart = info->var.lower_margin;
 431         const u32 vsend = vsstart + info->var.vsync_len;
 432         const u32 vbend = vsend + info->var.upper_margin;
 433         const u32 vtotal = info->var.yres + vbend;
 434         const u32 width = (info->var.xres_virtual + 7) & ~7;
 435         const unsigned bpp = info->var.bits_per_pixel;
 436
 437         PM3_WAIT(par, 20);
 438         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
 439         PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
 440         PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
 441         PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
 442
 443         PM3_WRITE_REG(par, PM3HTotal,
 444                            pm3fb_shift_bpp(bpp, htotal - 1));
 445         PM3_WRITE_REG(par, PM3HsEnd,
 446                            pm3fb_shift_bpp(bpp, hsend));
 447         PM3_WRITE_REG(par, PM3HsStart,
 448                            pm3fb_shift_bpp(bpp, hsstart));
 449         PM3_WRITE_REG(par, PM3HbEnd,
 450                            pm3fb_shift_bpp(bpp, hbend));
 451         PM3_WRITE_REG(par, PM3HgEnd,
 452                            pm3fb_shift_bpp(bpp, hbend));
 453         PM3_WRITE_REG(par, PM3ScreenStride,
 454                            pm3fb_shift_bpp(bpp, width));
 455         PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
 456         PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
 457         PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
 458         PM3_WRITE_REG(par, PM3VbEnd, vbend);
 459
 460         switch (bpp) {
 461         case 8:
 462                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 463                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 464                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 465                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 466                 break;
 467
 468         case 16:
 469 #ifndef __BIG_ENDIAN
 470                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 471                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 472                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 473                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 474 #else
 475                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 476                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 477                                    PM3ByApertureMode_BYTESWAP_BADC);
 478                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 479                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 480                                    PM3ByApertureMode_BYTESWAP_BADC);
 481 #endif /* ! __BIG_ENDIAN */
 482                 break;
 483
 484         case 32:
 485 #ifndef __BIG_ENDIAN
 486                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 487                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 488                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 489                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 490 #else
 491                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 492                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 493                                    PM3ByApertureMode_BYTESWAP_DCBA);
 494                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 495                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 496                                    PM3ByApertureMode_BYTESWAP_DCBA);
 497 #endif /* ! __BIG_ENDIAN */
 498                 break;
 499
 500         default:
 501                 DPRINTK("Unsupported depth %d\n", bpp);
 502                 break;
 503         }
 504
 505         /*
 506          * Oxygen VX1 - it appears that setting PM3VideoControl and
 507          * then PM3RD_SyncControl to the same SYNC settings undoes
 508          * any net change - they seem to xor together.  Only set the
 509          * sync options in PM3RD_SyncControl.  --rmk
 510          */
 511         {
 512                 unsigned int video = par->video;
 513
 514                 video &= ~(PM3VideoControl_HSYNC_MASK |
 515                            PM3VideoControl_VSYNC_MASK);
 516                 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 517                          PM3VideoControl_VSYNC_ACTIVE_HIGH;
 518                 PM3_WRITE_REG(par, PM3VideoControl, video);
 519         }
 520         PM3_WRITE_REG(par, PM3VClkCtl,
 521                            (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
 522         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
 523         PM3_WRITE_REG(par, PM3ChipConfig,
 524                            (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
 525
 526         wmb();
 527         {
 528                 unsigned char uninitialized_var(m);     /* ClkPreScale */
 529                 unsigned char uninitialized_var(n);     /* ClkFeedBackScale */
 530                 unsigned char uninitialized_var(p);     /* ClkPostScale */
 531                 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
 532
 533                 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
 534
 535                 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
 536                         pixclock, (int) m, (int) n, (int) p);
 537
 538                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
 539                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
 540                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
 541         }
 542         /*
 543            PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
 544          */
 545         /*
 546            PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
 547          */
 548         if ((par->video & PM3VideoControl_HSYNC_MASK) ==
 549             PM3VideoControl_HSYNC_ACTIVE_HIGH)
 550                 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
 551         if ((par->video & PM3VideoControl_VSYNC_MASK) ==
 552             PM3VideoControl_VSYNC_ACTIVE_HIGH)
 553                 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
 554
 555         PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
 556         DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
 557
 558         PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
 559
 560         switch (pm3fb_depth(&info->var)) {
 561         case 8:
 562                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 563                                   PM3RD_PixelSize_8_BIT_PIXELS);
 564                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 565                                   PM3RD_ColorFormat_CI8_COLOR |
 566                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 567                 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 568                 break;
 569         case 12:
 570                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 571                                   PM3RD_PixelSize_16_BIT_PIXELS);
 572                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 573                                   PM3RD_ColorFormat_4444_COLOR |
 574                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 575                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 576                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 577                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 578                 break;
 579         case 15:
 580                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 581                                   PM3RD_PixelSize_16_BIT_PIXELS);
 582                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 583                                   PM3RD_ColorFormat_5551_FRONT_COLOR |
 584                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 585                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 586                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 587                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 588                 break;
 589         case 16:
 590                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 591                                   PM3RD_PixelSize_16_BIT_PIXELS);
 592                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 593                                   PM3RD_ColorFormat_565_FRONT_COLOR |
 594                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 595                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 596                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 597                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 598                 break;
 599         case 32:
 600                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 601                                   PM3RD_PixelSize_32_BIT_PIXELS);
 602                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 603                                   PM3RD_ColorFormat_8888_COLOR |
 604                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 605                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 606                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 607                 break;
 608         }
 609         PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
 610 }
 611
 612 /*
 613  * hardware independent functions
 614  */
 615 int pm3fb_init(void);
 616
 617 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 618 {
 619         u32 lpitch;
 620         unsigned bpp = var->red.length + var->green.length
 621                         + var->blue.length + var->transp.length;
 622
 623         if ( bpp != var->bits_per_pixel ) {
 624                 /* set predefined mode for bits_per_pixel settings */
 625
 626                 switch(var->bits_per_pixel) {
 627                 case 8:
 628                         var->red.length = var->green.length = var->blue.length = 8;
 629                         var->red.offset = var->green.offset = var->blue.offset = 0;
 630                         var->transp.offset = 0;
 631                         var->transp.length = 0;
 632                         break;
 633                 case 16:
 634                         var->red.length = var->blue.length = 5;
 635                         var->green.length = 6;
 636                         var->transp.length = 0;
 637                         break;
 638                 case 32:
 639                         var->red.length = var->green.length = var->blue.length = 8;
 640                         var->transp.length = 8;
 641                         break;
 642                 default:
 643                         DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 644                         return -EINVAL;
 645                 }
 646         }
 647         /* it is assumed BGRA order */
 648         if (var->bits_per_pixel > 8 )
 649         {
 650                 var->blue.offset = 0;
 651                 var->green.offset = var->blue.length;
 652                 var->red.offset = var->green.offset + var->green.length;
 653                 var->transp.offset = var->red.offset + var->red.length;
 654         }
 655         var->height = var->width = -1;
 656
 657         if (var->xres != var->xres_virtual) {
 658                 DPRINTK("virtual x resolution != physical x resolution not supported\n");
 659                 return -EINVAL;
 660         }
 661
 662         if (var->yres > var->yres_virtual) {
 663                 DPRINTK("virtual y resolution < physical y resolution not possible\n");
 664                 return -EINVAL;
 665         }
 666
 667         if (var->xoffset) {
 668                 DPRINTK("xoffset not supported\n");
 669                 return -EINVAL;
 670         }
 671
 672         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 673                 DPRINTK("interlace not supported\n");
 674                 return -EINVAL;
 675         }
 676
 677         var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
 678         lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
 679
 680         if (var->xres < 200 || var->xres > 2048) {
 681                 DPRINTK("width not supported: %u\n", var->xres);
 682                 return -EINVAL;
 683         }
 684
 685         if (var->yres < 200 || var->yres > 4095) {
 686                 DPRINTK("height not supported: %u\n", var->yres);
 687                 return -EINVAL;
 688         }
 689
 690         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 691                 DPRINTK("no memory for screen (%ux%ux%u)\n",
 692                         var->xres, var->yres_virtual, var->bits_per_pixel);
 693                 return -EINVAL;
 694         }
 695
 696         if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
 697                 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
 698                 return -EINVAL;
 699         }
 700
 701         var->accel_flags = 0;   /* Can't mmap if this is on */
 702
 703         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 704                 var->xres, var->yres, var->bits_per_pixel);
 705         return 0;
 706 }
 707
 708 static int pm3fb_set_par(struct fb_info *info)
 709 {
 710         struct pm3_par *par = info->par;
 711         const u32 xres = (info->var.xres + 31) & ~31;
 712         const unsigned bpp = info->var.bits_per_pixel;
 713
 714         par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres)
 715                                         + info->var.xoffset);
 716         par->video = 0;
 717
 718         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 719                 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
 720         else
 721                 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
 722
 723         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 724                 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
 725         else
 726                 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
 727
 728         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
 729                 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
 730         else
 731                 par->video |= PM3VideoControl_LINE_DOUBLE_OFF;
 732
 733         if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
 734                 par->video |= PM3VideoControl_ENABLE;
 735         else {
 736                 par->video |= PM3VideoControl_DISABLE;
 737                 DPRINTK("PM3Video disabled\n");
 738         }
 739         switch (bpp) {
 740         case 8:
 741                 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
 742                 break;
 743         case 16:
 744                 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
 745                 break;
 746         case 32:
 747                 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
 748                 break;
 749         default:
 750                 DPRINTK("Unsupported depth\n");
 751                 break;
 752         }
 753
 754         info->fix.visual =
 755                 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 756         info->fix.line_length = ((info->var.xres_virtual + 7)  & ~7)
 757                                         * bpp / 8;
 758
 759 /*      pm3fb_clear_memory(info, 0);*/
 760         pm3fb_clear_colormap(par, 0, 0, 0);
 761         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode,
 762                           PM3RD_CursorMode_CURSOR_DISABLE);
 763         pm3fb_init_engine(info);
 764         pm3fb_write_mode(info);
 765         return 0;
 766 }
 767
 768 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 769                            unsigned blue, unsigned transp,
 770                            struct fb_info *info)
 771 {
 772         struct pm3_par *par = info->par;
 773
 774         if (regno >= 256)  /* no. of hw registers */
 775            return -EINVAL;
 776
 777         /* grayscale works only partially under directcolor */
 778         if (info->var.grayscale) {
 779            /* grayscale = 0.30*R + 0.59*G + 0.11*B */
 780            red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 781         }
 782
 783         /* Directcolor:
 784          *   var->{color}.offset contains start of bitfield
 785          *   var->{color}.length contains length of bitfield
 786          *   {hardwarespecific} contains width of DAC
 787          *   pseudo_palette[X] is programmed to (X << red.offset) |
 788          *                                      (X << green.offset) |
 789          *                                      (X << blue.offset)
 790          *   RAMDAC[X] is programmed to (red, green, blue)
 791          *   color depth = SUM(var->{color}.length)
 792          *
 793          * Pseudocolor:
 794          *      var->{color}.offset is 0
 795          *      var->{color}.length contains width of DAC or the number of unique
 796          *                      colors available (color depth)
 797          *      pseudo_palette is not used
 798          *      RAMDAC[X] is programmed to (red, green, blue)
 799          *      color depth = var->{color}.length
 800          */
 801
 802         /*
 803          * This is the point where the color is converted to something that
 804          * is acceptable by the hardware.
 805          */
 806 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 807         red = CNVT_TOHW(red, info->var.red.length);
 808         green = CNVT_TOHW(green, info->var.green.length);
 809         blue = CNVT_TOHW(blue, info->var.blue.length);
 810         transp = CNVT_TOHW(transp, info->var.transp.length);
 811 #undef CNVT_TOHW
 812
 813         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 814         info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 815                 u32 v;
 816
 817                 if (regno >= 16)
 818                         return -EINVAL;
 819
 820                 v = (red << info->var.red.offset) |
 821                         (green << info->var.green.offset) |
 822                         (blue << info->var.blue.offset) |
 823                         (transp << info->var.transp.offset);
 824
 825                 switch (info->var.bits_per_pixel) {
 826                 case 8:
 827                         break;
 828                 case 16:
 829                 case 32:
 830                         ((u32*)(info->pseudo_palette))[regno] = v;
 831                         break;
 832                 }
 833                 return 0;
 834         }
 835         else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
 836                 pm3fb_set_color(par, regno, red, green, blue);
 837
 838         return 0;
 839 }
 840
 841 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
 842                                  struct fb_info *info)
 843 {
 844         struct pm3_par *par = info->par;
 845         const u32 xres = (var->xres + 31) & ~31;
 846
 847         par->base = pm3fb_shift_bpp(var->bits_per_pixel,
 848                                         (var->yoffset * xres)
 849                                         + var->xoffset);
 850         PM3_WAIT(par, 1);
 851         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
 852         return 0;
 853 }
 854
 855 static int pm3fb_blank(int blank_mode, struct fb_info *info)
 856 {
 857         struct pm3_par *par = info->par;
 858         u32 video = par->video;
 859
 860         /*
 861          * Oxygen VX1 - it appears that setting PM3VideoControl and
 862          * then PM3RD_SyncControl to the same SYNC settings undoes
 863          * any net change - they seem to xor together.  Only set the
 864          * sync options in PM3RD_SyncControl.  --rmk
 865          */
 866         video &= ~(PM3VideoControl_HSYNC_MASK |
 867                    PM3VideoControl_VSYNC_MASK);
 868         video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 869                  PM3VideoControl_VSYNC_ACTIVE_HIGH;
 870
 871         switch (blank_mode) {
 872         case FB_BLANK_UNBLANK:
 873                 video |= PM3VideoControl_ENABLE;
 874                 break;
 875         case FB_BLANK_NORMAL:
 876                 video &= ~(PM3VideoControl_ENABLE);
 877                 break;
 878         case FB_BLANK_HSYNC_SUSPEND:
 879                 video &= ~(PM3VideoControl_HSYNC_MASK |
 880                           PM3VideoControl_BLANK_ACTIVE_LOW);
 881                 break;
 882         case FB_BLANK_VSYNC_SUSPEND:
 883                 video &= ~(PM3VideoControl_VSYNC_MASK |
 884                           PM3VideoControl_BLANK_ACTIVE_LOW);
 885                 break;
 886         case FB_BLANK_POWERDOWN:
 887                 video &= ~(PM3VideoControl_HSYNC_MASK |
 888                           PM3VideoControl_VSYNC_MASK |
 889                           PM3VideoControl_BLANK_ACTIVE_LOW);
 890                 break;
 891         default:
 892                 DPRINTK("Unsupported blanking %d\n", blank_mode);
 893                 return 1;
 894         }
 895
 896         PM3_WAIT(par, 1);
 897         PM3_WRITE_REG(par,PM3VideoControl, video);
 898         return 0;
 899 }
 900
 901         /*
 902          *  Frame buffer operations
 903          */
 904
 905 static struct fb_ops pm3fb_ops = {
 906         .owner          = THIS_MODULE,
 907         .fb_check_var   = pm3fb_check_var,
 908         .fb_set_par     = pm3fb_set_par,
 909         .fb_setcolreg   = pm3fb_setcolreg,
 910         .fb_pan_display = pm3fb_pan_display,
 911         .fb_fillrect    = pm3fb_fillrect,
 912         .fb_copyarea    = cfb_copyarea,
 913         .fb_imageblit   = cfb_imageblit,
 914         .fb_blank       = pm3fb_blank,
 915         .fb_sync        = pm3fb_sync,
 916 };
 917
 918 /* ------------------------------------------------------------------------- */
 919
 920         /*
 921          *  Initialization
 922          */
 923
 924 /* mmio register are already mapped when this function is called */
 925 /* the pm3fb_fix.smem_start is also set */
 926 static unsigned long pm3fb_size_memory(struct pm3_par *par)
 927 {
 928         unsigned long   memsize = 0, tempBypass, i, temp1, temp2;
 929         unsigned char   __iomem *screen_mem;
 930
 931         pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
 932         /* Linear frame buffer - request region and map it. */
 933         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
 934                                  "pm3fb smem")) {
 935                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
 936                 return 0;
 937         }
 938         screen_mem =
 939                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 940         if (!screen_mem) {
 941                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
 942                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
 943                 return 0;
 944         }
 945
 946         /* TODO: card-specific stuff, *before* accessing *any* FB memory */
 947         /* For Appian Jeronimo 2000 board second head */
 948
 949         tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
 950
 951         DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
 952
 953         PM3_WAIT(par, 1);
 954         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
 955
 956         /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */
 957         for (i = 0; i < 32; i++) {
 958                 fb_writel(i * 0x00345678,
 959                           (screen_mem + (i * 1048576)));
 960                 mb();
 961                 temp1 = fb_readl((screen_mem + (i * 1048576)));
 962
 963                 /* Let's check for wrapover, write will fail at 16MB boundary */
 964                 if (temp1 == (i * 0x00345678))
 965                         memsize = i;
 966                 else
 967                         break;
 968         }
 969
 970         DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
 971
 972         if (memsize + 1 == i) {
 973                 for (i = 0; i < 32; i++) {
 974                         /* Clear first 32MB ; 0 is 0, no need to byteswap */
 975                         writel(0x0000000, (screen_mem + (i * 1048576)));
 976                 }
 977                 wmb();
 978
 979                 for (i = 32; i < 64; i++) {
 980                         fb_writel(i * 0x00345678,
 981                                   (screen_mem + (i * 1048576)));
 982                         mb();
 983                         temp1 =
 984                             fb_readl((screen_mem + (i * 1048576)));
 985                         temp2 =
 986                             fb_readl((screen_mem + ((i - 32) * 1048576)));
 987                         /* different value, different RAM... */
 988                         if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
 989                                 memsize = i;
 990                         else
 991                                 break;
 992                 }
 993         }
 994         DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
 995
 996         PM3_WAIT(par, 1);
 997         PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
 998
 999         iounmap(screen_mem);
1000         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1001         memsize = 1048576 * (memsize + 1);
1002
1003         DPRINTK("Returning 0x%08lx bytes\n", memsize);
1004
1005         return memsize;
1006 }
1007
1008 static int __devinit pm3fb_probe(struct pci_dev *dev,
1009                                   const struct pci_device_id *ent)
1010 {
1011         struct fb_info *info;
1012         struct pm3_par *par;
1013         struct device* device = &dev->dev; /* for pci drivers */
1014         int err, retval = -ENXIO;
1015
1016         err = pci_enable_device(dev);
1017         if (err) {
1018                 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1019                 return err;
1020         }
1021         /*
1022          * Dynamically allocate info and par
1023          */
1024         info = framebuffer_alloc(sizeof(struct pm3_par), device);
1025
1026         if (!info)
1027                 return -ENOMEM;
1028         par = info->par;
1029
1030         /*
1031          * Here we set the screen_base to the virtual memory address
1032          * for the framebuffer.
1033          */
1034         pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1035         pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1036
1037         /* Registers - request region and map it. */
1038         if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1039                                  "pm3fb regbase")) {
1040                 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1041                 goto err_exit_neither;
1042         }
1043         par->v_regs =
1044                 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1045         if (!par->v_regs) {
1046                 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1047                         pm3fb_fix.id);
1048                 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1049                 goto err_exit_neither;
1050         }
1051
1052 #if defined(__BIG_ENDIAN)
1053         pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1054         DPRINTK("Adjusting register base for big-endian.\n");
1055 #endif
1056         /* Linear frame buffer - request region and map it. */
1057         pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1058         pm3fb_fix.smem_len = pm3fb_size_memory(par);
1059         if (!pm3fb_fix.smem_len)
1060         {
1061                 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1062                 goto err_exit_mmio;
1063         }
1064         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1065                                  "pm3fb smem")) {
1066                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1067                 goto err_exit_mmio;
1068         }
1069         info->screen_base =
1070                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1071         if (!info->screen_base) {
1072                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1073                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1074                 goto err_exit_mmio;
1075         }
1076         info->screen_size = pm3fb_fix.smem_len;
1077
1078         info->fbops = &pm3fb_ops;
1079
1080         par->video = PM3_READ_REG(par, PM3VideoControl);
1081
1082         info->fix = pm3fb_fix;
1083         info->pseudo_palette = par->palette;
1084         info->flags = FBINFO_DEFAULT |
1085                         FBINFO_HWACCEL_FILLRECT;/* | FBINFO_HWACCEL_YPAN;*/
1086
1087         /*
1088          * This should give a reasonable default video mode. The following is
1089          * done when we can set a video mode.
1090          */
1091         if (!mode_option)
1092                 mode_option = "640x480@60";
1093
1094         retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1095
1096         if (!retval || retval == 4) {
1097                 retval = -EINVAL;
1098                 goto err_exit_both;
1099         }
1100
1101         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1102                 retval = -ENOMEM;
1103                 goto err_exit_both;
1104         }
1105
1106         /*
1107          * For drivers that can...
1108          */
1109         pm3fb_check_var(&info->var, info);
1110
1111         if (register_framebuffer(info) < 0) {
1112                 retval = -EINVAL;
1113                 goto err_exit_all;
1114         }
1115         printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1116            info->fix.id);
1117         pci_set_drvdata(dev, info);
1118         return 0;
1119
1120  err_exit_all:
1121         fb_dealloc_cmap(&info->cmap);
1122  err_exit_both:
1123         iounmap(info->screen_base);
1124         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1125  err_exit_mmio:
1126         iounmap(par->v_regs);
1127         release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1128  err_exit_neither:
1129         framebuffer_release(info);
1130         return retval;
1131 }
1132
1133         /*
1134          *  Cleanup
1135          */
1136 static void __devexit pm3fb_remove(struct pci_dev *dev)
1137 {
1138         struct fb_info *info = pci_get_drvdata(dev);
1139
1140         if (info) {
1141                 struct fb_fix_screeninfo *fix = &info->fix;
1142                 struct pm3_par *par = info->par;
1143
1144                 unregister_framebuffer(info);
1145                 fb_dealloc_cmap(&info->cmap);
1146
1147                 iounmap(info->screen_base);
1148                 release_mem_region(fix->smem_start, fix->smem_len);
1149                 iounmap(par->v_regs);
1150                 release_mem_region(fix->mmio_start, fix->mmio_len);
1151
1152                 pci_set_drvdata(dev, NULL);
1153                 framebuffer_release(info);
1154         }
1155 }
1156
1157 static struct pci_device_id pm3fb_id_table[] = {
1158         { PCI_VENDOR_ID_3DLABS, 0x0a,
1159           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1160         { 0, }
1161 };
1162
1163 /* For PCI drivers */
1164 static struct pci_driver pm3fb_driver = {
1165         .name =         "pm3fb",
1166         .id_table =     pm3fb_id_table,
1167         .probe =        pm3fb_probe,
1168         .remove =       __devexit_p(pm3fb_remove),
1169 };
1170
1171 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1172
1173 #ifndef MODULE
1174         /*
1175          *  Setup
1176          */
1177
1178 /*
1179  * Only necessary if your driver takes special options,
1180  * otherwise we fall back on the generic fb_setup().
1181  */
1182 static int __init pm3fb_setup(char *options)
1183 {
1184         /* Parse user speficied options (`video=pm3fb:') */
1185         return 0;
1186 }
1187 #endif /* MODULE */
1188
1189 int __init pm3fb_init(void)
1190 {
1191         /*
1192          *  For kernel boot options (in 'video=pm3fb:<options>' format)
1193          */
1194 #ifndef MODULE
1195         char *option = NULL;
1196
1197         if (fb_get_options("pm3fb", &option))
1198                 return -ENODEV;
1199         pm3fb_setup(option);
1200 #endif
1201
1202         return pci_register_driver(&pm3fb_driver);
1203 }
1204
1205 static void __exit pm3fb_exit(void)
1206 {
1207         pci_unregister_driver(&pm3fb_driver);
1208 }
1209
1210 module_init(pm3fb_init);
1211 module_exit(pm3fb_exit);
1212
1213 MODULE_LICENSE("GPL");