4 /* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */
7 /*** HW-specific data ***/
9 /* Information about the 852GM/855GM variants */
10 #define INTEL_85X_CAPID 0x44
11 #define INTEL_85X_VARIANT_MASK 0x7
12 #define INTEL_85X_VARIANT_SHIFT 5
13 #define INTEL_VAR_855GME 0x0
14 #define INTEL_VAR_855GM 0x4
15 #define INTEL_VAR_852GME 0x2
16 #define INTEL_VAR_852GM 0x5
18 /* Information about DVO/LVDS Ports */
25 * The Bridge device's PCI config space has information about the
26 * fb aperture size and the amount of pre-reserved memory.
28 #define INTEL_GMCH_CTRL 0x52
29 #define INTEL_GMCH_ENABLED 0x4
30 #define INTEL_GMCH_MEM_MASK 0x1
31 #define INTEL_GMCH_MEM_64M 0x1
32 #define INTEL_GMCH_MEM_128M 0
34 #define INTEL_830_GMCH_GMS_MASK (0x7 << 4)
35 #define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4)
36 #define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4)
37 #define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4)
38 #define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
39 #define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
41 #define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
42 #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
43 #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
44 #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
45 #define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
46 #define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
47 #define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
49 #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
50 #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
58 /* Primary ring buffer */
59 #define PRI_RING_TAIL 0x2030
60 #define RING_TAIL_MASK 0x001ffff8
61 #define RING_INUSE 0x1
63 #define PRI_RING_HEAD 0x2034
64 #define RING_HEAD_WRAP_MASK 0x7ff
65 #define RING_HEAD_WRAP_SHIFT 21
66 #define RING_HEAD_MASK 0x001ffffc
68 #define PRI_RING_START 0x2038
69 #define RING_START_MASK 0xfffff000
71 #define PRI_RING_LENGTH 0x203c
72 #define RING_LENGTH_MASK 0x001ff000
73 #define RING_REPORT_MASK (0x3 << 1)
74 #define RING_NO_REPORT (0x0 << 1)
75 #define RING_REPORT_64K (0x1 << 1)
76 #define RING_REPORT_4K (0x2 << 1)
77 #define RING_REPORT_128K (0x3 << 1)
78 #define RING_ENABLE 0x1
81 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
82 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
84 #define RING_MIN_FREE 64
88 #define INSTDONE 0x2090
89 #define PRI_RING_EMPTY 1
95 #define VSYNC_PIPE_A_INTERRUPT (1 << 7)
96 #define PIPE_A_EVENT_INTERRUPT (1 << 4)
97 #define VSYNC_PIPE_B_INTERRUPT (1 << 5)
98 #define PIPE_B_EVENT_INTERRUPT (1 << 4)
99 #define HOST_PORT_EVENT_INTERRUPT (1 << 3)
100 #define CAPTURE_EVENT_INTERRUPT (1 << 2)
101 #define USER_DEFINED_INTERRUPT (1 << 1)
102 #define BREAKPOINT_INTERRUPT 1
104 #define INSTPM 0x20c0
105 #define SYNC_FLUSH_ENABLE (1 << 5)
107 #define INSTPS 0x20c4
109 #define MEM_MODE 0x20cc
111 #define MASK_SHIFT 16
113 #define FW_BLC_0 0x20d8
114 #define FW_DISPA_WM_SHIFT 0
115 #define FW_DISPA_WM_MASK 0x3f
116 #define FW_DISPA_BL_SHIFT 8
117 #define FW_DISPA_BL_MASK 0xf
118 #define FW_DISPB_WM_SHIFT 16
119 #define FW_DISPB_WM_MASK 0x1f
120 #define FW_DISPB_BL_SHIFT 24
121 #define FW_DISPB_BL_MASK 0x7
123 #define FW_BLC_1 0x20dc
124 #define FW_DISPC_WM_SHIFT 0
125 #define FW_DISPC_WM_MASK 0x1f
126 #define FW_DISPC_BL_SHIFT 8
127 #define FW_DISPC_BL_MASK 0x7
131 #define VGA0_DIVISOR 0x06000
132 #define VGA1_DIVISOR 0x06004
133 #define VGAPD 0x06010
134 #define VGAPD_0_P1_SHIFT 0
135 #define VGAPD_0_P1_FORCE_DIV2 (1 << 5)
136 #define VGAPD_0_P2_SHIFT 7
137 #define VGAPD_1_P1_SHIFT 8
138 #define VGAPD_1_P1_FORCE_DIV2 (1 << 13)
139 #define VGAPD_1_P2_SHIFT 15
141 #define DPLL_A 0x06014
142 #define DPLL_B 0x06018
143 #define DPLL_VCO_ENABLE (1 << 31)
144 #define DPLL_2X_CLOCK_ENABLE (1 << 30)
145 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
146 #define DPLL_VGA_MODE_DISABLE (1 << 28)
147 #define DPLL_P2_MASK 1
148 #define DPLL_P2_SHIFT 23
149 #define DPLL_I9XX_P2_SHIFT 24
150 #define DPLL_P1_FORCE_DIV2 (1 << 21)
151 #define DPLL_P1_MASK 0x1f
152 #define DPLL_P1_SHIFT 16
153 #define DPLL_REFERENCE_SELECT_MASK (0x3 << 13)
154 #define DPLL_REFERENCE_DEFAULT (0x0 << 13)
155 #define DPLL_REFERENCE_TVCLK (0x2 << 13)
156 #define DPLL_RATE_SELECT_MASK (1 << 8)
157 #define DPLL_RATE_SELECT_FP0 (0 << 8)
158 #define DPLL_RATE_SELECT_FP1 (1 << 8)
164 #define FP_DIVISOR_MASK 0x3f
165 #define FP_N_DIVISOR_SHIFT 16
166 #define FP_M1_DIVISOR_SHIFT 8
167 #define FP_M2_DIVISOR_SHIFT 0
169 /* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
170 /* Clock values are in units of kHz */
171 #define PLL_REFCLK 48000
172 #define MIN_CLOCK 25000
173 #define MAX_CLOCK 350000
180 /* palette registers */
181 #define PALETTE_A 0x0a000
182 #define PALETTE_B 0x0a800
183 #ifndef PALETTE_8_ENTRIES
184 #define PALETTE_8_ENTRIES 256
186 #define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4)
187 #define PALETTE_10_ENTRIES 128
188 #define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8)
189 #define PALETTE_8_MASK 0xff
190 #define PALETTE_8_RED_SHIFT 16
191 #define PALETTE_8_GREEN_SHIFT 8
192 #define PALETTE_8_BLUE_SHIFT 0
195 #define HTOTAL_A 0x60000
196 #define HBLANK_A 0x60004
197 #define HSYNC_A 0x60008
198 #define VTOTAL_A 0x6000c
199 #define VBLANK_A 0x60010
200 #define VSYNC_A 0x60014
201 #define SRC_SIZE_A 0x6001c
202 #define BCLRPAT_A 0x60020
204 #define HTOTAL_B 0x61000
205 #define HBLANK_B 0x61004
206 #define HSYNC_B 0x61008
207 #define VTOTAL_B 0x6100c
208 #define VBLANK_B 0x61010
209 #define VSYNC_B 0x61014
210 #define SRC_SIZE_B 0x6101c
211 #define BCLRPAT_B 0x61020
213 #define HTOTAL_MASK 0xfff
214 #define HTOTAL_SHIFT 16
215 #define HACTIVE_MASK 0x7ff
216 #define HACTIVE_SHIFT 0
217 #define HBLANKEND_MASK 0xfff
218 #define HBLANKEND_SHIFT 16
219 #define HBLANKSTART_MASK 0xfff
220 #define HBLANKSTART_SHIFT 0
221 #define HSYNCEND_MASK 0xfff
222 #define HSYNCEND_SHIFT 16
223 #define HSYNCSTART_MASK 0xfff
224 #define HSYNCSTART_SHIFT 0
225 #define VTOTAL_MASK 0xfff
226 #define VTOTAL_SHIFT 16
227 #define VACTIVE_MASK 0x7ff
228 #define VACTIVE_SHIFT 0
229 #define VBLANKEND_MASK 0xfff
230 #define VBLANKEND_SHIFT 16
231 #define VBLANKSTART_MASK 0xfff
232 #define VBLANKSTART_SHIFT 0
233 #define VSYNCEND_MASK 0xfff
234 #define VSYNCEND_SHIFT 16
235 #define VSYNCSTART_MASK 0xfff
236 #define VSYNCSTART_SHIFT 0
237 #define SRC_SIZE_HORIZ_MASK 0x7ff
238 #define SRC_SIZE_HORIZ_SHIFT 16
239 #define SRC_SIZE_VERT_MASK 0x7ff
240 #define SRC_SIZE_VERT_SHIFT 0
243 #define ADPA_DAC_ENABLE (1 << 31)
244 #define ADPA_DAC_DISABLE 0
245 #define ADPA_PIPE_SELECT_SHIFT 30
246 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
247 #define ADPA_SETS_HVPOLARITY 0
248 #define ADPA_DPMS_CONTROL_MASK (0x3 << 10)
249 #define ADPA_DPMS_D0 (0x0 << 10)
250 #define ADPA_DPMS_D2 (0x1 << 10)
251 #define ADPA_DPMS_D1 (0x2 << 10)
252 #define ADPA_DPMS_D3 (0x3 << 10)
253 #define ADPA_VSYNC_ACTIVE_SHIFT 4
254 #define ADPA_HSYNC_ACTIVE_SHIFT 3
255 #define ADPA_SYNC_ACTIVE_MASK 1
256 #define ADPA_SYNC_ACTIVE_HIGH 1
257 #define ADPA_SYNC_ACTIVE_LOW 0
263 #define PORT_ENABLE (1 << 31)
264 #define PORT_PIPE_SELECT_SHIFT 30
265 #define PORT_TV_FLAGS_MASK 0xFF
266 #define PORT_TV_FLAGS 0xC4 // ripped from my BIOS
267 // to understand and correct
269 #define DVOA_SRCDIM 0x61124
270 #define DVOB_SRCDIM 0x61144
271 #define DVOC_SRCDIM 0x61164
273 #define PIPEACONF 0x70008
274 #define PIPEBCONF 0x71008
275 #define PIPECONF_ENABLE (1 << 31)
276 #define PIPECONF_DISABLE 0
277 #define PIPECONF_DOUBLE_WIDE (1 << 30)
278 #define PIPECONF_SINGLE_WIDE 0
279 #define PIPECONF_LOCKED (1 << 25)
280 #define PIPECONF_UNLOCKED 0
281 #define PIPECONF_GAMMA (1 << 24)
282 #define PIPECONF_PALETTE 0
284 #define DISPARB 0x70030
285 #define DISPARB_AEND_MASK 0x1ff
286 #define DISPARB_AEND_SHIFT 0
287 #define DISPARB_BEND_MASK 0x3ff
288 #define DISPARB_BEND_SHIFT 9
290 /* Desktop HW cursor */
291 #define CURSOR_CONTROL 0x70080
292 #define CURSOR_ENABLE (1 << 31)
293 #define CURSOR_GAMMA_ENABLE (1 << 30)
294 #define CURSOR_STRIDE_MASK (0x3 << 28)
295 #define CURSOR_STRIDE_256 (0x0 << 28)
296 #define CURSOR_STRIDE_512 (0x1 << 28)
297 #define CURSOR_STRIDE_1K (0x2 << 28)
298 #define CURSOR_STRIDE_2K (0x3 << 28)
299 #define CURSOR_FORMAT_MASK (0x7 << 24)
300 #define CURSOR_FORMAT_2C (0x0 << 24)
301 #define CURSOR_FORMAT_3C (0x1 << 24)
302 #define CURSOR_FORMAT_4C (0x2 << 24)
303 #define CURSOR_FORMAT_ARGB (0x4 << 24)
304 #define CURSOR_FORMAT_XRGB (0x5 << 24)
306 /* Mobile HW cursor (and i810) */
307 #define CURSOR_A_CONTROL CURSOR_CONTROL
308 #define CURSOR_B_CONTROL 0x700c0
309 #define CURSOR_MODE_MASK 0x27
310 #define CURSOR_MODE_DISABLE 0
311 #define CURSOR_MODE_64_3C 0x04
312 #define CURSOR_MODE_64_4C_AX 0x05
313 #define CURSOR_MODE_64_4C 0x06
314 #define CURSOR_MODE_64_32B_AX 0x07
315 #define CURSOR_MODE_64_ARGB_AX 0x27
316 #define CURSOR_PIPE_SELECT_SHIFT 28
317 #define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26)
318 #define CURSOR_MEM_TYPE_LOCAL (1 << 25)
320 /* All platforms (desktop has no pipe B) */
321 #define CURSOR_A_BASEADDR 0x70084
322 #define CURSOR_B_BASEADDR 0x700c4
323 #define CURSOR_BASE_MASK 0xffffff00
325 #define CURSOR_A_POSITION 0x70088
326 #define CURSOR_B_POSITION 0x700c8
327 #define CURSOR_POS_SIGN (1 << 15)
328 #define CURSOR_POS_MASK 0x7ff
329 #define CURSOR_X_SHIFT 0
330 #define CURSOR_Y_SHIFT 16
332 #define CURSOR_A_PALETTE0 0x70090
333 #define CURSOR_A_PALETTE1 0x70094
334 #define CURSOR_A_PALETTE2 0x70098
335 #define CURSOR_A_PALETTE3 0x7009c
336 #define CURSOR_B_PALETTE0 0x700d0
337 #define CURSOR_B_PALETTE1 0x700d4
338 #define CURSOR_B_PALETTE2 0x700d8
339 #define CURSOR_B_PALETTE3 0x700dc
340 #define CURSOR_COLOR_MASK 0xff
341 #define CURSOR_RED_SHIFT 16
342 #define CURSOR_GREEN_SHIFT 8
343 #define CURSOR_BLUE_SHIFT 0
344 #define CURSOR_PALETTE_MASK 0xffffff
347 #define CURSOR_SIZE 0x700a0
348 #define CURSOR_SIZE_MASK 0x3ff
349 #define CURSOR_SIZE_H_SHIFT 0
350 #define CURSOR_SIZE_V_SHIFT 12
352 #define DSPACNTR 0x70180
353 #define DSPBCNTR 0x71180
354 #define DISPPLANE_PLANE_ENABLE (1 << 31)
355 #define DISPPLANE_PLANE_DISABLE 0
356 #define DISPPLANE_GAMMA_ENABLE (1<<30)
357 #define DISPPLANE_GAMMA_DISABLE 0
358 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
359 #define DISPPLANE_8BPP (0x2<<26)
360 #define DISPPLANE_15_16BPP (0x4<<26)
361 #define DISPPLANE_16BPP (0x5<<26)
362 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
363 #define DISPPLANE_32BPP (0x7<<26)
364 #define DISPPLANE_STEREO_ENABLE (1<<25)
365 #define DISPPLANE_STEREO_DISABLE 0
366 #define DISPPLANE_SEL_PIPE_SHIFT 24
367 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
368 #define DISPPLANE_SRC_KEY_DISABLE 0
369 #define DISPPLANE_LINE_DOUBLE (1<<20)
370 #define DISPPLANE_NO_LINE_DOUBLE 0
371 #define DISPPLANE_STEREO_POLARITY_FIRST 0
372 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
374 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
375 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
376 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
377 #define DISPPLANE_SPRITE_ABOVE_OVERLAY 1
379 #define DSPABASE 0x70184
380 #define DSPASTRIDE 0x70188
382 #define DSPBBASE 0x71184
383 #define DSPBSTRIDE 0x71188
385 #define VGACNTRL 0x71400
386 #define VGA_DISABLE (1 << 31)
388 #define VGA_PIPE_SELECT_SHIFT 29
389 #define VGA_PALETTE_READ_SELECT 23
390 #define VGA_PALETTE_A_WRITE_DISABLE (1 << 22)
391 #define VGA_PALETTE_B_WRITE_DISABLE (1 << 21)
392 #define VGA_LEGACY_PALETTE (1 << 20)
393 #define VGA_6BIT_DAC 0
394 #define VGA_8BIT_DAC (1 << 20)
396 #define ADD_ID 0x71408
397 #define ADD_ID_MASK 0xff
399 /* BIOS scratch area registers (830M and 845G). */
408 /* BIOS scratch area registers (852GM, 855GM, 865G). */
409 #define SWF00 0x70410
410 #define SWF01 0x70414
411 #define SWF02 0x70418
412 #define SWF03 0x7041c
413 #define SWF04 0x70420
414 #define SWF05 0x70424
415 #define SWF06 0x70428
425 #define SWF30 0x72414
426 #define SWF31 0x72418
427 #define SWF32 0x7241c
429 /* Memory Commands */
430 #define MI_NOOP (0x00 << 23)
431 #define MI_NOOP_WRITE_ID (1 << 22)
432 #define MI_NOOP_ID_MASK ((1 << 22) - 1)
434 #define MI_FLUSH (0x04 << 23)
435 #define MI_WRITE_DIRTY_STATE (1 << 4)
436 #define MI_END_SCENE (1 << 3)
437 #define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
438 #define MI_INVALIDATE_MAP_CACHE (1 << 0)
440 #define MI_STORE_DWORD_IMM ((0x20 << 23) | 1)
443 #define COLOR_BLT_CMD ((2 << 29) | (0x40 << 22) | 3)
444 #define XY_COLOR_BLT_CMD ((2 << 29) | (0x50 << 22) | 4)
445 #define XY_SETUP_CLIP_BLT_CMD ((2 << 29) | (0x03 << 22) | 1)
446 #define XY_SRC_COPY_BLT_CMD ((2 << 29) | (0x53 << 22) | 6)
447 #define SRC_COPY_BLT_CMD ((2 << 29) | (0x43 << 22) | 4)
448 #define XY_MONO_PAT_BLT_CMD ((2 << 29) | (0x52 << 22) | 7)
449 #define XY_MONO_SRC_BLT_CMD ((2 << 29) | (0x54 << 22) | 6)
450 #define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) | (0x71 << 22) | 5)
451 #define TXT_IMM_BLT_CMD ((2 << 29) | (0x30 << 22) | 2)
452 #define SETUP_BLT_CMD ((2 << 29) | (0x00 << 22) | 6)
454 #define DW_LENGTH_MASK 0xff
456 #define WRITE_ALPHA (1 << 21)
457 #define WRITE_RGB (1 << 20)
458 #define VERT_SEED (3 << 8)
459 #define HORIZ_SEED (3 << 12)
461 #define COLOR_DEPTH_8 (0 << 24)
462 #define COLOR_DEPTH_16 (1 << 24)
463 #define COLOR_DEPTH_32 (3 << 24)
465 #define SRC_ROP_GXCOPY 0xcc
466 #define SRC_ROP_GXXOR 0x66
468 #define PAT_ROP_GXCOPY 0xf0
469 #define PAT_ROP_GXXOR 0x5a
471 #define PITCH_SHIFT 0
473 #define WIDTH_SHIFT 0
474 #define HEIGHT_SHIFT 16
477 #define MAX_MONO_IMM_SIZE 128
483 #define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
484 #define INREG16(addr) readw((u16 __iomem *)(dinfo->mmio_base + (addr)))
485 #define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
486 #define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
488 #define OUTREG16(addr, val) writew((val),(u16 __iomem *)(dinfo->mmio_base + \
490 #define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \
493 /* Ring buffer macros */
494 #define OUT_RING(n) do { \
495 writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
496 dinfo->ring_tail += 4; \
497 dinfo->ring_tail &= dinfo->ring_tail_mask; \
500 #define START_RING(n) do { \
501 if (dinfo->ring_space < (n) * 4) \
502 wait_ring(dinfo,(n) * 4); \
503 dinfo->ring_space -= (n) * 4; \
506 #define ADVANCE_RING() do { \
507 OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
510 #define DO_RING_IDLE() do { \
513 head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
514 tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
516 } while (head != tail); \
520 /* function protoypes */
521 extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
522 extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
524 extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
525 extern const char *intelfbhw_dvo_to_string(int dvo);
526 extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
527 struct fb_var_screeninfo *var);
528 extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
529 struct fb_info *info);
530 extern void intelfbhw_do_blank(int blank, struct fb_info *info);
531 extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
532 unsigned red, unsigned green, unsigned blue,
534 extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
535 struct intelfb_hwstate *hw, int flag);
536 extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
537 struct intelfb_hwstate *hw);
538 extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
539 struct intelfb_hwstate *hw,
540 struct fb_var_screeninfo *var);
541 extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
542 const struct intelfb_hwstate *hw, int blank);
543 extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
544 extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
545 extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
546 extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
547 u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
549 extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
550 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
552 extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
553 u32 w, u32 h, const u8* cdat, u32 x, u32 y,
555 extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
556 extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
557 extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
558 extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
559 extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
561 extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
562 int height, u8 *data);
563 extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
564 extern int intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable);
565 extern void intelfbhw_disable_irq(struct intelfb_info *dinfo);
567 #endif /* _INTELFBHW_H */