2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <asm/pgtable.h>
49 #include <linux/zorro.h>
52 #include <linux/pci.h>
55 #include <asm/amigahw.h>
57 #ifdef CONFIG_PPC_PREP
58 #include <asm/machdep.h>
59 #define isPReP machine_is(prep)
64 #include <video/vga.h>
65 #include <video/cirrus.h>
67 /*****************************************************************
69 * debugging and utility macros
73 /* disable runtime assertions? */
74 /* #define CIRRUSFB_NDEBUG */
76 /* debugging assertions */
77 #ifndef CIRRUSFB_NDEBUG
78 #define assert(expr) \
80 printk("Assertion failed! %s,%s,%s,line=%d\n", \
81 #expr, __FILE__, __func__, __LINE__); \
87 #define MB_ (1024 * 1024)
89 /*****************************************************************
99 BT_PICCOLO, /* GD5426 */
100 BT_PICASSO, /* GD5426 or GD5428 */
101 BT_SPECTRUM, /* GD5426 or GD5428 */
102 BT_PICASSO4, /* GD5446 */
103 BT_ALPINE, /* GD543x/4x */
105 BT_LAGUNA, /* GD5462/64 */
106 BT_LAGUNAB, /* GD5465 */
110 * per-board-type information, used for enumerating and abstracting
111 * chip-specific information
112 * NOTE: MUST be in the same order as enum cirrus_board in order to
113 * use direct indexing on this array
114 * NOTE: '__initdata' cannot be used as some of this info
115 * is required at runtime. Maybe separate into an init-only and
118 static const struct cirrusfb_board_info_rec {
119 char *name; /* ASCII name of chipset */
120 long maxclock[5]; /* maximum video clock */
121 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
122 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
123 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
124 /* construct bit 19 of screen start address */
125 bool scrn_start_bit19 : 1;
127 /* initial SR07 value, then for each mode */
129 unsigned char sr07_1bpp;
130 unsigned char sr07_1bpp_mux;
131 unsigned char sr07_8bpp;
132 unsigned char sr07_8bpp_mux;
134 unsigned char sr1f; /* SR1F VGA initial register value */
135 } cirrusfb_board_info[] = {
140 /* the SD64/P4 have a higher max. videoclock */
141 135100, 135100, 85500, 85500, 0
145 .scrn_start_bit19 = true,
152 .name = "CL Piccolo",
155 90000, 90000, 90000, 90000, 90000
159 .scrn_start_bit19 = false,
166 .name = "CL Picasso",
169 90000, 90000, 90000, 90000, 90000
173 .scrn_start_bit19 = false,
180 .name = "CL Spectrum",
183 90000, 90000, 90000, 90000, 90000
187 .scrn_start_bit19 = false,
194 .name = "CL Picasso4",
196 135100, 135100, 85500, 85500, 0
200 .scrn_start_bit19 = true,
203 .sr07_1bpp_mux = 0xA6,
205 .sr07_8bpp_mux = 0xA7,
211 /* for the GD5430. GD5446 can do more... */
212 85500, 85500, 50000, 28500, 0
216 .scrn_start_bit19 = true,
219 .sr07_1bpp_mux = 0xA6,
221 .sr07_8bpp_mux = 0xA7,
227 135100, 200000, 200000, 135100, 135100
231 .scrn_start_bit19 = true,
240 /* taken from X11 code */
241 170000, 170000, 170000, 170000, 135100,
245 .scrn_start_bit19 = true,
248 .name = "CL Laguna AGP",
250 /* taken from X11 code */
251 170000, 250000, 170000, 170000, 135100,
255 .scrn_start_bit19 = true,
260 #define CHIP(id, btype) \
261 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
263 static struct pci_device_id cirrusfb_pci_table[] = {
264 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
265 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
266 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
267 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
268 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
269 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
271 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
272 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
273 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
274 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
277 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
279 #endif /* CONFIG_PCI */
282 static const struct zorro_device_id cirrusfb_zorro_table[] = {
284 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
285 .driver_data = BT_SD64,
287 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
288 .driver_data = BT_PICCOLO,
290 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
291 .driver_data = BT_PICASSO,
293 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
294 .driver_data = BT_SPECTRUM,
296 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
297 .driver_data = BT_PICASSO4,
302 static const struct {
305 } cirrusfb_zorro_table2[] = {
307 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
311 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
315 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
319 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
327 #endif /* CONFIG_ZORRO */
329 #ifdef CIRRUSFB_DEBUG
330 enum cirrusfb_dbg_reg_class {
334 #endif /* CIRRUSFB_DEBUG */
336 /* info about board */
337 struct cirrusfb_info {
339 u8 __iomem *laguna_mmio;
340 enum cirrus_board btype;
341 unsigned char SFR; /* Shadow of special function register */
345 u32 pseudo_palette[16];
347 void (*unmap)(struct fb_info *info);
350 static int noaccel __devinitdata;
351 static char *mode_option __devinitdata = "640x480@60";
353 /****************************************************************************/
354 /**** BEGIN PROTOTYPES ******************************************************/
356 /*--- Interface used by the world ------------------------------------------*/
357 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
358 struct fb_info *info);
360 /*--- Internal routines ----------------------------------------------------*/
361 static void init_vgachip(struct fb_info *info);
362 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
363 static void WGen(const struct cirrusfb_info *cinfo,
364 int regnum, unsigned char val);
365 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
366 static void AttrOn(const struct cirrusfb_info *cinfo);
367 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
368 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
369 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
370 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
371 unsigned char red, unsigned char green, unsigned char blue);
373 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
374 unsigned char *red, unsigned char *green,
375 unsigned char *blue);
377 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
378 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
379 u_short curx, u_short cury,
380 u_short destx, u_short desty,
381 u_short width, u_short height,
382 u_short line_length);
383 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
384 u_short x, u_short y,
385 u_short width, u_short height,
386 u32 fg_color, u32 bg_color,
387 u_short line_length, u_char blitmode);
389 static void bestclock(long freq, int *nom, int *den, int *div);
391 #ifdef CIRRUSFB_DEBUG
392 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
393 static void cirrusfb_dbg_print_regs(struct fb_info *info,
395 enum cirrusfb_dbg_reg_class reg_class, ...);
396 #endif /* CIRRUSFB_DEBUG */
398 /*** END PROTOTYPES ********************************************************/
399 /*****************************************************************************/
400 /*** BEGIN Interface Used by the World ***************************************/
402 static inline int is_laguna(const struct cirrusfb_info *cinfo)
404 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
407 static int opencount;
409 /*--- Open /dev/fbx ---------------------------------------------------------*/
410 static int cirrusfb_open(struct fb_info *info, int user)
412 if (opencount++ == 0)
413 switch_monitor(info->par, 1);
417 /*--- Close /dev/fbx --------------------------------------------------------*/
418 static int cirrusfb_release(struct fb_info *info, int user)
420 if (--opencount == 0)
421 switch_monitor(info->par, 0);
425 /**** END Interface used by the World *************************************/
426 /****************************************************************************/
427 /**** BEGIN Hardware specific Routines **************************************/
429 /* Check if the MCLK is not a better clock source */
430 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
432 struct cirrusfb_info *cinfo = info->par;
433 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
435 /* Read MCLK value */
436 mclk = (14318 * mclk) >> 3;
437 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
439 /* Determine if we should use MCLK instead of VCLK, and if so, what we
440 * should divide it by to get VCLK
443 if (abs(freq - mclk) < 250) {
444 dev_dbg(info->device, "Using VCLK = MCLK\n");
446 } else if (abs(freq - (mclk / 2)) < 250) {
447 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
454 static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
455 struct fb_info *info)
459 struct cirrusfb_info *cinfo = info->par;
460 unsigned maxclockidx = var->bits_per_pixel >> 3;
462 /* convert from ps to kHz */
463 freq = PICOS2KHZ(var->pixclock);
465 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
467 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
468 cinfo->multiplexing = 0;
470 /* If the frequency is greater than we can support, we might be able
471 * to use multiplexing for the video mode */
472 if (freq > maxclock) {
473 switch (cinfo->btype) {
476 cinfo->multiplexing = 1;
480 dev_err(info->device,
481 "Frequency greater than maxclock (%ld kHz)\n",
487 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
488 * the VCLK is double the pixel clock. */
489 switch (var->bits_per_pixel) {
492 if (var->xres <= 800)
493 /* Xbh has this type of clock for 32-bit */
501 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
502 struct fb_info *info)
505 /* memory size in pixels */
506 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
508 switch (var->bits_per_pixel) {
512 var->green = var->red;
513 var->blue = var->red;
519 var->green = var->red;
520 var->blue = var->red;
526 var->green.offset = -3;
527 var->blue.offset = 8;
529 var->red.offset = 11;
530 var->green.offset = 5;
531 var->blue.offset = 0;
534 var->green.length = 6;
535 var->blue.length = 5;
541 var->green.offset = 8;
542 var->blue.offset = 16;
544 var->red.offset = 16;
545 var->green.offset = 8;
546 var->blue.offset = 0;
549 var->green.length = 8;
550 var->blue.length = 8;
554 dev_dbg(info->device,
555 "Unsupported bpp size: %d\n", var->bits_per_pixel);
557 /* should never occur */
561 if (var->xres_virtual < var->xres)
562 var->xres_virtual = var->xres;
563 /* use highest possible virtual resolution */
564 if (var->yres_virtual == -1) {
565 var->yres_virtual = pixels / var->xres_virtual;
567 dev_info(info->device,
568 "virtual resolution set to maximum of %dx%d\n",
569 var->xres_virtual, var->yres_virtual);
571 if (var->yres_virtual < var->yres)
572 var->yres_virtual = var->yres;
574 if (var->xres_virtual * var->yres_virtual > pixels) {
575 dev_err(info->device, "mode %dx%dx%d rejected... "
576 "virtual resolution too high to fit into video memory!\n",
577 var->xres_virtual, var->yres_virtual,
578 var->bits_per_pixel);
582 if (var->xoffset < 0)
584 if (var->yoffset < 0)
587 /* truncate xoffset and yoffset to maximum if too high */
588 if (var->xoffset > var->xres_virtual - var->xres)
589 var->xoffset = var->xres_virtual - var->xres - 1;
590 if (var->yoffset > var->yres_virtual - var->yres)
591 var->yoffset = var->yres_virtual - var->yres - 1;
594 var->green.msb_right =
595 var->blue.msb_right =
598 var->transp.msb_right = 0;
601 if (var->vmode & FB_VMODE_DOUBLE)
603 else if (var->vmode & FB_VMODE_INTERLACED)
604 yres = (yres + 1) / 2;
607 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
608 "special treatment required! (TODO)\n");
612 if (cirrusfb_check_pixclock(var, info))
618 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
620 struct cirrusfb_info *cinfo = info->par;
621 unsigned char old1f, old1e;
623 assert(cinfo != NULL);
624 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
627 dev_dbg(info->device, "Set %s as pixclock source.\n",
628 (div == 2) ? "MCLK/2" : "MCLK");
630 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
634 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
636 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
639 /*************************************************************************
640 cirrusfb_set_par_foo()
642 actually writes the values for a new video mode into the hardware,
643 **************************************************************************/
644 static int cirrusfb_set_par_foo(struct fb_info *info)
646 struct cirrusfb_info *cinfo = info->par;
647 struct fb_var_screeninfo *var = &info->var;
648 u8 __iomem *regbase = cinfo->regbase;
651 const struct cirrusfb_board_info_rec *bi;
652 int hdispend, hsyncstart, hsyncend, htotal;
653 int yres, vdispend, vsyncstart, vsyncend, vtotal;
656 unsigned int control = 0, format = 0, threshold = 0;
658 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
659 var->xres, var->yres, var->bits_per_pixel);
661 switch (var->bits_per_pixel) {
663 info->fix.line_length = var->xres_virtual / 8;
664 info->fix.visual = FB_VISUAL_MONO10;
668 info->fix.line_length = var->xres_virtual;
669 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
674 info->fix.line_length = var->xres_virtual *
675 var->bits_per_pixel >> 3;
676 info->fix.visual = FB_VISUAL_TRUECOLOR;
679 info->fix.type = FB_TYPE_PACKED_PIXELS;
683 bi = &cirrusfb_board_info[cinfo->btype];
685 hsyncstart = var->xres + var->right_margin;
686 hsyncend = hsyncstart + var->hsync_len;
687 htotal = (hsyncend + var->left_margin) / 8 - 5;
688 hdispend = var->xres / 8 - 1;
689 hsyncstart = hsyncstart / 8 + 1;
690 hsyncend = hsyncend / 8 + 1;
693 vsyncstart = yres + var->lower_margin;
694 vsyncend = vsyncstart + var->vsync_len;
695 vtotal = vsyncend + var->upper_margin;
698 if (var->vmode & FB_VMODE_DOUBLE) {
703 } else if (var->vmode & FB_VMODE_INTERLACED) {
704 yres = (yres + 1) / 2;
705 vsyncstart = (vsyncstart + 1) / 2;
706 vsyncend = (vsyncend + 1) / 2;
707 vtotal = (vtotal + 1) / 2;
720 if (cinfo->multiplexing) {
726 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
727 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
729 /* if debugging is enabled, all parameters get output before writing */
730 dev_dbg(info->device, "CRT0: %d\n", htotal);
731 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
733 dev_dbg(info->device, "CRT1: %d\n", hdispend);
734 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
736 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
737 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
739 /* + 128: Compatible read */
740 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
741 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
742 128 + ((htotal + 5) % 32));
744 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
745 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
748 if ((htotal + 5) & 32)
750 dev_dbg(info->device, "CRT5: %d\n", tmp);
751 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
753 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
754 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
756 tmp = 16; /* LineCompare bit #9 */
761 if (vsyncstart & 256)
763 if ((vdispend + 1) & 256)
769 if (vsyncstart & 512)
771 dev_dbg(info->device, "CRT7: %d\n", tmp);
772 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
774 tmp = 0x40; /* LineCompare bit #8 */
775 if ((vdispend + 1) & 512)
777 if (var->vmode & FB_VMODE_DOUBLE)
779 dev_dbg(info->device, "CRT9: %d\n", tmp);
780 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
782 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
783 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
785 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
786 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
788 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
789 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
791 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
792 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
794 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
795 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
797 dev_dbg(info->device, "CRT18: 0xff\n");
798 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
801 if (var->vmode & FB_VMODE_INTERLACED)
803 if ((htotal + 5) & 64)
805 if ((htotal + 5) & 128)
812 dev_dbg(info->device, "CRT1a: %d\n", tmp);
813 vga_wcrt(regbase, CL_CRT1A, tmp);
815 freq = PICOS2KHZ(var->pixclock);
816 if (cinfo->btype == BT_ALPINE && var->bits_per_pixel == 24)
819 bestclock(freq, &nom, &den, &div);
821 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
822 freq, nom, den, div);
825 /* hardware RefClock: 14.31818 MHz */
826 /* formula: VClk = (OSC * N) / (D * (1+P)) */
827 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
829 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4) {
830 /* if freq is close to mclk or mclk/2 select mclk
833 int divMCLK = cirrusfb_check_mclk(info, freq);
836 cirrusfb_set_mclk_as_source(info, divMCLK);
839 if (is_laguna(cinfo)) {
840 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
841 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
842 unsigned short tile_control;
844 if (cinfo->btype == BT_LAGUNAB) {
845 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
846 tile_control &= ~0x80;
847 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
850 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
851 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
852 control = fb_readw(cinfo->laguna_mmio + 0x402);
853 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
856 threshold &= 0xffe0 & 0x3fbf;
862 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
863 if ((cinfo->btype == BT_SD64) ||
864 (cinfo->btype == BT_ALPINE) ||
865 (cinfo->btype == BT_GD5480))
868 dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
869 /* Laguna chipset has reversed clock registers */
870 if (is_laguna(cinfo)) {
871 vga_wseq(regbase, CL_SEQRE, tmp);
872 vga_wseq(regbase, CL_SEQR1E, nom);
874 vga_wseq(regbase, CL_SEQRB, nom);
875 vga_wseq(regbase, CL_SEQR1B, tmp);
881 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
883 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
884 * address wrap, no compat. */
885 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
887 /* don't know if it would hurt to also program this if no interlaced */
888 /* mode is used, but I feel better this way.. :-) */
889 if (var->vmode & FB_VMODE_INTERLACED)
890 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
892 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
894 /* adjust horizontal/vertical sync type (low/high) */
895 /* enable display memory & CRTC I/O address for color mode */
897 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
899 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
901 if (is_laguna(cinfo))
903 WGen(cinfo, VGA_MIS_W, tmp);
905 /* text cursor on and start line */
906 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
907 /* text cursor end line */
908 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
910 /******************************************************
916 /* programming for different color depths */
917 if (var->bits_per_pixel == 1) {
918 dev_dbg(info->device, "preparing for 1 bit deep display\n");
919 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
922 switch (cinfo->btype) {
930 vga_wseq(regbase, CL_SEQR7,
931 cinfo->multiplexing ?
932 bi->sr07_1bpp_mux : bi->sr07_1bpp);
937 vga_wseq(regbase, CL_SEQR7,
938 vga_rseq(regbase, CL_SEQR7) & ~0x01);
942 dev_warn(info->device, "unknown Board\n");
946 /* Extended Sequencer Mode */
947 switch (cinfo->btype) {
949 /* setting the SEQRF on SD64 is not necessary
953 vga_wseq(regbase, CL_SEQR1F, 0x1a);
958 /* ### ueberall 0x22? */
959 /* ##vorher 1c MCLK select */
960 vga_wseq(regbase, CL_SEQR1F, 0x22);
961 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
962 vga_wseq(regbase, CL_SEQRF, 0xb0);
966 /* ##vorher 22 MCLK select */
967 vga_wseq(regbase, CL_SEQR1F, 0x22);
968 /* ## vorher d0 avoid FIFO underruns..? */
969 vga_wseq(regbase, CL_SEQRF, 0xd0);
981 dev_warn(info->device, "unknown Board\n");
985 /* pixel mask: pass-through for first plane */
986 WGen(cinfo, VGA_PEL_MSK, 0x01);
987 if (cinfo->multiplexing)
988 /* hidden dac reg: 1280x1024 */
991 /* hidden dac: nothing */
993 /* memory mode: odd/even, ext. memory */
994 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
995 /* plane mask: only write to first plane */
996 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
999 /******************************************************
1005 else if (var->bits_per_pixel == 8) {
1006 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1007 switch (cinfo->btype) {
1015 vga_wseq(regbase, CL_SEQR7,
1016 cinfo->multiplexing ?
1017 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1022 vga_wseq(regbase, CL_SEQR7,
1023 vga_rseq(regbase, CL_SEQR7) | 0x01);
1028 dev_warn(info->device, "unknown Board\n");
1032 switch (cinfo->btype) {
1035 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1041 /* ### vorher 1c MCLK select */
1042 vga_wseq(regbase, CL_SEQR1F, 0x22);
1043 /* Fast Page-Mode writes */
1044 vga_wseq(regbase, CL_SEQRF, 0xb0);
1049 /* ### INCOMPLETE!! */
1050 vga_wseq(regbase, CL_SEQRF, 0xb8);
1053 /* We already set SRF and SR1F */
1063 dev_warn(info->device, "unknown board\n");
1067 /* mode register: 256 color mode */
1068 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1069 if (cinfo->multiplexing)
1070 /* hidden dac reg: 1280x1024 */
1073 /* hidden dac: nothing */
1077 /******************************************************
1083 else if (var->bits_per_pixel == 16) {
1084 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1085 switch (cinfo->btype) {
1087 /* Extended Sequencer Mode: 256c col. mode */
1088 vga_wseq(regbase, CL_SEQR7, 0xf7);
1090 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1095 vga_wseq(regbase, CL_SEQR7, 0x87);
1096 /* Fast Page-Mode writes */
1097 vga_wseq(regbase, CL_SEQRF, 0xb0);
1099 vga_wseq(regbase, CL_SEQR1F, 0x22);
1103 vga_wseq(regbase, CL_SEQR7, 0x27);
1104 /* Fast Page-Mode writes */
1105 vga_wseq(regbase, CL_SEQRF, 0xb0);
1107 vga_wseq(regbase, CL_SEQR1F, 0x22);
1112 vga_wseq(regbase, CL_SEQR7, 0xa7);
1116 vga_wseq(regbase, CL_SEQR7, 0x17);
1117 /* We already set SRF and SR1F */
1122 vga_wseq(regbase, CL_SEQR7,
1123 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1130 dev_warn(info->device, "unknown Board\n");
1134 /* mode register: 256 color mode */
1135 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1137 WHDR(cinfo, 0xc1); /* Copy Xbh */
1138 #elif defined(CONFIG_ZORRO)
1139 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1140 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1144 /******************************************************
1150 else if (var->bits_per_pixel == 24) {
1151 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1152 switch (cinfo->btype) {
1154 /* Extended Sequencer Mode: 256c col. mode */
1155 vga_wseq(regbase, CL_SEQR7, 0xf5);
1157 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1162 vga_wseq(regbase, CL_SEQR7, 0x85);
1163 /* Fast Page-Mode writes */
1164 vga_wseq(regbase, CL_SEQRF, 0xb0);
1166 vga_wseq(regbase, CL_SEQR1F, 0x22);
1170 vga_wseq(regbase, CL_SEQR7, 0x25);
1171 /* Fast Page-Mode writes */
1172 vga_wseq(regbase, CL_SEQRF, 0xb0);
1174 vga_wseq(regbase, CL_SEQR1F, 0x22);
1179 vga_wseq(regbase, CL_SEQR7, 0xa5);
1183 vga_wseq(regbase, CL_SEQR7, 0x15);
1184 /* We already set SRF and SR1F */
1189 vga_wseq(regbase, CL_SEQR7,
1190 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1197 dev_warn(info->device, "unknown Board\n");
1201 /* mode register: 256 color mode */
1202 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1203 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1207 /******************************************************
1209 * unknown/unsupported bpp
1214 dev_err(info->device,
1215 "What's this? requested color depth == %d.\n",
1216 var->bits_per_pixel);
1218 pitch = info->fix.line_length >> 3;
1219 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1222 tmp |= 0x10; /* offset overflow bit */
1224 /* screen start addr #16-18, fastpagemode cycles */
1225 vga_wcrt(regbase, CL_CRT1B, tmp);
1227 /* screen start address bit 19 */
1228 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1229 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1231 if (is_laguna(cinfo)) {
1233 if ((htotal + 5) & 256)
1237 if (hsyncstart & 256)
1241 if (vdispend & 1024)
1243 if (vsyncstart & 1024)
1246 vga_wcrt(regbase, CL_CRT1E, tmp);
1247 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1251 vga_wattr(regbase, CL_AR33, 0);
1253 /* [ EGS: SetOffset(); ] */
1254 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1257 if (is_laguna(cinfo)) {
1259 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1260 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1261 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1263 /* finally, turn on everything - turn off "FullBandwidth" bit */
1264 /* also, set "DotClock%2" bit where requested */
1267 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1268 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1272 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1273 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1275 #ifdef CIRRUSFB_DEBUG
1276 cirrusfb_dbg_reg_dump(info, NULL);
1282 /* for some reason incomprehensible to me, cirrusfb requires that you write
1283 * the registers twice for the settings to take..grr. -dte */
1284 static int cirrusfb_set_par(struct fb_info *info)
1286 cirrusfb_set_par_foo(info);
1287 return cirrusfb_set_par_foo(info);
1290 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1291 unsigned blue, unsigned transp,
1292 struct fb_info *info)
1294 struct cirrusfb_info *cinfo = info->par;
1299 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1301 red >>= (16 - info->var.red.length);
1302 green >>= (16 - info->var.green.length);
1303 blue >>= (16 - info->var.blue.length);
1307 v = (red << info->var.red.offset) |
1308 (green << info->var.green.offset) |
1309 (blue << info->var.blue.offset);
1311 cinfo->pseudo_palette[regno] = v;
1315 if (info->var.bits_per_pixel == 8)
1316 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1322 /*************************************************************************
1323 cirrusfb_pan_display()
1325 performs display panning - provided hardware permits this
1326 **************************************************************************/
1327 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1328 struct fb_info *info)
1332 unsigned char tmp, xpix;
1333 struct cirrusfb_info *cinfo = info->par;
1335 dev_dbg(info->device,
1336 "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1338 /* no range checks for xoffset and yoffset, */
1339 /* as fb_pan_display has already done this */
1340 if (var->vmode & FB_VMODE_YWRAP)
1343 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1345 base = var->yoffset * info->fix.line_length + xoffset;
1347 if (info->var.bits_per_pixel == 1) {
1348 /* base is already correct */
1349 xpix = (unsigned char) (var->xoffset % 8);
1352 xpix = (unsigned char) ((xoffset % 4) * 2);
1355 if (!is_laguna(cinfo))
1356 cirrusfb_WaitBLT(cinfo->regbase);
1358 /* lower 8 + 8 bits of screen start address */
1359 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1360 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1362 /* 0xf2 is %11110010, exclude tmp bits */
1363 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1364 /* construct bits 16, 17 and 18 of screen start address */
1372 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1374 /* construct bit 19 of screen start address */
1375 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1376 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1377 if (is_laguna(cinfo))
1378 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1380 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1381 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1384 /* write pixel panning value to AR33; this does not quite work in 8bpp
1386 * ### Piccolo..? Will this work?
1388 if (info->var.bits_per_pixel == 1)
1389 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1394 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1397 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1398 * then the caller blanks by setting the CLUT (Color Look Up Table)
1399 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1400 * failed due to e.g. a video mode which doesn't support it.
1401 * Implements VESA suspend and powerdown modes on hardware that
1402 * supports disabling hsync/vsync:
1403 * blank_mode == 2: suspend vsync
1404 * blank_mode == 3: suspend hsync
1405 * blank_mode == 4: powerdown
1408 struct cirrusfb_info *cinfo = info->par;
1409 int current_mode = cinfo->blank_mode;
1411 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1413 if (info->state != FBINFO_STATE_RUNNING ||
1414 current_mode == blank_mode) {
1415 dev_dbg(info->device, "EXIT, returning 0\n");
1420 if (current_mode == FB_BLANK_NORMAL ||
1421 current_mode == FB_BLANK_UNBLANK)
1422 /* clear "FullBandwidth" bit */
1425 /* set "FullBandwidth" bit */
1428 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1429 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1431 switch (blank_mode) {
1432 case FB_BLANK_UNBLANK:
1433 case FB_BLANK_NORMAL:
1436 case FB_BLANK_VSYNC_SUSPEND:
1439 case FB_BLANK_HSYNC_SUSPEND:
1442 case FB_BLANK_POWERDOWN:
1446 dev_dbg(info->device, "EXIT, returning 1\n");
1450 vga_wgfx(cinfo->regbase, CL_GRE, val);
1452 cinfo->blank_mode = blank_mode;
1453 dev_dbg(info->device, "EXIT, returning 0\n");
1455 /* Let fbcon do a soft blank for us */
1456 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1459 /**** END Hardware specific Routines **************************************/
1460 /****************************************************************************/
1461 /**** BEGIN Internal Routines ***********************************************/
1463 static void init_vgachip(struct fb_info *info)
1465 struct cirrusfb_info *cinfo = info->par;
1466 const struct cirrusfb_board_info_rec *bi;
1468 assert(cinfo != NULL);
1470 bi = &cirrusfb_board_info[cinfo->btype];
1472 /* reset board globally */
1473 switch (cinfo->btype) {
1492 /* disable flickerfixer */
1493 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1496 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1497 case BT_GD5480: /* fall through */
1498 /* from Klaus' NetBSD driver: */
1499 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1500 case BT_ALPINE: /* fall through */
1501 /* put blitter into 542x compat */
1502 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1507 /* Nothing to do to reset the board. */
1511 dev_err(info->device, "Warning: Unknown board type\n");
1515 /* make sure RAM size set by this point */
1516 assert(info->screen_size > 0);
1518 /* the P4 is not fully initialized here; I rely on it having been */
1519 /* inited under AmigaOS already, which seems to work just fine */
1520 /* (Klaus advised to do it this way) */
1522 if (cinfo->btype != BT_PICASSO4) {
1523 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1524 WGen(cinfo, CL_POS102, 0x01);
1525 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1527 if (cinfo->btype != BT_SD64)
1528 WGen(cinfo, CL_VSSM2, 0x01);
1530 /* reset sequencer logic */
1531 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1533 /* FullBandwidth (video off) and 8/9 dot clock */
1534 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1536 /* "magic cookie" - doesn't make any sense to me.. */
1537 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1538 /* unlock all extension registers */
1539 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1541 switch (cinfo->btype) {
1543 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1550 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1553 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1554 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1558 /* plane mask: nothing */
1559 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1560 /* character map select: doesn't even matter in gx mode */
1561 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1562 /* memory mode: chain4, ext. memory */
1563 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1565 /* controller-internal base address of video memory */
1567 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1569 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1570 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1572 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1573 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1574 /* graphics cursor Y position (..."... ) */
1575 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1576 /* graphics cursor attributes */
1577 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1578 /* graphics cursor pattern address */
1579 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1581 /* writing these on a P4 might give problems.. */
1582 if (cinfo->btype != BT_PICASSO4) {
1583 /* configuration readback and ext. color */
1584 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1585 /* signature generator */
1586 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1589 /* MCLK select etc. */
1591 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1593 /* Screen A preset row scan: none */
1594 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1595 /* Text cursor start: disable text cursor */
1596 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1597 /* Text cursor end: - */
1598 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1599 /* text cursor location high: 0 */
1600 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1601 /* text cursor location low: 0 */
1602 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1604 /* Underline Row scanline: - */
1605 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1606 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1607 /* ext. display controls: ext.adr. wrap */
1608 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1610 /* Set/Reset registes: - */
1611 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1612 /* Set/Reset enable: - */
1613 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1614 /* Color Compare: - */
1615 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1616 /* Data Rotate: - */
1617 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1618 /* Read Map Select: - */
1619 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1620 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1621 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1622 /* Miscellaneous: memory map base address, graphics mode */
1623 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1624 /* Color Don't care: involve all planes */
1625 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1626 /* Bit Mask: no mask at all */
1627 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1629 if (cinfo->btype == BT_ALPINE || is_laguna(cinfo))
1630 /* (5434 can't have bit 3 set for bitblt) */
1631 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1633 /* Graphics controller mode extensions: finer granularity,
1634 * 8byte data latches
1636 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1638 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1639 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1640 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1641 /* Background color byte 1: - */
1642 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1643 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1645 /* Attribute Controller palette registers: "identity mapping" */
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1647 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1648 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1649 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1650 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1651 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1652 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1653 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1654 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1655 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1656 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1657 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1658 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1659 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1660 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1661 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1663 /* Attribute Controller mode: graphics mode */
1664 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1665 /* Overscan color reg.: reg. 0 */
1666 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1667 /* Color Plane enable: Enable all 4 planes */
1668 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1669 /* Color Select: - */
1670 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1672 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1674 /* BLT Start/status: Blitter reset */
1675 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1676 /* - " - : "end-of-reset" */
1677 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1680 WHDR(cinfo, 0); /* Hidden DAC register: - */
1684 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1686 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1687 static int IsOn = 0; /* XXX not ok for multiple boards */
1689 if (cinfo->btype == BT_PICASSO4)
1690 return; /* nothing to switch */
1691 if (cinfo->btype == BT_ALPINE)
1692 return; /* nothing to switch */
1693 if (cinfo->btype == BT_GD5480)
1694 return; /* nothing to switch */
1695 if (cinfo->btype == BT_PICASSO) {
1696 if ((on && !IsOn) || (!on && IsOn))
1701 switch (cinfo->btype) {
1703 WSFR(cinfo, cinfo->SFR | 0x21);
1706 WSFR(cinfo, cinfo->SFR | 0x28);
1711 default: /* do nothing */ break;
1714 switch (cinfo->btype) {
1716 WSFR(cinfo, cinfo->SFR & 0xde);
1719 WSFR(cinfo, cinfo->SFR & 0xd7);
1724 default: /* do nothing */
1728 #endif /* CONFIG_ZORRO */
1731 /******************************************/
1732 /* Linux 2.6-style accelerated functions */
1733 /******************************************/
1735 static int cirrusfb_sync(struct fb_info *info)
1737 struct cirrusfb_info *cinfo = info->par;
1739 if (!is_laguna(cinfo)) {
1740 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1746 static void cirrusfb_fillrect(struct fb_info *info,
1747 const struct fb_fillrect *region)
1749 struct fb_fillrect modded;
1751 struct cirrusfb_info *cinfo = info->par;
1752 int m = info->var.bits_per_pixel;
1753 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1754 cinfo->pseudo_palette[region->color] : region->color;
1756 if (info->state != FBINFO_STATE_RUNNING)
1758 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1759 cfb_fillrect(info, region);
1763 vxres = info->var.xres_virtual;
1764 vyres = info->var.yres_virtual;
1766 memcpy(&modded, region, sizeof(struct fb_fillrect));
1768 if (!modded.width || !modded.height ||
1769 modded.dx >= vxres || modded.dy >= vyres)
1772 if (modded.dx + modded.width > vxres)
1773 modded.width = vxres - modded.dx;
1774 if (modded.dy + modded.height > vyres)
1775 modded.height = vyres - modded.dy;
1777 cirrusfb_RectFill(cinfo->regbase,
1778 info->var.bits_per_pixel,
1779 (region->dx * m) / 8, region->dy,
1780 (region->width * m) / 8, region->height,
1782 info->fix.line_length, 0x40);
1785 static void cirrusfb_copyarea(struct fb_info *info,
1786 const struct fb_copyarea *area)
1788 struct fb_copyarea modded;
1790 struct cirrusfb_info *cinfo = info->par;
1791 int m = info->var.bits_per_pixel;
1793 if (info->state != FBINFO_STATE_RUNNING)
1795 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1796 cfb_copyarea(info, area);
1800 vxres = info->var.xres_virtual;
1801 vyres = info->var.yres_virtual;
1802 memcpy(&modded, area, sizeof(struct fb_copyarea));
1804 if (!modded.width || !modded.height ||
1805 modded.sx >= vxres || modded.sy >= vyres ||
1806 modded.dx >= vxres || modded.dy >= vyres)
1809 if (modded.sx + modded.width > vxres)
1810 modded.width = vxres - modded.sx;
1811 if (modded.dx + modded.width > vxres)
1812 modded.width = vxres - modded.dx;
1813 if (modded.sy + modded.height > vyres)
1814 modded.height = vyres - modded.sy;
1815 if (modded.dy + modded.height > vyres)
1816 modded.height = vyres - modded.dy;
1818 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1819 (area->sx * m) / 8, area->sy,
1820 (area->dx * m) / 8, area->dy,
1821 (area->width * m) / 8, area->height,
1822 info->fix.line_length);
1826 static void cirrusfb_imageblit(struct fb_info *info,
1827 const struct fb_image *image)
1829 struct cirrusfb_info *cinfo = info->par;
1830 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
1832 if (info->state != FBINFO_STATE_RUNNING)
1834 /* Alpine acceleration does not work at 24bpp ?!? */
1835 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1 ||
1836 (cinfo->btype == BT_ALPINE && op == 0xc))
1837 cfb_imageblit(info, image);
1839 unsigned size = ((image->width + 7) >> 3) * image->height;
1840 int m = info->var.bits_per_pixel;
1843 if (info->var.bits_per_pixel == 8) {
1844 fg = image->fg_color;
1845 bg = image->bg_color;
1847 fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
1848 bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
1850 if (info->var.bits_per_pixel == 24) {
1851 /* clear background first */
1852 cirrusfb_RectFill(cinfo->regbase,
1853 info->var.bits_per_pixel,
1854 (image->dx * m) / 8, image->dy,
1855 (image->width * m) / 8,
1858 info->fix.line_length, 0x40);
1860 cirrusfb_RectFill(cinfo->regbase,
1861 info->var.bits_per_pixel,
1862 (image->dx * m) / 8, image->dy,
1863 (image->width * m) / 8, image->height,
1865 info->fix.line_length, op);
1866 memcpy(info->screen_base, image->data, size);
1870 #ifdef CONFIG_PPC_PREP
1871 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
1872 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
1873 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
1875 *display = PREP_VIDEO_BASE;
1876 *registers = (unsigned long) PREP_IO_BASE;
1879 #endif /* CONFIG_PPC_PREP */
1882 static int release_io_ports;
1884 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1885 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1886 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1888 static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
1889 u8 __iomem *regbase)
1892 struct cirrusfb_info *cinfo = info->par;
1894 if (is_laguna(cinfo)) {
1895 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1897 mem = ((SR14 & 7) + 1) << 20;
1899 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1900 switch ((SRF & 0x18)) {
1907 /* 64-bit DRAM data bus width; assume 2MB.
1908 * Also indicates 2MB memory on the 5430.
1914 dev_warn(info->device, "Unknown memory size!\n");
1917 /* If DRAM bank switching is enabled, there must be
1918 * twice as much memory installed. (4MB on the 5434)
1924 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1928 static void get_pci_addrs(const struct pci_dev *pdev,
1929 unsigned long *display, unsigned long *registers)
1931 assert(pdev != NULL);
1932 assert(display != NULL);
1933 assert(registers != NULL);
1938 /* This is a best-guess for now */
1940 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1941 *display = pci_resource_start(pdev, 1);
1942 *registers = pci_resource_start(pdev, 0);
1944 *display = pci_resource_start(pdev, 0);
1945 *registers = pci_resource_start(pdev, 1);
1948 assert(*display != 0);
1951 static void cirrusfb_pci_unmap(struct fb_info *info)
1953 struct pci_dev *pdev = to_pci_dev(info->device);
1954 struct cirrusfb_info *cinfo = info->par;
1956 if (cinfo->laguna_mmio == NULL)
1957 iounmap(cinfo->laguna_mmio);
1958 iounmap(info->screen_base);
1959 #if 0 /* if system didn't claim this region, we would... */
1960 release_mem_region(0xA0000, 65535);
1962 if (release_io_ports)
1963 release_region(0x3C0, 32);
1964 pci_release_regions(pdev);
1966 #endif /* CONFIG_PCI */
1969 static void cirrusfb_zorro_unmap(struct fb_info *info)
1971 struct cirrusfb_info *cinfo = info->par;
1972 struct zorro_dev *zdev = to_zorro_dev(info->device);
1974 zorro_release_device(zdev);
1976 if (cinfo->btype == BT_PICASSO4) {
1977 cinfo->regbase -= 0x600000;
1978 iounmap((void *)cinfo->regbase);
1979 iounmap(info->screen_base);
1981 if (zorro_resource_start(zdev) > 0x01000000)
1982 iounmap(info->screen_base);
1985 #endif /* CONFIG_ZORRO */
1987 /* function table of the above functions */
1988 static struct fb_ops cirrusfb_ops = {
1989 .owner = THIS_MODULE,
1990 .fb_open = cirrusfb_open,
1991 .fb_release = cirrusfb_release,
1992 .fb_setcolreg = cirrusfb_setcolreg,
1993 .fb_check_var = cirrusfb_check_var,
1994 .fb_set_par = cirrusfb_set_par,
1995 .fb_pan_display = cirrusfb_pan_display,
1996 .fb_blank = cirrusfb_blank,
1997 .fb_fillrect = cirrusfb_fillrect,
1998 .fb_copyarea = cirrusfb_copyarea,
1999 .fb_sync = cirrusfb_sync,
2000 .fb_imageblit = cirrusfb_imageblit,
2003 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
2005 struct cirrusfb_info *cinfo = info->par;
2006 struct fb_var_screeninfo *var = &info->var;
2008 info->pseudo_palette = cinfo->pseudo_palette;
2009 info->flags = FBINFO_DEFAULT
2010 | FBINFO_HWACCEL_XPAN
2011 | FBINFO_HWACCEL_YPAN
2012 | FBINFO_HWACCEL_FILLRECT
2013 | FBINFO_HWACCEL_IMAGEBLIT
2014 | FBINFO_HWACCEL_COPYAREA;
2015 if (noaccel || is_laguna(cinfo))
2016 info->flags |= FBINFO_HWACCEL_DISABLED;
2017 info->fbops = &cirrusfb_ops;
2019 if (cinfo->btype == BT_GD5480) {
2020 if (var->bits_per_pixel == 16)
2021 info->screen_base += 1 * MB_;
2022 if (var->bits_per_pixel == 32)
2023 info->screen_base += 2 * MB_;
2026 /* Fill fix common fields */
2027 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2028 sizeof(info->fix.id));
2030 /* monochrome: only 1 memory plane */
2031 /* 8 bit and above: Use whole memory area */
2032 info->fix.smem_len = info->screen_size;
2033 if (var->bits_per_pixel == 1)
2034 info->fix.smem_len /= 4;
2035 info->fix.type_aux = 0;
2036 info->fix.xpanstep = 1;
2037 info->fix.ypanstep = 1;
2038 info->fix.ywrapstep = 0;
2040 /* FIXME: map region at 0xB8000 if available, fill in here */
2041 info->fix.mmio_len = 0;
2042 info->fix.accel = FB_ACCEL_NONE;
2044 fb_alloc_cmap(&info->cmap, 256, 0);
2049 static int __devinit cirrusfb_register(struct fb_info *info)
2051 struct cirrusfb_info *cinfo = info->par;
2055 assert(cinfo->btype != BT_NONE);
2057 /* set all the vital stuff */
2058 cirrusfb_set_fbinfo(info);
2060 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2062 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2064 dev_dbg(info->device, "wrong initial video mode\n");
2066 goto err_dealloc_cmap;
2069 info->var.activate = FB_ACTIVATE_NOW;
2071 err = cirrusfb_check_var(&info->var, info);
2073 /* should never happen */
2074 dev_dbg(info->device,
2075 "choking on default var... umm, no good.\n");
2076 goto err_dealloc_cmap;
2079 err = register_framebuffer(info);
2081 dev_err(info->device,
2082 "could not register fb device; err = %d!\n", err);
2083 goto err_dealloc_cmap;
2089 fb_dealloc_cmap(&info->cmap);
2093 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2095 struct cirrusfb_info *cinfo = info->par;
2097 switch_monitor(cinfo, 0);
2098 unregister_framebuffer(info);
2099 fb_dealloc_cmap(&info->cmap);
2100 dev_dbg(info->device, "Framebuffer unregistered\n");
2102 framebuffer_release(info);
2106 static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
2107 const struct pci_device_id *ent)
2109 struct cirrusfb_info *cinfo;
2110 struct fb_info *info;
2111 unsigned long board_addr, board_size;
2114 ret = pci_enable_device(pdev);
2116 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2120 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2122 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2128 cinfo->btype = (enum cirrus_board) ent->driver_data;
2130 dev_dbg(info->device,
2131 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2132 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2133 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2134 (unsigned long long)pdev->resource[1].start);
2137 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2138 #ifdef CONFIG_PPC_PREP
2139 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2141 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2142 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2144 dev_dbg(info->device,
2145 "Attempt to get PCI info for Cirrus Graphics Card\n");
2146 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2147 /* FIXME: this forces VGA. alternatives? */
2148 cinfo->regbase = NULL;
2149 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2152 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2153 board_addr, info->fix.mmio_start);
2155 board_size = (cinfo->btype == BT_GD5480) ?
2156 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2158 ret = pci_request_regions(pdev, "cirrusfb");
2160 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2162 goto err_release_fb;
2164 #if 0 /* if the system didn't claim this region, we would... */
2165 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2166 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2169 goto err_release_regions;
2172 if (request_region(0x3C0, 32, "cirrusfb"))
2173 release_io_ports = 1;
2175 info->screen_base = ioremap(board_addr, board_size);
2176 if (!info->screen_base) {
2178 goto err_release_legacy;
2181 info->fix.smem_start = board_addr;
2182 info->screen_size = board_size;
2183 cinfo->unmap = cirrusfb_pci_unmap;
2185 dev_info(info->device,
2186 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2187 info->screen_size >> 10, board_addr);
2188 pci_set_drvdata(pdev, info);
2190 ret = cirrusfb_register(info);
2194 pci_set_drvdata(pdev, NULL);
2195 iounmap(info->screen_base);
2197 if (release_io_ports)
2198 release_region(0x3C0, 32);
2200 release_mem_region(0xA0000, 65535);
2201 err_release_regions:
2203 pci_release_regions(pdev);
2205 if (cinfo->laguna_mmio != NULL)
2206 iounmap(cinfo->laguna_mmio);
2207 framebuffer_release(info);
2212 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2214 struct fb_info *info = pci_get_drvdata(pdev);
2216 cirrusfb_cleanup(info);
2219 static struct pci_driver cirrusfb_pci_driver = {
2221 .id_table = cirrusfb_pci_table,
2222 .probe = cirrusfb_pci_register,
2223 .remove = __devexit_p(cirrusfb_pci_unregister),
2226 .suspend = cirrusfb_pci_suspend,
2227 .resume = cirrusfb_pci_resume,
2231 #endif /* CONFIG_PCI */
2234 static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2235 const struct zorro_device_id *ent)
2237 struct cirrusfb_info *cinfo;
2238 struct fb_info *info;
2239 enum cirrus_board btype;
2240 struct zorro_dev *z2 = NULL;
2241 unsigned long board_addr, board_size, size;
2244 btype = ent->driver_data;
2245 if (cirrusfb_zorro_table2[btype].id2)
2246 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2247 size = cirrusfb_zorro_table2[btype].size;
2249 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2251 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2256 dev_info(info->device, "%s board detected\n",
2257 cirrusfb_board_info[btype].name);
2260 cinfo->btype = btype;
2263 assert(btype != BT_NONE);
2265 board_addr = zorro_resource_start(z);
2266 board_size = zorro_resource_len(z);
2267 info->screen_size = size;
2269 if (!zorro_request_device(z, "cirrusfb")) {
2270 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2273 goto err_release_fb;
2278 if (btype == BT_PICASSO4) {
2279 dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
2281 /* To be precise, for the P4 this is not the */
2282 /* begin of the board, but the begin of RAM. */
2283 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2284 /* (note the ugly hardcoded 16M number) */
2285 cinfo->regbase = ioremap(board_addr, 16777216);
2286 if (!cinfo->regbase)
2287 goto err_release_region;
2289 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2291 cinfo->regbase += 0x600000;
2292 info->fix.mmio_start = board_addr + 0x600000;
2294 info->fix.smem_start = board_addr + 16777216;
2295 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2296 if (!info->screen_base)
2297 goto err_unmap_regbase;
2299 dev_info(info->device, " REG at $%lx\n",
2300 (unsigned long) z2->resource.start);
2302 info->fix.smem_start = board_addr;
2303 if (board_addr > 0x01000000)
2304 info->screen_base = ioremap(board_addr, board_size);
2306 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2307 if (!info->screen_base)
2308 goto err_release_region;
2310 /* set address for REG area of board */
2311 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2312 info->fix.mmio_start = z2->resource.start;
2314 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2317 cinfo->unmap = cirrusfb_zorro_unmap;
2319 dev_info(info->device,
2320 "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
2321 board_size / MB_, board_addr);
2323 zorro_set_drvdata(z, info);
2325 ret = cirrusfb_register(info);
2329 if (btype == BT_PICASSO4 || board_addr > 0x01000000)
2330 iounmap(info->screen_base);
2333 if (btype == BT_PICASSO4)
2334 iounmap(cinfo->regbase - 0x600000);
2336 release_region(board_addr, board_size);
2338 framebuffer_release(info);
2343 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2345 struct fb_info *info = zorro_get_drvdata(z);
2347 cirrusfb_cleanup(info);
2350 static struct zorro_driver cirrusfb_zorro_driver = {
2352 .id_table = cirrusfb_zorro_table,
2353 .probe = cirrusfb_zorro_register,
2354 .remove = __devexit_p(cirrusfb_zorro_unregister),
2356 #endif /* CONFIG_ZORRO */
2359 static int __init cirrusfb_setup(char *options)
2363 if (!options || !*options)
2366 while ((this_opt = strsep(&options, ",")) != NULL) {
2370 if (!strcmp(this_opt, "noaccel"))
2372 else if (!strncmp(this_opt, "mode:", 5))
2373 mode_option = this_opt + 5;
2375 mode_option = this_opt;
2385 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2386 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2387 MODULE_LICENSE("GPL");
2389 static int __init cirrusfb_init(void)
2394 char *option = NULL;
2396 if (fb_get_options("cirrusfb", &option))
2398 cirrusfb_setup(option);
2402 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2405 error |= pci_register_driver(&cirrusfb_pci_driver);
2410 static void __exit cirrusfb_exit(void)
2413 pci_unregister_driver(&cirrusfb_pci_driver);
2416 zorro_unregister_driver(&cirrusfb_zorro_driver);
2420 module_init(cirrusfb_init);
2422 module_param(mode_option, charp, 0);
2423 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2424 module_param(noaccel, bool, 0);
2425 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2428 module_exit(cirrusfb_exit);
2431 /**********************************************************************/
2432 /* about the following functions - I have used the same names for the */
2433 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2434 /* they just made sense for this purpose. Apart from that, I wrote */
2435 /* these functions myself. */
2436 /**********************************************************************/
2438 /*** WGen() - write into one of the external/general registers ***/
2439 static void WGen(const struct cirrusfb_info *cinfo,
2440 int regnum, unsigned char val)
2442 unsigned long regofs = 0;
2444 if (cinfo->btype == BT_PICASSO) {
2445 /* Picasso II specific hack */
2446 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2447 regnum == CL_VSSM2) */
2448 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2452 vga_w(cinfo->regbase, regofs + regnum, val);
2455 /*** RGen() - read out one of the external/general registers ***/
2456 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2458 unsigned long regofs = 0;
2460 if (cinfo->btype == BT_PICASSO) {
2461 /* Picasso II specific hack */
2462 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2463 regnum == CL_VSSM2) */
2464 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2468 return vga_r(cinfo->regbase, regofs + regnum);
2471 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2472 static void AttrOn(const struct cirrusfb_info *cinfo)
2474 assert(cinfo != NULL);
2476 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2477 /* if we're just in "write value" mode, write back the */
2478 /* same value as before to not modify anything */
2479 vga_w(cinfo->regbase, VGA_ATT_IW,
2480 vga_r(cinfo->regbase, VGA_ATT_R));
2482 /* turn on video bit */
2483 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2484 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2486 /* dummy write on Reg0 to be on "write index" mode next time */
2487 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2490 /*** WHDR() - write into the Hidden DAC register ***/
2491 /* as the HDR is the only extension register that requires special treatment
2492 * (the other extension registers are accessible just like the "ordinary"
2493 * registers of their functional group) here is a specialized routine for
2496 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2498 unsigned char dummy;
2500 if (is_laguna(cinfo))
2502 if (cinfo->btype == BT_PICASSO) {
2503 /* Klaus' hint for correct access to HDR on some boards */
2504 /* first write 0 to pixel mask (3c6) */
2505 WGen(cinfo, VGA_PEL_MSK, 0x00);
2507 /* next read dummy from pixel address (3c8) */
2508 dummy = RGen(cinfo, VGA_PEL_IW);
2511 /* now do the usual stuff to access the HDR */
2513 dummy = RGen(cinfo, VGA_PEL_MSK);
2515 dummy = RGen(cinfo, VGA_PEL_MSK);
2517 dummy = RGen(cinfo, VGA_PEL_MSK);
2519 dummy = RGen(cinfo, VGA_PEL_MSK);
2522 WGen(cinfo, VGA_PEL_MSK, val);
2525 if (cinfo->btype == BT_PICASSO) {
2526 /* now first reset HDR access counter */
2527 dummy = RGen(cinfo, VGA_PEL_IW);
2530 /* and at the end, restore the mask value */
2531 /* ## is this mask always 0xff? */
2532 WGen(cinfo, VGA_PEL_MSK, 0xff);
2537 /*** WSFR() - write to the "special function register" (SFR) ***/
2538 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2541 assert(cinfo->regbase != NULL);
2543 z_writeb(val, cinfo->regbase + 0x8000);
2547 /* The Picasso has a second register for switching the monitor bit */
2548 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2551 /* writing an arbitrary value to this one causes the monitor switcher */
2552 /* to flip to Amiga display */
2553 assert(cinfo->regbase != NULL);
2555 z_writeb(val, cinfo->regbase + 0x9000);
2559 /*** WClut - set CLUT entry (range: 0..63) ***/
2560 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2561 unsigned char green, unsigned char blue)
2563 unsigned int data = VGA_PEL_D;
2565 /* address write mode register is not translated.. */
2566 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2568 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2569 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2571 /* but DAC data register IS, at least for Picasso II */
2572 if (cinfo->btype == BT_PICASSO)
2574 vga_w(cinfo->regbase, data, red);
2575 vga_w(cinfo->regbase, data, green);
2576 vga_w(cinfo->regbase, data, blue);
2578 vga_w(cinfo->regbase, data, blue);
2579 vga_w(cinfo->regbase, data, green);
2580 vga_w(cinfo->regbase, data, red);
2585 /*** RClut - read CLUT entry (range 0..63) ***/
2586 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2587 unsigned char *green, unsigned char *blue)
2589 unsigned int data = VGA_PEL_D;
2591 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2593 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2594 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2595 if (cinfo->btype == BT_PICASSO)
2597 *red = vga_r(cinfo->regbase, data);
2598 *green = vga_r(cinfo->regbase, data);
2599 *blue = vga_r(cinfo->regbase, data);
2601 *blue = vga_r(cinfo->regbase, data);
2602 *green = vga_r(cinfo->regbase, data);
2603 *red = vga_r(cinfo->regbase, data);
2608 /*******************************************************************
2611 Wait for the BitBLT engine to complete a possible earlier job
2612 *********************************************************************/
2614 /* FIXME: use interrupts instead */
2615 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2617 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2621 /*******************************************************************
2624 perform accelerated "scrolling"
2625 ********************************************************************/
2627 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2628 u_short nwidth, u_short nheight,
2629 u_long nsrc, u_long ndest,
2630 u_short bltmode, u_short line_length)
2633 /* pitch: set to line_length */
2634 /* dest pitch low */
2635 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2637 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2638 /* source pitch low */
2639 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2640 /* source pitch hi */
2641 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2643 /* BLT width: actual number of pixels - 1 */
2645 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2647 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2649 /* BLT height: actual number of lines -1 */
2650 /* BLT height low */
2651 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2653 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2655 /* BLT destination */
2657 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2659 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2661 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2665 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2667 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2669 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2672 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2674 /* BLT ROP: SrcCopy */
2675 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2677 /* and finally: GO! */
2678 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2681 /*******************************************************************
2684 perform accelerated "scrolling"
2685 ********************************************************************/
2687 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2688 u_short curx, u_short cury,
2689 u_short destx, u_short desty,
2690 u_short width, u_short height,
2691 u_short line_length)
2693 u_short nwidth = width - 1;
2694 u_short nheight = height - 1;
2699 /* if source adr < dest addr, do the Blt backwards */
2700 if (cury <= desty) {
2701 if (cury == desty) {
2702 /* if src and dest are on the same line, check x */
2708 /* standard case: forward blitting */
2709 nsrc = (cury * line_length) + curx;
2710 ndest = (desty * line_length) + destx;
2712 /* this means start addresses are at the end,
2713 * counting backwards
2715 nsrc += nheight * line_length + nwidth;
2716 ndest += nheight * line_length + nwidth;
2719 cirrusfb_WaitBLT(regbase);
2721 cirrusfb_set_blitter(regbase, nwidth, nheight,
2722 nsrc, ndest, bltmode, line_length);
2725 /*******************************************************************
2728 perform accelerated rectangle fill
2729 ********************************************************************/
2731 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2732 u_short x, u_short y, u_short width, u_short height,
2733 u32 fg_color, u32 bg_color, u_short line_length,
2736 u_long ndest = (y * line_length) + x;
2739 cirrusfb_WaitBLT(regbase);
2741 /* This is a ColorExpand Blt, using the */
2742 /* same color for foreground and background */
2743 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2744 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2747 if (bits_per_pixel >= 16) {
2748 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2749 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2752 if (bits_per_pixel >= 24) {
2753 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2754 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2757 if (bits_per_pixel == 32) {
2758 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2759 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2762 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2763 0, ndest, op | blitmode, line_length);
2766 /**************************************************************************
2767 * bestclock() - determine closest possible clock lower(?) than the
2768 * desired pixel clock
2769 **************************************************************************/
2770 static void bestclock(long freq, int *nom, int *den, int *div)
2775 assert(nom != NULL);
2776 assert(den != NULL);
2777 assert(div != NULL);
2788 for (n = 32; n < 128; n++) {
2791 d = (14318 * n) / freq;
2792 if ((d >= 7) && (d <= 63)) {
2799 h = ((14318 * n) / temp) >> s;
2800 h = h > freq ? h - freq : freq - h;
2809 if ((d >= 7) && (d <= 63)) {
2814 h = ((14318 * n) / d) >> s;
2815 h = h > freq ? h - freq : freq - h;
2826 /* -------------------------------------------------------------------------
2828 * debugging functions
2830 * -------------------------------------------------------------------------
2833 #ifdef CIRRUSFB_DEBUG
2836 * cirrusfb_dbg_print_regs
2837 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2838 * @reg_class: type of registers to read: %CRT, or %SEQ
2841 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2842 * old-style I/O ports are queried for information, otherwise MMIO is
2843 * used at the given @base address to query the information.
2846 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2848 enum cirrusfb_dbg_reg_class reg_class, ...)
2851 unsigned char val = 0;
2855 va_start(list, reg_class);
2857 name = va_arg(list, char *);
2858 while (name != NULL) {
2859 reg = va_arg(list, int);
2861 switch (reg_class) {
2863 val = vga_rcrt(regbase, (unsigned char) reg);
2866 val = vga_rseq(regbase, (unsigned char) reg);
2869 /* should never occur */
2874 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2876 name = va_arg(list, char *);
2883 * cirrusfb_dbg_reg_dump
2884 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2887 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2888 * old-style I/O ports are queried for information, otherwise MMIO is
2889 * used at the given @base address to query the information.
2892 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2894 dev_dbg(info->device, "VGA CRTC register dump:\n");
2896 cirrusfb_dbg_print_regs(info, regbase, CRT,
2946 dev_dbg(info->device, "\n");
2948 dev_dbg(info->device, "VGA SEQ register dump:\n");
2950 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2979 dev_dbg(info->device, "\n");
2982 #endif /* CIRRUSFB_DEBUG */