2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <asm/pgtable.h>
49 #include <linux/zorro.h>
52 #include <linux/pci.h>
55 #include <asm/amigahw.h>
57 #ifdef CONFIG_PPC_PREP
58 #include <asm/machdep.h>
59 #define isPReP machine_is(prep)
64 #include <video/vga.h>
65 #include <video/cirrus.h>
67 /*****************************************************************
69 * debugging and utility macros
73 /* disable runtime assertions? */
74 /* #define CIRRUSFB_NDEBUG */
76 /* debugging assertions */
77 #ifndef CIRRUSFB_NDEBUG
78 #define assert(expr) \
80 printk("Assertion failed! %s,%s,%s,line=%d\n", \
81 #expr, __FILE__, __func__, __LINE__); \
87 #define MB_ (1024 * 1024)
89 /*****************************************************************
102 BT_PICASSO4, /* GD5446 */
103 BT_ALPINE, /* GD543x/4x */
105 BT_LAGUNA, /* GD546x */
109 * per-board-type information, used for enumerating and abstracting
110 * chip-specific information
111 * NOTE: MUST be in the same order as enum cirrus_board in order to
112 * use direct indexing on this array
113 * NOTE: '__initdata' cannot be used as some of this info
114 * is required at runtime. Maybe separate into an init-only and
117 static const struct cirrusfb_board_info_rec {
118 char *name; /* ASCII name of chipset */
119 long maxclock[5]; /* maximum video clock */
120 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
121 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
122 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
123 /* construct bit 19 of screen start address */
124 bool scrn_start_bit19 : 1;
126 /* initial SR07 value, then for each mode */
128 unsigned char sr07_1bpp;
129 unsigned char sr07_1bpp_mux;
130 unsigned char sr07_8bpp;
131 unsigned char sr07_8bpp_mux;
133 unsigned char sr1f; /* SR1F VGA initial register value */
134 } cirrusfb_board_info[] = {
139 /* the SD64/P4 have a higher max. videoclock */
140 135100, 135100, 85500, 85500, 0
144 .scrn_start_bit19 = true,
151 .name = "CL Piccolo",
154 90000, 90000, 90000, 90000, 90000
158 .scrn_start_bit19 = false,
165 .name = "CL Picasso",
168 90000, 90000, 90000, 90000, 90000
172 .scrn_start_bit19 = false,
179 .name = "CL Spectrum",
182 90000, 90000, 90000, 90000, 90000
186 .scrn_start_bit19 = false,
193 .name = "CL Picasso4",
195 135100, 135100, 85500, 85500, 0
199 .scrn_start_bit19 = true,
208 /* for the GD5430. GD5446 can do more... */
209 85500, 85500, 50000, 28500, 0
213 .scrn_start_bit19 = true,
216 .sr07_1bpp_mux = 0xA7,
218 .sr07_8bpp_mux = 0xA7,
224 135100, 200000, 200000, 135100, 135100
228 .scrn_start_bit19 = true,
238 135100, 135100, 135100, 135100, 135100,
242 .scrn_start_bit19 = true,
247 #define CHIP(id, btype) \
248 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
250 static struct pci_device_id cirrusfb_pci_table[] = {
251 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
252 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
253 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
254 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
255 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
256 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
257 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
258 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
259 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
260 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
261 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
264 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
266 #endif /* CONFIG_PCI */
269 static const struct zorro_device_id cirrusfb_zorro_table[] = {
271 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
272 .driver_data = BT_SD64,
274 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
275 .driver_data = BT_PICCOLO,
277 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
278 .driver_data = BT_PICASSO,
280 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
281 .driver_data = BT_SPECTRUM,
283 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
284 .driver_data = BT_PICASSO4,
289 static const struct {
292 } cirrusfb_zorro_table2[] = {
294 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
298 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
302 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
306 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
314 #endif /* CONFIG_ZORRO */
316 #ifdef CIRRUSFB_DEBUG
317 enum cirrusfb_dbg_reg_class {
321 #endif /* CIRRUSFB_DEBUG */
323 /* info about board */
324 struct cirrusfb_info {
326 u8 __iomem *laguna_mmio;
327 enum cirrus_board btype;
328 unsigned char SFR; /* Shadow of special function register */
332 u32 pseudo_palette[16];
334 void (*unmap)(struct fb_info *info);
337 static int noaccel __devinitdata;
338 static char *mode_option __devinitdata = "640x480@60";
340 /****************************************************************************/
341 /**** BEGIN PROTOTYPES ******************************************************/
343 /*--- Interface used by the world ------------------------------------------*/
344 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
345 struct fb_info *info);
347 /*--- Internal routines ----------------------------------------------------*/
348 static void init_vgachip(struct fb_info *info);
349 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
350 static void WGen(const struct cirrusfb_info *cinfo,
351 int regnum, unsigned char val);
352 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
353 static void AttrOn(const struct cirrusfb_info *cinfo);
354 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
355 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
356 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
357 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
358 unsigned char red, unsigned char green, unsigned char blue);
360 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
361 unsigned char *red, unsigned char *green,
362 unsigned char *blue);
364 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
365 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
366 u_short curx, u_short cury,
367 u_short destx, u_short desty,
368 u_short width, u_short height,
369 u_short line_length);
370 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
371 u_short x, u_short y,
372 u_short width, u_short height,
373 u_char color, u_short line_length);
375 static void bestclock(long freq, int *nom, int *den, int *div);
377 #ifdef CIRRUSFB_DEBUG
378 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
379 static void cirrusfb_dbg_print_regs(struct fb_info *info,
381 enum cirrusfb_dbg_reg_class reg_class, ...);
382 #endif /* CIRRUSFB_DEBUG */
384 /*** END PROTOTYPES ********************************************************/
385 /*****************************************************************************/
386 /*** BEGIN Interface Used by the World ***************************************/
388 static int opencount;
390 /*--- Open /dev/fbx ---------------------------------------------------------*/
391 static int cirrusfb_open(struct fb_info *info, int user)
393 if (opencount++ == 0)
394 switch_monitor(info->par, 1);
398 /*--- Close /dev/fbx --------------------------------------------------------*/
399 static int cirrusfb_release(struct fb_info *info, int user)
401 if (--opencount == 0)
402 switch_monitor(info->par, 0);
406 /**** END Interface used by the World *************************************/
407 /****************************************************************************/
408 /**** BEGIN Hardware specific Routines **************************************/
410 /* Check if the MCLK is not a better clock source */
411 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
413 struct cirrusfb_info *cinfo = info->par;
414 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
416 /* Read MCLK value */
417 mclk = (14318 * mclk) >> 3;
418 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
420 /* Determine if we should use MCLK instead of VCLK, and if so, what we
421 * should divide it by to get VCLK
424 if (abs(freq - mclk) < 250) {
425 dev_dbg(info->device, "Using VCLK = MCLK\n");
427 } else if (abs(freq - (mclk / 2)) < 250) {
428 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
435 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
436 struct fb_info *info)
439 /* memory size in pixels */
440 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
442 switch (var->bits_per_pixel) {
446 var->green = var->red;
447 var->blue = var->red;
453 var->green = var->red;
454 var->blue = var->red;
460 var->green.offset = -3;
461 var->blue.offset = 8;
463 var->red.offset = 11;
464 var->green.offset = 5;
465 var->blue.offset = 0;
468 var->green.length = 6;
469 var->blue.length = 5;
475 var->green.offset = 16;
476 var->blue.offset = 24;
478 var->red.offset = 16;
479 var->green.offset = 8;
480 var->blue.offset = 0;
483 var->green.length = 8;
484 var->blue.length = 8;
488 dev_dbg(info->device,
489 "Unsupported bpp size: %d\n", var->bits_per_pixel);
491 /* should never occur */
495 if (var->xres_virtual < var->xres)
496 var->xres_virtual = var->xres;
497 /* use highest possible virtual resolution */
498 if (var->yres_virtual == -1) {
499 var->yres_virtual = pixels / var->xres_virtual;
501 dev_info(info->device,
502 "virtual resolution set to maximum of %dx%d\n",
503 var->xres_virtual, var->yres_virtual);
505 if (var->yres_virtual < var->yres)
506 var->yres_virtual = var->yres;
508 if (var->xres_virtual * var->yres_virtual > pixels) {
509 dev_err(info->device, "mode %dx%dx%d rejected... "
510 "virtual resolution too high to fit into video memory!\n",
511 var->xres_virtual, var->yres_virtual,
512 var->bits_per_pixel);
517 if (var->xoffset < 0)
519 if (var->yoffset < 0)
522 /* truncate xoffset and yoffset to maximum if too high */
523 if (var->xoffset > var->xres_virtual - var->xres)
524 var->xoffset = var->xres_virtual - var->xres - 1;
525 if (var->yoffset > var->yres_virtual - var->yres)
526 var->yoffset = var->yres_virtual - var->yres - 1;
529 var->green.msb_right =
530 var->blue.msb_right =
533 var->transp.msb_right = 0;
536 if (var->vmode & FB_VMODE_DOUBLE)
538 else if (var->vmode & FB_VMODE_INTERLACED)
539 yres = (yres + 1) / 2;
542 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
543 "special treatment required! (TODO)\n");
550 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
551 struct fb_info *info)
555 int maxclockidx = var->bits_per_pixel >> 3;
556 struct cirrusfb_info *cinfo = info->par;
558 switch (var->bits_per_pixel) {
560 info->fix.line_length = var->xres_virtual / 8;
561 info->fix.visual = FB_VISUAL_MONO10;
565 info->fix.line_length = var->xres_virtual;
566 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
571 info->fix.line_length = var->xres_virtual * maxclockidx;
572 info->fix.visual = FB_VISUAL_TRUECOLOR;
576 dev_dbg(info->device,
577 "Unsupported bpp size: %d\n", var->bits_per_pixel);
579 /* should never occur */
583 info->fix.type = FB_TYPE_PACKED_PIXELS;
585 /* convert from ps to kHz */
586 freq = PICOS2KHZ(var->pixclock);
588 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
590 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
591 cinfo->multiplexing = 0;
593 /* If the frequency is greater than we can support, we might be able
594 * to use multiplexing for the video mode */
595 if (freq > maxclock) {
596 switch (cinfo->btype) {
599 cinfo->multiplexing = 1;
603 dev_err(info->device,
604 "Frequency greater than maxclock (%ld kHz)\n",
610 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
611 * the VCLK is double the pixel clock. */
612 switch (var->bits_per_pixel) {
615 if (var->xres <= 800)
616 /* Xbh has this type of clock for 32-bit */
624 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
626 struct cirrusfb_info *cinfo = info->par;
627 unsigned char old1f, old1e;
629 assert(cinfo != NULL);
630 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
633 dev_dbg(info->device, "Set %s as pixclock source.\n",
634 (div == 2) ? "MCLK/2" : "MCLK");
636 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
640 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
642 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
645 /*************************************************************************
646 cirrusfb_set_par_foo()
648 actually writes the values for a new video mode into the hardware,
649 **************************************************************************/
650 static int cirrusfb_set_par_foo(struct fb_info *info)
652 struct cirrusfb_info *cinfo = info->par;
653 struct fb_var_screeninfo *var = &info->var;
654 u8 __iomem *regbase = cinfo->regbase;
658 const struct cirrusfb_board_info_rec *bi;
659 int hdispend, hsyncstart, hsyncend, htotal;
660 int yres, vdispend, vsyncstart, vsyncend, vtotal;
663 unsigned int control = 0, format = 0, threshold = 0;
665 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
666 var->xres, var->yres, var->bits_per_pixel);
667 dev_dbg(info->device, "pixclock: %d\n", var->pixclock);
671 err = cirrusfb_decode_var(var, info);
673 /* should never happen */
674 dev_dbg(info->device, "mode change aborted. invalid var.\n");
678 bi = &cirrusfb_board_info[cinfo->btype];
680 hsyncstart = var->xres + var->right_margin;
681 hsyncend = hsyncstart + var->hsync_len;
682 htotal = (hsyncend + var->left_margin) / 8 - 5;
683 hdispend = var->xres / 8 - 1;
684 hsyncstart = hsyncstart / 8 + 1;
685 hsyncend = hsyncend / 8 + 1;
688 vsyncstart = yres + var->lower_margin;
689 vsyncend = vsyncstart + var->vsync_len;
690 vtotal = vsyncend + var->upper_margin;
693 if (var->vmode & FB_VMODE_DOUBLE) {
698 } else if (var->vmode & FB_VMODE_INTERLACED) {
699 yres = (yres + 1) / 2;
700 vsyncstart = (vsyncstart + 1) / 2;
701 vsyncend = (vsyncend + 1) / 2;
702 vtotal = (vtotal + 1) / 2;
715 if (cinfo->multiplexing) {
721 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
722 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
724 /* if debugging is enabled, all parameters get output before writing */
725 dev_dbg(info->device, "CRT0: %d\n", htotal);
726 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
728 dev_dbg(info->device, "CRT1: %d\n", hdispend);
729 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
731 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
732 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
734 /* + 128: Compatible read */
735 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
736 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
737 128 + ((htotal + 5) % 32));
739 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
740 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
743 if ((htotal + 5) & 32)
745 dev_dbg(info->device, "CRT5: %d\n", tmp);
746 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
748 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
749 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
751 tmp = 16; /* LineCompare bit #9 */
756 if (vsyncstart & 256)
758 if ((vdispend + 1) & 256)
764 if (vsyncstart & 512)
766 dev_dbg(info->device, "CRT7: %d\n", tmp);
767 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
769 tmp = 0x40; /* LineCompare bit #8 */
770 if ((vdispend + 1) & 512)
772 if (var->vmode & FB_VMODE_DOUBLE)
774 dev_dbg(info->device, "CRT9: %d\n", tmp);
775 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
777 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
778 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
780 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
781 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
783 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
784 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
786 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
787 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
789 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
790 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
792 dev_dbg(info->device, "CRT18: 0xff\n");
793 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
796 if (var->vmode & FB_VMODE_INTERLACED)
798 if ((htotal + 5) & 64)
800 if ((htotal + 5) & 128)
807 dev_dbg(info->device, "CRT1a: %d\n", tmp);
808 vga_wcrt(regbase, CL_CRT1A, tmp);
810 freq = PICOS2KHZ(var->pixclock);
811 bestclock(freq, &nom, &den, &div);
813 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
814 freq, nom, den, div);
817 /* hardware RefClock: 14.31818 MHz */
818 /* formula: VClk = (OSC * N) / (D * (1+P)) */
819 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
821 if (cinfo->btype == BT_ALPINE) {
822 /* if freq is close to mclk or mclk/2 select mclk
825 int divMCLK = cirrusfb_check_mclk(info, freq);
828 cirrusfb_set_mclk_as_source(info, divMCLK);
831 if (cinfo->btype == BT_LAGUNA) {
832 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
833 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
834 unsigned short tile_control;
836 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
837 fb_writew(tile_control & ~0x80, cinfo->laguna_mmio + 0x2c4);
839 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
840 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
841 control = fb_readw(cinfo->laguna_mmio + 0x402);
842 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
845 threshold &= 0xffe0 & 0x3fbf;
851 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
852 if ((cinfo->btype == BT_SD64) ||
853 (cinfo->btype == BT_ALPINE) ||
854 (cinfo->btype == BT_GD5480))
857 dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
858 /* Laguna chipset has reversed clock registers */
859 if (cinfo->btype == BT_LAGUNA) {
860 vga_wseq(regbase, CL_SEQRE, tmp);
861 vga_wseq(regbase, CL_SEQR1E, nom);
863 vga_wseq(regbase, CL_SEQRB, nom);
864 vga_wseq(regbase, CL_SEQR1B, tmp);
870 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
872 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
873 * address wrap, no compat. */
874 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
876 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
877 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
879 /* don't know if it would hurt to also program this if no interlaced */
880 /* mode is used, but I feel better this way.. :-) */
881 if (var->vmode & FB_VMODE_INTERLACED)
882 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
884 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
886 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
888 /* adjust horizontal/vertical sync type (low/high) */
889 /* enable display memory & CRTC I/O address for color mode */
891 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
893 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
895 if (cinfo->btype == BT_LAGUNA)
897 WGen(cinfo, VGA_MIS_W, tmp);
899 /* Screen A Preset Row-Scan register */
900 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
901 /* text cursor on and start line */
902 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
903 /* text cursor end line */
904 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
906 /******************************************************
912 /* programming for different color depths */
913 if (var->bits_per_pixel == 1) {
914 dev_dbg(info->device, "preparing for 1 bit deep display\n");
915 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
918 switch (cinfo->btype) {
926 vga_wseq(regbase, CL_SEQR7,
927 cinfo->multiplexing ?
928 bi->sr07_1bpp_mux : bi->sr07_1bpp);
932 vga_wseq(regbase, CL_SEQR7,
933 vga_rseq(regbase, CL_SEQR7) & ~0x01);
937 dev_warn(info->device, "unknown Board\n");
941 /* Extended Sequencer Mode */
942 switch (cinfo->btype) {
944 /* setting the SEQRF on SD64 is not necessary
948 vga_wseq(regbase, CL_SEQR1F, 0x1a);
953 /* ### ueberall 0x22? */
954 /* ##vorher 1c MCLK select */
955 vga_wseq(regbase, CL_SEQR1F, 0x22);
956 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
957 vga_wseq(regbase, CL_SEQRF, 0xb0);
961 /* ##vorher 22 MCLK select */
962 vga_wseq(regbase, CL_SEQR1F, 0x22);
963 /* ## vorher d0 avoid FIFO underruns..? */
964 vga_wseq(regbase, CL_SEQRF, 0xd0);
975 dev_warn(info->device, "unknown Board\n");
979 /* pixel mask: pass-through for first plane */
980 WGen(cinfo, VGA_PEL_MSK, 0x01);
981 if (cinfo->multiplexing)
982 /* hidden dac reg: 1280x1024 */
985 /* hidden dac: nothing */
987 /* memory mode: odd/even, ext. memory */
988 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
989 /* plane mask: only write to first plane */
990 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
993 /******************************************************
999 else if (var->bits_per_pixel == 8) {
1000 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1001 switch (cinfo->btype) {
1009 vga_wseq(regbase, CL_SEQR7,
1010 cinfo->multiplexing ?
1011 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1015 vga_wseq(regbase, CL_SEQR7,
1016 vga_rseq(regbase, CL_SEQR7) | 0x01);
1021 dev_warn(info->device, "unknown Board\n");
1025 switch (cinfo->btype) {
1028 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1034 /* ### vorher 1c MCLK select */
1035 vga_wseq(regbase, CL_SEQR1F, 0x22);
1036 /* Fast Page-Mode writes */
1037 vga_wseq(regbase, CL_SEQRF, 0xb0);
1042 /* ### INCOMPLETE!! */
1043 vga_wseq(regbase, CL_SEQRF, 0xb8);
1045 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1049 /* We already set SRF and SR1F */
1058 dev_warn(info->device, "unknown board\n");
1062 /* mode register: 256 color mode */
1063 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1064 if (cinfo->multiplexing)
1065 /* hidden dac reg: 1280x1024 */
1068 /* hidden dac: nothing */
1072 /******************************************************
1078 else if (var->bits_per_pixel == 16) {
1079 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1080 switch (cinfo->btype) {
1082 /* Extended Sequencer Mode: 256c col. mode */
1083 vga_wseq(regbase, CL_SEQR7, 0xf7);
1085 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1090 vga_wseq(regbase, CL_SEQR7, 0x87);
1091 /* Fast Page-Mode writes */
1092 vga_wseq(regbase, CL_SEQRF, 0xb0);
1094 vga_wseq(regbase, CL_SEQR1F, 0x22);
1098 vga_wseq(regbase, CL_SEQR7, 0x27);
1099 /* Fast Page-Mode writes */
1100 vga_wseq(regbase, CL_SEQRF, 0xb0);
1102 vga_wseq(regbase, CL_SEQR1F, 0x22);
1106 vga_wseq(regbase, CL_SEQR7, 0x27);
1107 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1111 vga_wseq(regbase, CL_SEQR7, 0xa7);
1115 vga_wseq(regbase, CL_SEQR7, 0x17);
1116 /* We already set SRF and SR1F */
1120 vga_wseq(regbase, CL_SEQR7,
1121 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1128 dev_warn(info->device, "unknown Board\n");
1132 /* mode register: 256 color mode */
1133 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1135 WHDR(cinfo, 0xc1); /* Copy Xbh */
1136 #elif defined(CONFIG_ZORRO)
1137 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1138 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1142 /******************************************************
1148 else if (var->bits_per_pixel == 32) {
1149 dev_dbg(info->device, "preparing for 32 bit deep display\n");
1150 switch (cinfo->btype) {
1152 /* Extended Sequencer Mode: 256c col. mode */
1153 vga_wseq(regbase, CL_SEQR7, 0xf9);
1155 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1160 vga_wseq(regbase, CL_SEQR7, 0x85);
1161 /* Fast Page-Mode writes */
1162 vga_wseq(regbase, CL_SEQRF, 0xb0);
1164 vga_wseq(regbase, CL_SEQR1F, 0x22);
1168 vga_wseq(regbase, CL_SEQR7, 0x25);
1169 /* Fast Page-Mode writes */
1170 vga_wseq(regbase, CL_SEQRF, 0xb0);
1172 vga_wseq(regbase, CL_SEQR1F, 0x22);
1176 vga_wseq(regbase, CL_SEQR7, 0x25);
1177 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1181 vga_wseq(regbase, CL_SEQR7, 0xa9);
1185 vga_wseq(regbase, CL_SEQR7, 0x19);
1186 /* We already set SRF and SR1F */
1190 vga_wseq(regbase, CL_SEQR7,
1191 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1198 dev_warn(info->device, "unknown Board\n");
1202 /* mode register: 256 color mode */
1203 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1204 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1208 /******************************************************
1210 * unknown/unsupported bpp
1215 dev_err(info->device,
1216 "What's this? requested color depth == %d.\n",
1217 var->bits_per_pixel);
1219 pitch = info->fix.line_length >> 3;
1220 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1223 tmp |= 0x10; /* offset overflow bit */
1225 /* screen start addr #16-18, fastpagemode cycles */
1226 vga_wcrt(regbase, CL_CRT1B, tmp);
1228 /* screen start address bit 19 */
1229 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1230 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1232 if (cinfo->btype == BT_LAGUNA) {
1234 if ((htotal + 5) & 256)
1238 if (hsyncstart & 256)
1242 if (vdispend & 1024)
1244 if (vsyncstart & 1024)
1247 vga_wcrt(regbase, CL_CRT1E, tmp);
1248 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1253 vga_wattr(regbase, CL_AR33, 0);
1255 /* [ EGS: SetOffset(); ] */
1256 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1259 if (cinfo->btype == BT_LAGUNA) {
1261 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1262 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1263 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1265 /* finally, turn on everything - turn off "FullBandwidth" bit */
1266 /* also, set "DotClock%2" bit where requested */
1269 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1270 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1274 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1275 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1277 /* pan to requested offset */
1278 cirrusfb_pan_display(var, info);
1280 #ifdef CIRRUSFB_DEBUG
1281 cirrusfb_dbg_reg_dump(info, NULL);
1287 /* for some reason incomprehensible to me, cirrusfb requires that you write
1288 * the registers twice for the settings to take..grr. -dte */
1289 static int cirrusfb_set_par(struct fb_info *info)
1291 cirrusfb_set_par_foo(info);
1292 return cirrusfb_set_par_foo(info);
1295 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1296 unsigned blue, unsigned transp,
1297 struct fb_info *info)
1299 struct cirrusfb_info *cinfo = info->par;
1304 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1306 red >>= (16 - info->var.red.length);
1307 green >>= (16 - info->var.green.length);
1308 blue >>= (16 - info->var.blue.length);
1312 v = (red << info->var.red.offset) |
1313 (green << info->var.green.offset) |
1314 (blue << info->var.blue.offset);
1316 cinfo->pseudo_palette[regno] = v;
1320 if (info->var.bits_per_pixel == 8)
1321 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1327 /*************************************************************************
1328 cirrusfb_pan_display()
1330 performs display panning - provided hardware permits this
1331 **************************************************************************/
1332 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1333 struct fb_info *info)
1338 unsigned char tmp, xpix;
1339 struct cirrusfb_info *cinfo = info->par;
1341 dev_dbg(info->device,
1342 "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1344 /* no range checks for xoffset and yoffset, */
1345 /* as fb_pan_display has already done this */
1346 if (var->vmode & FB_VMODE_YWRAP)
1349 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1350 yoffset = var->yoffset;
1352 base = yoffset * info->fix.line_length + xoffset;
1354 if (info->var.bits_per_pixel == 1) {
1355 /* base is already correct */
1356 xpix = (unsigned char) (var->xoffset % 8);
1359 xpix = (unsigned char) ((xoffset % 4) * 2);
1362 if (cinfo->btype != BT_LAGUNA)
1363 cirrusfb_WaitBLT(cinfo->regbase);
1365 /* lower 8 + 8 bits of screen start address */
1366 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1367 (unsigned char) (base & 0xff));
1368 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1369 (unsigned char) (base >> 8));
1371 /* 0xf2 is %11110010, exclude tmp bits */
1372 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1373 /* construct bits 16, 17 and 18 of screen start address */
1381 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1383 /* construct bit 19 of screen start address */
1384 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1385 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D) & ~0x80;
1386 tmp |= (base >> 12) & 0x80;
1387 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1390 /* write pixel panning value to AR33; this does not quite work in 8bpp
1392 * ### Piccolo..? Will this work?
1394 if (info->var.bits_per_pixel == 1)
1395 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1397 if (cinfo->btype != BT_LAGUNA)
1398 cirrusfb_WaitBLT(cinfo->regbase);
1403 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1406 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1407 * then the caller blanks by setting the CLUT (Color Look Up Table)
1408 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1409 * failed due to e.g. a video mode which doesn't support it.
1410 * Implements VESA suspend and powerdown modes on hardware that
1411 * supports disabling hsync/vsync:
1412 * blank_mode == 2: suspend vsync
1413 * blank_mode == 3: suspend hsync
1414 * blank_mode == 4: powerdown
1417 struct cirrusfb_info *cinfo = info->par;
1418 int current_mode = cinfo->blank_mode;
1420 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1422 if (info->state != FBINFO_STATE_RUNNING ||
1423 current_mode == blank_mode) {
1424 dev_dbg(info->device, "EXIT, returning 0\n");
1429 if (current_mode == FB_BLANK_NORMAL ||
1430 current_mode == FB_BLANK_UNBLANK)
1431 /* clear "FullBandwidth" bit */
1434 /* set "FullBandwidth" bit */
1437 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1438 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1440 switch (blank_mode) {
1441 case FB_BLANK_UNBLANK:
1442 case FB_BLANK_NORMAL:
1445 case FB_BLANK_VSYNC_SUSPEND:
1448 case FB_BLANK_HSYNC_SUSPEND:
1451 case FB_BLANK_POWERDOWN:
1455 dev_dbg(info->device, "EXIT, returning 1\n");
1459 vga_wgfx(cinfo->regbase, CL_GRE, val);
1461 cinfo->blank_mode = blank_mode;
1462 dev_dbg(info->device, "EXIT, returning 0\n");
1464 /* Let fbcon do a soft blank for us */
1465 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1468 /**** END Hardware specific Routines **************************************/
1469 /****************************************************************************/
1470 /**** BEGIN Internal Routines ***********************************************/
1472 static void init_vgachip(struct fb_info *info)
1474 struct cirrusfb_info *cinfo = info->par;
1475 const struct cirrusfb_board_info_rec *bi;
1477 assert(cinfo != NULL);
1479 bi = &cirrusfb_board_info[cinfo->btype];
1481 /* reset board globally */
1482 switch (cinfo->btype) {
1501 /* disable flickerfixer */
1502 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1504 /* from Klaus' NetBSD driver: */
1505 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1506 /* put blitter into 542x compat */
1507 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1509 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1513 /* from Klaus' NetBSD driver: */
1514 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1519 /* Nothing to do to reset the board. */
1523 dev_err(info->device, "Warning: Unknown board type\n");
1527 /* make sure RAM size set by this point */
1528 assert(info->screen_size > 0);
1530 /* the P4 is not fully initialized here; I rely on it having been */
1531 /* inited under AmigaOS already, which seems to work just fine */
1532 /* (Klaus advised to do it this way) */
1534 if (cinfo->btype != BT_PICASSO4) {
1535 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1536 WGen(cinfo, CL_POS102, 0x01);
1537 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1539 if (cinfo->btype != BT_SD64)
1540 WGen(cinfo, CL_VSSM2, 0x01);
1542 /* reset sequencer logic */
1543 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1545 /* FullBandwidth (video off) and 8/9 dot clock */
1546 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1547 /* polarity (-/-), disable access to display memory,
1548 * VGA_CRTC_START_HI base address: color
1550 WGen(cinfo, VGA_MIS_W, 0xc1);
1552 /* "magic cookie" - doesn't make any sense to me.. */
1553 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1554 /* unlock all extension registers */
1555 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1558 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1560 switch (cinfo->btype) {
1562 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1568 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1571 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1572 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1576 /* plane mask: nothing */
1577 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1578 /* character map select: doesn't even matter in gx mode */
1579 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1580 /* memory mode: chain4, ext. memory */
1581 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1583 /* controller-internal base address of video memory */
1585 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1587 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1588 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1590 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1591 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1592 /* graphics cursor Y position (..."... ) */
1593 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1594 /* graphics cursor attributes */
1595 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1596 /* graphics cursor pattern address */
1597 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1599 /* writing these on a P4 might give problems.. */
1600 if (cinfo->btype != BT_PICASSO4) {
1601 /* configuration readback and ext. color */
1602 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1603 /* signature generator */
1604 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1607 /* MCLK select etc. */
1609 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1611 /* Screen A preset row scan: none */
1612 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1613 /* Text cursor start: disable text cursor */
1614 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1615 /* Text cursor end: - */
1616 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1617 /* Screen start address high: 0 */
1618 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1619 /* Screen start address low: 0 */
1620 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1621 /* text cursor location high: 0 */
1622 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1623 /* text cursor location low: 0 */
1624 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1626 /* Underline Row scanline: - */
1627 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1628 /* mode control: timing enable, byte mode, no compat modes */
1629 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
1630 /* Line Compare: not needed */
1631 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1632 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1633 /* ext. display controls: ext.adr. wrap */
1634 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1636 /* Set/Reset registes: - */
1637 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1638 /* Set/Reset enable: - */
1639 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1640 /* Color Compare: - */
1641 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1642 /* Data Rotate: - */
1643 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1644 /* Read Map Select: - */
1645 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1646 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1647 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1648 /* Miscellaneous: memory map base address, graphics mode */
1649 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1650 /* Color Don't care: involve all planes */
1651 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1652 /* Bit Mask: no mask at all */
1653 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1655 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_LAGUNA)
1656 /* (5434 can't have bit 3 set for bitblt) */
1657 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1659 /* Graphics controller mode extensions: finer granularity,
1660 * 8byte data latches
1662 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1664 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1665 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1666 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1667 /* Background color byte 1: - */
1668 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1669 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1671 /* Attribute Controller palette registers: "identity mapping" */
1672 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1673 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1674 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1675 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1676 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1677 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1678 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1679 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1680 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1681 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1682 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1683 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1684 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1685 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1686 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1687 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1689 /* Attribute Controller mode: graphics mode */
1690 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1691 /* Overscan color reg.: reg. 0 */
1692 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1693 /* Color Plane enable: Enable all 4 planes */
1694 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1695 /* Color Select: - */
1696 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1698 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1700 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1701 /* polarity (-/-), enable display mem,
1702 * VGA_CRTC_START_HI i/o base = color
1704 WGen(cinfo, VGA_MIS_W, 0xc3);
1706 /* BLT Start/status: Blitter reset */
1707 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1708 /* - " - : "end-of-reset" */
1709 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1712 WHDR(cinfo, 0); /* Hidden DAC register: - */
1716 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1718 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1719 static int IsOn = 0; /* XXX not ok for multiple boards */
1721 if (cinfo->btype == BT_PICASSO4)
1722 return; /* nothing to switch */
1723 if (cinfo->btype == BT_ALPINE)
1724 return; /* nothing to switch */
1725 if (cinfo->btype == BT_GD5480)
1726 return; /* nothing to switch */
1727 if (cinfo->btype == BT_PICASSO) {
1728 if ((on && !IsOn) || (!on && IsOn))
1733 switch (cinfo->btype) {
1735 WSFR(cinfo, cinfo->SFR | 0x21);
1738 WSFR(cinfo, cinfo->SFR | 0x28);
1743 default: /* do nothing */ break;
1746 switch (cinfo->btype) {
1748 WSFR(cinfo, cinfo->SFR & 0xde);
1751 WSFR(cinfo, cinfo->SFR & 0xd7);
1756 default: /* do nothing */
1760 #endif /* CONFIG_ZORRO */
1763 /******************************************/
1764 /* Linux 2.6-style accelerated functions */
1765 /******************************************/
1767 static void cirrusfb_fillrect(struct fb_info *info,
1768 const struct fb_fillrect *region)
1770 struct fb_fillrect modded;
1772 struct cirrusfb_info *cinfo = info->par;
1773 int m = info->var.bits_per_pixel;
1774 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1775 cinfo->pseudo_palette[region->color] : region->color;
1777 if (info->state != FBINFO_STATE_RUNNING)
1779 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1780 cfb_fillrect(info, region);
1784 vxres = info->var.xres_virtual;
1785 vyres = info->var.yres_virtual;
1787 memcpy(&modded, region, sizeof(struct fb_fillrect));
1789 if (!modded.width || !modded.height ||
1790 modded.dx >= vxres || modded.dy >= vyres)
1793 if (modded.dx + modded.width > vxres)
1794 modded.width = vxres - modded.dx;
1795 if (modded.dy + modded.height > vyres)
1796 modded.height = vyres - modded.dy;
1798 cirrusfb_RectFill(cinfo->regbase,
1799 info->var.bits_per_pixel,
1800 (region->dx * m) / 8, region->dy,
1801 (region->width * m) / 8, region->height,
1803 info->fix.line_length);
1806 static void cirrusfb_copyarea(struct fb_info *info,
1807 const struct fb_copyarea *area)
1809 struct fb_copyarea modded;
1811 struct cirrusfb_info *cinfo = info->par;
1812 int m = info->var.bits_per_pixel;
1814 if (info->state != FBINFO_STATE_RUNNING)
1816 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1817 cfb_copyarea(info, area);
1821 vxres = info->var.xres_virtual;
1822 vyres = info->var.yres_virtual;
1823 memcpy(&modded, area, sizeof(struct fb_copyarea));
1825 if (!modded.width || !modded.height ||
1826 modded.sx >= vxres || modded.sy >= vyres ||
1827 modded.dx >= vxres || modded.dy >= vyres)
1830 if (modded.sx + modded.width > vxres)
1831 modded.width = vxres - modded.sx;
1832 if (modded.dx + modded.width > vxres)
1833 modded.width = vxres - modded.dx;
1834 if (modded.sy + modded.height > vyres)
1835 modded.height = vyres - modded.sy;
1836 if (modded.dy + modded.height > vyres)
1837 modded.height = vyres - modded.dy;
1839 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1840 (area->sx * m) / 8, area->sy,
1841 (area->dx * m) / 8, area->dy,
1842 (area->width * m) / 8, area->height,
1843 info->fix.line_length);
1847 static void cirrusfb_imageblit(struct fb_info *info,
1848 const struct fb_image *image)
1850 struct cirrusfb_info *cinfo = info->par;
1852 if (cinfo->btype != BT_LAGUNA)
1853 cirrusfb_WaitBLT(cinfo->regbase);
1854 cfb_imageblit(info, image);
1857 #ifdef CONFIG_PPC_PREP
1858 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
1859 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
1860 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
1862 *display = PREP_VIDEO_BASE;
1863 *registers = (unsigned long) PREP_IO_BASE;
1866 #endif /* CONFIG_PPC_PREP */
1869 static int release_io_ports;
1871 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1872 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1873 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1875 static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
1876 u8 __iomem *regbase)
1879 struct cirrusfb_info *cinfo = info->par;
1881 if (cinfo->btype == BT_LAGUNA) {
1882 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1884 mem = ((SR14 & 7) + 1) << 20;
1886 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1887 switch ((SRF & 0x18)) {
1894 /* 64-bit DRAM data bus width; assume 2MB.
1895 * Also indicates 2MB memory on the 5430.
1901 dev_warn(info->device, "Unknown memory size!\n");
1904 /* If DRAM bank switching is enabled, there must be
1905 * twice as much memory installed. (4MB on the 5434)
1911 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1915 static void get_pci_addrs(const struct pci_dev *pdev,
1916 unsigned long *display, unsigned long *registers)
1918 assert(pdev != NULL);
1919 assert(display != NULL);
1920 assert(registers != NULL);
1925 /* This is a best-guess for now */
1927 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1928 *display = pci_resource_start(pdev, 1);
1929 *registers = pci_resource_start(pdev, 0);
1931 *display = pci_resource_start(pdev, 0);
1932 *registers = pci_resource_start(pdev, 1);
1935 assert(*display != 0);
1938 static void cirrusfb_pci_unmap(struct fb_info *info)
1940 struct pci_dev *pdev = to_pci_dev(info->device);
1941 struct cirrusfb_info *cinfo = info->par;
1943 if (cinfo->laguna_mmio == NULL)
1944 iounmap(cinfo->laguna_mmio);
1945 iounmap(info->screen_base);
1946 #if 0 /* if system didn't claim this region, we would... */
1947 release_mem_region(0xA0000, 65535);
1949 if (release_io_ports)
1950 release_region(0x3C0, 32);
1951 pci_release_regions(pdev);
1953 #endif /* CONFIG_PCI */
1956 static void cirrusfb_zorro_unmap(struct fb_info *info)
1958 struct cirrusfb_info *cinfo = info->par;
1959 struct zorro_dev *zdev = to_zorro_dev(info->device);
1961 zorro_release_device(zdev);
1963 if (cinfo->btype == BT_PICASSO4) {
1964 cinfo->regbase -= 0x600000;
1965 iounmap((void *)cinfo->regbase);
1966 iounmap(info->screen_base);
1968 if (zorro_resource_start(zdev) > 0x01000000)
1969 iounmap(info->screen_base);
1972 #endif /* CONFIG_ZORRO */
1974 /* function table of the above functions */
1975 static struct fb_ops cirrusfb_ops = {
1976 .owner = THIS_MODULE,
1977 .fb_open = cirrusfb_open,
1978 .fb_release = cirrusfb_release,
1979 .fb_setcolreg = cirrusfb_setcolreg,
1980 .fb_check_var = cirrusfb_check_var,
1981 .fb_set_par = cirrusfb_set_par,
1982 .fb_pan_display = cirrusfb_pan_display,
1983 .fb_blank = cirrusfb_blank,
1984 .fb_fillrect = cirrusfb_fillrect,
1985 .fb_copyarea = cirrusfb_copyarea,
1986 .fb_imageblit = cirrusfb_imageblit,
1989 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
1991 struct cirrusfb_info *cinfo = info->par;
1992 struct fb_var_screeninfo *var = &info->var;
1994 info->pseudo_palette = cinfo->pseudo_palette;
1995 info->flags = FBINFO_DEFAULT
1996 | FBINFO_HWACCEL_XPAN
1997 | FBINFO_HWACCEL_YPAN
1998 | FBINFO_HWACCEL_FILLRECT
1999 | FBINFO_HWACCEL_COPYAREA;
2000 if (noaccel || cinfo->btype == BT_LAGUNA)
2001 info->flags |= FBINFO_HWACCEL_DISABLED;
2002 info->fbops = &cirrusfb_ops;
2003 if (cinfo->btype == BT_GD5480) {
2004 if (var->bits_per_pixel == 16)
2005 info->screen_base += 1 * MB_;
2006 if (var->bits_per_pixel == 32)
2007 info->screen_base += 2 * MB_;
2010 /* Fill fix common fields */
2011 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2012 sizeof(info->fix.id));
2014 /* monochrome: only 1 memory plane */
2015 /* 8 bit and above: Use whole memory area */
2016 info->fix.smem_len = info->screen_size;
2017 if (var->bits_per_pixel == 1)
2018 info->fix.smem_len /= 4;
2019 info->fix.type_aux = 0;
2020 info->fix.xpanstep = 1;
2021 info->fix.ypanstep = 1;
2022 info->fix.ywrapstep = 0;
2024 /* FIXME: map region at 0xB8000 if available, fill in here */
2025 info->fix.mmio_len = 0;
2026 info->fix.accel = FB_ACCEL_NONE;
2028 fb_alloc_cmap(&info->cmap, 256, 0);
2033 static int __devinit cirrusfb_register(struct fb_info *info)
2035 struct cirrusfb_info *cinfo = info->par;
2039 assert(cinfo->btype != BT_NONE);
2041 /* set all the vital stuff */
2042 cirrusfb_set_fbinfo(info);
2044 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2046 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2048 dev_dbg(info->device, "wrong initial video mode\n");
2050 goto err_dealloc_cmap;
2053 info->var.activate = FB_ACTIVATE_NOW;
2055 err = cirrusfb_decode_var(&info->var, info);
2057 /* should never happen */
2058 dev_dbg(info->device,
2059 "choking on default var... umm, no good.\n");
2060 goto err_dealloc_cmap;
2063 err = register_framebuffer(info);
2065 dev_err(info->device,
2066 "could not register fb device; err = %d!\n", err);
2067 goto err_dealloc_cmap;
2073 fb_dealloc_cmap(&info->cmap);
2075 framebuffer_release(info);
2079 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2081 struct cirrusfb_info *cinfo = info->par;
2083 switch_monitor(cinfo, 0);
2084 unregister_framebuffer(info);
2085 fb_dealloc_cmap(&info->cmap);
2086 dev_dbg(info->device, "Framebuffer unregistered\n");
2088 framebuffer_release(info);
2092 static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
2093 const struct pci_device_id *ent)
2095 struct cirrusfb_info *cinfo;
2096 struct fb_info *info;
2097 unsigned long board_addr, board_size;
2100 ret = pci_enable_device(pdev);
2102 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2106 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2108 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2114 cinfo->btype = (enum cirrus_board) ent->driver_data;
2116 dev_dbg(info->device,
2117 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2118 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2119 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2120 (unsigned long long)pdev->resource[1].start);
2123 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2124 #ifdef CONFIG_PPC_PREP
2125 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2127 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2128 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2130 dev_dbg(info->device,
2131 "Attempt to get PCI info for Cirrus Graphics Card\n");
2132 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2133 /* FIXME: this forces VGA. alternatives? */
2134 cinfo->regbase = NULL;
2135 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2138 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2139 board_addr, info->fix.mmio_start);
2141 board_size = (cinfo->btype == BT_GD5480) ?
2142 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2144 ret = pci_request_regions(pdev, "cirrusfb");
2146 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2148 goto err_release_fb;
2150 #if 0 /* if the system didn't claim this region, we would... */
2151 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2152 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2155 goto err_release_regions;
2158 if (request_region(0x3C0, 32, "cirrusfb"))
2159 release_io_ports = 1;
2161 info->screen_base = ioremap(board_addr, board_size);
2162 if (!info->screen_base) {
2164 goto err_release_legacy;
2167 info->fix.smem_start = board_addr;
2168 info->screen_size = board_size;
2169 cinfo->unmap = cirrusfb_pci_unmap;
2171 dev_info(info->device,
2172 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2173 info->screen_size >> 10, board_addr);
2174 pci_set_drvdata(pdev, info);
2176 ret = cirrusfb_register(info);
2178 iounmap(info->screen_base);
2182 if (release_io_ports)
2183 release_region(0x3C0, 32);
2185 release_mem_region(0xA0000, 65535);
2186 err_release_regions:
2188 pci_release_regions(pdev);
2190 if (cinfo->laguna_mmio == NULL)
2191 iounmap(cinfo->laguna_mmio);
2192 framebuffer_release(info);
2198 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2200 struct fb_info *info = pci_get_drvdata(pdev);
2202 cirrusfb_cleanup(info);
2205 static struct pci_driver cirrusfb_pci_driver = {
2207 .id_table = cirrusfb_pci_table,
2208 .probe = cirrusfb_pci_register,
2209 .remove = __devexit_p(cirrusfb_pci_unregister),
2212 .suspend = cirrusfb_pci_suspend,
2213 .resume = cirrusfb_pci_resume,
2217 #endif /* CONFIG_PCI */
2220 static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2221 const struct zorro_device_id *ent)
2223 struct cirrusfb_info *cinfo;
2224 struct fb_info *info;
2225 enum cirrus_board btype;
2226 struct zorro_dev *z2 = NULL;
2227 unsigned long board_addr, board_size, size;
2230 btype = ent->driver_data;
2231 if (cirrusfb_zorro_table2[btype].id2)
2232 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2233 size = cirrusfb_zorro_table2[btype].size;
2235 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2237 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2242 dev_info(info->device, "%s board detected\n",
2243 cirrusfb_board_info[btype].name);
2246 cinfo->btype = btype;
2249 assert(btype != BT_NONE);
2251 board_addr = zorro_resource_start(z);
2252 board_size = zorro_resource_len(z);
2253 info->screen_size = size;
2255 if (!zorro_request_device(z, "cirrusfb")) {
2256 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2259 goto err_release_fb;
2264 if (btype == BT_PICASSO4) {
2265 dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
2267 /* To be precise, for the P4 this is not the */
2268 /* begin of the board, but the begin of RAM. */
2269 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2270 /* (note the ugly hardcoded 16M number) */
2271 cinfo->regbase = ioremap(board_addr, 16777216);
2272 if (!cinfo->regbase)
2273 goto err_release_region;
2275 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2277 cinfo->regbase += 0x600000;
2278 info->fix.mmio_start = board_addr + 0x600000;
2280 info->fix.smem_start = board_addr + 16777216;
2281 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2282 if (!info->screen_base)
2283 goto err_unmap_regbase;
2285 dev_info(info->device, " REG at $%lx\n",
2286 (unsigned long) z2->resource.start);
2288 info->fix.smem_start = board_addr;
2289 if (board_addr > 0x01000000)
2290 info->screen_base = ioremap(board_addr, board_size);
2292 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2293 if (!info->screen_base)
2294 goto err_release_region;
2296 /* set address for REG area of board */
2297 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2298 info->fix.mmio_start = z2->resource.start;
2300 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2303 cinfo->unmap = cirrusfb_zorro_unmap;
2305 dev_info(info->device,
2306 "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
2307 board_size / MB_, board_addr);
2309 zorro_set_drvdata(z, info);
2311 ret = cirrusfb_register(info);
2313 if (btype == BT_PICASSO4) {
2314 iounmap(info->screen_base);
2315 iounmap(cinfo->regbase - 0x600000);
2316 } else if (board_addr > 0x01000000)
2317 iounmap(info->screen_base);
2322 /* Parental advisory: explicit hack */
2323 iounmap(cinfo->regbase - 0x600000);
2325 release_region(board_addr, board_size);
2327 framebuffer_release(info);
2332 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2334 struct fb_info *info = zorro_get_drvdata(z);
2336 cirrusfb_cleanup(info);
2339 static struct zorro_driver cirrusfb_zorro_driver = {
2341 .id_table = cirrusfb_zorro_table,
2342 .probe = cirrusfb_zorro_register,
2343 .remove = __devexit_p(cirrusfb_zorro_unregister),
2345 #endif /* CONFIG_ZORRO */
2348 static int __init cirrusfb_setup(char *options)
2352 if (!options || !*options)
2355 while ((this_opt = strsep(&options, ",")) != NULL) {
2359 if (!strcmp(this_opt, "noaccel"))
2361 else if (!strncmp(this_opt, "mode:", 5))
2362 mode_option = this_opt + 5;
2364 mode_option = this_opt;
2374 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2375 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2376 MODULE_LICENSE("GPL");
2378 static int __init cirrusfb_init(void)
2383 char *option = NULL;
2385 if (fb_get_options("cirrusfb", &option))
2387 cirrusfb_setup(option);
2391 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2394 error |= pci_register_driver(&cirrusfb_pci_driver);
2399 static void __exit cirrusfb_exit(void)
2402 pci_unregister_driver(&cirrusfb_pci_driver);
2405 zorro_unregister_driver(&cirrusfb_zorro_driver);
2409 module_init(cirrusfb_init);
2411 module_param(mode_option, charp, 0);
2412 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2413 module_param(noaccel, bool, 0);
2414 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2417 module_exit(cirrusfb_exit);
2420 /**********************************************************************/
2421 /* about the following functions - I have used the same names for the */
2422 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2423 /* they just made sense for this purpose. Apart from that, I wrote */
2424 /* these functions myself. */
2425 /**********************************************************************/
2427 /*** WGen() - write into one of the external/general registers ***/
2428 static void WGen(const struct cirrusfb_info *cinfo,
2429 int regnum, unsigned char val)
2431 unsigned long regofs = 0;
2433 if (cinfo->btype == BT_PICASSO) {
2434 /* Picasso II specific hack */
2435 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2436 regnum == CL_VSSM2) */
2437 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2441 vga_w(cinfo->regbase, regofs + regnum, val);
2444 /*** RGen() - read out one of the external/general registers ***/
2445 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2447 unsigned long regofs = 0;
2449 if (cinfo->btype == BT_PICASSO) {
2450 /* Picasso II specific hack */
2451 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2452 regnum == CL_VSSM2) */
2453 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2457 return vga_r(cinfo->regbase, regofs + regnum);
2460 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2461 static void AttrOn(const struct cirrusfb_info *cinfo)
2463 assert(cinfo != NULL);
2465 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2466 /* if we're just in "write value" mode, write back the */
2467 /* same value as before to not modify anything */
2468 vga_w(cinfo->regbase, VGA_ATT_IW,
2469 vga_r(cinfo->regbase, VGA_ATT_R));
2471 /* turn on video bit */
2472 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2473 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2475 /* dummy write on Reg0 to be on "write index" mode next time */
2476 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2479 /*** WHDR() - write into the Hidden DAC register ***/
2480 /* as the HDR is the only extension register that requires special treatment
2481 * (the other extension registers are accessible just like the "ordinary"
2482 * registers of their functional group) here is a specialized routine for
2485 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2487 unsigned char dummy;
2489 if (cinfo->btype == BT_LAGUNA)
2491 if (cinfo->btype == BT_PICASSO) {
2492 /* Klaus' hint for correct access to HDR on some boards */
2493 /* first write 0 to pixel mask (3c6) */
2494 WGen(cinfo, VGA_PEL_MSK, 0x00);
2496 /* next read dummy from pixel address (3c8) */
2497 dummy = RGen(cinfo, VGA_PEL_IW);
2500 /* now do the usual stuff to access the HDR */
2502 dummy = RGen(cinfo, VGA_PEL_MSK);
2504 dummy = RGen(cinfo, VGA_PEL_MSK);
2506 dummy = RGen(cinfo, VGA_PEL_MSK);
2508 dummy = RGen(cinfo, VGA_PEL_MSK);
2511 WGen(cinfo, VGA_PEL_MSK, val);
2514 if (cinfo->btype == BT_PICASSO) {
2515 /* now first reset HDR access counter */
2516 dummy = RGen(cinfo, VGA_PEL_IW);
2519 /* and at the end, restore the mask value */
2520 /* ## is this mask always 0xff? */
2521 WGen(cinfo, VGA_PEL_MSK, 0xff);
2526 /*** WSFR() - write to the "special function register" (SFR) ***/
2527 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2530 assert(cinfo->regbase != NULL);
2532 z_writeb(val, cinfo->regbase + 0x8000);
2536 /* The Picasso has a second register for switching the monitor bit */
2537 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2540 /* writing an arbitrary value to this one causes the monitor switcher */
2541 /* to flip to Amiga display */
2542 assert(cinfo->regbase != NULL);
2544 z_writeb(val, cinfo->regbase + 0x9000);
2548 /*** WClut - set CLUT entry (range: 0..63) ***/
2549 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2550 unsigned char green, unsigned char blue)
2552 unsigned int data = VGA_PEL_D;
2554 /* address write mode register is not translated.. */
2555 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2557 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2558 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2559 cinfo->btype == BT_LAGUNA) {
2560 /* but DAC data register IS, at least for Picasso II */
2561 if (cinfo->btype == BT_PICASSO)
2563 vga_w(cinfo->regbase, data, red);
2564 vga_w(cinfo->regbase, data, green);
2565 vga_w(cinfo->regbase, data, blue);
2567 vga_w(cinfo->regbase, data, blue);
2568 vga_w(cinfo->regbase, data, green);
2569 vga_w(cinfo->regbase, data, red);
2574 /*** RClut - read CLUT entry (range 0..63) ***/
2575 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2576 unsigned char *green, unsigned char *blue)
2578 unsigned int data = VGA_PEL_D;
2580 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2582 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2583 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2584 if (cinfo->btype == BT_PICASSO)
2586 *red = vga_r(cinfo->regbase, data);
2587 *green = vga_r(cinfo->regbase, data);
2588 *blue = vga_r(cinfo->regbase, data);
2590 *blue = vga_r(cinfo->regbase, data);
2591 *green = vga_r(cinfo->regbase, data);
2592 *red = vga_r(cinfo->regbase, data);
2597 /*******************************************************************
2600 Wait for the BitBLT engine to complete a possible earlier job
2601 *********************************************************************/
2603 /* FIXME: use interrupts instead */
2604 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2606 /* now busy-wait until we're done */
2607 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2611 /*******************************************************************
2614 perform accelerated "scrolling"
2615 ********************************************************************/
2617 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2618 u_short curx, u_short cury,
2619 u_short destx, u_short desty,
2620 u_short width, u_short height,
2621 u_short line_length)
2623 u_short nwidth, nheight;
2628 nheight = height - 1;
2631 /* if source adr < dest addr, do the Blt backwards */
2632 if (cury <= desty) {
2633 if (cury == desty) {
2634 /* if src and dest are on the same line, check x */
2641 /* standard case: forward blitting */
2642 nsrc = (cury * line_length) + curx;
2643 ndest = (desty * line_length) + destx;
2645 /* this means start addresses are at the end,
2646 * counting backwards
2648 nsrc = cury * line_length + curx +
2649 nheight * line_length + nwidth;
2650 ndest = desty * line_length + destx +
2651 nheight * line_length + nwidth;
2655 run-down of registers to be programmed:
2663 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2667 cirrusfb_WaitBLT(regbase);
2669 /* pitch: set to line_length */
2670 /* dest pitch low */
2671 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2673 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2674 /* source pitch low */
2675 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2676 /* source pitch hi */
2677 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2679 /* BLT width: actual number of pixels - 1 */
2681 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2683 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2685 /* BLT height: actual number of lines -1 */
2686 /* BLT height low */
2687 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2689 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2691 /* BLT destination */
2693 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2695 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2697 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2701 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2703 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2705 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2708 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2710 /* BLT ROP: SrcCopy */
2711 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2713 /* and finally: GO! */
2714 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2717 /*******************************************************************
2720 perform accelerated rectangle fill
2721 ********************************************************************/
2723 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2724 u_short x, u_short y, u_short width, u_short height,
2725 u_char color, u_short line_length)
2727 u_short nwidth, nheight;
2732 nheight = height - 1;
2734 ndest = (y * line_length) + x;
2736 cirrusfb_WaitBLT(regbase);
2738 /* pitch: set to line_length */
2739 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2740 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
2741 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2742 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
2744 /* BLT width: actual number of pixels - 1 */
2745 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2746 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
2748 /* BLT height: actual number of lines -1 */
2749 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2750 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
2752 /* BLT destination */
2754 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2756 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2758 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2760 /* BLT source: set to 0 (is a dummy here anyway) */
2761 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
2762 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
2763 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
2765 /* This is a ColorExpand Blt, using the */
2766 /* same color for foreground and background */
2767 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
2768 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
2771 if (bits_per_pixel == 16) {
2772 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2773 vga_wgfx(regbase, CL_GR11, color); /* background color */
2776 } else if (bits_per_pixel == 32) {
2777 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2778 vga_wgfx(regbase, CL_GR11, color); /* background color */
2779 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
2780 vga_wgfx(regbase, CL_GR13, color); /* background color */
2781 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
2782 vga_wgfx(regbase, CL_GR15, 0); /* background color */
2786 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
2787 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
2789 /* BLT ROP: SrcCopy */
2790 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2792 /* and finally: GO! */
2793 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2796 /**************************************************************************
2797 * bestclock() - determine closest possible clock lower(?) than the
2798 * desired pixel clock
2799 **************************************************************************/
2800 static void bestclock(long freq, int *nom, int *den, int *div)
2805 assert(nom != NULL);
2806 assert(den != NULL);
2807 assert(div != NULL);
2818 for (n = 32; n < 128; n++) {
2821 d = (14318 * n) / freq;
2822 if ((d >= 7) && (d <= 63)) {
2829 h = ((14318 * n) / temp) >> s;
2830 h = h > freq ? h - freq : freq - h;
2839 if ((d >= 7) && (d <= 63)) {
2844 h = ((14318 * n) / d) >> s;
2845 h = h > freq ? h - freq : freq - h;
2856 /* -------------------------------------------------------------------------
2858 * debugging functions
2860 * -------------------------------------------------------------------------
2863 #ifdef CIRRUSFB_DEBUG
2866 * cirrusfb_dbg_print_regs
2867 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2868 * @reg_class: type of registers to read: %CRT, or %SEQ
2871 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2872 * old-style I/O ports are queried for information, otherwise MMIO is
2873 * used at the given @base address to query the information.
2876 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2878 enum cirrusfb_dbg_reg_class reg_class, ...)
2881 unsigned char val = 0;
2885 va_start(list, reg_class);
2887 name = va_arg(list, char *);
2888 while (name != NULL) {
2889 reg = va_arg(list, int);
2891 switch (reg_class) {
2893 val = vga_rcrt(regbase, (unsigned char) reg);
2896 val = vga_rseq(regbase, (unsigned char) reg);
2899 /* should never occur */
2904 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2906 name = va_arg(list, char *);
2913 * cirrusfb_dbg_reg_dump
2914 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2917 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2918 * old-style I/O ports are queried for information, otherwise MMIO is
2919 * used at the given @base address to query the information.
2922 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2924 dev_dbg(info->device, "VGA CRTC register dump:\n");
2926 cirrusfb_dbg_print_regs(info, regbase, CRT,
2976 dev_dbg(info->device, "\n");
2978 dev_dbg(info->device, "VGA SEQ register dump:\n");
2980 cirrusfb_dbg_print_regs(info, regbase, SEQ,
3009 dev_dbg(info->device, "\n");
3012 #endif /* CIRRUSFB_DEBUG */