SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/usb/musb/musb_gadget_ep0.c

   1 /*
   2  * MUSB OTG peripheral driver ep0 handling
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2006 by Texas Instruments
   6  * Copyright (C) 2006-2007 Nokia Corporation
   7  * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  26  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/list.h>
  38 #include <linux/timer.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/init.h>
  41 #include <linux/device.h>
  42 #include <linux/interrupt.h>
  43
  44 #include "musb_core.h"
  45
  46 /* ep0 is always musb->endpoints[0].ep_in */
  47 #define next_ep0_request(musb)  next_in_request(&(musb)->endpoints[0])
  48
  49 /*
  50  * locking note:  we use only the controller lock, for simpler correctness.
  51  * It's always held with IRQs blocked.
  52  *
  53  * It protects the ep0 request queue as well as ep0_state, not just the
  54  * controller and indexed registers.  And that lock stays held unless it
  55  * needs to be dropped to allow reentering this driver ... like upcalls to
  56  * the gadget driver, or adjusting endpoint halt status.
  57  */
  58
  59 static char *decode_ep0stage(u8 stage)
  60 {
  61         switch (stage) {
  62         case MUSB_EP0_STAGE_IDLE:       return "idle";
  63         case MUSB_EP0_STAGE_SETUP:      return "setup";
  64         case MUSB_EP0_STAGE_TX:         return "in";
  65         case MUSB_EP0_STAGE_RX:         return "out";
  66         case MUSB_EP0_STAGE_ACKWAIT:    return "wait";
  67         case MUSB_EP0_STAGE_STATUSIN:   return "in/status";
  68         case MUSB_EP0_STAGE_STATUSOUT:  return "out/status";
  69         default:                        return "?";
  70         }
  71 }
  72
  73 /* handle a standard GET_STATUS request
  74  * Context:  caller holds controller lock
  75  */
  76 static int service_tx_status_request(
  77         struct musb *musb,
  78         const struct usb_ctrlrequest *ctrlrequest)
  79 {
  80         void __iomem    *mbase = musb->mregs;
  81         int handled = 1;
  82         u8 result[2], epnum = 0;
  83         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  84
  85         result[1] = 0;
  86
  87         switch (recip) {
  88         case USB_RECIP_DEVICE:
  89                 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  90                 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  91 #ifdef CONFIG_USB_MUSB_OTG
  92                 if (musb->g.is_otg) {
  93                         result[0] |= musb->g.b_hnp_enable
  94                                 << USB_DEVICE_B_HNP_ENABLE;
  95                         result[0] |= musb->g.a_alt_hnp_support
  96                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  97                         result[0] |= musb->g.a_hnp_support
  98                                 << USB_DEVICE_A_HNP_SUPPORT;
  99                 }
 100 #endif
 101                 break;
 102
 103         case USB_RECIP_INTERFACE:
 104                 result[0] = 0;
 105                 break;
 106
 107         case USB_RECIP_ENDPOINT: {
 108                 int             is_in;
 109                 struct musb_ep  *ep;
 110                 u16             tmp;
 111                 void __iomem    *regs;
 112
 113                 epnum = (u8) ctrlrequest->wIndex;
 114                 if (!epnum) {
 115                         result[0] = 0;
 116                         break;
 117                 }
 118
 119                 is_in = epnum & USB_DIR_IN;
 120                 if (is_in) {
 121                         epnum &= 0x0f;
 122                         ep = &musb->endpoints[epnum].ep_in;
 123                 } else {
 124                         ep = &musb->endpoints[epnum].ep_out;
 125                 }
 126                 regs = musb->endpoints[epnum].regs;
 127
 128                 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
 129                         handled = -EINVAL;
 130                         break;
 131                 }
 132
 133                 musb_ep_select(mbase, epnum);
 134                 if (is_in)
 135                         tmp = musb_readw(regs, MUSB_TXCSR)
 136                                                 & MUSB_TXCSR_P_SENDSTALL;
 137                 else
 138                         tmp = musb_readw(regs, MUSB_RXCSR)
 139                                                 & MUSB_RXCSR_P_SENDSTALL;
 140                 musb_ep_select(mbase, 0);
 141
 142                 result[0] = tmp ? 1 : 0;
 143                 } break;
 144
 145         default:
 146                 /* class, vendor, etc ... delegate */
 147                 handled = 0;
 148                 break;
 149         }
 150
 151         /* fill up the fifo; caller updates csr0 */
 152         if (handled > 0) {
 153                 u16     len = le16_to_cpu(ctrlrequest->wLength);
 154
 155                 if (len > 2)
 156                         len = 2;
 157                 musb_write_fifo(&musb->endpoints[0], len, result);
 158         }
 159
 160         return handled;
 161 }
 162
 163 /*
 164  * handle a control-IN request, the end0 buffer contains the current request
 165  * that is supposed to be a standard control request. Assumes the fifo to
 166  * be at least 2 bytes long.
 167  *
 168  * @return 0 if the request was NOT HANDLED,
 169  * < 0 when error
 170  * > 0 when the request is processed
 171  *
 172  * Context:  caller holds controller lock
 173  */
 174 static int
 175 service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 176 {
 177         int handled = 0;        /* not handled */
 178
 179         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 180                         == USB_TYPE_STANDARD) {
 181                 switch (ctrlrequest->bRequest) {
 182                 case USB_REQ_GET_STATUS:
 183                         handled = service_tx_status_request(musb,
 184                                         ctrlrequest);
 185                         break;
 186
 187                 /* case USB_REQ_SYNC_FRAME: */
 188
 189                 default:
 190                         break;
 191                 }
 192         }
 193         return handled;
 194 }
 195
 196 /*
 197  * Context:  caller holds controller lock
 198  */
 199 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 200 {
 201         musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
 202 }
 203
 204 /*
 205  * Tries to start B-device HNP negotiation if enabled via sysfs
 206  */
 207 static inline void musb_try_b_hnp_enable(struct musb *musb)
 208 {
 209         void __iomem    *mbase = musb->mregs;
 210         u8              devctl;
 211
 212         DBG(1, "HNP: Setting HR\n");
 213         devctl = musb_readb(mbase, MUSB_DEVCTL);
 214         musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
 215 }
 216
 217 /*
 218  * Handle all control requests with no DATA stage, including standard
 219  * requests such as:
 220  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 221  *      always delegated to the gadget driver
 222  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 223  *      always handled here, except for class/vendor/... features
 224  *
 225  * Context:  caller holds controller lock
 226  */
 227 static int
 228 service_zero_data_request(struct musb *musb,
 229                 struct usb_ctrlrequest *ctrlrequest)
 230 __releases(musb->lock)
 231 __acquires(musb->lock)
 232 {
 233         int handled = -EINVAL;
 234         void __iomem *mbase = musb->mregs;
 235         const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
 236
 237         /* the gadget driver handles everything except what we MUST handle */
 238         if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
 239                         == USB_TYPE_STANDARD) {
 240                 switch (ctrlrequest->bRequest) {
 241                 case USB_REQ_SET_ADDRESS:
 242                         /* change it after the status stage */
 243                         musb->set_address = true;
 244                         musb->address = (u8) (ctrlrequest->wValue & 0x7f);
 245                         handled = 1;
 246                         break;
 247
 248                 case USB_REQ_CLEAR_FEATURE:
 249                         switch (recip) {
 250                         case USB_RECIP_DEVICE:
 251                                 if (ctrlrequest->wValue
 252                                                 != USB_DEVICE_REMOTE_WAKEUP)
 253                                         break;
 254                                 musb->may_wakeup = 0;
 255                                 handled = 1;
 256                                 break;
 257                         case USB_RECIP_INTERFACE:
 258                                 break;
 259                         case USB_RECIP_ENDPOINT:{
 260                                 const u8                epnum =
 261                                         ctrlrequest->wIndex & 0x0f;
 262                                 struct musb_ep          *musb_ep;
 263                                 struct musb_hw_ep       *ep;
 264                                 void __iomem            *regs;
 265                                 int                     is_in;
 266                                 u16                     csr;
 267
 268                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 269                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 270                                         break;
 271
 272                                 ep = musb->endpoints + epnum;
 273                                 regs = ep->regs;
 274                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 275                                 if (is_in)
 276                                         musb_ep = &ep->ep_in;
 277                                 else
 278                                         musb_ep = &ep->ep_out;
 279                                 if (!musb_ep->desc)
 280                                         break;
 281
 282                                 handled = 1;
 283                                 /* Ignore request if endpoint is wedged */
 284                                 if (musb_ep->wedged)
 285                                         break;
 286
 287                                 musb_ep_select(mbase, epnum);
 288                                 if (is_in) {
 289                                         csr  = musb_readw(regs, MUSB_TXCSR);
 290                                         csr |= MUSB_TXCSR_CLRDATATOG |
 291                                                MUSB_TXCSR_P_WZC_BITS;
 292                                         csr &= ~(MUSB_TXCSR_P_SENDSTALL |
 293                                                  MUSB_TXCSR_P_SENTSTALL |
 294                                                  MUSB_TXCSR_TXPKTRDY);
 295                                         musb_writew(regs, MUSB_TXCSR, csr);
 296                                 } else {
 297                                         csr  = musb_readw(regs, MUSB_RXCSR);
 298                                         csr |= MUSB_RXCSR_CLRDATATOG |
 299                                                MUSB_RXCSR_P_WZC_BITS;
 300                                         csr &= ~(MUSB_RXCSR_P_SENDSTALL |
 301                                                  MUSB_RXCSR_P_SENTSTALL);
 302                                         musb_writew(regs, MUSB_RXCSR, csr);
 303                                 }
 304
 305                                 /* select ep0 again */
 306                                 musb_ep_select(mbase, 0);
 307                                 } break;
 308                         default:
 309                                 /* class, vendor, etc ... delegate */
 310                                 handled = 0;
 311                                 break;
 312                         }
 313                         break;
 314
 315                 case USB_REQ_SET_FEATURE:
 316                         switch (recip) {
 317                         case USB_RECIP_DEVICE:
 318                                 handled = 1;
 319                                 switch (ctrlrequest->wValue) {
 320                                 case USB_DEVICE_REMOTE_WAKEUP:
 321                                         musb->may_wakeup = 1;
 322                                         break;
 323                                 case USB_DEVICE_TEST_MODE:
 324                                         if (musb->g.speed != USB_SPEED_HIGH)
 325                                                 goto stall;
 326                                         if (ctrlrequest->wIndex & 0xff)
 327                                                 goto stall;
 328
 329                                         switch (ctrlrequest->wIndex >> 8) {
 330                                         case 1:
 331                                                 pr_debug("TEST_J\n");
 332                                                 /* TEST_J */
 333                                                 musb->test_mode_nr =
 334                                                         MUSB_TEST_J;
 335                                                 break;
 336                                         case 2:
 337                                                 /* TEST_K */
 338                                                 pr_debug("TEST_K\n");
 339                                                 musb->test_mode_nr =
 340                                                         MUSB_TEST_K;
 341                                                 break;
 342                                         case 3:
 343                                                 /* TEST_SE0_NAK */
 344                                                 pr_debug("TEST_SE0_NAK\n");
 345                                                 musb->test_mode_nr =
 346                                                         MUSB_TEST_SE0_NAK;
 347                                                 break;
 348                                         case 4:
 349                                                 /* TEST_PACKET */
 350                                                 pr_debug("TEST_PACKET\n");
 351                                                 musb->test_mode_nr =
 352                                                         MUSB_TEST_PACKET;
 353                                                 break;
 354
 355                                         case 0xc0:
 356                                                 /* TEST_FORCE_HS */
 357                                                 pr_debug("TEST_FORCE_HS\n");
 358                                                 musb->test_mode_nr =
 359                                                         MUSB_TEST_FORCE_HS;
 360                                                 break;
 361                                         case 0xc1:
 362                                                 /* TEST_FORCE_FS */
 363                                                 pr_debug("TEST_FORCE_FS\n");
 364                                                 musb->test_mode_nr =
 365                                                         MUSB_TEST_FORCE_FS;
 366                                                 break;
 367                                         case 0xc2:
 368                                                 /* TEST_FIFO_ACCESS */
 369                                                 pr_debug("TEST_FIFO_ACCESS\n");
 370                                                 musb->test_mode_nr =
 371                                                         MUSB_TEST_FIFO_ACCESS;
 372                                                 break;
 373                                         case 0xc3:
 374                                                 /* TEST_FORCE_HOST */
 375                                                 pr_debug("TEST_FORCE_HOST\n");
 376                                                 musb->test_mode_nr =
 377                                                         MUSB_TEST_FORCE_HOST;
 378                                                 break;
 379                                         default:
 380                                                 goto stall;
 381                                         }
 382
 383                                         /* enter test mode after irq */
 384                                         if (handled > 0)
 385                                                 musb->test_mode = true;
 386                                         break;
 387 #ifdef CONFIG_USB_MUSB_OTG
 388                                 case USB_DEVICE_B_HNP_ENABLE:
 389                                         if (!musb->g.is_otg)
 390                                                 goto stall;
 391                                         musb->g.b_hnp_enable = 1;
 392                                         musb_try_b_hnp_enable(musb);
 393                                         break;
 394                                 case USB_DEVICE_A_HNP_SUPPORT:
 395                                         if (!musb->g.is_otg)
 396                                                 goto stall;
 397                                         musb->g.a_hnp_support = 1;
 398                                         break;
 399                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 400                                         if (!musb->g.is_otg)
 401                                                 goto stall;
 402                                         musb->g.a_alt_hnp_support = 1;
 403                                         break;
 404 #endif
 405 stall:
 406                                 default:
 407                                         handled = -EINVAL;
 408                                         break;
 409                                 }
 410                                 break;
 411
 412                         case USB_RECIP_INTERFACE:
 413                                 break;
 414
 415                         case USB_RECIP_ENDPOINT:{
 416                                 const u8                epnum =
 417                                         ctrlrequest->wIndex & 0x0f;
 418                                 struct musb_ep          *musb_ep;
 419                                 struct musb_hw_ep       *ep;
 420                                 void __iomem            *regs;
 421                                 int                     is_in;
 422                                 u16                     csr;
 423
 424                                 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
 425                                     ctrlrequest->wValue != USB_ENDPOINT_HALT)
 426                                         break;
 427
 428                                 ep = musb->endpoints + epnum;
 429                                 regs = ep->regs;
 430                                 is_in = ctrlrequest->wIndex & USB_DIR_IN;
 431                                 if (is_in)
 432                                         musb_ep = &ep->ep_in;
 433                                 else
 434                                         musb_ep = &ep->ep_out;
 435                                 if (!musb_ep->desc)
 436                                         break;
 437
 438                                 musb_ep_select(mbase, epnum);
 439                                 if (is_in) {
 440                                         csr = musb_readw(regs, MUSB_TXCSR);
 441                                         if (csr & MUSB_TXCSR_FIFONOTEMPTY)
 442                                                 csr |= MUSB_TXCSR_FLUSHFIFO;
 443                                         csr |= MUSB_TXCSR_P_SENDSTALL
 444                                                 | MUSB_TXCSR_CLRDATATOG
 445                                                 | MUSB_TXCSR_P_WZC_BITS;
 446                                         musb_writew(regs, MUSB_TXCSR, csr);
 447                                 } else {
 448                                         csr = musb_readw(regs, MUSB_RXCSR);
 449                                         csr |= MUSB_RXCSR_P_SENDSTALL
 450                                                 | MUSB_RXCSR_FLUSHFIFO
 451                                                 | MUSB_RXCSR_CLRDATATOG
 452                                                 | MUSB_RXCSR_P_WZC_BITS;
 453                                         musb_writew(regs, MUSB_RXCSR, csr);
 454                                 }
 455
 456                                 /* select ep0 again */
 457                                 musb_ep_select(mbase, 0);
 458                                 handled = 1;
 459                                 } break;
 460
 461                         default:
 462                                 /* class, vendor, etc ... delegate */
 463                                 handled = 0;
 464                                 break;
 465                         }
 466                         break;
 467                 default:
 468                         /* delegate SET_CONFIGURATION, etc */
 469                         handled = 0;
 470                 }
 471         } else
 472                 handled = 0;
 473         return handled;
 474 }
 475
 476 /* we have an ep0out data packet
 477  * Context:  caller holds controller lock
 478  */
 479 static void ep0_rxstate(struct musb *musb)
 480 {
 481         void __iomem            *regs = musb->control_ep->regs;
 482         struct usb_request      *req;
 483         u16                     count, csr;
 484
 485         req = next_ep0_request(musb);
 486
 487         /* read packet and ack; or stall because of gadget driver bug:
 488          * should have provided the rx buffer before setup() returned.
 489          */
 490         if (req) {
 491                 void            *buf = req->buf + req->actual;
 492                 unsigned        len = req->length - req->actual;
 493
 494                 /* read the buffer */
 495                 count = musb_readb(regs, MUSB_COUNT0);
 496                 if (count > len) {
 497                         req->status = -EOVERFLOW;
 498                         count = len;
 499                 }
 500                 musb_read_fifo(&musb->endpoints[0], count, buf);
 501                 req->actual += count;
 502                 csr = MUSB_CSR0_P_SVDRXPKTRDY;
 503                 if (count < 64 || req->actual == req->length) {
 504                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 505                         csr |= MUSB_CSR0_P_DATAEND;
 506                 } else
 507                         req = NULL;
 508         } else
 509                 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
 510
 511
 512         /* Completion handler may choose to stall, e.g. because the
 513          * message just received holds invalid data.
 514          */
 515         if (req) {
 516                 musb->ackpend = csr;
 517                 musb_g_ep0_giveback(musb, req);
 518                 if (!musb->ackpend)
 519                         return;
 520                 musb->ackpend = 0;
 521         }
 522         musb_ep_select(musb->mregs, 0);
 523         musb_writew(regs, MUSB_CSR0, csr);
 524 }
 525
 526 /*
 527  * transmitting to the host (IN), this code might be called from IRQ
 528  * and from kernel thread.
 529  *
 530  * Context:  caller holds controller lock
 531  */
 532 static void ep0_txstate(struct musb *musb)
 533 {
 534         void __iomem            *regs = musb->control_ep->regs;
 535         struct usb_request      *request = next_ep0_request(musb);
 536         u16                     csr = MUSB_CSR0_TXPKTRDY;
 537         u8                      *fifo_src;
 538         u8                      fifo_count;
 539
 540         if (!request) {
 541                 /* WARN_ON(1); */
 542                 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
 543                 return;
 544         }
 545
 546         /* load the data */
 547         fifo_src = (u8 *) request->buf + request->actual;
 548         fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
 549                 request->length - request->actual);
 550         musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
 551         request->actual += fifo_count;
 552
 553         /* update the flags */
 554         if (fifo_count < MUSB_MAX_END0_PACKET
 555                         || (request->actual == request->length
 556                                 && !request->zero)) {
 557                 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 558                 csr |= MUSB_CSR0_P_DATAEND;
 559         } else
 560                 request = NULL;
 561
 562         /* report completions as soon as the fifo's loaded; there's no
 563          * win in waiting till this last packet gets acked.  (other than
 564          * very precise fault reporting, needed by USB TMC; possible with
 565          * this hardware, but not usable from portable gadget drivers.)
 566          */
 567         if (request) {
 568                 musb->ackpend = csr;
 569                 musb_g_ep0_giveback(musb, request);
 570                 if (!musb->ackpend)
 571                         return;
 572                 musb->ackpend = 0;
 573         }
 574
 575         /* send it out, triggering a "txpktrdy cleared" irq */
 576         musb_ep_select(musb->mregs, 0);
 577         musb_writew(regs, MUSB_CSR0, csr);
 578 }
 579
 580 /*
 581  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 582  * Fields are left in USB byte-order.
 583  *
 584  * Context:  caller holds controller lock.
 585  */
 586 static void
 587 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
 588 {
 589         struct usb_request      *r;
 590         void __iomem            *regs = musb->control_ep->regs;
 591
 592         musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
 593
 594         /* NOTE:  earlier 2.6 versions changed setup packets to host
 595          * order, but now USB packets always stay in USB byte order.
 596          */
 597         DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
 598                 req->bRequestType,
 599                 req->bRequest,
 600                 le16_to_cpu(req->wValue),
 601                 le16_to_cpu(req->wIndex),
 602                 le16_to_cpu(req->wLength));
 603
 604         /* clean up any leftover transfers */
 605         r = next_ep0_request(musb);
 606         if (r)
 607                 musb_g_ep0_giveback(musb, r);
 608
 609         /* For zero-data requests we want to delay the STATUS stage to
 610          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 611          * packets until there's a buffer to store them in.
 612          *
 613          * If we write data, the controller acts happier if we enable
 614          * the TX FIFO right away, and give the controller a moment
 615          * to switch modes...
 616          */
 617         musb->set_address = false;
 618         musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
 619         if (req->wLength == 0) {
 620                 if (req->bRequestType & USB_DIR_IN)
 621                         musb->ackpend |= MUSB_CSR0_TXPKTRDY;
 622                 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
 623         } else if (req->bRequestType & USB_DIR_IN) {
 624                 musb->ep0_state = MUSB_EP0_STAGE_TX;
 625                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
 626                 while ((musb_readw(regs, MUSB_CSR0)
 627                                 & MUSB_CSR0_RXPKTRDY) != 0)
 628                         cpu_relax();
 629                 musb->ackpend = 0;
 630         } else
 631                 musb->ep0_state = MUSB_EP0_STAGE_RX;
 632 }
 633
 634 static int
 635 forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
 636 __releases(musb->lock)
 637 __acquires(musb->lock)
 638 {
 639         int retval;
 640         if (!musb->gadget_driver)
 641                 return -EOPNOTSUPP;
 642         spin_unlock(&musb->lock);
 643         retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
 644         spin_lock(&musb->lock);
 645         return retval;
 646 }
 647
 648 /*
 649  * Handle peripheral ep0 interrupt
 650  *
 651  * Context: irq handler; we won't re-enter the driver that way.
 652  */
 653 irqreturn_t musb_g_ep0_irq(struct musb *musb)
 654 {
 655         u16             csr;
 656         u16             len;
 657         void __iomem    *mbase = musb->mregs;
 658         void __iomem    *regs = musb->endpoints[0].regs;
 659         irqreturn_t     retval = IRQ_NONE;
 660
 661         musb_ep_select(mbase, 0);       /* select ep0 */
 662         csr = musb_readw(regs, MUSB_CSR0);
 663         len = musb_readb(regs, MUSB_COUNT0);
 664
 665         DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
 666                         csr, len,
 667                         musb_readb(mbase, MUSB_FADDR),
 668                         decode_ep0stage(musb->ep0_state));
 669
 670         /* I sent a stall.. need to acknowledge it now.. */
 671         if (csr & MUSB_CSR0_P_SENTSTALL) {
 672                 musb_writew(regs, MUSB_CSR0,
 673                                 csr & ~MUSB_CSR0_P_SENTSTALL);
 674                 retval = IRQ_HANDLED;
 675                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 676                 csr = musb_readw(regs, MUSB_CSR0);
 677         }
 678
 679         /* request ended "early" */
 680         if (csr & MUSB_CSR0_P_SETUPEND) {
 681                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
 682                 retval = IRQ_HANDLED;
 683                 /* Transition into the early status phase */
 684                 switch (musb->ep0_state) {
 685                 case MUSB_EP0_STAGE_TX:
 686                         musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
 687                         break;
 688                 case MUSB_EP0_STAGE_RX:
 689                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 690                         break;
 691                 default:
 692                         ERR("SetupEnd came in a wrong ep0stage %s\n",
 693                             decode_ep0stage(musb->ep0_state));
 694                 }
 695                 csr = musb_readw(regs, MUSB_CSR0);
 696                 /* NOTE:  request may need completion */
 697         }
 698
 699         /* docs from Mentor only describe tx, rx, and idle/setup states.
 700          * we need to handle nuances around status stages, and also the
 701          * case where status and setup stages come back-to-back ...
 702          */
 703         switch (musb->ep0_state) {
 704
 705         case MUSB_EP0_STAGE_TX:
 706                 /* irq on clearing txpktrdy */
 707                 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
 708                         ep0_txstate(musb);
 709                         retval = IRQ_HANDLED;
 710                 }
 711                 break;
 712
 713         case MUSB_EP0_STAGE_RX:
 714                 /* irq on set rxpktrdy */
 715                 if (csr & MUSB_CSR0_RXPKTRDY) {
 716                         ep0_rxstate(musb);
 717                         retval = IRQ_HANDLED;
 718                 }
 719                 break;
 720
 721         case MUSB_EP0_STAGE_STATUSIN:
 722                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 723
 724                 /* update address (if needed) only @ the end of the
 725                  * status phase per usb spec, which also guarantees
 726                  * we get 10 msec to receive this irq... until this
 727                  * is done we won't see the next packet.
 728                  */
 729                 if (musb->set_address) {
 730                         musb->set_address = false;
 731                         musb_writeb(mbase, MUSB_FADDR, musb->address);
 732                 }
 733
 734                 /* enter test mode if needed (exit by reset) */
 735                 else if (musb->test_mode) {
 736                         DBG(1, "entering TESTMODE\n");
 737
 738                         if (MUSB_TEST_PACKET == musb->test_mode_nr)
 739                                 musb_load_testpacket(musb);
 740
 741                         musb_writeb(mbase, MUSB_TESTMODE,
 742                                         musb->test_mode_nr);
 743                 }
 744                 /* FALLTHROUGH */
 745
 746         case MUSB_EP0_STAGE_STATUSOUT:
 747                 /* end of sequence #1: write to host (TX state) */
 748                 {
 749                         struct usb_request      *req;
 750
 751                         req = next_ep0_request(musb);
 752                         if (req)
 753                                 musb_g_ep0_giveback(musb, req);
 754                 }
 755
 756                 /*
 757                  * In case when several interrupts can get coalesced,
 758                  * check to see if we've already received a SETUP packet...
 759                  */
 760                 if (csr & MUSB_CSR0_RXPKTRDY)
 761                         goto setup;
 762
 763                 retval = IRQ_HANDLED;
 764                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 765                 break;
 766
 767         case MUSB_EP0_STAGE_IDLE:
 768                 /*
 769                  * This state is typically (but not always) indiscernible
 770                  * from the status states since the corresponding interrupts
 771                  * tend to happen within too little period of time (with only
 772                  * a zero-length packet in between) and so get coalesced...
 773                  */
 774                 retval = IRQ_HANDLED;
 775                 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
 776                 /* FALLTHROUGH */
 777
 778         case MUSB_EP0_STAGE_SETUP:
 779 setup:
 780                 if (csr & MUSB_CSR0_RXPKTRDY) {
 781                         struct usb_ctrlrequest  setup;
 782                         int                     handled = 0;
 783
 784                         if (len != 8) {
 785                                 ERR("SETUP packet len %d != 8 ?\n", len);
 786                                 break;
 787                         }
 788                         musb_read_setup(musb, &setup);
 789                         retval = IRQ_HANDLED;
 790
 791                         /* sometimes the RESET won't be reported */
 792                         if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
 793                                 u8      power;
 794
 795                                 printk(KERN_NOTICE "%s: peripheral reset "
 796                                                 "irq lost!\n",
 797                                                 musb_driver_name);
 798                                 power = musb_readb(mbase, MUSB_POWER);
 799                                 musb->g.speed = (power & MUSB_POWER_HSMODE)
 800                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 801
 802                         }
 803
 804                         switch (musb->ep0_state) {
 805
 806                         /* sequence #3 (no data stage), includes requests
 807                          * we can't forward (notably SET_ADDRESS and the
 808                          * device/endpoint feature set/clear operations)
 809                          * plus SET_CONFIGURATION and others we must
 810                          */
 811                         case MUSB_EP0_STAGE_ACKWAIT:
 812                                 handled = service_zero_data_request(
 813                                                 musb, &setup);
 814
 815                                 /*
 816                                  * We're expecting no data in any case, so
 817                                  * always set the DATAEND bit -- doing this
 818                                  * here helps avoid SetupEnd interrupt coming
 819                                  * in the idle stage when we're stalling...
 820                                  */
 821                                 musb->ackpend |= MUSB_CSR0_P_DATAEND;
 822
 823                                 /* status stage might be immediate */
 824                                 if (handled > 0)
 825                                         musb->ep0_state =
 826                                                 MUSB_EP0_STAGE_STATUSIN;
 827                                 break;
 828
 829                         /* sequence #1 (IN to host), includes GET_STATUS
 830                          * requests that we can't forward, GET_DESCRIPTOR
 831                          * and others that we must
 832                          */
 833                         case MUSB_EP0_STAGE_TX:
 834                                 handled = service_in_request(musb, &setup);
 835                                 if (handled > 0) {
 836                                         musb->ackpend = MUSB_CSR0_TXPKTRDY
 837                                                 | MUSB_CSR0_P_DATAEND;
 838                                         musb->ep0_state =
 839                                                 MUSB_EP0_STAGE_STATUSOUT;
 840                                 }
 841                                 break;
 842
 843                         /* sequence #2 (OUT from host), always forward */
 844                         default:                /* MUSB_EP0_STAGE_RX */
 845                                 break;
 846                         }
 847
 848                         DBG(3, "handled %d, csr %04x, ep0stage %s\n",
 849                                 handled, csr,
 850                                 decode_ep0stage(musb->ep0_state));
 851
 852                         /* unless we need to delegate this to the gadget
 853                          * driver, we know how to wrap this up:  csr0 has
 854                          * not yet been written.
 855                          */
 856                         if (handled < 0)
 857                                 goto stall;
 858                         else if (handled > 0)
 859                                 goto finish;
 860
 861                         handled = forward_to_driver(musb, &setup);
 862                         if (handled < 0) {
 863                                 musb_ep_select(mbase, 0);
 864 stall:
 865                                 DBG(3, "stall (%d)\n", handled);
 866                                 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
 867                                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 868 finish:
 869                                 musb_writew(regs, MUSB_CSR0,
 870                                                 musb->ackpend);
 871                                 musb->ackpend = 0;
 872                         }
 873                 }
 874                 break;
 875
 876         case MUSB_EP0_STAGE_ACKWAIT:
 877                 /* This should not happen. But happens with tusb6010 with
 878                  * g_file_storage and high speed. Do nothing.
 879                  */
 880                 retval = IRQ_HANDLED;
 881                 break;
 882
 883         default:
 884                 /* "can't happen" */
 885                 WARN_ON(1);
 886                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
 887                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 888                 break;
 889         }
 890
 891         return retval;
 892 }
 893
 894
 895 static int
 896 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 897 {
 898         /* always enabled */
 899         return -EINVAL;
 900 }
 901
 902 static int musb_g_ep0_disable(struct usb_ep *e)
 903 {
 904         /* always enabled */
 905         return -EINVAL;
 906 }
 907
 908 static int
 909 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 910 {
 911         struct musb_ep          *ep;
 912         struct musb_request     *req;
 913         struct musb             *musb;
 914         int                     status;
 915         unsigned long           lockflags;
 916         void __iomem            *regs;
 917
 918         if (!e || !r)
 919                 return -EINVAL;
 920
 921         ep = to_musb_ep(e);
 922         musb = ep->musb;
 923         regs = musb->control_ep->regs;
 924
 925         req = to_musb_request(r);
 926         req->musb = musb;
 927         req->request.actual = 0;
 928         req->request.status = -EINPROGRESS;
 929         req->tx = ep->is_in;
 930
 931         spin_lock_irqsave(&musb->lock, lockflags);
 932
 933         if (!list_empty(&ep->req_list)) {
 934                 status = -EBUSY;
 935                 goto cleanup;
 936         }
 937
 938         switch (musb->ep0_state) {
 939         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
 940         case MUSB_EP0_STAGE_TX:         /* control-IN data */
 941         case MUSB_EP0_STAGE_ACKWAIT:    /* zero-length data */
 942                 status = 0;
 943                 break;
 944         default:
 945                 DBG(1, "ep0 request queued in state %d\n",
 946                                 musb->ep0_state);
 947                 status = -EINVAL;
 948                 goto cleanup;
 949         }
 950
 951         /* add request to the list */
 952         list_add_tail(&(req->request.list), &(ep->req_list));
 953
 954         DBG(3, "queue to %s (%s), length=%d\n",
 955                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 956                         req->request.length);
 957
 958         musb_ep_select(musb->mregs, 0);
 959
 960         /* sequence #1, IN ... start writing the data */
 961         if (musb->ep0_state == MUSB_EP0_STAGE_TX)
 962                 ep0_txstate(musb);
 963
 964         /* sequence #3, no-data ... issue IN status */
 965         else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
 966                 if (req->request.length)
 967                         status = -EINVAL;
 968                 else {
 969                         musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
 970                         musb_writew(regs, MUSB_CSR0,
 971                                         musb->ackpend | MUSB_CSR0_P_DATAEND);
 972                         musb->ackpend = 0;
 973                         musb_g_ep0_giveback(ep->musb, r);
 974                 }
 975
 976         /* else for sequence #2 (OUT), caller provides a buffer
 977          * before the next packet arrives.  deferred responses
 978          * (after SETUP is acked) are racey.
 979          */
 980         } else if (musb->ackpend) {
 981                 musb_writew(regs, MUSB_CSR0, musb->ackpend);
 982                 musb->ackpend = 0;
 983         }
 984
 985 cleanup:
 986         spin_unlock_irqrestore(&musb->lock, lockflags);
 987         return status;
 988 }
 989
 990 static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
 991 {
 992         /* we just won't support this */
 993         return -EINVAL;
 994 }
 995
 996 static int musb_g_ep0_halt(struct usb_ep *e, int value)
 997 {
 998         struct musb_ep          *ep;
 999         struct musb             *musb;
1000         void __iomem            *base, *regs;
1001         unsigned long           flags;
1002         int                     status;
1003         u16                     csr;
1004
1005         if (!e || !value)
1006                 return -EINVAL;
1007
1008         ep = to_musb_ep(e);
1009         musb = ep->musb;
1010         base = musb->mregs;
1011         regs = musb->control_ep->regs;
1012         status = 0;
1013
1014         spin_lock_irqsave(&musb->lock, flags);
1015
1016         if (!list_empty(&ep->req_list)) {
1017                 status = -EBUSY;
1018                 goto cleanup;
1019         }
1020
1021         musb_ep_select(base, 0);
1022         csr = musb->ackpend;
1023
1024         switch (musb->ep0_state) {
1025
1026         /* Stalls are usually issued after parsing SETUP packet, either
1027          * directly in irq context from setup() or else later.
1028          */
1029         case MUSB_EP0_STAGE_TX:         /* control-IN data */
1030         case MUSB_EP0_STAGE_ACKWAIT:    /* STALL for zero-length data */
1031         case MUSB_EP0_STAGE_RX:         /* control-OUT data */
1032                 csr = musb_readw(regs, MUSB_CSR0);
1033                 /* FALLTHROUGH */
1034
1035         /* It's also OK to issue stalls during callbacks when a non-empty
1036          * DATA stage buffer has been read (or even written).
1037          */
1038         case MUSB_EP0_STAGE_STATUSIN:   /* control-OUT status */
1039         case MUSB_EP0_STAGE_STATUSOUT:  /* control-IN status */
1040
1041                 csr |= MUSB_CSR0_P_SENDSTALL;
1042                 musb_writew(regs, MUSB_CSR0, csr);
1043                 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
1044                 musb->ackpend = 0;
1045                 break;
1046         default:
1047                 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
1048                 status = -EINVAL;
1049         }
1050
1051 cleanup:
1052         spin_unlock_irqrestore(&musb->lock, flags);
1053         return status;
1054 }
1055
1056 const struct usb_ep_ops musb_g_ep0_ops = {
1057         .enable         = musb_g_ep0_enable,
1058         .disable        = musb_g_ep0_disable,
1059         .alloc_request  = musb_alloc_request,
1060         .free_request   = musb_free_request,
1061         .queue          = musb_g_ep0_queue,
1062         .dequeue        = musb_g_ep0_dequeue,
1063         .set_halt       = musb_g_ep0_halt,
1064 };