2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
47 #include "musb_core.h"
50 /* MUSB PERIPHERAL status 3-mar-2006:
52 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
55 * + remote wakeup to Linux hosts work, but saw USBCV failures;
56 * in one test run (operator error?)
57 * + endpoint halt tests -- in both usbtest and usbcv -- seem
58 * to break when dma is enabled ... is something wrongly
61 * - Mass storage behaved ok when last tested. Network traffic patterns
62 * (with lots of short transfers etc) need retesting; they turn up the
63 * worst cases of the DMA, since short packets are typical but are not
67 * + both pio and dma behave in with network and g_zero tests
68 * + no cppi throughput issues other than no-hw-queueing
69 * + failed with FLAT_REG (DaVinci)
70 * + seems to behave with double buffering, PIO -and- CPPI
71 * + with gadgetfs + AIO, requests got lost?
74 * + both pio and dma behave in with network and g_zero tests
75 * + dma is slow in typical case (short_not_ok is clear)
76 * + double buffering ok with PIO
77 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
78 * + request lossage observed with gadgetfs
80 * - ISO not tested ... might work, but only weakly isochronous
82 * - Gadget driver disabling of softconnect during bind() is ignored; so
83 * drivers can't hold off host requests until userspace is ready.
84 * (Workaround: they can turn it off later.)
86 * - PORTABILITY (assumes PIO works):
87 * + DaVinci, basically works with cppi dma
88 * + OMAP 2430, ditto with mentor dma
89 * + TUSB 6010, platform-specific dma in the works
92 /* ----------------------------------------------------------------------- */
95 * Immediately complete a request.
97 * @param request the request to complete
98 * @param status the status to complete the request with
99 * Context: controller locked, IRQs blocked.
101 void musb_g_giveback(
103 struct usb_request *request,
105 __releases(ep->musb->lock)
106 __acquires(ep->musb->lock)
108 struct musb_request *req;
112 req = to_musb_request(request);
114 list_del(&request->list);
115 if (req->request.status == -EINPROGRESS)
116 req->request.status = status;
120 spin_unlock(&musb->lock);
121 if (is_dma_capable()) {
123 dma_unmap_single(musb->controller,
129 req->request.dma = DMA_ADDR_INVALID;
131 } else if (req->request.dma != DMA_ADDR_INVALID)
132 dma_sync_single_for_cpu(musb->controller,
139 if (request->status == 0)
140 DBG(5, "%s done request %p, %d/%d\n",
141 ep->end_point.name, request,
142 req->request.actual, req->request.length);
144 DBG(2, "%s request %p, %d/%d fault %d\n",
145 ep->end_point.name, request,
146 req->request.actual, req->request.length,
148 req->request.complete(&req->ep->end_point, &req->request);
149 spin_lock(&musb->lock);
153 /* ----------------------------------------------------------------------- */
156 * Abort requests queued to an endpoint using the status. Synchronous.
157 * caller locked controller and blocked irqs, and selected this ep.
159 static void nuke(struct musb_ep *ep, const int status)
161 struct musb_request *req = NULL;
162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
166 if (is_dma_capable() && ep->dma) {
167 struct dma_controller *c = ep->musb->dma_controller;
172 * The programming guide says that we must not clear
173 * the DMAMODE bit before DMAENAB, so we only
174 * clear it in the second write...
176 musb_writew(epio, MUSB_TXCSR,
177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
178 musb_writew(epio, MUSB_TXCSR,
179 0 | MUSB_TXCSR_FLUSHFIFO);
181 musb_writew(epio, MUSB_RXCSR,
182 0 | MUSB_RXCSR_FLUSHFIFO);
183 musb_writew(epio, MUSB_RXCSR,
184 0 | MUSB_RXCSR_FLUSHFIFO);
187 value = c->channel_abort(ep->dma);
188 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
189 c->channel_release(ep->dma);
193 while (!list_empty(&(ep->req_list))) {
194 req = container_of(ep->req_list.next, struct musb_request,
196 musb_g_giveback(ep, &req->request, status);
200 /* ----------------------------------------------------------------------- */
202 /* Data transfers - pure PIO, pure DMA, or mixed mode */
205 * This assumes the separate CPPI engine is responding to DMA requests
206 * from the usb core ... sequenced a bit differently from mentor dma.
209 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
211 if (can_bulk_split(musb, ep->type))
212 return ep->hw_ep->max_packet_sz_tx;
214 return ep->packet_sz;
218 #ifdef CONFIG_USB_INVENTRA_DMA
220 /* Peripheral tx (IN) using Mentor DMA works as follows:
221 Only mode 0 is used for transfers <= wPktSize,
222 mode 1 is used for larger transfers,
224 One of the following happens:
225 - Host sends IN token which causes an endpoint interrupt
227 -> if DMA is currently busy, exit.
228 -> if queue is non-empty, txstate().
230 - Request is queued by the gadget driver.
231 -> if queue was previously empty, txstate()
236 | (data is transferred to the FIFO, then sent out when
237 | IN token(s) are recd from Host.
238 | -> DMA interrupt on completion
240 | -> stop DMA, ~DMAENAB,
241 | -> set TxPktRdy for last short pkt or zlp
242 | -> Complete Request
243 | -> Continue next request (call txstate)
244 |___________________________________|
246 * Non-Mentor DMA engines can of course work differently, such as by
247 * upleveling from irq-per-packet to irq-per-buffer.
253 * An endpoint is transmitting data. This can be called either from
254 * the IRQ routine or from ep.queue() to kickstart a request on an
257 * Context: controller locked, IRQs blocked, endpoint selected
259 static void txstate(struct musb *musb, struct musb_request *req)
261 u8 epnum = req->epnum;
262 struct musb_ep *musb_ep;
263 void __iomem *epio = musb->endpoints[epnum].regs;
264 struct usb_request *request;
265 u16 fifo_count = 0, csr;
270 /* we shouldn't get here while DMA is active ... but we do ... */
271 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
272 DBG(4, "dma pending...\n");
276 /* read TXCSR before */
277 csr = musb_readw(epio, MUSB_TXCSR);
279 request = &req->request;
280 fifo_count = min(max_ep_writesize(musb, musb_ep),
281 (int)(request->length - request->actual));
283 if (csr & MUSB_TXCSR_TXPKTRDY) {
284 DBG(5, "%s old packet still ready , txcsr %03x\n",
285 musb_ep->end_point.name, csr);
289 if (csr & MUSB_TXCSR_P_SENDSTALL) {
290 DBG(5, "%s stalling, txcsr %03x\n",
291 musb_ep->end_point.name, csr);
295 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
296 epnum, musb_ep->packet_sz, fifo_count,
299 #ifndef CONFIG_MUSB_PIO_ONLY
300 if (is_dma_capable() && musb_ep->dma) {
301 struct dma_controller *c = musb->dma_controller;
303 use_dma = (request->dma != DMA_ADDR_INVALID);
305 /* MUSB_TXCSR_P_ISO is still set correctly */
307 #ifdef CONFIG_USB_INVENTRA_DMA
311 /* setup DMA, then program endpoint CSR */
312 request_size = min(request->length,
313 musb_ep->dma->max_len);
314 if (request_size < musb_ep->packet_sz)
315 musb_ep->dma->desired_mode = 0;
317 musb_ep->dma->desired_mode = 1;
319 use_dma = use_dma && c->channel_program(
320 musb_ep->dma, musb_ep->packet_sz,
321 musb_ep->dma->desired_mode,
322 request->dma, request_size);
324 if (musb_ep->dma->desired_mode == 0) {
326 * We must not clear the DMAMODE bit
327 * before the DMAENAB bit -- and the
328 * latter doesn't always get cleared
329 * before we get here...
331 csr &= ~(MUSB_TXCSR_AUTOSET
332 | MUSB_TXCSR_DMAENAB);
333 musb_writew(epio, MUSB_TXCSR, csr
334 | MUSB_TXCSR_P_WZC_BITS);
335 csr &= ~MUSB_TXCSR_DMAMODE;
336 csr |= (MUSB_TXCSR_DMAENAB |
338 /* against programming guide */
340 csr |= (MUSB_TXCSR_AUTOSET
345 csr &= ~MUSB_TXCSR_P_UNDERRUN;
346 musb_writew(epio, MUSB_TXCSR, csr);
350 #elif defined(CONFIG_USB_TI_CPPI_DMA)
351 /* program endpoint CSR first, then setup DMA */
352 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
353 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
355 musb_writew(epio, MUSB_TXCSR,
356 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
359 /* ensure writebuffer is empty */
360 csr = musb_readw(epio, MUSB_TXCSR);
362 /* NOTE host side sets DMAENAB later than this; both are
363 * OK since the transfer dma glue (between CPPI and Mentor
364 * fifos) just tells CPPI it could start. Data only moves
365 * to the USB TX fifo when both fifos are ready.
368 /* "mode" is irrelevant here; handle terminating ZLPs like
369 * PIO does, since the hardware RNDIS mode seems unreliable
370 * except for the last-packet-is-already-short case.
372 use_dma = use_dma && c->channel_program(
373 musb_ep->dma, musb_ep->packet_sz,
378 c->channel_release(musb_ep->dma);
380 csr &= ~MUSB_TXCSR_DMAENAB;
381 musb_writew(epio, MUSB_TXCSR, csr);
382 /* invariant: prequest->buf is non-null */
384 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
385 use_dma = use_dma && c->channel_program(
386 musb_ep->dma, musb_ep->packet_sz,
395 musb_write_fifo(musb_ep->hw_ep, fifo_count,
396 (u8 *) (request->buf + request->actual));
397 request->actual += fifo_count;
398 csr |= MUSB_TXCSR_TXPKTRDY;
399 csr &= ~MUSB_TXCSR_P_UNDERRUN;
400 musb_writew(epio, MUSB_TXCSR, csr);
403 /* host may already have the data when this message shows... */
404 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
405 musb_ep->end_point.name, use_dma ? "dma" : "pio",
406 request->actual, request->length,
407 musb_readw(epio, MUSB_TXCSR),
409 musb_readw(epio, MUSB_TXMAXP));
413 * FIFO state update (e.g. data ready).
414 * Called from IRQ, with controller locked.
416 void musb_g_tx(struct musb *musb, u8 epnum)
419 struct usb_request *request;
420 u8 __iomem *mbase = musb->mregs;
421 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
422 void __iomem *epio = musb->endpoints[epnum].regs;
423 struct dma_channel *dma;
425 musb_ep_select(mbase, epnum);
426 request = next_request(musb_ep);
428 csr = musb_readw(epio, MUSB_TXCSR);
429 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
431 dma = is_dma_capable() ? musb_ep->dma : NULL;
433 /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
434 * probably rates reporting as a host error
436 if (csr & MUSB_TXCSR_P_SENTSTALL) {
437 csr |= MUSB_TXCSR_P_WZC_BITS;
438 csr &= ~MUSB_TXCSR_P_SENTSTALL;
439 musb_writew(epio, MUSB_TXCSR, csr);
443 if (csr & MUSB_TXCSR_P_UNDERRUN) {
444 /* we NAKed, no big deal ... little reason to care */
445 csr |= MUSB_TXCSR_P_WZC_BITS;
446 csr &= ~(MUSB_TXCSR_P_UNDERRUN
447 | MUSB_TXCSR_TXPKTRDY);
448 musb_writew(epio, MUSB_TXCSR, csr);
449 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
453 /* SHOULD NOT HAPPEN ... has with cppi though, after
454 * changing SENDSTALL (and other cases); harmless?
456 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
463 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
465 csr |= MUSB_TXCSR_P_WZC_BITS;
466 csr &= ~(MUSB_TXCSR_DMAENAB
467 | MUSB_TXCSR_P_UNDERRUN
468 | MUSB_TXCSR_TXPKTRDY);
469 musb_writew(epio, MUSB_TXCSR, csr);
470 /* ensure writebuffer is empty */
471 csr = musb_readw(epio, MUSB_TXCSR);
472 request->actual += musb_ep->dma->actual_len;
473 DBG(4, "TXCSR%d %04x, dma off, "
476 musb_ep->dma->actual_len,
480 if (is_dma || request->actual == request->length) {
482 /* First, maybe a terminating short packet.
483 * Some DMA engines might handle this by
489 % musb_ep->packet_sz)
491 #ifdef CONFIG_USB_INVENTRA_DMA
493 ((!dma->desired_mode) ||
495 (musb_ep->packet_sz - 1))))
498 /* on dma completion, fifo may not
499 * be available yet ...
501 if (csr & MUSB_TXCSR_TXPKTRDY)
504 DBG(4, "sending zero pkt\n");
505 musb_writew(epio, MUSB_TXCSR,
507 | MUSB_TXCSR_TXPKTRDY);
511 /* ... or if not, then complete it */
512 musb_g_giveback(musb_ep, request, 0);
514 /* kickstart next transfer if appropriate;
515 * the packet that just completed might not
516 * be transmitted for hours or days.
517 * REVISIT for double buffering...
518 * FIXME revisit for stalls too...
520 musb_ep_select(mbase, epnum);
521 csr = musb_readw(epio, MUSB_TXCSR);
522 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
524 request = musb_ep->desc
525 ? next_request(musb_ep)
528 DBG(4, "%s idle now\n",
529 musb_ep->end_point.name);
534 txstate(musb, to_musb_request(request));
540 /* ------------------------------------------------------------ */
542 #ifdef CONFIG_USB_INVENTRA_DMA
544 /* Peripheral rx (OUT) using Mentor DMA works as follows:
545 - Only mode 0 is used.
547 - Request is queued by the gadget class driver.
548 -> if queue was previously empty, rxstate()
550 - Host sends OUT token which causes an endpoint interrupt
552 | -> if request queued, call rxstate
554 | | -> DMA interrupt on completion
558 | | -> if data recd = max expected
559 | | by the request, or host
560 | | sent a short packet,
561 | | complete the request,
562 | | and start the next one.
563 | |_____________________________________|
564 | else just wait for the host
565 | to send the next OUT token.
566 |__________________________________________________|
568 * Non-Mentor DMA engines can of course work differently.
574 * Context: controller locked, IRQs blocked, endpoint selected
576 static void rxstate(struct musb *musb, struct musb_request *req)
578 const u8 epnum = req->epnum;
579 struct usb_request *request = &req->request;
580 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
581 void __iomem *epio = musb->endpoints[epnum].regs;
582 unsigned fifo_count = 0;
583 u16 len = musb_ep->packet_sz;
584 u16 csr = musb_readw(epio, MUSB_RXCSR);
586 /* We shouldn't get here while DMA is active, but we do... */
587 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
588 DBG(4, "DMA pending...\n");
592 if (csr & MUSB_RXCSR_P_SENDSTALL) {
593 DBG(5, "%s stalling, RXCSR %04x\n",
594 musb_ep->end_point.name, csr);
598 if (is_cppi_enabled() && musb_ep->dma) {
599 struct dma_controller *c = musb->dma_controller;
600 struct dma_channel *channel = musb_ep->dma;
602 /* NOTE: CPPI won't actually stop advancing the DMA
603 * queue after short packet transfers, so this is almost
604 * always going to run as IRQ-per-packet DMA so that
605 * faults will be handled correctly.
607 if (c->channel_program(channel,
609 !request->short_not_ok,
610 request->dma + request->actual,
611 request->length - request->actual)) {
613 /* make sure that if an rxpkt arrived after the irq,
614 * the cppi engine will be ready to take it as soon
617 csr &= ~(MUSB_RXCSR_AUTOCLEAR
618 | MUSB_RXCSR_DMAMODE);
619 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
620 musb_writew(epio, MUSB_RXCSR, csr);
625 if (csr & MUSB_RXCSR_RXPKTRDY) {
626 len = musb_readw(epio, MUSB_RXCOUNT);
627 if (request->actual < request->length) {
628 #ifdef CONFIG_USB_INVENTRA_DMA
629 if (is_dma_capable() && musb_ep->dma) {
630 struct dma_controller *c;
631 struct dma_channel *channel;
634 c = musb->dma_controller;
635 channel = musb_ep->dma;
637 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
638 * mode 0 only. So we do not get endpoint interrupts due to DMA
639 * completion. We only get interrupts from DMA controller.
641 * We could operate in DMA mode 1 if we knew the size of the tranfer
642 * in advance. For mass storage class, request->length = what the host
643 * sends, so that'd work. But for pretty much everything else,
644 * request->length is routinely more than what the host sends. For
645 * most these gadgets, end of is signified either by a short packet,
646 * or filling the last byte of the buffer. (Sending extra data in
647 * that last pckate should trigger an overflow fault.) But in mode 1,
648 * we don't get DMA completion interrrupt for short packets.
650 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
651 * to get endpoint interrupt on every DMA req, but that didn't seem
654 * REVISIT an updated g_file_storage can set req->short_not_ok, which
655 * then becomes usable as a runtime "use mode 1" hint...
658 csr |= MUSB_RXCSR_DMAENAB;
660 csr |= MUSB_RXCSR_AUTOCLEAR;
661 /* csr |= MUSB_RXCSR_DMAMODE; */
663 /* this special sequence (enabling and then
664 * disabling MUSB_RXCSR_DMAMODE) is required
665 * to get DMAReq to activate
667 musb_writew(epio, MUSB_RXCSR,
668 csr | MUSB_RXCSR_DMAMODE);
670 musb_writew(epio, MUSB_RXCSR, csr);
672 if (request->actual < request->length) {
673 int transfer_size = 0;
675 transfer_size = min(request->length,
680 if (transfer_size <= musb_ep->packet_sz)
681 musb_ep->dma->desired_mode = 0;
683 musb_ep->dma->desired_mode = 1;
685 use_dma = c->channel_program(
688 channel->desired_mode,
697 #endif /* Mentor's DMA */
699 fifo_count = request->length - request->actual;
700 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
701 musb_ep->end_point.name,
705 fifo_count = min_t(unsigned, len, fifo_count);
707 #ifdef CONFIG_USB_TUSB_OMAP_DMA
708 if (tusb_dma_omap() && musb_ep->dma) {
709 struct dma_controller *c = musb->dma_controller;
710 struct dma_channel *channel = musb_ep->dma;
711 u32 dma_addr = request->dma + request->actual;
714 ret = c->channel_program(channel,
716 channel->desired_mode,
724 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
725 (request->buf + request->actual));
726 request->actual += fifo_count;
728 /* REVISIT if we left anything in the fifo, flush
729 * it and report -EOVERFLOW
733 csr |= MUSB_RXCSR_P_WZC_BITS;
734 csr &= ~MUSB_RXCSR_RXPKTRDY;
735 musb_writew(epio, MUSB_RXCSR, csr);
739 /* reach the end or short packet detected */
740 if (request->actual == request->length || len < musb_ep->packet_sz)
741 musb_g_giveback(musb_ep, request, 0);
745 * Data ready for a request; called from IRQ
747 void musb_g_rx(struct musb *musb, u8 epnum)
750 struct usb_request *request;
751 void __iomem *mbase = musb->mregs;
752 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
753 void __iomem *epio = musb->endpoints[epnum].regs;
754 struct dma_channel *dma;
756 musb_ep_select(mbase, epnum);
758 request = next_request(musb_ep);
760 csr = musb_readw(epio, MUSB_RXCSR);
761 dma = is_dma_capable() ? musb_ep->dma : NULL;
763 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
764 csr, dma ? " (dma)" : "", request);
766 if (csr & MUSB_RXCSR_P_SENTSTALL) {
767 csr |= MUSB_RXCSR_P_WZC_BITS;
768 csr &= ~MUSB_RXCSR_P_SENTSTALL;
769 musb_writew(epio, MUSB_RXCSR, csr);
773 if (csr & MUSB_RXCSR_P_OVERRUN) {
774 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
775 csr &= ~MUSB_RXCSR_P_OVERRUN;
776 musb_writew(epio, MUSB_RXCSR, csr);
778 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
779 if (request && request->status == -EINPROGRESS)
780 request->status = -EOVERFLOW;
782 if (csr & MUSB_RXCSR_INCOMPRX) {
783 /* REVISIT not necessarily an error */
784 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
787 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
788 /* "should not happen"; likely RXPKTRDY pending for DMA */
789 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
790 "%s busy, csr %04x\n",
791 musb_ep->end_point.name, csr);
795 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
796 csr &= ~(MUSB_RXCSR_AUTOCLEAR
798 | MUSB_RXCSR_DMAMODE);
799 musb_writew(epio, MUSB_RXCSR,
800 MUSB_RXCSR_P_WZC_BITS | csr);
802 request->actual += musb_ep->dma->actual_len;
804 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
806 musb_readw(epio, MUSB_RXCSR),
807 musb_ep->dma->actual_len, request);
809 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
810 /* Autoclear doesn't clear RxPktRdy for short packets */
811 if ((dma->desired_mode == 0)
813 & (musb_ep->packet_sz - 1))) {
815 csr &= ~MUSB_RXCSR_RXPKTRDY;
816 musb_writew(epio, MUSB_RXCSR, csr);
819 /* incomplete, and not short? wait for next IN packet */
820 if ((request->actual < request->length)
821 && (musb_ep->dma->actual_len
822 == musb_ep->packet_sz))
825 musb_g_giveback(musb_ep, request, 0);
827 request = next_request(musb_ep);
832 /* analyze request if the ep is hot */
834 rxstate(musb, to_musb_request(request));
836 DBG(3, "packet waiting for %s%s request\n",
837 musb_ep->desc ? "" : "inactive ",
838 musb_ep->end_point.name);
842 /* ------------------------------------------------------------ */
844 static int musb_gadget_enable(struct usb_ep *ep,
845 const struct usb_endpoint_descriptor *desc)
848 struct musb_ep *musb_ep;
849 struct musb_hw_ep *hw_ep;
856 int status = -EINVAL;
861 musb_ep = to_musb_ep(ep);
862 hw_ep = musb_ep->hw_ep;
864 musb = musb_ep->musb;
866 epnum = musb_ep->current_epnum;
868 spin_lock_irqsave(&musb->lock, flags);
874 musb_ep->type = usb_endpoint_type(desc);
876 /* check direction and (later) maxpacket size against endpoint */
877 if (usb_endpoint_num(desc) != epnum)
880 /* REVISIT this rules out high bandwidth periodic transfers */
881 tmp = le16_to_cpu(desc->wMaxPacketSize);
884 musb_ep->packet_sz = tmp;
886 /* enable the interrupts for the endpoint, set the endpoint
887 * packet size (or fail), set the mode, clear the fifo
889 musb_ep_select(mbase, epnum);
890 if (usb_endpoint_dir_in(desc)) {
891 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
893 if (hw_ep->is_shared_fifo)
897 if (tmp > hw_ep->max_packet_sz_tx)
900 int_txe |= (1 << epnum);
901 musb_writew(mbase, MUSB_INTRTXE, int_txe);
903 /* REVISIT if can_bulk_split(), use by updating "tmp";
904 * likewise high bandwidth periodic tx
906 musb_writew(regs, MUSB_TXMAXP, tmp);
908 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
909 if (musb_readw(regs, MUSB_TXCSR)
910 & MUSB_TXCSR_FIFONOTEMPTY)
911 csr |= MUSB_TXCSR_FLUSHFIFO;
912 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
913 csr |= MUSB_TXCSR_P_ISO;
915 /* set twice in case of double buffering */
916 musb_writew(regs, MUSB_TXCSR, csr);
917 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
918 musb_writew(regs, MUSB_TXCSR, csr);
921 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
923 if (hw_ep->is_shared_fifo)
927 if (tmp > hw_ep->max_packet_sz_rx)
930 int_rxe |= (1 << epnum);
931 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
933 /* REVISIT if can_bulk_combine() use by updating "tmp"
934 * likewise high bandwidth periodic rx
936 musb_writew(regs, MUSB_RXMAXP, tmp);
938 /* force shared fifo to OUT-only mode */
939 if (hw_ep->is_shared_fifo) {
940 csr = musb_readw(regs, MUSB_TXCSR);
941 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
942 musb_writew(regs, MUSB_TXCSR, csr);
945 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
946 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
947 csr |= MUSB_RXCSR_P_ISO;
948 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
949 csr |= MUSB_RXCSR_DISNYET;
951 /* set twice in case of double buffering */
952 musb_writew(regs, MUSB_RXCSR, csr);
953 musb_writew(regs, MUSB_RXCSR, csr);
956 /* NOTE: all the I/O code _should_ work fine without DMA, in case
957 * for some reason you run out of channels here.
959 if (is_dma_capable() && musb->dma_controller) {
960 struct dma_controller *c = musb->dma_controller;
962 musb_ep->dma = c->channel_alloc(c, hw_ep,
963 (desc->bEndpointAddress & USB_DIR_IN));
967 musb_ep->desc = desc;
972 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
973 musb_driver_name, musb_ep->end_point.name,
974 ({ char *s; switch (musb_ep->type) {
975 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
976 case USB_ENDPOINT_XFER_INT: s = "int"; break;
977 default: s = "iso"; break;
979 musb_ep->is_in ? "IN" : "OUT",
980 musb_ep->dma ? "dma, " : "",
983 schedule_work(&musb->irq_work);
986 spin_unlock_irqrestore(&musb->lock, flags);
991 * Disable an endpoint flushing all requests queued.
993 static int musb_gadget_disable(struct usb_ep *ep)
998 struct musb_ep *musb_ep;
1002 musb_ep = to_musb_ep(ep);
1003 musb = musb_ep->musb;
1004 epnum = musb_ep->current_epnum;
1005 epio = musb->endpoints[epnum].regs;
1007 spin_lock_irqsave(&musb->lock, flags);
1008 musb_ep_select(musb->mregs, epnum);
1010 /* zero the endpoint sizes */
1011 if (musb_ep->is_in) {
1012 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1013 int_txe &= ~(1 << epnum);
1014 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1015 musb_writew(epio, MUSB_TXMAXP, 0);
1017 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1018 int_rxe &= ~(1 << epnum);
1019 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1020 musb_writew(epio, MUSB_RXMAXP, 0);
1023 musb_ep->desc = NULL;
1025 /* abort all pending DMA and requests */
1026 nuke(musb_ep, -ESHUTDOWN);
1028 schedule_work(&musb->irq_work);
1030 spin_unlock_irqrestore(&(musb->lock), flags);
1032 DBG(2, "%s\n", musb_ep->end_point.name);
1038 * Allocate a request for an endpoint.
1039 * Reused by ep0 code.
1041 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1043 struct musb_ep *musb_ep = to_musb_ep(ep);
1044 struct musb_request *request = NULL;
1046 request = kzalloc(sizeof *request, gfp_flags);
1048 INIT_LIST_HEAD(&request->request.list);
1049 request->request.dma = DMA_ADDR_INVALID;
1050 request->epnum = musb_ep->current_epnum;
1051 request->ep = musb_ep;
1054 return &request->request;
1059 * Reused by ep0 code.
1061 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1063 kfree(to_musb_request(req));
1066 static LIST_HEAD(buffers);
1068 struct free_record {
1069 struct list_head list;
1076 * Context: controller locked, IRQs blocked.
1078 static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1080 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1081 req->tx ? "TX/IN" : "RX/OUT",
1082 &req->request, req->request.length, req->epnum);
1084 musb_ep_select(musb->mregs, req->epnum);
1091 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1094 struct musb_ep *musb_ep;
1095 struct musb_request *request;
1098 unsigned long lockflags;
1105 musb_ep = to_musb_ep(ep);
1106 musb = musb_ep->musb;
1108 request = to_musb_request(req);
1109 request->musb = musb;
1111 if (request->ep != musb_ep)
1114 DBG(4, "<== to %s request=%p\n", ep->name, req);
1116 /* request is mine now... */
1117 request->request.actual = 0;
1118 request->request.status = -EINPROGRESS;
1119 request->epnum = musb_ep->current_epnum;
1120 request->tx = musb_ep->is_in;
1122 if (is_dma_capable() && musb_ep->dma) {
1123 if (request->request.dma == DMA_ADDR_INVALID) {
1124 request->request.dma = dma_map_single(
1126 request->request.buf,
1127 request->request.length,
1131 request->mapped = 1;
1133 dma_sync_single_for_device(musb->controller,
1134 request->request.dma,
1135 request->request.length,
1139 request->mapped = 0;
1141 } else if (!req->buf) {
1144 request->mapped = 0;
1146 spin_lock_irqsave(&musb->lock, lockflags);
1148 /* don't queue if the ep is down */
1149 if (!musb_ep->desc) {
1150 DBG(4, "req %p queued to %s while ep %s\n",
1151 req, ep->name, "disabled");
1152 status = -ESHUTDOWN;
1156 /* add request to the list */
1157 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1159 /* it this is the head of the queue, start i/o ... */
1160 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1161 musb_ep_restart(musb, request);
1164 spin_unlock_irqrestore(&musb->lock, lockflags);
1168 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1170 struct musb_ep *musb_ep = to_musb_ep(ep);
1171 struct usb_request *r;
1172 unsigned long flags;
1174 struct musb *musb = musb_ep->musb;
1176 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1179 spin_lock_irqsave(&musb->lock, flags);
1181 list_for_each_entry(r, &musb_ep->req_list, list) {
1186 DBG(3, "request %p not queued to %s\n", request, ep->name);
1191 /* if the hardware doesn't have the request, easy ... */
1192 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1193 musb_g_giveback(musb_ep, request, -ECONNRESET);
1195 /* ... else abort the dma transfer ... */
1196 else if (is_dma_capable() && musb_ep->dma) {
1197 struct dma_controller *c = musb->dma_controller;
1199 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1200 if (c->channel_abort)
1201 status = c->channel_abort(musb_ep->dma);
1205 musb_g_giveback(musb_ep, request, -ECONNRESET);
1207 /* NOTE: by sticking to easily tested hardware/driver states,
1208 * we leave counting of in-flight packets imprecise.
1210 musb_g_giveback(musb_ep, request, -ECONNRESET);
1214 spin_unlock_irqrestore(&musb->lock, flags);
1219 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1220 * data but will queue requests.
1222 * exported to ep0 code
1224 int musb_gadget_set_halt(struct usb_ep *ep, int value)
1226 struct musb_ep *musb_ep = to_musb_ep(ep);
1227 u8 epnum = musb_ep->current_epnum;
1228 struct musb *musb = musb_ep->musb;
1229 void __iomem *epio = musb->endpoints[epnum].regs;
1230 void __iomem *mbase;
1231 unsigned long flags;
1233 struct musb_request *request;
1238 mbase = musb->mregs;
1240 spin_lock_irqsave(&musb->lock, flags);
1242 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1247 musb_ep_select(mbase, epnum);
1249 request = to_musb_request(next_request(musb_ep));
1252 DBG(3, "request in progress, cannot halt %s\n",
1257 /* Cannot portably stall with non-empty FIFO */
1258 if (musb_ep->is_in) {
1259 csr = musb_readw(epio, MUSB_TXCSR);
1260 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1261 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1267 musb_ep->wedged = 0;
1269 /* set/clear the stall and toggle bits */
1270 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1271 if (musb_ep->is_in) {
1272 csr = musb_readw(epio, MUSB_TXCSR);
1273 csr |= MUSB_TXCSR_P_WZC_BITS
1274 | MUSB_TXCSR_CLRDATATOG;
1276 csr |= MUSB_TXCSR_P_SENDSTALL;
1278 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1279 | MUSB_TXCSR_P_SENTSTALL);
1280 csr &= ~MUSB_TXCSR_TXPKTRDY;
1281 musb_writew(epio, MUSB_TXCSR, csr);
1283 csr = musb_readw(epio, MUSB_RXCSR);
1284 csr |= MUSB_RXCSR_P_WZC_BITS
1285 | MUSB_RXCSR_FLUSHFIFO
1286 | MUSB_RXCSR_CLRDATATOG;
1288 csr |= MUSB_RXCSR_P_SENDSTALL;
1290 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1291 | MUSB_RXCSR_P_SENTSTALL);
1292 musb_writew(epio, MUSB_RXCSR, csr);
1295 /* maybe start the first request in the queue */
1296 if (!musb_ep->busy && !value && request) {
1297 DBG(3, "restarting the request\n");
1298 musb_ep_restart(musb, request);
1302 spin_unlock_irqrestore(&musb->lock, flags);
1307 * Sets the halt feature with the clear requests ignored
1309 int musb_gadget_set_wedge(struct usb_ep *ep)
1311 struct musb_ep *musb_ep = to_musb_ep(ep);
1316 musb_ep->wedged = 1;
1318 return usb_ep_set_halt(ep);
1321 static int musb_gadget_fifo_status(struct usb_ep *ep)
1323 struct musb_ep *musb_ep = to_musb_ep(ep);
1324 void __iomem *epio = musb_ep->hw_ep->regs;
1325 int retval = -EINVAL;
1327 if (musb_ep->desc && !musb_ep->is_in) {
1328 struct musb *musb = musb_ep->musb;
1329 int epnum = musb_ep->current_epnum;
1330 void __iomem *mbase = musb->mregs;
1331 unsigned long flags;
1333 spin_lock_irqsave(&musb->lock, flags);
1335 musb_ep_select(mbase, epnum);
1336 /* FIXME return zero unless RXPKTRDY is set */
1337 retval = musb_readw(epio, MUSB_RXCOUNT);
1339 spin_unlock_irqrestore(&musb->lock, flags);
1344 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1346 struct musb_ep *musb_ep = to_musb_ep(ep);
1347 struct musb *musb = musb_ep->musb;
1348 u8 epnum = musb_ep->current_epnum;
1349 void __iomem *epio = musb->endpoints[epnum].regs;
1350 void __iomem *mbase;
1351 unsigned long flags;
1354 mbase = musb->mregs;
1356 spin_lock_irqsave(&musb->lock, flags);
1357 musb_ep_select(mbase, (u8) epnum);
1359 /* disable interrupts */
1360 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1361 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1363 if (musb_ep->is_in) {
1364 csr = musb_readw(epio, MUSB_TXCSR);
1365 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1366 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1367 musb_writew(epio, MUSB_TXCSR, csr);
1368 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1369 musb_writew(epio, MUSB_TXCSR, csr);
1372 csr = musb_readw(epio, MUSB_RXCSR);
1373 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1374 musb_writew(epio, MUSB_RXCSR, csr);
1375 musb_writew(epio, MUSB_RXCSR, csr);
1378 /* re-enable interrupt */
1379 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1380 spin_unlock_irqrestore(&musb->lock, flags);
1383 static const struct usb_ep_ops musb_ep_ops = {
1384 .enable = musb_gadget_enable,
1385 .disable = musb_gadget_disable,
1386 .alloc_request = musb_alloc_request,
1387 .free_request = musb_free_request,
1388 .queue = musb_gadget_queue,
1389 .dequeue = musb_gadget_dequeue,
1390 .set_halt = musb_gadget_set_halt,
1391 .set_wedge = musb_gadget_set_wedge,
1392 .fifo_status = musb_gadget_fifo_status,
1393 .fifo_flush = musb_gadget_fifo_flush
1396 /* ----------------------------------------------------------------------- */
1398 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1400 struct musb *musb = gadget_to_musb(gadget);
1402 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1405 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1407 struct musb *musb = gadget_to_musb(gadget);
1408 void __iomem *mregs = musb->mregs;
1409 unsigned long flags;
1410 int status = -EINVAL;
1414 spin_lock_irqsave(&musb->lock, flags);
1416 switch (musb->xceiv->state) {
1417 case OTG_STATE_B_PERIPHERAL:
1418 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1419 * that's part of the standard usb 1.1 state machine, and
1420 * doesn't affect OTG transitions.
1422 if (musb->may_wakeup && musb->is_suspended)
1425 case OTG_STATE_B_IDLE:
1426 /* Start SRP ... OTG not required. */
1427 devctl = musb_readb(mregs, MUSB_DEVCTL);
1428 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1429 devctl |= MUSB_DEVCTL_SESSION;
1430 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1431 devctl = musb_readb(mregs, MUSB_DEVCTL);
1433 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1434 devctl = musb_readb(mregs, MUSB_DEVCTL);
1439 while (devctl & MUSB_DEVCTL_SESSION) {
1440 devctl = musb_readb(mregs, MUSB_DEVCTL);
1445 /* Block idling for at least 1s */
1446 musb_platform_try_idle(musb,
1447 jiffies + msecs_to_jiffies(1 * HZ));
1452 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1458 power = musb_readb(mregs, MUSB_POWER);
1459 power |= MUSB_POWER_RESUME;
1460 musb_writeb(mregs, MUSB_POWER, power);
1461 DBG(2, "issue wakeup\n");
1463 /* FIXME do this next chunk in a timer callback, no udelay */
1466 power = musb_readb(mregs, MUSB_POWER);
1467 power &= ~MUSB_POWER_RESUME;
1468 musb_writeb(mregs, MUSB_POWER, power);
1470 spin_unlock_irqrestore(&musb->lock, flags);
1475 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1477 struct musb *musb = gadget_to_musb(gadget);
1479 musb->is_self_powered = !!is_selfpowered;
1483 static void musb_pullup(struct musb *musb, int is_on)
1487 power = musb_readb(musb->mregs, MUSB_POWER);
1489 power |= MUSB_POWER_SOFTCONN;
1491 power &= ~MUSB_POWER_SOFTCONN;
1493 /* FIXME if on, HdrcStart; if off, HdrcStop */
1495 DBG(3, "gadget %s D+ pullup %s\n",
1496 musb->gadget_driver->function, is_on ? "on" : "off");
1497 musb_writeb(musb->mregs, MUSB_POWER, power);
1501 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1503 DBG(2, "<= %s =>\n", __func__);
1506 * FIXME iff driver's softconnect flag is set (as it is during probe,
1507 * though that can clear it), just musb_pullup().
1514 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1516 struct musb *musb = gadget_to_musb(gadget);
1518 if (!musb->xceiv->set_power)
1520 return otg_set_power(musb->xceiv, mA);
1523 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1525 struct musb *musb = gadget_to_musb(gadget);
1526 unsigned long flags;
1530 /* NOTE: this assumes we are sensing vbus; we'd rather
1531 * not pullup unless the B-session is active.
1533 spin_lock_irqsave(&musb->lock, flags);
1534 if (is_on != musb->softconnect) {
1535 musb->softconnect = is_on;
1536 musb_pullup(musb, is_on);
1538 spin_unlock_irqrestore(&musb->lock, flags);
1542 static const struct usb_gadget_ops musb_gadget_operations = {
1543 .get_frame = musb_gadget_get_frame,
1544 .wakeup = musb_gadget_wakeup,
1545 .set_selfpowered = musb_gadget_set_self_powered,
1546 /* .vbus_session = musb_gadget_vbus_session, */
1547 .vbus_draw = musb_gadget_vbus_draw,
1548 .pullup = musb_gadget_pullup,
1551 /* ----------------------------------------------------------------------- */
1555 /* Only this registration code "knows" the rule (from USB standards)
1556 * about there being only one external upstream port. It assumes
1557 * all peripheral ports are external...
1559 static struct musb *the_gadget;
1561 static void musb_gadget_release(struct device *dev)
1563 /* kref_put(WHAT) */
1564 dev_dbg(dev, "%s\n", __func__);
1569 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1571 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1573 memset(ep, 0, sizeof *ep);
1575 ep->current_epnum = epnum;
1580 INIT_LIST_HEAD(&ep->req_list);
1582 sprintf(ep->name, "ep%d%s", epnum,
1583 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1584 is_in ? "in" : "out"));
1585 ep->end_point.name = ep->name;
1586 INIT_LIST_HEAD(&ep->end_point.ep_list);
1588 ep->end_point.maxpacket = 64;
1589 ep->end_point.ops = &musb_g_ep0_ops;
1590 musb->g.ep0 = &ep->end_point;
1593 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1595 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1596 ep->end_point.ops = &musb_ep_ops;
1597 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1602 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1603 * to the rest of the driver state.
1605 static inline void __init musb_g_init_endpoints(struct musb *musb)
1608 struct musb_hw_ep *hw_ep;
1611 /* intialize endpoint list just once */
1612 INIT_LIST_HEAD(&(musb->g.ep_list));
1614 for (epnum = 0, hw_ep = musb->endpoints;
1615 epnum < musb->nr_endpoints;
1617 if (hw_ep->is_shared_fifo /* || !epnum */) {
1618 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1621 if (hw_ep->max_packet_sz_tx) {
1622 init_peripheral_ep(musb, &hw_ep->ep_in,
1626 if (hw_ep->max_packet_sz_rx) {
1627 init_peripheral_ep(musb, &hw_ep->ep_out,
1635 /* called once during driver setup to initialize and link into
1636 * the driver model; memory is zeroed.
1638 int __init musb_gadget_setup(struct musb *musb)
1642 /* REVISIT minor race: if (erroneously) setting up two
1643 * musb peripherals at the same time, only the bus lock
1650 musb->g.ops = &musb_gadget_operations;
1651 musb->g.is_dualspeed = 1;
1652 musb->g.speed = USB_SPEED_UNKNOWN;
1654 /* this "gadget" abstracts/virtualizes the controller */
1655 dev_set_name(&musb->g.dev, "gadget");
1656 musb->g.dev.parent = musb->controller;
1657 musb->g.dev.dma_mask = musb->controller->dma_mask;
1658 musb->g.dev.release = musb_gadget_release;
1659 musb->g.name = musb_driver_name;
1661 if (is_otg_enabled(musb))
1664 musb_g_init_endpoints(musb);
1666 musb->is_active = 0;
1667 musb_platform_try_idle(musb, 0);
1669 status = device_register(&musb->g.dev);
1675 void musb_gadget_cleanup(struct musb *musb)
1677 if (musb != the_gadget)
1680 device_unregister(&musb->g.dev);
1685 * Register the gadget driver. Used by gadget drivers when
1686 * registering themselves with the controller.
1688 * -EINVAL something went wrong (not driver)
1689 * -EBUSY another gadget is already using the controller
1690 * -ENOMEM no memeory to perform the operation
1692 * @param driver the gadget driver
1693 * @return <0 if error, 0 if everything is fine
1695 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1698 unsigned long flags;
1699 struct musb *musb = the_gadget;
1702 || driver->speed != USB_SPEED_HIGH
1707 /* driver must be initialized to support peripheral mode */
1708 if (!musb || !(musb->board_mode == MUSB_OTG
1709 || musb->board_mode != MUSB_OTG)) {
1710 DBG(1, "%s, no dev??\n", __func__);
1714 DBG(3, "registering driver %s\n", driver->function);
1715 spin_lock_irqsave(&musb->lock, flags);
1717 if (musb->gadget_driver) {
1718 DBG(1, "%s is already bound to %s\n",
1720 musb->gadget_driver->driver.name);
1723 musb->gadget_driver = driver;
1724 musb->g.dev.driver = &driver->driver;
1725 driver->driver.bus = NULL;
1726 musb->softconnect = 1;
1730 spin_unlock_irqrestore(&musb->lock, flags);
1733 retval = driver->bind(&musb->g);
1735 DBG(3, "bind to driver %s failed --> %d\n",
1736 driver->driver.name, retval);
1737 musb->gadget_driver = NULL;
1738 musb->g.dev.driver = NULL;
1741 spin_lock_irqsave(&musb->lock, flags);
1743 otg_set_peripheral(musb->xceiv, &musb->g);
1744 musb->is_active = 1;
1746 /* FIXME this ignores the softconnect flag. Drivers are
1747 * allowed hold the peripheral inactive until for example
1748 * userspace hooks up printer hardware or DSP codecs, so
1749 * hosts only see fully functional devices.
1752 if (!is_otg_enabled(musb))
1755 otg_set_peripheral(musb->xceiv, &musb->g);
1757 spin_unlock_irqrestore(&musb->lock, flags);
1759 if (is_otg_enabled(musb)) {
1760 DBG(3, "OTG startup...\n");
1762 /* REVISIT: funcall to other code, which also
1763 * handles power budgeting ... this way also
1764 * ensures HdrcStart is indirectly called.
1766 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1768 DBG(1, "add_hcd failed, %d\n", retval);
1769 spin_lock_irqsave(&musb->lock, flags);
1770 otg_set_peripheral(musb->xceiv, NULL);
1771 musb->gadget_driver = NULL;
1772 musb->g.dev.driver = NULL;
1773 spin_unlock_irqrestore(&musb->lock, flags);
1780 EXPORT_SYMBOL(usb_gadget_register_driver);
1782 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1785 struct musb_hw_ep *hw_ep;
1787 /* don't disconnect if it's not connected */
1788 if (musb->g.speed == USB_SPEED_UNKNOWN)
1791 musb->g.speed = USB_SPEED_UNKNOWN;
1793 /* deactivate the hardware */
1794 if (musb->softconnect) {
1795 musb->softconnect = 0;
1796 musb_pullup(musb, 0);
1800 /* killing any outstanding requests will quiesce the driver;
1801 * then report disconnect
1804 for (i = 0, hw_ep = musb->endpoints;
1805 i < musb->nr_endpoints;
1807 musb_ep_select(musb->mregs, i);
1808 if (hw_ep->is_shared_fifo /* || !epnum */) {
1809 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1811 if (hw_ep->max_packet_sz_tx)
1812 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1813 if (hw_ep->max_packet_sz_rx)
1814 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1818 spin_unlock(&musb->lock);
1819 driver->disconnect(&musb->g);
1820 spin_lock(&musb->lock);
1825 * Unregister the gadget driver. Used by gadget drivers when
1826 * unregistering themselves from the controller.
1828 * @param driver the gadget driver to unregister
1830 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1832 unsigned long flags;
1834 struct musb *musb = the_gadget;
1836 if (!driver || !driver->unbind || !musb)
1839 /* REVISIT always use otg_set_peripheral() here too;
1840 * this needs to shut down the OTG engine.
1843 spin_lock_irqsave(&musb->lock, flags);
1845 #ifdef CONFIG_USB_MUSB_OTG
1846 musb_hnp_stop(musb);
1849 if (musb->gadget_driver == driver) {
1851 (void) musb_gadget_vbus_draw(&musb->g, 0);
1853 musb->xceiv->state = OTG_STATE_UNDEFINED;
1854 stop_activity(musb, driver);
1855 otg_set_peripheral(musb->xceiv, NULL);
1857 DBG(3, "unregistering driver %s\n", driver->function);
1858 spin_unlock_irqrestore(&musb->lock, flags);
1859 driver->unbind(&musb->g);
1860 spin_lock_irqsave(&musb->lock, flags);
1862 musb->gadget_driver = NULL;
1863 musb->g.dev.driver = NULL;
1865 musb->is_active = 0;
1866 musb_platform_try_idle(musb, 0);
1869 spin_unlock_irqrestore(&musb->lock, flags);
1871 if (is_otg_enabled(musb) && retval == 0) {
1872 usb_remove_hcd(musb_to_hcd(musb));
1873 /* FIXME we need to be able to register another
1874 * gadget driver here and have everything work;
1875 * that currently misbehaves.
1881 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1884 /* ----------------------------------------------------------------------- */
1886 /* lifecycle operations called through plat_uds.c */
1888 void musb_g_resume(struct musb *musb)
1890 musb->is_suspended = 0;
1891 switch (musb->xceiv->state) {
1892 case OTG_STATE_B_IDLE:
1894 case OTG_STATE_B_WAIT_ACON:
1895 case OTG_STATE_B_PERIPHERAL:
1896 musb->is_active = 1;
1897 if (musb->gadget_driver && musb->gadget_driver->resume) {
1898 spin_unlock(&musb->lock);
1899 musb->gadget_driver->resume(&musb->g);
1900 spin_lock(&musb->lock);
1904 WARNING("unhandled RESUME transition (%s)\n",
1905 otg_state_string(musb));
1909 /* called when SOF packets stop for 3+ msec */
1910 void musb_g_suspend(struct musb *musb)
1914 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1915 DBG(3, "devctl %02x\n", devctl);
1917 switch (musb->xceiv->state) {
1918 case OTG_STATE_B_IDLE:
1919 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1920 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1922 case OTG_STATE_B_PERIPHERAL:
1923 musb->is_suspended = 1;
1924 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1925 spin_unlock(&musb->lock);
1926 musb->gadget_driver->suspend(&musb->g);
1927 spin_lock(&musb->lock);
1931 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1932 * A_PERIPHERAL may need care too
1934 WARNING("unhandled SUSPEND transition (%s)\n",
1935 otg_state_string(musb));
1939 /* Called during SRP */
1940 void musb_g_wakeup(struct musb *musb)
1942 musb_gadget_wakeup(&musb->g);
1945 /* called when VBUS drops below session threshold, and in other cases */
1946 void musb_g_disconnect(struct musb *musb)
1948 void __iomem *mregs = musb->mregs;
1949 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1951 DBG(3, "devctl %02x\n", devctl);
1954 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1956 /* don't draw vbus until new b-default session */
1957 (void) musb_gadget_vbus_draw(&musb->g, 0);
1959 musb->g.speed = USB_SPEED_UNKNOWN;
1960 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1961 spin_unlock(&musb->lock);
1962 musb->gadget_driver->disconnect(&musb->g);
1963 spin_lock(&musb->lock);
1966 switch (musb->xceiv->state) {
1968 #ifdef CONFIG_USB_MUSB_OTG
1969 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1970 otg_state_string(musb));
1971 musb->xceiv->state = OTG_STATE_A_IDLE;
1972 MUSB_HST_MODE(musb);
1974 case OTG_STATE_A_PERIPHERAL:
1975 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1976 MUSB_HST_MODE(musb);
1978 case OTG_STATE_B_WAIT_ACON:
1979 case OTG_STATE_B_HOST:
1981 case OTG_STATE_B_PERIPHERAL:
1982 case OTG_STATE_B_IDLE:
1983 musb->xceiv->state = OTG_STATE_B_IDLE;
1985 case OTG_STATE_B_SRP_INIT:
1989 musb->is_active = 0;
1992 void musb_g_reset(struct musb *musb)
1993 __releases(musb->lock)
1994 __acquires(musb->lock)
1996 void __iomem *mbase = musb->mregs;
1997 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2000 DBG(3, "<== %s addr=%x driver '%s'\n",
2001 (devctl & MUSB_DEVCTL_BDEVICE)
2002 ? "B-Device" : "A-Device",
2003 musb_readb(mbase, MUSB_FADDR),
2005 ? musb->gadget_driver->driver.name
2009 /* report disconnect, if we didn't already (flushing EP state) */
2010 if (musb->g.speed != USB_SPEED_UNKNOWN)
2011 musb_g_disconnect(musb);
2014 else if (devctl & MUSB_DEVCTL_HR)
2015 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2018 /* what speed did we negotiate? */
2019 power = musb_readb(mbase, MUSB_POWER);
2020 musb->g.speed = (power & MUSB_POWER_HSMODE)
2021 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2023 /* start in USB_STATE_DEFAULT */
2024 musb->is_active = 1;
2025 musb->is_suspended = 0;
2026 MUSB_DEV_MODE(musb);
2028 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2030 musb->may_wakeup = 0;
2031 musb->g.b_hnp_enable = 0;
2032 musb->g.a_alt_hnp_support = 0;
2033 musb->g.a_hnp_support = 0;
2035 /* Normal reset, as B-Device;
2036 * or else after HNP, as A-Device
2038 if (devctl & MUSB_DEVCTL_BDEVICE) {
2039 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2040 musb->g.is_a_peripheral = 0;
2041 } else if (is_otg_enabled(musb)) {
2042 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2043 musb->g.is_a_peripheral = 1;
2047 /* start with default limits on VBUS power draw */
2048 (void) musb_gadget_vbus_draw(&musb->g,
2049 is_otg_enabled(musb) ? 8 : 100);