SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/usb/host/uhci-hcd.c

   1 /*
   2  * Universal Host Controller Interface driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Linus Torvalds
   7  * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
   8  * (C) Copyright 1999 Randy Dunlap
   9  * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10  * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11  * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12  * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13  * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14  *               support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15  * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16  * (C) Copyright 2004 Alan Stern, stern@rowland.harvard.edu
  17  *
  18  * Intel documents this fairly well, and as far as I know there
  19  * are no royalties or anything like that, but even so there are
  20  * people who decided that they want to do the same thing in a
  21  * completely different way.
  22  *
  23  * WARNING! The USB documentation is downright evil. Most of it
  24  * is just crap, written by a committee. You're better off ignoring
  25  * most of it, the important stuff is:
  26  *  - the low-level protocol (fairly simple but lots of small details)
  27  *  - working around the horridness of the rest
  28  */
  29
  30 #include <linux/config.h>
  31 #ifdef CONFIG_USB_DEBUG
  32 #define DEBUG
  33 #else
  34 #undef DEBUG
  35 #endif
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/kernel.h>
  39 #include <linux/init.h>
  40 #include <linux/delay.h>
  41 #include <linux/ioport.h>
  42 #include <linux/sched.h>
  43 #include <linux/slab.h>
  44 #include <linux/smp_lock.h>
  45 #include <linux/errno.h>
  46 #include <linux/unistd.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/debugfs.h>
  50 #include <linux/pm.h>
  51 #include <linux/dmapool.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/usb.h>
  54 #include <linux/bitops.h>
  55
  56 #include <asm/uaccess.h>
  57 #include <asm/io.h>
  58 #include <asm/irq.h>
  59 #include <asm/system.h>
  60
  61 #include "../core/hcd.h"
  62 #include "uhci-hcd.h"
  63
  64 /*
  65  * Version Information
  66  */
  67 #define DRIVER_VERSION "v2.2"
  68 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
  69 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
  70 Alan Stern"
  71 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
  72
  73 /*
  74  * debug = 0, no debugging messages
  75  * debug = 1, dump failed URB's except for stalls
  76  * debug = 2, dump all failed URB's (including stalls)
  77  *            show all queues in /debug/uhci/[pci_addr]
  78  * debug = 3, show all TD's in URB's when dumping
  79  */
  80 #ifdef DEBUG
  81 static int debug = 1;
  82 #else
  83 static int debug = 0;
  84 #endif
  85 module_param(debug, int, S_IRUGO | S_IWUSR);
  86 MODULE_PARM_DESC(debug, "Debug level");
  87 static char *errbuf;
  88 #define ERRBUF_LEN    (32 * 1024)
  89
  90 static kmem_cache_t *uhci_up_cachep;    /* urb_priv */
  91
  92 static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
  93
  94 /* If a transfer is still active after this much time, turn off FSBR */
  95 #define IDLE_TIMEOUT    msecs_to_jiffies(50)
  96 #define FSBR_DELAY      msecs_to_jiffies(50)
  97
  98 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
  99 /* depth first traversal. We'll do it in groups of this number of TD's */
 100 /* to make sure it doesn't hog all of the bandwidth */
 101 #define DEPTH_INTERVAL 5
 102
 103 #include "uhci-hub.c"
 104 #include "uhci-debug.c"
 105 #include "uhci-q.c"
 106
 107 static int ports_active(struct uhci_hcd *uhci)
 108 {
 109         unsigned long io_addr = uhci->io_addr;
 110         int connection = 0;
 111         int i;
 112
 113         for (i = 0; i < uhci->rh_numports; i++)
 114                 connection |= (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_CCS);
 115
 116         return connection;
 117 }
 118
 119 static int suspend_allowed(struct uhci_hcd *uhci)
 120 {
 121         unsigned long io_addr = uhci->io_addr;
 122         int i;
 123
 124         if (to_pci_dev(uhci_dev(uhci))->vendor != PCI_VENDOR_ID_INTEL)
 125                 return 1;
 126
 127         /* Some of Intel's USB controllers have a bug that causes false
 128          * resume indications if any port has an over current condition.
 129          * To prevent problems, we will not allow a global suspend if
 130          * any ports are OC.
 131          *
 132          * Some motherboards using Intel's chipsets (but not using all
 133          * the USB ports) appear to hardwire the over current inputs active
 134          * to disable the USB ports.
 135          */
 136
 137         /* check for over current condition on any port */
 138         for (i = 0; i < uhci->rh_numports; i++) {
 139                 if (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_OC)
 140                         return 0;
 141         }
 142
 143         return 1;
 144 }
 145
 146 static void reset_hc(struct uhci_hcd *uhci)
 147 {
 148         unsigned long io_addr = uhci->io_addr;
 149
 150         /* Turn off PIRQ, SMI, and all interrupts.  This also turns off
 151          * the BIOS's USB Legacy Support.
 152          */
 153         pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP, 0);
 154         outw(0, uhci->io_addr + USBINTR);
 155
 156         /* Global reset for 50ms */
 157         uhci->state = UHCI_RESET;
 158         outw(USBCMD_GRESET, io_addr + USBCMD);
 159         msleep(50);
 160         outw(0, io_addr + USBCMD);
 161
 162         /* Another 10ms delay */
 163         msleep(10);
 164         uhci->resume_detect = 0;
 165         uhci->is_stopped = UHCI_IS_STOPPED;
 166 }
 167
 168 static void suspend_hc(struct uhci_hcd *uhci)
 169 {
 170         unsigned long io_addr = uhci->io_addr;
 171
 172         dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
 173         uhci->state = UHCI_SUSPENDED;
 174         uhci->resume_detect = 0;
 175         outw(USBCMD_EGSM, io_addr + USBCMD);
 176
 177         /* FIXME: Wait for the controller to actually stop */
 178         uhci_get_current_frame_number(uhci);
 179         uhci->is_stopped = UHCI_IS_STOPPED;
 180
 181         uhci_scan_schedule(uhci, NULL);
 182 }
 183
 184 static void wakeup_hc(struct uhci_hcd *uhci)
 185 {
 186         unsigned long io_addr = uhci->io_addr;
 187
 188         switch (uhci->state) {
 189                 case UHCI_SUSPENDED:            /* Start the resume */
 190                         dev_dbg(uhci_dev(uhci), "%s\n", __FUNCTION__);
 191
 192                         /* Global resume for >= 20ms */
 193                         outw(USBCMD_FGR | USBCMD_EGSM, io_addr + USBCMD);
 194                         uhci->state = UHCI_RESUMING_1;
 195                         uhci->state_end = jiffies + msecs_to_jiffies(20);
 196                         uhci->is_stopped = 0;
 197                         break;
 198
 199                 case UHCI_RESUMING_1:           /* End global resume */
 200                         uhci->state = UHCI_RESUMING_2;
 201                         outw(0, io_addr + USBCMD);
 202                         /* Falls through */
 203
 204                 case UHCI_RESUMING_2:           /* Wait for EOP to be sent */
 205                         if (inw(io_addr + USBCMD) & USBCMD_FGR)
 206                                 break;
 207
 208                         /* Run for at least 1 second, and
 209                          * mark it configured with a 64-byte max packet */
 210                         uhci->state = UHCI_RUNNING_GRACE;
 211                         uhci->state_end = jiffies + HZ;
 212                         outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP,
 213                                         io_addr + USBCMD);
 214                         break;
 215
 216                 case UHCI_RUNNING_GRACE:        /* Now allowed to suspend */
 217                         uhci->state = UHCI_RUNNING;
 218                         break;
 219
 220                 default:
 221                         break;
 222         }
 223 }
 224
 225 static int start_hc(struct uhci_hcd *uhci)
 226 {
 227         unsigned long io_addr = uhci->io_addr;
 228         int timeout = 10;
 229
 230         /*
 231          * Reset the HC - this will force us to get a
 232          * new notification of any already connected
 233          * ports due to the virtual disconnect that it
 234          * implies.
 235          */
 236         outw(USBCMD_HCRESET, io_addr + USBCMD);
 237         while (inw(io_addr + USBCMD) & USBCMD_HCRESET) {
 238                 if (--timeout < 0) {
 239                         dev_err(uhci_dev(uhci), "USBCMD_HCRESET timed out!\n");
 240                         return -ETIMEDOUT;
 241                 }
 242                 msleep(1);
 243         }
 244
 245         /* Mark controller as running before we enable interrupts */
 246         uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
 247
 248         /* Turn on PIRQ and all interrupts */
 249         pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
 250                         USBLEGSUP_DEFAULT);
 251         outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
 252                 io_addr + USBINTR);
 253
 254         /* Start at frame 0 */
 255         outw(0, io_addr + USBFRNUM);
 256         outl(uhci->fl->dma_handle, io_addr + USBFLBASEADD);
 257
 258         /* Run and mark it configured with a 64-byte max packet */
 259         uhci->state = UHCI_RUNNING_GRACE;
 260         uhci->state_end = jiffies + HZ;
 261         outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, io_addr + USBCMD);
 262         uhci->is_stopped = 0;
 263
 264         return 0;
 265 }
 266
 267 static void hc_state_transitions(struct uhci_hcd *uhci)
 268 {
 269         switch (uhci->state) {
 270                 case UHCI_RUNNING:
 271
 272                         /* global suspend if nothing connected for 1 second */
 273                         if (!ports_active(uhci) && suspend_allowed(uhci)) {
 274                                 uhci->state = UHCI_SUSPENDING_GRACE;
 275                                 uhci->state_end = jiffies + HZ;
 276                         }
 277                         break;
 278
 279                 case UHCI_SUSPENDING_GRACE:
 280                         if (ports_active(uhci))
 281                                 uhci->state = UHCI_RUNNING;
 282                         else if (time_after_eq(jiffies, uhci->state_end))
 283                                 suspend_hc(uhci);
 284                         break;
 285
 286                 case UHCI_SUSPENDED:
 287
 288                         /* wakeup if requested by a device */
 289                         if (uhci->resume_detect)
 290                                 wakeup_hc(uhci);
 291                         break;
 292
 293                 case UHCI_RESUMING_1:
 294                 case UHCI_RESUMING_2:
 295                 case UHCI_RUNNING_GRACE:
 296                         if (time_after_eq(jiffies, uhci->state_end))
 297                                 wakeup_hc(uhci);
 298                         break;
 299
 300                 default:
 301                         break;
 302         }
 303 }
 304
 305 static int init_stall_timer(struct usb_hcd *hcd);
 306
 307 static void stall_callback(unsigned long ptr)
 308 {
 309         struct usb_hcd *hcd = (struct usb_hcd *)ptr;
 310         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 311         struct urb_priv *up;
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&uhci->lock, flags);
 315         uhci_scan_schedule(uhci, NULL);
 316
 317         list_for_each_entry(up, &uhci->urb_list, urb_list) {
 318                 struct urb *u = up->urb;
 319
 320                 spin_lock(&u->lock);
 321
 322                 /* Check if the FSBR timed out */
 323                 if (up->fsbr && !up->fsbr_timeout && time_after_eq(jiffies, up->fsbrtime + IDLE_TIMEOUT))
 324                         uhci_fsbr_timeout(uhci, u);
 325
 326                 spin_unlock(&u->lock);
 327         }
 328
 329         /* Really disable FSBR */
 330         if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
 331                 uhci->fsbrtimeout = 0;
 332                 uhci->skel_term_qh->link = UHCI_PTR_TERM;
 333         }
 334
 335         /* Poll for and perform state transitions */
 336         hc_state_transitions(uhci);
 337         if (unlikely(uhci->suspended_ports && uhci->state != UHCI_SUSPENDED))
 338                 uhci_check_ports(uhci);
 339
 340         init_stall_timer(hcd);
 341         spin_unlock_irqrestore(&uhci->lock, flags);
 342 }
 343
 344 static int init_stall_timer(struct usb_hcd *hcd)
 345 {
 346         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 347
 348         init_timer(&uhci->stall_timer);
 349         uhci->stall_timer.function = stall_callback;
 350         uhci->stall_timer.data = (unsigned long)hcd;
 351         uhci->stall_timer.expires = jiffies + msecs_to_jiffies(100);
 352         add_timer(&uhci->stall_timer);
 353
 354         return 0;
 355 }
 356
 357 static irqreturn_t uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
 358 {
 359         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 360         unsigned long io_addr = uhci->io_addr;
 361         unsigned short status;
 362
 363         /*
 364          * Read the interrupt status, and write it back to clear the
 365          * interrupt cause.  Contrary to the UHCI specification, the
 366          * "HC Halted" status bit is persistent: it is RO, not R/WC.
 367          */
 368         status = inw(io_addr + USBSTS);
 369         if (!(status & ~USBSTS_HCH))    /* shared interrupt, not mine */
 370                 return IRQ_NONE;
 371         outw(status, io_addr + USBSTS);         /* Clear it */
 372
 373         if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
 374                 if (status & USBSTS_HSE)
 375                         dev_err(uhci_dev(uhci), "host system error, "
 376                                         "PCI problems?\n");
 377                 if (status & USBSTS_HCPE)
 378                         dev_err(uhci_dev(uhci), "host controller process "
 379                                         "error, something bad happened!\n");
 380                 if ((status & USBSTS_HCH) && uhci->state > 0) {
 381                         dev_err(uhci_dev(uhci), "host controller halted, "
 382                                         "very bad!\n");
 383                         /* FIXME: Reset the controller, fix the offending TD */
 384                 }
 385         }
 386
 387         if (status & USBSTS_RD)
 388                 uhci->resume_detect = 1;
 389
 390         spin_lock(&uhci->lock);
 391         uhci_scan_schedule(uhci, regs);
 392         spin_unlock(&uhci->lock);
 393
 394         return IRQ_HANDLED;
 395 }
 396
 397 /*
 398  * Store the current frame number in uhci->frame_number if the controller
 399  * is runnning
 400  */
 401 static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
 402 {
 403         if (!uhci->is_stopped)
 404                 uhci->frame_number = inw(uhci->io_addr + USBFRNUM);
 405 }
 406
 407 /*
 408  * De-allocate all resources
 409  */
 410 static void release_uhci(struct uhci_hcd *uhci)
 411 {
 412         int i;
 413
 414         for (i = 0; i < UHCI_NUM_SKELQH; i++)
 415                 if (uhci->skelqh[i]) {
 416                         uhci_free_qh(uhci, uhci->skelqh[i]);
 417                         uhci->skelqh[i] = NULL;
 418                 }
 419
 420         if (uhci->term_td) {
 421                 uhci_free_td(uhci, uhci->term_td);
 422                 uhci->term_td = NULL;
 423         }
 424
 425         if (uhci->qh_pool) {
 426                 dma_pool_destroy(uhci->qh_pool);
 427                 uhci->qh_pool = NULL;
 428         }
 429
 430         if (uhci->td_pool) {
 431                 dma_pool_destroy(uhci->td_pool);
 432                 uhci->td_pool = NULL;
 433         }
 434
 435         if (uhci->fl) {
 436                 dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
 437                                 uhci->fl, uhci->fl->dma_handle);
 438                 uhci->fl = NULL;
 439         }
 440
 441         if (uhci->dentry) {
 442                 debugfs_remove(uhci->dentry);
 443                 uhci->dentry = NULL;
 444         }
 445 }
 446
 447 static int uhci_reset(struct usb_hcd *hcd)
 448 {
 449         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 450
 451         uhci->io_addr = (unsigned long) hcd->rsrc_start;
 452
 453         /* Kick BIOS off this hardware and reset, so we won't get
 454          * interrupts from any previous setup.
 455          */
 456         reset_hc(uhci);
 457         return 0;
 458 }
 459
 460 /*
 461  * Allocate a frame list, and then setup the skeleton
 462  *
 463  * The hardware doesn't really know any difference
 464  * in the queues, but the order does matter for the
 465  * protocols higher up. The order is:
 466  *
 467  *  - any isochronous events handled before any
 468  *    of the queues. We don't do that here, because
 469  *    we'll create the actual TD entries on demand.
 470  *  - The first queue is the interrupt queue.
 471  *  - The second queue is the control queue, split into low- and full-speed
 472  *  - The third queue is bulk queue.
 473  *  - The fourth queue is the bandwidth reclamation queue, which loops back
 474  *    to the full-speed control queue.
 475  */
 476 static int uhci_start(struct usb_hcd *hcd)
 477 {
 478         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 479         int retval = -EBUSY;
 480         int i, port;
 481         unsigned io_size;
 482         dma_addr_t dma_handle;
 483         struct usb_device *udev;
 484         struct dentry *dentry;
 485
 486         io_size = (unsigned) hcd->rsrc_len;
 487
 488         dentry = debugfs_create_file(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, uhci, &uhci_debug_operations);
 489         if (!dentry) {
 490                 dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n");
 491                 retval = -ENOMEM;
 492                 goto err_create_debug_entry;
 493         }
 494         uhci->dentry = dentry;
 495
 496         uhci->fsbr = 0;
 497         uhci->fsbrtimeout = 0;
 498
 499         spin_lock_init(&uhci->lock);
 500         INIT_LIST_HEAD(&uhci->qh_remove_list);
 501
 502         INIT_LIST_HEAD(&uhci->td_remove_list);
 503
 504         INIT_LIST_HEAD(&uhci->urb_remove_list);
 505
 506         INIT_LIST_HEAD(&uhci->urb_list);
 507
 508         INIT_LIST_HEAD(&uhci->complete_list);
 509
 510         init_waitqueue_head(&uhci->waitqh);
 511
 512         uhci->fl = dma_alloc_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
 513                         &dma_handle, 0);
 514         if (!uhci->fl) {
 515                 dev_err(uhci_dev(uhci), "unable to allocate "
 516                                 "consistent memory for frame list\n");
 517                 goto err_alloc_fl;
 518         }
 519
 520         memset((void *)uhci->fl, 0, sizeof(*uhci->fl));
 521
 522         uhci->fl->dma_handle = dma_handle;
 523
 524         uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
 525                         sizeof(struct uhci_td), 16, 0);
 526         if (!uhci->td_pool) {
 527                 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
 528                 goto err_create_td_pool;
 529         }
 530
 531         uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
 532                         sizeof(struct uhci_qh), 16, 0);
 533         if (!uhci->qh_pool) {
 534                 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
 535                 goto err_create_qh_pool;
 536         }
 537
 538         /* Initialize the root hub */
 539
 540         /* UHCI specs says devices must have 2 ports, but goes on to say */
 541         /*  they may have more but give no way to determine how many they */
 542         /*  have. However, according to the UHCI spec, Bit 7 is always set */
 543         /*  to 1. So we try to use this to our advantage */
 544         for (port = 0; port < (io_size - 0x10) / 2; port++) {
 545                 unsigned int portstatus;
 546
 547                 portstatus = inw(uhci->io_addr + 0x10 + (port * 2));
 548                 if (!(portstatus & 0x0080))
 549                         break;
 550         }
 551         if (debug)
 552                 dev_info(uhci_dev(uhci), "detected %d ports\n", port);
 553
 554         /* This is experimental so anything less than 2 or greater than 8 is */
 555         /*  something weird and we'll ignore it */
 556         if (port < 2 || port > UHCI_RH_MAXCHILD) {
 557                 dev_info(uhci_dev(uhci), "port count misdetected? "
 558                                 "forcing to 2 ports\n");
 559                 port = 2;
 560         }
 561
 562         uhci->rh_numports = port;
 563
 564         udev = usb_alloc_dev(NULL, &hcd->self, 0);
 565         if (!udev) {
 566                 dev_err(uhci_dev(uhci), "unable to allocate root hub\n");
 567                 goto err_alloc_root_hub;
 568         }
 569
 570         uhci->term_td = uhci_alloc_td(uhci, udev);
 571         if (!uhci->term_td) {
 572                 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
 573                 goto err_alloc_term_td;
 574         }
 575
 576         for (i = 0; i < UHCI_NUM_SKELQH; i++) {
 577                 uhci->skelqh[i] = uhci_alloc_qh(uhci, udev);
 578                 if (!uhci->skelqh[i]) {
 579                         dev_err(uhci_dev(uhci), "unable to allocate QH\n");
 580                         goto err_alloc_skelqh;
 581                 }
 582         }
 583
 584         /*
 585          * 8 Interrupt queues; link all higher int queues to int1,
 586          * then link int1 to control and control to bulk
 587          */
 588         uhci->skel_int128_qh->link =
 589                         uhci->skel_int64_qh->link =
 590                         uhci->skel_int32_qh->link =
 591                         uhci->skel_int16_qh->link =
 592                         uhci->skel_int8_qh->link =
 593                         uhci->skel_int4_qh->link =
 594                         uhci->skel_int2_qh->link =
 595                         cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;
 596         uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;
 597
 598         uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
 599         uhci->skel_fs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;
 600         uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;
 601
 602         /* This dummy TD is to work around a bug in Intel PIIX controllers */
 603         uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |
 604                 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
 605         uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
 606
 607         uhci->skel_term_qh->link = UHCI_PTR_TERM;
 608         uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
 609
 610         /*
 611          * Fill the frame list: make all entries point to the proper
 612          * interrupt queue.
 613          *
 614          * The interrupt queues will be interleaved as evenly as possible.
 615          * There's not much to be done about period-1 interrupts; they have
 616          * to occur in every frame.  But we can schedule period-2 interrupts
 617          * in odd-numbered frames, period-4 interrupts in frames congruent
 618          * to 2 (mod 4), and so on.  This way each frame only has two
 619          * interrupt QHs, which will help spread out bandwidth utilization.
 620          */
 621         for (i = 0; i < UHCI_NUMFRAMES; i++) {
 622                 int irq;
 623
 624                 /*
 625                  * ffs (Find First bit Set) does exactly what we need:
 626                  * 1,3,5,...  => ffs = 0 => use skel_int2_qh = skelqh[6],
 627                  * 2,6,10,... => ffs = 1 => use skel_int4_qh = skelqh[5], etc.
 628                  * ffs > 6 => not on any high-period queue, so use
 629                  *      skel_int1_qh = skelqh[7].
 630                  * Add UHCI_NUMFRAMES to insure at least one bit is set.
 631                  */
 632                 irq = 6 - (int) __ffs(i + UHCI_NUMFRAMES);
 633                 if (irq < 0)
 634                         irq = 7;
 635
 636                 /* Only place we don't use the frame list routines */
 637                 uhci->fl->frame[i] = UHCI_PTR_QH |
 638                                 cpu_to_le32(uhci->skelqh[irq]->dma_handle);
 639         }
 640
 641         /*
 642          * Some architectures require a full mb() to enforce completion of
 643          * the memory writes above before the I/O transfers in start_hc().
 644          */
 645         mb();
 646         if ((retval = start_hc(uhci)) != 0)
 647                 goto err_alloc_skelqh;
 648
 649         init_stall_timer(hcd);
 650
 651         udev->speed = USB_SPEED_FULL;
 652
 653         if (usb_hcd_register_root_hub(udev, hcd) != 0) {
 654                 dev_err(uhci_dev(uhci), "unable to start root hub\n");
 655                 retval = -ENOMEM;
 656                 goto err_start_root_hub;
 657         }
 658
 659         return 0;
 660
 661 /*
 662  * error exits:
 663  */
 664 err_start_root_hub:
 665         reset_hc(uhci);
 666
 667         del_timer_sync(&uhci->stall_timer);
 668
 669 err_alloc_skelqh:
 670         for (i = 0; i < UHCI_NUM_SKELQH; i++)
 671                 if (uhci->skelqh[i]) {
 672                         uhci_free_qh(uhci, uhci->skelqh[i]);
 673                         uhci->skelqh[i] = NULL;
 674                 }
 675
 676         uhci_free_td(uhci, uhci->term_td);
 677         uhci->term_td = NULL;
 678
 679 err_alloc_term_td:
 680         usb_put_dev(udev);
 681
 682 err_alloc_root_hub:
 683         dma_pool_destroy(uhci->qh_pool);
 684         uhci->qh_pool = NULL;
 685
 686 err_create_qh_pool:
 687         dma_pool_destroy(uhci->td_pool);
 688         uhci->td_pool = NULL;
 689
 690 err_create_td_pool:
 691         dma_free_coherent(uhci_dev(uhci), sizeof(*uhci->fl),
 692                         uhci->fl, uhci->fl->dma_handle);
 693         uhci->fl = NULL;
 694
 695 err_alloc_fl:
 696         debugfs_remove(uhci->dentry);
 697         uhci->dentry = NULL;
 698
 699 err_create_debug_entry:
 700         return retval;
 701 }
 702
 703 static void uhci_stop(struct usb_hcd *hcd)
 704 {
 705         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 706
 707         del_timer_sync(&uhci->stall_timer);
 708         reset_hc(uhci);
 709
 710         spin_lock_irq(&uhci->lock);
 711         uhci_scan_schedule(uhci, NULL);
 712         spin_unlock_irq(&uhci->lock);
 713
 714         release_uhci(uhci);
 715 }
 716
 717 #ifdef CONFIG_PM
 718 static int uhci_suspend(struct usb_hcd *hcd, pm_message_t message)
 719 {
 720         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 721
 722         spin_lock_irq(&uhci->lock);
 723
 724         /* Don't try to suspend broken motherboards, reset instead */
 725         if (suspend_allowed(uhci))
 726                 suspend_hc(uhci);
 727         else {
 728                 spin_unlock_irq(&uhci->lock);
 729                 reset_hc(uhci);
 730                 spin_lock_irq(&uhci->lock);
 731                 uhci_scan_schedule(uhci, NULL);
 732         }
 733
 734         spin_unlock_irq(&uhci->lock);
 735         return 0;
 736 }
 737
 738 static int uhci_resume(struct usb_hcd *hcd)
 739 {
 740         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 741         int rc;
 742
 743         pci_set_master(to_pci_dev(uhci_dev(uhci)));
 744
 745         spin_lock_irq(&uhci->lock);
 746
 747         if (uhci->state == UHCI_SUSPENDED) {
 748
 749                 /*
 750                  * Some systems don't maintain the UHCI register values
 751                  * during a PM suspend/resume cycle, so reinitialize
 752                  * the Frame Number, Framelist Base Address, Interrupt
 753                  * Enable, and Legacy Support registers.
 754                  */
 755                 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
 756                                 0);
 757                 outw(uhci->frame_number, uhci->io_addr + USBFRNUM);
 758                 outl(uhci->fl->dma_handle, uhci->io_addr + USBFLBASEADD);
 759                 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC |
 760                                 USBINTR_SP, uhci->io_addr + USBINTR);
 761                 uhci->resume_detect = 1;
 762                 pci_write_config_word(to_pci_dev(uhci_dev(uhci)), USBLEGSUP,
 763                                 USBLEGSUP_DEFAULT);
 764         } else {
 765                 spin_unlock_irq(&uhci->lock);
 766                 reset_hc(uhci);
 767                 if ((rc = start_hc(uhci)) != 0)
 768                         return rc;
 769                 spin_lock_irq(&uhci->lock);
 770         }
 771         hcd->state = HC_STATE_RUNNING;
 772
 773         spin_unlock_irq(&uhci->lock);
 774         return 0;
 775 }
 776 #endif
 777
 778 /* Wait until all the URBs for a particular device/endpoint are gone */
 779 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
 780                 struct usb_host_endpoint *ep)
 781 {
 782         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 783
 784         wait_event_interruptible(uhci->waitqh, list_empty(&ep->urb_list));
 785 }
 786
 787 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
 788 {
 789         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 790         int frame_number;
 791         unsigned long flags;
 792
 793         /* Minimize latency by avoiding the spinlock */
 794         local_irq_save(flags);
 795         rmb();
 796         frame_number = (uhci->is_stopped ? uhci->frame_number :
 797                         inw(uhci->io_addr + USBFRNUM));
 798         local_irq_restore(flags);
 799         return frame_number;
 800 }
 801
 802 static const char hcd_name[] = "uhci_hcd";
 803
 804 static const struct hc_driver uhci_driver = {
 805         .description =          hcd_name,
 806         .product_desc =         "UHCI Host Controller",
 807         .hcd_priv_size =        sizeof(struct uhci_hcd),
 808
 809         /* Generic hardware linkage */
 810         .irq =                  uhci_irq,
 811         .flags =                HCD_USB11,
 812
 813         /* Basic lifecycle operations */
 814         .reset =                uhci_reset,
 815         .start =                uhci_start,
 816 #ifdef CONFIG_PM
 817         .suspend =              uhci_suspend,
 818         .resume =               uhci_resume,
 819 #endif
 820         .stop =                 uhci_stop,
 821
 822         .urb_enqueue =          uhci_urb_enqueue,
 823         .urb_dequeue =          uhci_urb_dequeue,
 824
 825         .endpoint_disable =     uhci_hcd_endpoint_disable,
 826         .get_frame_number =     uhci_hcd_get_frame_number,
 827
 828         .hub_status_data =      uhci_hub_status_data,
 829         .hub_control =          uhci_hub_control,
 830 };
 831
 832 static const struct pci_device_id uhci_pci_ids[] = { {
 833         /* handle any USB UHCI controller */
 834         PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x00), ~0),
 835         .driver_data =  (unsigned long) &uhci_driver,
 836         }, { /* end: all zeroes */ }
 837 };
 838
 839 MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
 840
 841 static struct pci_driver uhci_pci_driver = {
 842         .name =         (char *)hcd_name,
 843         .id_table =     uhci_pci_ids,
 844
 845         .probe =        usb_hcd_pci_probe,
 846         .remove =       usb_hcd_pci_remove,
 847
 848 #ifdef  CONFIG_PM
 849         .suspend =      usb_hcd_pci_suspend,
 850         .resume =       usb_hcd_pci_resume,
 851 #endif  /* PM */
 852 };
 853
 854 static int __init uhci_hcd_init(void)
 855 {
 856         int retval = -ENOMEM;
 857
 858         printk(KERN_INFO DRIVER_DESC " " DRIVER_VERSION "\n");
 859
 860         if (usb_disabled())
 861                 return -ENODEV;
 862
 863         if (debug) {
 864                 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
 865                 if (!errbuf)
 866                         goto errbuf_failed;
 867         }
 868
 869         uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
 870         if (!uhci_debugfs_root)
 871                 goto debug_failed;
 872
 873         uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
 874                 sizeof(struct urb_priv), 0, 0, NULL, NULL);
 875         if (!uhci_up_cachep)
 876                 goto up_failed;
 877
 878         retval = pci_register_driver(&uhci_pci_driver);
 879         if (retval)
 880                 goto init_failed;
 881
 882         return 0;
 883
 884 init_failed:
 885         if (kmem_cache_destroy(uhci_up_cachep))
 886                 warn("not all urb_priv's were freed!");
 887
 888 up_failed:
 889         debugfs_remove(uhci_debugfs_root);
 890
 891 debug_failed:
 892         kfree(errbuf);
 893
 894 errbuf_failed:
 895
 896         return retval;
 897 }
 898
 899 static void __exit uhci_hcd_cleanup(void)
 900 {
 901         pci_unregister_driver(&uhci_pci_driver);
 902
 903         if (kmem_cache_destroy(uhci_up_cachep))
 904                 warn("not all urb_priv's were freed!");
 905
 906         debugfs_remove(uhci_debugfs_root);
 907         kfree(errbuf);
 908 }
 909
 910 module_init(uhci_hcd_init);
 911 module_exit(uhci_hcd_cleanup);
 912
 913 MODULE_AUTHOR(DRIVER_AUTHOR);
 914 MODULE_DESCRIPTION(DRIVER_DESC);
 915 MODULE_LICENSE("GPL");