SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11
  12 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  13 {
  14         int             last = urb_priv->length - 1;
  15
  16         if (last >= 0) {
  17                 int             i;
  18                 struct td       *td;
  19
  20                 for (i = 0; i <= last; i++) {
  21                         td = urb_priv->td [i];
  22                         if (td)
  23                                 td_free (hc, td);
  24                 }
  25         }
  26
  27         list_del (&urb_priv->pending);
  28         kfree (urb_priv);
  29 }
  30
  31 /*-------------------------------------------------------------------------*/
  32
  33 /*
  34  * URB goes back to driver, and isn't reissued.
  35  * It's completely gone from HC data structures.
  36  * PRECONDITION:  ohci lock held, irqs blocked.
  37  */
  38 static void
  39 finish_urb (struct ohci_hcd *ohci, struct urb *urb)
  40 __releases(ohci->lock)
  41 __acquires(ohci->lock)
  42 {
  43         // ASSERT (urb->hcpriv != 0);
  44
  45         urb_free_priv (ohci, urb->hcpriv);
  46
  47         spin_lock (&urb->lock);
  48         if (likely (urb->status == -EINPROGRESS))
  49                 urb->status = 0;
  50         spin_unlock (&urb->lock);
  51
  52         switch (usb_pipetype (urb->pipe)) {
  53         case PIPE_ISOCHRONOUS:
  54                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  55                 break;
  56         case PIPE_INTERRUPT:
  57                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  58                 break;
  59         }
  60
  61 #ifdef OHCI_VERBOSE_DEBUG
  62         urb_print (urb, "RET", usb_pipeout (urb->pipe));
  63 #endif
  64
  65         /* urb->complete() can reenter this HCD */
  66         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  67         spin_unlock (&ohci->lock);
  68         usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb);
  69         spin_lock (&ohci->lock);
  70
  71         /* stop periodic dma if it's not needed */
  72         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  73                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  74                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  75                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  76         }
  77 }
  78
  79
  80 /*-------------------------------------------------------------------------*
  81  * ED handling functions
  82  *-------------------------------------------------------------------------*/
  83
  84 /* search for the right schedule branch to use for a periodic ed.
  85  * does some load balancing; returns the branch, or negative errno.
  86  */
  87 static int balance (struct ohci_hcd *ohci, int interval, int load)
  88 {
  89         int     i, branch = -ENOSPC;
  90
  91         /* iso periods can be huge; iso tds specify frame numbers */
  92         if (interval > NUM_INTS)
  93                 interval = NUM_INTS;
  94
  95         /* search for the least loaded schedule branch of that period
  96          * that has enough bandwidth left unreserved.
  97          */
  98         for (i = 0; i < interval ; i++) {
  99                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 100                         int     j;
 101
 102                         /* usb 1.1 says 90% of one frame */
 103                         for (j = i; j < NUM_INTS; j += interval) {
 104                                 if ((ohci->load [j] + load) > 900)
 105                                         break;
 106                         }
 107                         if (j < NUM_INTS)
 108                                 continue;
 109                         branch = i;
 110                 }
 111         }
 112         return branch;
 113 }
 114
 115 /*-------------------------------------------------------------------------*/
 116
 117 /* both iso and interrupt requests have periods; this routine puts them
 118  * into the schedule tree in the apppropriate place.  most iso devices use
 119  * 1msec periods, but that's not required.
 120  */
 121 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 122 {
 123         unsigned        i;
 124
 125         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 126                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 127                 ed, ed->branch, ed->load, ed->interval);
 128
 129         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 130                 struct ed       **prev = &ohci->periodic [i];
 131                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 132                 struct ed       *here = *prev;
 133
 134                 /* sorting each branch by period (slow before fast)
 135                  * lets us share the faster parts of the tree.
 136                  * (plus maybe: put interrupt eds before iso)
 137                  */
 138                 while (here && ed != here) {
 139                         if (ed->interval > here->interval)
 140                                 break;
 141                         prev = &here->ed_next;
 142                         prev_p = &here->hwNextED;
 143                         here = *prev;
 144                 }
 145                 if (ed != here) {
 146                         ed->ed_next = here;
 147                         if (here)
 148                                 ed->hwNextED = *prev_p;
 149                         wmb ();
 150                         *prev = ed;
 151                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 152                         wmb();
 153                 }
 154                 ohci->load [i] += ed->load;
 155         }
 156         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 157 }
 158
 159 /* link an ed into one of the HC chains */
 160
 161 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 162 {
 163         int     branch;
 164
 165         if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
 166                 return -EAGAIN;
 167
 168         ed->state = ED_OPER;
 169         ed->ed_prev = NULL;
 170         ed->ed_next = NULL;
 171         ed->hwNextED = 0;
 172         if (quirk_zfmicro(ohci)
 173                         && (ed->type == PIPE_INTERRUPT)
 174                         && !(ohci->eds_scheduled++))
 175                 mod_timer(&ohci->unlink_watchdog, round_jiffies_relative(HZ));
 176         wmb ();
 177
 178         /* we care about rm_list when setting CLE/BLE in case the HC was at
 179          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 180          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 181          *
 182          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 183          * periodic ones are singly linked (ed_next). that's because the
 184          * periodic schedule encodes a tree like figure 3-5 in the ohci
 185          * spec:  each qh can have several "previous" nodes, and the tree
 186          * doesn't have unused/idle descriptors.
 187          */
 188         switch (ed->type) {
 189         case PIPE_CONTROL:
 190                 if (ohci->ed_controltail == NULL) {
 191                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 192                         ohci_writel (ohci, ed->dma,
 193                                         &ohci->regs->ed_controlhead);
 194                 } else {
 195                         ohci->ed_controltail->ed_next = ed;
 196                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 197                                                                 ed->dma);
 198                 }
 199                 ed->ed_prev = ohci->ed_controltail;
 200                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 201                         wmb();
 202                         ohci->hc_control |= OHCI_CTRL_CLE;
 203                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 204                         ohci_writel (ohci, ohci->hc_control,
 205                                         &ohci->regs->control);
 206                 }
 207                 ohci->ed_controltail = ed;
 208                 break;
 209
 210         case PIPE_BULK:
 211                 if (ohci->ed_bulktail == NULL) {
 212                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 213                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 214                 } else {
 215                         ohci->ed_bulktail->ed_next = ed;
 216                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 217                                                                 ed->dma);
 218                 }
 219                 ed->ed_prev = ohci->ed_bulktail;
 220                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 221                         wmb();
 222                         ohci->hc_control |= OHCI_CTRL_BLE;
 223                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 224                         ohci_writel (ohci, ohci->hc_control,
 225                                         &ohci->regs->control);
 226                 }
 227                 ohci->ed_bulktail = ed;
 228                 break;
 229
 230         // case PIPE_INTERRUPT:
 231         // case PIPE_ISOCHRONOUS:
 232         default:
 233                 branch = balance (ohci, ed->interval, ed->load);
 234                 if (branch < 0) {
 235                         ohci_dbg (ohci,
 236                                 "ERR %d, interval %d msecs, load %d\n",
 237                                 branch, ed->interval, ed->load);
 238                         // FIXME if there are TDs queued, fail them!
 239                         return branch;
 240                 }
 241                 ed->branch = branch;
 242                 periodic_link (ohci, ed);
 243         }
 244
 245         /* the HC may not see the schedule updates yet, but if it does
 246          * then they'll be properly ordered.
 247          */
 248         return 0;
 249 }
 250
 251 /*-------------------------------------------------------------------------*/
 252
 253 /* scan the periodic table to find and unlink this ED */
 254 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 255 {
 256         int     i;
 257
 258         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 259                 struct ed       *temp;
 260                 struct ed       **prev = &ohci->periodic [i];
 261                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 262
 263                 while (*prev && (temp = *prev) != ed) {
 264                         prev_p = &temp->hwNextED;
 265                         prev = &temp->ed_next;
 266                 }
 267                 if (*prev) {
 268                         *prev_p = ed->hwNextED;
 269                         *prev = ed->ed_next;
 270                 }
 271                 ohci->load [i] -= ed->load;
 272         }
 273         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 274
 275         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 276                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 277                 ed, ed->branch, ed->load, ed->interval);
 278 }
 279
 280 /* unlink an ed from one of the HC chains.
 281  * just the link to the ed is unlinked.
 282  * the link from the ed still points to another operational ed or 0
 283  * so the HC can eventually finish the processing of the unlinked ed
 284  * (assuming it already started that, which needn't be true).
 285  *
 286  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 287  * it won't.  ED_SKIP means the HC will finish its current transaction,
 288  * but won't start anything new.  The TD queue may still grow; device
 289  * drivers don't know about this HCD-internal state.
 290  *
 291  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 292  *
 293  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 294  *    immediately.  HC should be working on them.
 295  *
 296  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 297  *    to care about this ED; safe to disable the endpoint.
 298  *
 299  * When finish_unlinks() runs later, after SOF interrupt, it will often
 300  * complete one or more URB unlinks before making that state change.
 301  */
 302 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 303 {
 304         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 305         wmb ();
 306         ed->state = ED_UNLINK;
 307
 308         /* To deschedule something from the control or bulk list, just
 309          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 310          * head/current registers until later, and "later" isn't very
 311          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 312          * the HC is reading the ED queues (while we modify them).
 313          *
 314          * For now, ed_schedule() is "later".  It might be good paranoia
 315          * to scrub those registers in finish_unlinks(), in case of bugs
 316          * that make the HC try to use them.
 317          */
 318         switch (ed->type) {
 319         case PIPE_CONTROL:
 320                 /* remove ED from the HC's list: */
 321                 if (ed->ed_prev == NULL) {
 322                         if (!ed->hwNextED) {
 323                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 324                                 ohci_writel (ohci, ohci->hc_control,
 325                                                 &ohci->regs->control);
 326                                 // a ohci_readl() later syncs CLE with the HC
 327                         } else
 328                                 ohci_writel (ohci,
 329                                         hc32_to_cpup (ohci, &ed->hwNextED),
 330                                         &ohci->regs->ed_controlhead);
 331                 } else {
 332                         ed->ed_prev->ed_next = ed->ed_next;
 333                         ed->ed_prev->hwNextED = ed->hwNextED;
 334                 }
 335                 /* remove ED from the HCD's list: */
 336                 if (ohci->ed_controltail == ed) {
 337                         ohci->ed_controltail = ed->ed_prev;
 338                         if (ohci->ed_controltail)
 339                                 ohci->ed_controltail->ed_next = NULL;
 340                 } else if (ed->ed_next) {
 341                         ed->ed_next->ed_prev = ed->ed_prev;
 342                 }
 343                 break;
 344
 345         case PIPE_BULK:
 346                 /* remove ED from the HC's list: */
 347                 if (ed->ed_prev == NULL) {
 348                         if (!ed->hwNextED) {
 349                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 350                                 ohci_writel (ohci, ohci->hc_control,
 351                                                 &ohci->regs->control);
 352                                 // a ohci_readl() later syncs BLE with the HC
 353                         } else
 354                                 ohci_writel (ohci,
 355                                         hc32_to_cpup (ohci, &ed->hwNextED),
 356                                         &ohci->regs->ed_bulkhead);
 357                 } else {
 358                         ed->ed_prev->ed_next = ed->ed_next;
 359                         ed->ed_prev->hwNextED = ed->hwNextED;
 360                 }
 361                 /* remove ED from the HCD's list: */
 362                 if (ohci->ed_bulktail == ed) {
 363                         ohci->ed_bulktail = ed->ed_prev;
 364                         if (ohci->ed_bulktail)
 365                                 ohci->ed_bulktail->ed_next = NULL;
 366                 } else if (ed->ed_next) {
 367                         ed->ed_next->ed_prev = ed->ed_prev;
 368                 }
 369                 break;
 370
 371         // case PIPE_INTERRUPT:
 372         // case PIPE_ISOCHRONOUS:
 373         default:
 374                 periodic_unlink (ohci, ed);
 375                 break;
 376         }
 377 }
 378
 379
 380 /*-------------------------------------------------------------------------*/
 381
 382 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 383  * of enumeration, usb_set_configuration() or usb_set_interface().
 384  */
 385 static struct ed *ed_get (
 386         struct ohci_hcd         *ohci,
 387         struct usb_host_endpoint *ep,
 388         struct usb_device       *udev,
 389         unsigned int            pipe,
 390         int                     interval
 391 ) {
 392         struct ed               *ed;
 393         unsigned long           flags;
 394
 395         spin_lock_irqsave (&ohci->lock, flags);
 396
 397         if (!(ed = ep->hcpriv)) {
 398                 struct td       *td;
 399                 int             is_out;
 400                 u32             info;
 401
 402                 ed = ed_alloc (ohci, GFP_ATOMIC);
 403                 if (!ed) {
 404                         /* out of memory */
 405                         goto done;
 406                 }
 407
 408                 /* dummy td; end of td list for ed */
 409                 td = td_alloc (ohci, GFP_ATOMIC);
 410                 if (!td) {
 411                         /* out of memory */
 412                         ed_free (ohci, ed);
 413                         ed = NULL;
 414                         goto done;
 415                 }
 416                 ed->dummy = td;
 417                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 418                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 419                 ed->state = ED_IDLE;
 420
 421                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 422
 423                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 424                  * suceeds ... otherwise we wouldn't need "pipe".
 425                  */
 426                 info = usb_pipedevice (pipe);
 427                 ed->type = usb_pipetype(pipe);
 428
 429                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 430                 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
 431                 if (udev->speed == USB_SPEED_LOW)
 432                         info |= ED_LOWSPEED;
 433                 /* only control transfers store pids in tds */
 434                 if (ed->type != PIPE_CONTROL) {
 435                         info |= is_out ? ED_OUT : ED_IN;
 436                         if (ed->type != PIPE_BULK) {
 437                                 /* periodic transfers... */
 438                                 if (ed->type == PIPE_ISOCHRONOUS)
 439                                         info |= ED_ISO;
 440                                 else if (interval > 32) /* iso can be bigger */
 441                                         interval = 32;
 442                                 ed->interval = interval;
 443                                 ed->load = usb_calc_bus_time (
 444                                         udev->speed, !is_out,
 445                                         ed->type == PIPE_ISOCHRONOUS,
 446                                         le16_to_cpu(ep->desc.wMaxPacketSize))
 447                                                 / 1000;
 448                         }
 449                 }
 450                 ed->hwINFO = cpu_to_hc32(ohci, info);
 451
 452                 ep->hcpriv = ed;
 453         }
 454
 455 done:
 456         spin_unlock_irqrestore (&ohci->lock, flags);
 457         return ed;
 458 }
 459
 460 /*-------------------------------------------------------------------------*/
 461
 462 /* request unlinking of an endpoint from an operational HC.
 463  * put the ep on the rm_list
 464  * real work is done at the next start frame (SF) hardware interrupt
 465  * caller guarantees HCD is running, so hardware access is safe,
 466  * and that ed->state is ED_OPER
 467  */
 468 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 469 {
 470         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 471         ed_deschedule (ohci, ed);
 472
 473         /* rm_list is just singly linked, for simplicity */
 474         ed->ed_next = ohci->ed_rm_list;
 475         ed->ed_prev = NULL;
 476         ohci->ed_rm_list = ed;
 477
 478         /* enable SOF interrupt */
 479         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 480         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 481         // flush those writes, and get latest HCCA contents
 482         (void) ohci_readl (ohci, &ohci->regs->control);
 483
 484         /* SF interrupt might get delayed; record the frame counter value that
 485          * indicates when the HC isn't looking at it, so concurrent unlinks
 486          * behave.  frame_no wraps every 2^16 msec, and changes right before
 487          * SF is triggered.
 488          */
 489         ed->tick = ohci_frame_no(ohci) + 1;
 490
 491 }
 492
 493 /*-------------------------------------------------------------------------*
 494  * TD handling functions
 495  *-------------------------------------------------------------------------*/
 496
 497 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 498
 499 static void
 500 td_fill (struct ohci_hcd *ohci, u32 info,
 501         dma_addr_t data, int len,
 502         struct urb *urb, int index)
 503 {
 504         struct td               *td, *td_pt;
 505         struct urb_priv         *urb_priv = urb->hcpriv;
 506         int                     is_iso = info & TD_ISO;
 507         int                     hash;
 508
 509         // ASSERT (index < urb_priv->length);
 510
 511         /* aim for only one interrupt per urb.  mostly applies to control
 512          * and iso; other urbs rarely need more than one TD per urb.
 513          * this way, only final tds (or ones with an error) cause IRQs.
 514          * at least immediately; use DI=6 in case any control request is
 515          * tempted to die part way through.  (and to force the hc to flush
 516          * its donelist soonish, even on unlink paths.)
 517          *
 518          * NOTE: could delay interrupts even for the last TD, and get fewer
 519          * interrupts ... increasing per-urb latency by sharing interrupts.
 520          * Drivers that queue bulk urbs may request that behavior.
 521          */
 522         if (index != (urb_priv->length - 1)
 523                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 524                 info |= TD_DI_SET (6);
 525
 526         /* use this td as the next dummy */
 527         td_pt = urb_priv->td [index];
 528
 529         /* fill the old dummy TD */
 530         td = urb_priv->td [index] = urb_priv->ed->dummy;
 531         urb_priv->ed->dummy = td_pt;
 532
 533         td->ed = urb_priv->ed;
 534         td->next_dl_td = NULL;
 535         td->index = index;
 536         td->urb = urb;
 537         td->data_dma = data;
 538         if (!len)
 539                 data = 0;
 540
 541         td->hwINFO = cpu_to_hc32 (ohci, info);
 542         if (is_iso) {
 543                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 544                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 545                                                 (data & 0x0FFF) | 0xE000);
 546                 td->ed->last_iso = info & 0xffff;
 547         } else {
 548                 td->hwCBP = cpu_to_hc32 (ohci, data);
 549         }
 550         if (data)
 551                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 552         else
 553                 td->hwBE = 0;
 554         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 555
 556         /* append to queue */
 557         list_add_tail (&td->td_list, &td->ed->td_list);
 558
 559         /* hash it for later reverse mapping */
 560         hash = TD_HASH_FUNC (td->td_dma);
 561         td->td_hash = ohci->td_hash [hash];
 562         ohci->td_hash [hash] = td;
 563
 564         /* HC might read the TD (or cachelines) right away ... */
 565         wmb ();
 566         td->ed->hwTailP = td->hwNextTD;
 567 }
 568
 569 /*-------------------------------------------------------------------------*/
 570
 571 /* Prepare all TDs of a transfer, and queue them onto the ED.
 572  * Caller guarantees HC is active.
 573  * Usually the ED is already on the schedule, so TDs might be
 574  * processed as soon as they're queued.
 575  */
 576 static void td_submit_urb (
 577         struct ohci_hcd *ohci,
 578         struct urb      *urb
 579 ) {
 580         struct urb_priv *urb_priv = urb->hcpriv;
 581         dma_addr_t      data;
 582         int             data_len = urb->transfer_buffer_length;
 583         int             cnt = 0;
 584         u32             info = 0;
 585         int             is_out = usb_pipeout (urb->pipe);
 586         int             periodic = 0;
 587
 588         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 589          * use the device toggle bits for resetting, and rely on the fact
 590          * that resetting toggle is meaningless if the endpoint is active.
 591          */
 592         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 593                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 594                         is_out, 1);
 595                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 596         }
 597
 598         urb_priv->td_cnt = 0;
 599         list_add (&urb_priv->pending, &ohci->pending);
 600
 601         if (data_len)
 602                 data = urb->transfer_dma;
 603         else
 604                 data = 0;
 605
 606         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 607          * using TD_CC_GET, as well as by seeing them on the done list.
 608          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 609          */
 610         switch (urb_priv->ed->type) {
 611
 612         /* Bulk and interrupt are identical except for where in the schedule
 613          * their EDs live.
 614          */
 615         case PIPE_INTERRUPT:
 616                 /* ... and periodic urbs have extra accounting */
 617                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 618                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 619                 /* FALLTHROUGH */
 620         case PIPE_BULK:
 621                 info = is_out
 622                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 623                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 624                 /* TDs _could_ transfer up to 8K each */
 625                 while (data_len > 4096) {
 626                         td_fill (ohci, info, data, 4096, urb, cnt);
 627                         data += 4096;
 628                         data_len -= 4096;
 629                         cnt++;
 630                 }
 631                 /* maybe avoid ED halt on final TD short read */
 632                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 633                         info |= TD_R;
 634                 td_fill (ohci, info, data, data_len, urb, cnt);
 635                 cnt++;
 636                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 637                                 && cnt < urb_priv->length) {
 638                         td_fill (ohci, info, 0, 0, urb, cnt);
 639                         cnt++;
 640                 }
 641                 /* maybe kickstart bulk list */
 642                 if (urb_priv->ed->type == PIPE_BULK) {
 643                         wmb ();
 644                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 645                 }
 646                 break;
 647
 648         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 649          * any DATA phase works normally, and the STATUS ack is special.
 650          */
 651         case PIPE_CONTROL:
 652                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 653                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 654                 if (data_len > 0) {
 655                         info = TD_CC | TD_R | TD_T_DATA1;
 656                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 657                         /* NOTE:  mishandles transfers >8K, some >4K */
 658                         td_fill (ohci, info, data, data_len, urb, cnt++);
 659                 }
 660                 info = (is_out || data_len == 0)
 661                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 662                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 663                 td_fill (ohci, info, data, 0, urb, cnt++);
 664                 /* maybe kickstart control list */
 665                 wmb ();
 666                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 667                 break;
 668
 669         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 670          * Each TD could handle multiple consecutive frames (interval 1);
 671          * we could often reduce the number of TDs here.
 672          */
 673         case PIPE_ISOCHRONOUS:
 674                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
 675                         int     frame = urb->start_frame;
 676
 677                         // FIXME scheduling should handle frame counter
 678                         // roll-around ... exotic case (and OHCI has
 679                         // a 2^16 iso range, vs other HCs max of 2^10)
 680                         frame += cnt * urb->interval;
 681                         frame &= 0xffff;
 682                         td_fill (ohci, TD_CC | TD_ISO | frame,
 683                                 data + urb->iso_frame_desc [cnt].offset,
 684                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 685                 }
 686                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 687                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 688                 break;
 689         }
 690
 691         /* start periodic dma if needed */
 692         if (periodic) {
 693                 wmb ();
 694                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 695                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 696         }
 697
 698         // ASSERT (urb_priv->length == cnt);
 699 }
 700
 701 /*-------------------------------------------------------------------------*
 702  * Done List handling functions
 703  *-------------------------------------------------------------------------*/
 704
 705 /* calculate transfer length/status and update the urb
 706  * PRECONDITION:  irqsafe (only for urb->status locking)
 707  */
 708 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 709 {
 710         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 711         int     cc = 0;
 712
 713         list_del (&td->td_list);
 714
 715         /* ISO ... drivers see per-TD length/status */
 716         if (tdINFO & TD_ISO) {
 717                 u16     tdPSW = ohci_hwPSW (ohci, td, 0);
 718                 int     dlen = 0;
 719
 720                 /* NOTE:  assumes FC in tdINFO == 0, and that
 721                  * only the first of 0..MAXPSW psws is used.
 722                  */
 723
 724                 cc = (tdPSW >> 12) & 0xF;
 725                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 726                         return;
 727
 728                 if (usb_pipeout (urb->pipe))
 729                         dlen = urb->iso_frame_desc [td->index].length;
 730                 else {
 731                         /* short reads are always OK for ISO */
 732                         if (cc == TD_DATAUNDERRUN)
 733                                 cc = TD_CC_NOERROR;
 734                         dlen = tdPSW & 0x3ff;
 735                 }
 736                 urb->actual_length += dlen;
 737                 urb->iso_frame_desc [td->index].actual_length = dlen;
 738                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 739
 740                 if (cc != TD_CC_NOERROR)
 741                         ohci_vdbg (ohci,
 742                                 "urb %p iso td %p (%d) len %d cc %d\n",
 743                                 urb, td, 1 + td->index, dlen, cc);
 744
 745         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 746          * except that "setup" bytes aren't counted and "short" transfers
 747          * might not be reported as errors.
 748          */
 749         } else {
 750                 int     type = usb_pipetype (urb->pipe);
 751                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 752
 753                 cc = TD_CC_GET (tdINFO);
 754
 755                 /* update packet status if needed (short is normally ok) */
 756                 if (cc == TD_DATAUNDERRUN
 757                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 758                         cc = TD_CC_NOERROR;
 759                 if (cc != TD_CC_NOERROR && cc < 0x0E) {
 760                         spin_lock (&urb->lock);
 761                         if (urb->status == -EINPROGRESS)
 762                                 urb->status = cc_to_error [cc];
 763                         spin_unlock (&urb->lock);
 764                 }
 765
 766                 /* count all non-empty packets except control SETUP packet */
 767                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 768                         if (td->hwCBP == 0)
 769                                 urb->actual_length += tdBE - td->data_dma + 1;
 770                         else
 771                                 urb->actual_length +=
 772                                           hc32_to_cpup (ohci, &td->hwCBP)
 773                                         - td->data_dma;
 774                 }
 775
 776                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 777                         ohci_vdbg (ohci,
 778                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 779                                 urb, td, 1 + td->index, cc,
 780                                 urb->actual_length,
 781                                 urb->transfer_buffer_length);
 782         }
 783 }
 784
 785 /*-------------------------------------------------------------------------*/
 786
 787 static inline struct td *
 788 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
 789 {
 790         struct urb              *urb = td->urb;
 791         struct ed               *ed = td->ed;
 792         struct list_head        *tmp = td->td_list.next;
 793         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 794
 795         /* clear ed halt; this is the td that caused it, but keep it inactive
 796          * until its urb->complete() has a chance to clean up.
 797          */
 798         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 799         wmb ();
 800         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 801
 802         /* put any later tds from this urb onto the donelist, after 'td',
 803          * order won't matter here: no errors, and nothing was transferred.
 804          * also patch the ed so it looks as if those tds completed normally.
 805          */
 806         while (tmp != &ed->td_list) {
 807                 struct td       *next;
 808                 __hc32          info;
 809
 810                 next = list_entry (tmp, struct td, td_list);
 811                 tmp = next->td_list.next;
 812
 813                 if (next->urb != urb)
 814                         break;
 815
 816                 /* NOTE: if multi-td control DATA segments get supported,
 817                  * this urb had one of them, this td wasn't the last td
 818                  * in that segment (TD_R clear), this ed halted because
 819                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 820                  * then we need to leave the control STATUS packet queued
 821                  * and clear ED_SKIP.
 822                  */
 823                 info = next->hwINFO;
 824                 info |= cpu_to_hc32 (ohci, TD_DONE);
 825                 info &= ~cpu_to_hc32 (ohci, TD_CC);
 826                 next->hwINFO = info;
 827
 828                 next->next_dl_td = rev;
 829                 rev = next;
 830
 831                 ed->hwHeadP = next->hwNextTD | toggle;
 832         }
 833
 834         /* help for troubleshooting:  report anything that
 835          * looks odd ... that doesn't include protocol stalls
 836          * (or maybe some other things)
 837          */
 838         switch (cc) {
 839         case TD_DATAUNDERRUN:
 840                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 841                         break;
 842                 /* fallthrough */
 843         case TD_CC_STALL:
 844                 if (usb_pipecontrol (urb->pipe))
 845                         break;
 846                 /* fallthrough */
 847         default:
 848                 ohci_dbg (ohci,
 849                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 850                         urb, urb->dev->devpath,
 851                         usb_pipeendpoint (urb->pipe),
 852                         usb_pipein (urb->pipe) ? "in" : "out",
 853                         hc32_to_cpu (ohci, td->hwINFO),
 854                         cc, cc_to_error [cc]);
 855         }
 856
 857         return rev;
 858 }
 859
 860 /* replies to the request have to be on a FIFO basis so
 861  * we unreverse the hc-reversed done-list
 862  */
 863 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 864 {
 865         u32             td_dma;
 866         struct td       *td_rev = NULL;
 867         struct td       *td = NULL;
 868
 869         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 870         ohci->hcca->done_head = 0;
 871         wmb();
 872
 873         /* get TD from hc's singly linked list, and
 874          * prepend to ours.  ed->td_list changes later.
 875          */
 876         while (td_dma) {
 877                 int             cc;
 878
 879                 td = dma_to_td (ohci, td_dma);
 880                 if (!td) {
 881                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 882                         break;
 883                 }
 884
 885                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 886                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 887
 888                 /* Non-iso endpoints can halt on error; un-halt,
 889                  * and dequeue any other TDs from this urb.
 890                  * No other TD could have caused the halt.
 891                  */
 892                 if (cc != TD_CC_NOERROR
 893                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 894                         td_rev = ed_halted (ohci, td, cc, td_rev);
 895
 896                 td->next_dl_td = td_rev;
 897                 td_rev = td;
 898                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 899         }
 900         return td_rev;
 901 }
 902
 903 /*-------------------------------------------------------------------------*/
 904
 905 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 906 static void
 907 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 908 {
 909         struct ed       *ed, **last;
 910
 911 rescan_all:
 912         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 913                 struct list_head        *entry, *tmp;
 914                 int                     completed, modified;
 915                 __hc32                  *prev;
 916
 917                 /* only take off EDs that the HC isn't using, accounting for
 918                  * frame counter wraps and EDs with partially retired TDs
 919                  */
 920                 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
 921                         if (tick_before (tick, ed->tick)) {
 922 skip_ed:
 923                                 last = &ed->ed_next;
 924                                 continue;
 925                         }
 926
 927                         if (!list_empty (&ed->td_list)) {
 928                                 struct td       *td;
 929                                 u32             head;
 930
 931                                 td = list_entry (ed->td_list.next, struct td,
 932                                                         td_list);
 933                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 934                                                                 TD_MASK;
 935
 936                                 /* INTR_WDH may need to clean up first */
 937                                 if (td->td_dma != head) {
 938                                         if (ed == ohci->ed_to_check)
 939                                                 ohci->ed_to_check = NULL;
 940                                         else
 941                                                 goto skip_ed;
 942                                 }
 943                         }
 944                 }
 945
 946                 /* reentrancy:  if we drop the schedule lock, someone might
 947                  * have modified this list.  normally it's just prepending
 948                  * entries (which we'd ignore), but paranoia won't hurt.
 949                  */
 950                 *last = ed->ed_next;
 951                 ed->ed_next = NULL;
 952                 modified = 0;
 953
 954                 /* unlink urbs as requested, but rescan the list after
 955                  * we call a completion since it might have unlinked
 956                  * another (earlier) urb
 957                  *
 958                  * When we get here, the HC doesn't see this ed.  But it
 959                  * must not be rescheduled until all completed URBs have
 960                  * been given back to the driver.
 961                  */
 962 rescan_this:
 963                 completed = 0;
 964                 prev = &ed->hwHeadP;
 965                 list_for_each_safe (entry, tmp, &ed->td_list) {
 966                         struct td       *td;
 967                         struct urb      *urb;
 968                         urb_priv_t      *urb_priv;
 969                         __hc32          savebits;
 970
 971                         td = list_entry (entry, struct td, td_list);
 972                         urb = td->urb;
 973                         urb_priv = td->urb->hcpriv;
 974
 975                         if (urb->status == -EINPROGRESS) {
 976                                 prev = &td->hwNextTD;
 977                                 continue;
 978                         }
 979
 980                         /* patch pointer hc uses */
 981                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 982                         *prev = td->hwNextTD | savebits;
 983
 984                         /* HC may have partly processed this TD */
 985                         td_done (ohci, urb, td);
 986                         urb_priv->td_cnt++;
 987
 988                         /* if URB is done, clean up */
 989                         if (urb_priv->td_cnt == urb_priv->length) {
 990                                 modified = completed = 1;
 991                                 finish_urb (ohci, urb);
 992                         }
 993                 }
 994                 if (completed && !list_empty (&ed->td_list))
 995                         goto rescan_this;
 996
 997                 /* ED's now officially unlinked, hc doesn't see */
 998                 ed->state = ED_IDLE;
 999                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1000                         ohci->eds_scheduled--;
1001                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1002                 ed->hwNextED = 0;
1003                 wmb ();
1004                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1005
1006                 /* but if there's work queued, reschedule */
1007                 if (!list_empty (&ed->td_list)) {
1008                         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
1009                                 ed_schedule (ohci, ed);
1010                 }
1011
1012                 if (modified)
1013                         goto rescan_all;
1014         }
1015
1016         /* maybe reenable control and bulk lists */
1017         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
1018                         && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
1019                         && !ohci->ed_rm_list) {
1020                 u32     command = 0, control = 0;
1021
1022                 if (ohci->ed_controltail) {
1023                         command |= OHCI_CLF;
1024                         if (quirk_zfmicro(ohci))
1025                                 mdelay(1);
1026                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1027                                 control |= OHCI_CTRL_CLE;
1028                                 ohci_writel (ohci, 0,
1029                                         &ohci->regs->ed_controlcurrent);
1030                         }
1031                 }
1032                 if (ohci->ed_bulktail) {
1033                         command |= OHCI_BLF;
1034                         if (quirk_zfmicro(ohci))
1035                                 mdelay(1);
1036                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1037                                 control |= OHCI_CTRL_BLE;
1038                                 ohci_writel (ohci, 0,
1039                                         &ohci->regs->ed_bulkcurrent);
1040                         }
1041                 }
1042
1043                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1044                 if (control) {
1045                         ohci->hc_control |= control;
1046                         if (quirk_zfmicro(ohci))
1047                                 mdelay(1);
1048                         ohci_writel (ohci, ohci->hc_control,
1049                                         &ohci->regs->control);
1050                 }
1051                 if (command) {
1052                         if (quirk_zfmicro(ohci))
1053                                 mdelay(1);
1054                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1055                 }
1056         }
1057 }
1058
1059
1060
1061 /*-------------------------------------------------------------------------*/
1062
1063 /*
1064  * Used to take back a TD from the host controller. This would normally be
1065  * called from within dl_done_list, however it may be called directly if the
1066  * HC no longer sees the TD and it has not appeared on the donelist (after
1067  * two frames).  This bug has been observed on ZF Micro systems.
1068  */
1069 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1070 {
1071         struct urb      *urb = td->urb;
1072         urb_priv_t      *urb_priv = urb->hcpriv;
1073         struct ed       *ed = td->ed;
1074
1075         /* update URB's length and status from TD */
1076         td_done(ohci, urb, td);
1077         urb_priv->td_cnt++;
1078
1079         /* If all this urb's TDs are done, call complete() */
1080         if (urb_priv->td_cnt == urb_priv->length)
1081                 finish_urb(ohci, urb);
1082
1083         /* clean schedule:  unlink EDs that are no longer busy */
1084         if (list_empty(&ed->td_list)) {
1085                 if (ed->state == ED_OPER)
1086                         start_ed_unlink(ohci, ed);
1087
1088         /* ... reenabling halted EDs only after fault cleanup */
1089         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1090                         == cpu_to_hc32(ohci, ED_SKIP)) {
1091                 td = list_entry(ed->td_list.next, struct td, td_list);
1092                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1093                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1094                         /* ... hc may need waking-up */
1095                         switch (ed->type) {
1096                         case PIPE_CONTROL:
1097                                 ohci_writel(ohci, OHCI_CLF,
1098                                                 &ohci->regs->cmdstatus);
1099                                 break;
1100                         case PIPE_BULK:
1101                                 ohci_writel(ohci, OHCI_BLF,
1102                                                 &ohci->regs->cmdstatus);
1103                                 break;
1104                         }
1105                 }
1106         }
1107 }
1108
1109 /*
1110  * Process normal completions (error or success) and clean the schedules.
1111  *
1112  * This is the main path for handing urbs back to drivers.  The only other
1113  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1114  * instead of scanning the (re-reversed) donelist as this does.  There's
1115  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1116  * with TDs that appear to be orphaned are directly reclaimed.
1117  */
1118 static void
1119 dl_done_list (struct ohci_hcd *ohci)
1120 {
1121         struct td       *td = dl_reverse_done_list (ohci);
1122
1123         while (td) {
1124                 struct td       *td_next = td->next_dl_td;
1125                 takeback_td(ohci, td);
1126                 td = td_next;
1127         }
1128 }