2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: MAC routines
29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
42 /*--------------------- Export Definitions -------------------------*/
44 #define REV_ID_VT3253_A0 0x00
45 #define REV_ID_VT3253_A1 0x01
46 #define REV_ID_VT3253_B0 0x08
47 #define REV_ID_VT3253_B1 0x09
50 // Registers in the MAC
52 #define MAC_REG_BISTCMD 0x04
53 #define MAC_REG_BISTSR0 0x05
54 #define MAC_REG_BISTSR1 0x06
55 #define MAC_REG_BISTSR2 0x07
56 #define MAC_REG_I2MCSR 0x08
57 #define MAC_REG_I2MTGID 0x09
58 #define MAC_REG_I2MTGAD 0x0A
59 #define MAC_REG_I2MCFG 0x0B
60 #define MAC_REG_I2MDIPT 0x0C
61 #define MAC_REG_I2MDOPT 0x0E
62 #define MAC_REG_USBSUS 0x0F
64 #define MAC_REG_LOCALID 0x14
65 #define MAC_REG_TESTCFG 0x15
66 #define MAC_REG_JUMPER0 0x16
67 #define MAC_REG_JUMPER1 0x17
68 #define MAC_REG_TMCTL 0x18
69 #define MAC_REG_TMDATA0 0x1C
70 #define MAC_REG_TMDATA1 0x1D
71 #define MAC_REG_TMDATA2 0x1E
72 #define MAC_REG_TMDATA3 0x1F
74 // MAC Parameter related
75 #define MAC_REG_LRT 0x20 //
76 #define MAC_REG_SRT 0x21 //
77 #define MAC_REG_SIFS 0x22 //
78 #define MAC_REG_DIFS 0x23 //
79 #define MAC_REG_EIFS 0x24 //
80 #define MAC_REG_SLOT 0x25 //
81 #define MAC_REG_BI 0x26 //
82 #define MAC_REG_CWMAXMIN0 0x28 //
83 #define MAC_REG_LINKOFFTOTM 0x2A
84 #define MAC_REG_SWTMOT 0x2B
85 #define MAC_REG_RTSOKCNT 0x2C
86 #define MAC_REG_RTSFAILCNT 0x2D
87 #define MAC_REG_ACKFAILCNT 0x2E
88 #define MAC_REG_FCSERRCNT 0x2F
90 #define MAC_REG_TSFCNTR 0x30 //
91 #define MAC_REG_NEXTTBTT 0x38 //
92 #define MAC_REG_TSFOFST 0x40 //
93 #define MAC_REG_TFTCTL 0x48 //
94 // WMAC Control/Status Related
95 #define MAC_REG_ENCFG0 0x4C //
96 #define MAC_REG_ENCFG1 0x4D //
97 #define MAC_REG_ENCFG2 0x4E //
99 #define MAC_REG_CFG 0x50 //
100 #define MAC_REG_TEST 0x52 //
101 #define MAC_REG_HOSTCR 0x54 //
102 #define MAC_REG_MACCR 0x55 //
103 #define MAC_REG_RCR 0x56 //
104 #define MAC_REG_TCR 0x57 //
105 #define MAC_REG_IMR 0x58 //
106 #define MAC_REG_ISR 0x5C
107 #define MAC_REG_ISR1 0x5D
108 // Power Saving Related
109 #define MAC_REG_PSCFG 0x60 //
110 #define MAC_REG_PSCTL 0x61 //
111 #define MAC_REG_PSPWRSIG 0x62 //
112 #define MAC_REG_BBCR13 0x63
113 #define MAC_REG_AIDATIM 0x64
114 #define MAC_REG_PWBT 0x66
115 #define MAC_REG_WAKEOKTMR 0x68
116 #define MAC_REG_CALTMR 0x69
117 #define MAC_REG_SYNSPACCNT 0x6A
118 #define MAC_REG_WAKSYNOPT 0x6B
119 // Baseband/IF Control Group
120 #define MAC_REG_BBREGCTL 0x6C //
121 #define MAC_REG_CHANNEL 0x6D
122 #define MAC_REG_BBREGADR 0x6E
123 #define MAC_REG_BBREGDATA 0x6F
124 #define MAC_REG_IFREGCTL 0x70 //
125 #define MAC_REG_IFDATA 0x71 //
126 #define MAC_REG_ITRTMSET 0x74 //
127 #define MAC_REG_PAPEDELAY 0x77
128 #define MAC_REG_SOFTPWRCTL 0x78 //
129 #define MAC_REG_SOFTPWRCTL2 0x79 //
130 #define MAC_REG_GPIOCTL0 0x7A //
131 #define MAC_REG_GPIOCTL1 0x7B //
133 // MiscFF PIO related
134 #define MAC_REG_MISCFFNDEX 0xBC
135 #define MAC_REG_MISCFFCTL 0xBE
136 #define MAC_REG_MISCFFDATA 0xC0
138 // MAC Configuration Group
139 #define MAC_REG_PAR0 0xC4
140 #define MAC_REG_PAR4 0xC8
141 #define MAC_REG_BSSID0 0xCC
142 #define MAC_REG_BSSID4 0xD0
143 #define MAC_REG_MAR0 0xD4
144 #define MAC_REG_MAR4 0xD8
145 // MAC RSPPKT INFO Group
146 #define MAC_REG_RSPINF_B_1 0xDC
147 #define MAC_REG_RSPINF_B_2 0xE0
148 #define MAC_REG_RSPINF_B_5 0xE4
149 #define MAC_REG_RSPINF_B_11 0xE8
150 #define MAC_REG_RSPINF_A_6 0xEC
151 #define MAC_REG_RSPINF_A_9 0xEE
152 #define MAC_REG_RSPINF_A_12 0xF0
153 #define MAC_REG_RSPINF_A_18 0xF2
154 #define MAC_REG_RSPINF_A_24 0xF4
155 #define MAC_REG_RSPINF_A_36 0xF6
156 #define MAC_REG_RSPINF_A_48 0xF8
157 #define MAC_REG_RSPINF_A_54 0xFA
158 #define MAC_REG_RSPINF_A_72 0xFC
162 // Bits in the I2MCFG EEPROM register
164 #define I2MCFG_BOUNDCTL 0x80
165 #define I2MCFG_WAITCTL 0x20
166 #define I2MCFG_SCLOECTL 0x10
167 #define I2MCFG_WBUSYCTL 0x08
168 #define I2MCFG_NORETRY 0x04
169 #define I2MCFG_I2MLDSEQ 0x02
170 #define I2MCFG_I2CMFAST 0x01
173 // Bits in the I2MCSR EEPROM register
175 #define I2MCSR_EEMW 0x80
176 #define I2MCSR_EEMR 0x40
177 #define I2MCSR_AUTOLD 0x08
178 #define I2MCSR_NACK 0x02
179 #define I2MCSR_DONE 0x01
182 // Bits in the TMCTL register
184 #define TMCTL_TSUSP 0x04
185 #define TMCTL_TMD 0x02
186 #define TMCTL_TE 0x01
189 // Bits in the TFTCTL register
191 #define TFTCTL_HWUTSF 0x80 //
192 #define TFTCTL_TBTTSYNC 0x40
193 #define TFTCTL_HWUTSFEN 0x20
194 #define TFTCTL_TSFCNTRRD 0x10 //
195 #define TFTCTL_TBTTSYNCEN 0x08 //
196 #define TFTCTL_TSFSYNCEN 0x04 //
197 #define TFTCTL_TSFCNTRST 0x02 //
198 #define TFTCTL_TSFCNTREN 0x01 //
201 // Bits in the EnhanceCFG_0 register
203 #define EnCFG_BBType_a 0x00
204 #define EnCFG_BBType_b 0x01
205 #define EnCFG_BBType_g 0x02
206 #define EnCFG_BBType_MASK 0x03
207 #define EnCFG_ProtectMd 0x20
210 // Bits in the EnhanceCFG_1 register
212 #define EnCFG_BcnSusInd 0x01
213 #define EnCFG_BcnSusClr 0x02
216 // Bits in the EnhanceCFG_2 register
218 #define EnCFG_NXTBTTCFPSTR 0x01
219 #define EnCFG_BarkerPream 0x02
220 #define EnCFG_PktBurstMode 0x04
223 // Bits in the CFG register
225 #define CFG_TKIPOPT 0x80
226 #define CFG_RXDMAOPT 0x40
227 #define CFG_TMOT_SW 0x20
228 #define CFG_TMOT_HWLONG 0x10
229 #define CFG_TMOT_HW 0x00
230 #define CFG_CFPENDOPT 0x08
231 #define CFG_BCNSUSEN 0x04
232 #define CFG_NOTXTIMEOUT 0x02
233 #define CFG_NOBUFOPT 0x01
236 // Bits in the TEST register
238 #define TEST_LBEXT 0x80 //
239 #define TEST_LBINT 0x40 //
240 #define TEST_LBNONE 0x00 //
241 #define TEST_SOFTINT 0x20 //
242 #define TEST_CONTTX 0x10 //
243 #define TEST_TXPE 0x08 //
244 #define TEST_NAVDIS 0x04 //
245 #define TEST_NOCTS 0x02 //
246 #define TEST_NOACK 0x01 //
249 // Bits in the HOSTCR register
251 #define HOSTCR_TXONST 0x80 //
252 #define HOSTCR_RXONST 0x40 //
253 #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
254 #define HOSTCR_AP 0x10 // Port Type 1 = AP
255 #define HOSTCR_TXON 0x08 //0000 1000
256 #define HOSTCR_RXON 0x04 //0000 0100
257 #define HOSTCR_MACEN 0x02 //0000 0010
258 #define HOSTCR_SOFTRST 0x01 //0000 0001
261 // Bits in the MACCR register
263 #define MACCR_SYNCFLUSHOK 0x04 //
264 #define MACCR_SYNCFLUSH 0x02 //
265 #define MACCR_CLRNAV 0x01 //
268 // Bits in the RCR register
270 #define RCR_SSID 0x80
271 #define RCR_RXALLTYPE 0x40 //
272 #define RCR_UNICAST 0x20 //
273 #define RCR_BROADCAST 0x10 //
274 #define RCR_MULTICAST 0x08 //
275 #define RCR_WPAERR 0x04 //
276 #define RCR_ERRCRC 0x02 //
277 #define RCR_BSSID 0x01 //
280 // Bits in the TCR register
282 #define TCR_SYNCDCFOPT 0x02 //
283 #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
287 #define ISR_GPIO3 0x40
288 #define ISR_RXNOBUF 0x08
289 #define ISR_MIBNEARFULL 0x04
290 #define ISR_SOFTINT 0x02
291 #define ISR_FETALERR 0x01
293 #define LEDSTS_STS 0x06
294 #define LEDSTS_TMLEN 0x78
295 #define LEDSTS_OFF 0x00
296 #define LEDSTS_ON 0x02
297 #define LEDSTS_SLOW 0x04
298 #define LEDSTS_INTER 0x06
301 #define ISR_WATCHDOG 0x80
302 #define ISR_SOFTTIMER 0x40
303 #define ISR_GPIO0 0x20
304 #define ISR_TBTT 0x10
305 #define ISR_RXDMA0 0x08
306 #define ISR_BNTX 0x04
307 #define ISR_ACTX 0x01
310 // Bits in the PSCFG register
312 #define PSCFG_PHILIPMD 0x40 //
313 #define PSCFG_WAKECALEN 0x20 //
314 #define PSCFG_WAKETMREN 0x10 //
315 #define PSCFG_BBPSPROG 0x08 //
316 #define PSCFG_WAKESYN 0x04 //
317 #define PSCFG_SLEEPSYN 0x02 //
318 #define PSCFG_AUTOSLEEP 0x01 //
321 // Bits in the PSCTL register
323 #define PSCTL_WAKEDONE 0x20 //
324 #define PSCTL_PS 0x10 //
325 #define PSCTL_GO2DOZE 0x08 //
326 #define PSCTL_LNBCN 0x04 //
327 #define PSCTL_ALBCN 0x02 //
328 #define PSCTL_PSEN 0x01 //
331 // Bits in the PSPWSIG register
333 #define PSSIG_WPE3 0x80 //
334 #define PSSIG_WPE2 0x40 //
335 #define PSSIG_WPE1 0x20 //
336 #define PSSIG_WRADIOPE 0x10 //
337 #define PSSIG_SPE3 0x08 //
338 #define PSSIG_SPE2 0x04 //
339 #define PSSIG_SPE1 0x02 //
340 #define PSSIG_SRADIOPE 0x01 //
343 // Bits in the BBREGCTL register
345 #define BBREGCTL_DONE 0x04 //
346 #define BBREGCTL_REGR 0x02 //
347 #define BBREGCTL_REGW 0x01 //
350 // Bits in the IFREGCTL register
352 #define IFREGCTL_DONE 0x04 //
353 #define IFREGCTL_IFRF 0x02 //
354 #define IFREGCTL_REGW 0x01 //
357 // Bits in the SOFTPWRCTL register
359 #define SOFTPWRCTL_RFLEOPT 0x08 //
360 #define SOFTPWRCTL_TXPEINV 0x02 //
361 #define SOFTPWRCTL_SWPECTI 0x01 //
362 #define SOFTPWRCTL_SWPAPE 0x20 //
363 #define SOFTPWRCTL_SWCALEN 0x10 //
364 #define SOFTPWRCTL_SWRADIO_PE 0x08 //
365 #define SOFTPWRCTL_SWPE2 0x04 //
366 #define SOFTPWRCTL_SWPE1 0x02 //
367 #define SOFTPWRCTL_SWPE3 0x01 //
370 // Bits in the GPIOCTL1 register
372 #define GPIO3_MD 0x20 //
373 #define GPIO3_DATA 0x40 //
374 #define GPIO3_INTMD 0x80 //
377 // Bits in the MISCFFCTL register
379 #define MISCFFCTL_WRITE 0x0001 //
383 #define MAC_LB_EXT 0x02 //
384 #define MAC_LB_INTERNAL 0x01 //
385 #define MAC_LB_NONE 0x00 //
387 // Ethernet address filter type
388 #define PKT_TYPE_NONE 0x00 // turn off receiver
389 #define PKT_TYPE_ALL_MULTICAST 0x80
390 #define PKT_TYPE_PROMISCUOUS 0x40
391 #define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
392 #define PKT_TYPE_BROADCAST 0x10
393 #define PKT_TYPE_MULTICAST 0x08
394 #define PKT_TYPE_ERROR_WPA 0x04
395 #define PKT_TYPE_ERROR_CRC 0x02
396 #define PKT_TYPE_BSSID 0x01
398 #define Default_BI 0x200
401 #define MISCFIFO_KEYETRY0 32
402 #define MISCFIFO_KEYENTRYSIZE 22
404 // max time out delay time
405 #define W_MAX_TIMEOUT 0xFFF0U //
407 // wait time within loop
408 #define CB_DELAY_LOOP_WAIT 10 // 10ms
410 #define MAC_REVISION_A0 0x00
411 #define MAC_REVISION_A1 0x01
414 /*--------------------- Export Types ------------------------------*/
416 /*--------------------- Export Macros ------------------------------*/
418 /*--------------------- Export Classes ----------------------------*/
420 /*--------------------- Export Variables --------------------------*/
422 /*--------------------- Export Functions --------------------------*/
424 void MACvSetMultiAddrByHash (PSDevice pDevice, BYTE byHashIdx);
425 VOID MACvWriteMultiAddr (PSDevice pDevice, UINT uByteIdx, BYTE byData);
426 BOOL MACbShutdown(PSDevice pDevice);;
427 void MACvSetBBType(PSDevice pDevice,BYTE byType);
428 void MACvSetMISCFifo (PSDevice pDevice, WORD wOffset, DWORD dwData);
429 void MACvDisableKeyEntry(PSDevice pDevice, UINT uEntryIdx);
430 void MACvSetKeyEntry(PSDevice pDevice, WORD wKeyCtl, UINT uEntryIdx, UINT uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey);
432 void MACvRegBitsOff(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
433 void MACvRegBitsOn(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
434 void MACvWriteWord(PSDevice pDevice, BYTE byRegOfs, WORD wData);
436 void MACvWriteBSSIDAddress(PSDevice pDevice, PBYTE pbyEtherAddr);
437 void MACvEnableProtectMD(PSDevice pDevice);
438 void MACvDisableProtectMD(PSDevice pDevice);
439 void MACvEnableBarkerPreambleMd(PSDevice pDevice);
440 void MACvDisableBarkerPreambleMd(PSDevice pDevice);
441 void MACvWriteBeaconInterval(PSDevice pDevice, WORD wInterval);