SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/vme/bridges/vme_tsi148.c

   1 /*
   2  * Support for the Tundra TSI148 VME-PCI Bridge Chip
   3  *
   4  * Author: Martyn Welch <martyn.welch@gefanuc.com>
   5  * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/version.h>
  17 #include <linux/module.h>
  18 #include <linux/moduleparam.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/pci.h>
  24 #include <linux/poll.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/spinlock.h>
  28 #include <asm/time.h>
  29 #include <asm/io.h>
  30 #include <asm/uaccess.h>
  31
  32 #include "../vme.h"
  33 #include "../vme_bridge.h"
  34 #include "vme_tsi148.h"
  35
  36 static int __init tsi148_init(void);
  37 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  38 static void tsi148_remove(struct pci_dev *);
  39 static void __exit tsi148_exit(void);
  40
  41
  42 int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
  43         unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
  44 int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
  45         unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
  46
  47 int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
  48         unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
  49 int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
  50         unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
  51 ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
  52         loff_t);
  53 ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
  54         loff_t);
  55 unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
  56         unsigned int, unsigned int, loff_t);
  57 int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
  58         struct vme_dma_attr *, size_t);
  59 int tsi148_dma_list_exec(struct vme_dma_list *);
  60 int tsi148_dma_list_empty(struct vme_dma_list *);
  61 int tsi148_generate_irq(int, int);
  62 int tsi148_lm_set(unsigned long long, vme_address_t, vme_cycle_t);
  63 int tsi148_lm_get(unsigned long long *, vme_address_t *, vme_cycle_t *);
  64 int tsi148_lm_attach(int, void (*callback)(int));
  65 int tsi148_lm_detach(int);
  66 int tsi148_slot_get(void);
  67
  68 /* Modue parameter */
  69 int err_chk = 0;
  70
  71 /* XXX These should all be in a per device structure */
  72 struct vme_bridge *tsi148_bridge;
  73 wait_queue_head_t dma_queue[2];
  74 wait_queue_head_t iack_queue;
  75 void (*lm_callback[4])(int);    /* Called in interrupt handler, be careful! */
  76 void *crcsr_kernel;
  77 dma_addr_t crcsr_bus;
  78 struct vme_master_resource *flush_image;
  79 struct mutex vme_rmw;   /* Only one RMW cycle at a time */
  80 struct mutex vme_int;   /*
  81                                  * Only one VME interrupt can be
  82                                  * generated at a time, provide locking
  83                                  */
  84 struct mutex vme_irq;   /* Locking for VME irq callback configuration */
  85 struct mutex vme_lm;    /* Locking for location monitor operations */
  86
  87
  88 static char driver_name[] = "vme_tsi148";
  89
  90 static struct pci_device_id tsi148_ids[] = {
  91         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  92         { },
  93 };
  94
  95 static struct pci_driver tsi148_driver = {
  96         .name = driver_name,
  97         .id_table = tsi148_ids,
  98         .probe = tsi148_probe,
  99         .remove = tsi148_remove,
 100 };
 101
 102 static void reg_join(unsigned int high, unsigned int low,
 103         unsigned long long *variable)
 104 {
 105         *variable = (unsigned long long)high << 32;
 106         *variable |= (unsigned long long)low;
 107 }
 108
 109 static void reg_split(unsigned long long variable, unsigned int *high,
 110         unsigned int *low)
 111 {
 112         *low = (unsigned int)variable & 0xFFFFFFFF;
 113         *high = (unsigned int)(variable >> 32);
 114 }
 115
 116 /*
 117  * Wakes up DMA queue.
 118  */
 119 static u32 tsi148_DMA_irqhandler(int channel_mask)
 120 {
 121         u32 serviced = 0;
 122
 123         if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
 124                 wake_up(&dma_queue[0]);
 125                 serviced |= TSI148_LCSR_INTC_DMA0C;
 126         }
 127         if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
 128                 wake_up(&dma_queue[1]);
 129                 serviced |= TSI148_LCSR_INTC_DMA1C;
 130         }
 131
 132         return serviced;
 133 }
 134
 135 /*
 136  * Wake up location monitor queue
 137  */
 138 static u32 tsi148_LM_irqhandler(u32 stat)
 139 {
 140         int i;
 141         u32 serviced = 0;
 142
 143         for (i = 0; i < 4; i++) {
 144                 if(stat & TSI148_LCSR_INTS_LMS[i]) {
 145                         /* We only enable interrupts if the callback is set */
 146                         lm_callback[i](i);
 147                         serviced |= TSI148_LCSR_INTC_LMC[i];
 148                 }
 149         }
 150
 151         return serviced;
 152 }
 153
 154 /*
 155  * Wake up mail box queue.
 156  *
 157  * XXX This functionality is not exposed up though API.
 158  */
 159 static u32 tsi148_MB_irqhandler(u32 stat)
 160 {
 161         int i;
 162         u32 val;
 163         u32 serviced = 0;
 164
 165         for (i = 0; i < 4; i++) {
 166                 if(stat & TSI148_LCSR_INTS_MBS[i]) {
 167                         val = ioread32be(tsi148_bridge->base +
 168                                 TSI148_GCSR_MBOX[i]);
 169                         printk("VME Mailbox %d received: 0x%x\n", i, val);
 170                         serviced |= TSI148_LCSR_INTC_MBC[i];
 171                 }
 172         }
 173
 174         return serviced;
 175 }
 176
 177 /*
 178  * Display error & status message when PERR (PCI) exception interrupt occurs.
 179  */
 180 static u32 tsi148_PERR_irqhandler(void)
 181 {
 182         printk(KERN_ERR
 183                 "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
 184                 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU),
 185                 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL),
 186                 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT)
 187                 );
 188         printk(KERN_ERR
 189                 "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
 190                 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA),
 191                 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS)
 192                 );
 193
 194         iowrite32be(TSI148_LCSR_EDPAT_EDPCL,
 195                 tsi148_bridge->base + TSI148_LCSR_EDPAT);
 196
 197         return TSI148_LCSR_INTC_PERRC;
 198 }
 199
 200 /*
 201  * Save address and status when VME error interrupt occurs.
 202  */
 203 static u32 tsi148_VERR_irqhandler(void)
 204 {
 205         unsigned int error_addr_high, error_addr_low;
 206         unsigned long long error_addr;
 207         u32 error_attrib;
 208         struct vme_bus_error *error;
 209
 210         error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU);
 211         error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL);
 212         error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT);
 213
 214         reg_join(error_addr_high, error_addr_low, &error_addr);
 215
 216         /* Check for exception register overflow (we have lost error data) */
 217         if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
 218                 printk(KERN_ERR "VME Bus Exception Overflow Occurred\n");
 219         }
 220
 221         error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
 222                 GFP_ATOMIC);
 223         if (error) {
 224                 error->address = error_addr;
 225                 error->attributes = error_attrib;
 226                 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
 227         } else {
 228                 printk(KERN_ERR
 229                         "Unable to alloc memory for VMEbus Error reporting\n");
 230                 printk(KERN_ERR
 231                         "VME Bus Error at address: 0x%llx, attributes: %08x\n",
 232                         error_addr, error_attrib);
 233         }
 234
 235         /* Clear Status */
 236         iowrite32be(TSI148_LCSR_VEAT_VESCL,
 237                 tsi148_bridge->base + TSI148_LCSR_VEAT);
 238
 239         return TSI148_LCSR_INTC_VERRC;
 240 }
 241
 242 /*
 243  * Wake up IACK queue.
 244  */
 245 static u32 tsi148_IACK_irqhandler(void)
 246 {
 247         printk("tsi148_IACK_irqhandler\n");
 248         wake_up(&iack_queue);
 249
 250         return TSI148_LCSR_INTC_IACKC;
 251 }
 252
 253 /*
 254  * Calling VME bus interrupt callback if provided.
 255  */
 256 static u32 tsi148_VIRQ_irqhandler(u32 stat)
 257 {
 258         int vec, i, serviced = 0;
 259         void (*call)(int, int, void *);
 260         void *priv_data;
 261
 262         for (i = 7; i > 0; i--) {
 263                 if (stat & (1 << i)) {
 264                         /*
 265                          *      Note:   Even though the registers are defined
 266                          *      as 32-bits in the spec, we only want to issue
 267                          *      8-bit IACK cycles on the bus, read from offset
 268                          *      3.
 269                          */
 270                         vec = ioread8(tsi148_bridge->base +
 271                                 TSI148_LCSR_VIACK[i] + 3);
 272
 273                         call = tsi148_bridge->irq[i - 1].callback[vec].func;
 274                         priv_data =
 275                                 tsi148_bridge->irq[i-1].callback[vec].priv_data;
 276
 277                         if (call != NULL)
 278                                 call(i, vec, priv_data);
 279                         else
 280                                 printk("Spurilous VME interrupt, level:%x, "
 281                                         "vector:%x\n", i, vec);
 282
 283                         serviced |= (1 << i);
 284                 }
 285         }
 286
 287         return serviced;
 288 }
 289
 290 /*
 291  * Top level interrupt handler.  Clears appropriate interrupt status bits and
 292  * then calls appropriate sub handler(s).
 293  */
 294 static irqreturn_t tsi148_irqhandler(int irq, void *dev_id)
 295 {
 296         u32 stat, enable, serviced = 0;
 297
 298         /* Determine which interrupts are unmasked and set */
 299         enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
 300         stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS);
 301
 302         /* Only look at unmasked interrupts */
 303         stat &= enable;
 304
 305         if (unlikely(!stat)) {
 306                 return IRQ_NONE;
 307         }
 308
 309         /* Call subhandlers as appropriate */
 310         /* DMA irqs */
 311         if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
 312                 serviced |= tsi148_DMA_irqhandler(stat);
 313
 314         /* Location monitor irqs */
 315         if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
 316                         TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
 317                 serviced |= tsi148_LM_irqhandler(stat);
 318
 319         /* Mail box irqs */
 320         if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
 321                         TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
 322                 serviced |= tsi148_MB_irqhandler(stat);
 323
 324         /* PCI bus error */
 325         if (stat & TSI148_LCSR_INTS_PERRS)
 326                 serviced |= tsi148_PERR_irqhandler();
 327
 328         /* VME bus error */
 329         if (stat & TSI148_LCSR_INTS_VERRS)
 330                 serviced |= tsi148_VERR_irqhandler();
 331
 332         /* IACK irq */
 333         if (stat & TSI148_LCSR_INTS_IACKS)
 334                 serviced |= tsi148_IACK_irqhandler();
 335
 336         /* VME bus irqs */
 337         if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
 338                         TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
 339                         TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
 340                         TSI148_LCSR_INTS_IRQ1S))
 341                 serviced |= tsi148_VIRQ_irqhandler(stat);
 342
 343         /* Clear serviced interrupts */
 344         iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC);
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static int tsi148_irq_init(struct vme_bridge *bridge)
 350 {
 351         int result;
 352         unsigned int tmp;
 353         struct pci_dev *pdev;
 354
 355         /* Need pdev */
 356         pdev = container_of(bridge->parent, struct pci_dev, dev);
 357
 358         /* Initialise list for VME bus errors */
 359         INIT_LIST_HEAD(&(bridge->vme_errors));
 360
 361         result = request_irq(pdev->irq,
 362                              tsi148_irqhandler,
 363                              IRQF_SHARED,
 364                              driver_name, pdev);
 365         if (result) {
 366                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 367                         pdev->irq);
 368                 return result;
 369         }
 370
 371         /* Enable and unmask interrupts */
 372         tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
 373                 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
 374                 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
 375                 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
 376                 TSI148_LCSR_INTEO_IACKEO;
 377
 378         /* XXX This leaves the following interrupts masked.
 379          * TSI148_LCSR_INTEO_VIEEO
 380          * TSI148_LCSR_INTEO_SYSFLEO
 381          * TSI148_LCSR_INTEO_ACFLEO
 382          */
 383
 384         /* Don't enable Location Monitor interrupts here - they will be
 385          * enabled when the location monitors are properly configured and
 386          * a callback has been attached.
 387          * TSI148_LCSR_INTEO_LM0EO
 388          * TSI148_LCSR_INTEO_LM1EO
 389          * TSI148_LCSR_INTEO_LM2EO
 390          * TSI148_LCSR_INTEO_LM3EO
 391          */
 392
 393         /* Don't enable VME interrupts until we add a handler, else the board
 394          * will respond to it and we don't want that unless it knows how to
 395          * properly deal with it.
 396          * TSI148_LCSR_INTEO_IRQ7EO
 397          * TSI148_LCSR_INTEO_IRQ6EO
 398          * TSI148_LCSR_INTEO_IRQ5EO
 399          * TSI148_LCSR_INTEO_IRQ4EO
 400          * TSI148_LCSR_INTEO_IRQ3EO
 401          * TSI148_LCSR_INTEO_IRQ2EO
 402          * TSI148_LCSR_INTEO_IRQ1EO
 403          */
 404
 405         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 406         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 407
 408         return 0;
 409 }
 410
 411 static void tsi148_irq_exit(struct pci_dev *pdev)
 412 {
 413         /* Turn off interrupts */
 414         iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
 415         iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN);
 416
 417         /* Clear all interrupts */
 418         iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
 419
 420         /* Detach interrupt handler */
 421         free_irq(pdev->irq, pdev);
 422 }
 423
 424 /*
 425  * Check to see if an IACk has been received, return true (1) or false (0).
 426  */
 427 int tsi148_iack_received(void)
 428 {
 429         u32 tmp;
 430
 431         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
 432
 433         if (tmp & TSI148_LCSR_VICR_IRQS)
 434                 return 0;
 435         else
 436                 return 1;
 437 }
 438
 439 /*
 440  * Set up an VME interrupt
 441  */
 442 int tsi148_request_irq(int level, int statid,
 443         void (*callback)(int level, int vector, void *priv_data),
 444         void *priv_data)
 445 {
 446         u32 tmp;
 447
 448         mutex_lock(&(vme_irq));
 449
 450         if(tsi148_bridge->irq[level - 1].callback[statid].func) {
 451                 mutex_unlock(&(vme_irq));
 452                 printk("VME Interrupt already taken\n");
 453                 return -EBUSY;
 454         }
 455
 456
 457         tsi148_bridge->irq[level - 1].count++;
 458         tsi148_bridge->irq[level - 1].callback[statid].priv_data = priv_data;
 459         tsi148_bridge->irq[level - 1].callback[statid].func = callback;
 460
 461         /* Enable IRQ level */
 462         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
 463         tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
 464         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
 465
 466         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
 467         tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
 468         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
 469
 470         mutex_unlock(&(vme_irq));
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Free VME interrupt
 477  */
 478 void tsi148_free_irq(int level, int statid)
 479 {
 480         u32 tmp;
 481         struct pci_dev *pdev;
 482
 483         mutex_lock(&(vme_irq));
 484
 485         tsi148_bridge->irq[level - 1].count--;
 486
 487         /* Disable IRQ level if no more interrupts attached at this level*/
 488         if (tsi148_bridge->irq[level - 1].count == 0) {
 489                 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
 490                 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
 491                 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
 492
 493                 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
 494                 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
 495                 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
 496
 497                 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 498
 499                 synchronize_irq(pdev->irq);
 500         }
 501
 502         tsi148_bridge->irq[level - 1].callback[statid].func = NULL;
 503         tsi148_bridge->irq[level - 1].callback[statid].priv_data = NULL;
 504
 505         mutex_unlock(&(vme_irq));
 506 }
 507
 508 /*
 509  * Generate a VME bus interrupt at the requested level & vector. Wait for
 510  * interrupt to be acked.
 511  */
 512 int tsi148_generate_irq(int level, int statid)
 513 {
 514         u32 tmp;
 515
 516         mutex_lock(&(vme_int));
 517
 518         /* Read VICR register */
 519         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
 520
 521         /* Set Status/ID */
 522         tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
 523                 (statid & TSI148_LCSR_VICR_STID_M);
 524         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
 525
 526         /* Assert VMEbus IRQ */
 527         tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
 528         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
 529
 530         /* XXX Consider implementing a timeout? */
 531         wait_event_interruptible(iack_queue, tsi148_iack_received());
 532
 533         mutex_unlock(&(vme_int));
 534
 535         return 0;
 536 }
 537
 538 /*
 539  * Find the first error in this address range
 540  */
 541 static struct vme_bus_error *tsi148_find_error(vme_address_t aspace,
 542         unsigned long long address, size_t count)
 543 {
 544         struct list_head *err_pos;
 545         struct vme_bus_error *vme_err, *valid = NULL;
 546         unsigned long long bound;
 547
 548         bound = address + count;
 549
 550         /*
 551          * XXX We are currently not looking at the address space when parsing
 552          *     for errors. This is because parsing the Address Modifier Codes
 553          *     is going to be quite resource intensive to do properly. We
 554          *     should be OK just looking at the addresses and this is certainly
 555          *     much better than what we had before.
 556          */
 557         err_pos = NULL;
 558         /* Iterate through errors */
 559         list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
 560                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 561                 if((vme_err->address >= address) && (vme_err->address < bound)){
 562                         valid = vme_err;
 563                         break;
 564                 }
 565         }
 566
 567         return valid;
 568 }
 569
 570 /*
 571  * Clear errors in the provided address range.
 572  */
 573 static void tsi148_clear_errors(vme_address_t aspace,
 574         unsigned long long address, size_t count)
 575 {
 576         struct list_head *err_pos, *temp;
 577         struct vme_bus_error *vme_err;
 578         unsigned long long bound;
 579
 580         bound = address + count;
 581
 582         /*
 583          * XXX We are currently not looking at the address space when parsing
 584          *     for errors. This is because parsing the Address Modifier Codes
 585          *     is going to be quite resource intensive to do properly. We
 586          *     should be OK just looking at the addresses and this is certainly
 587          *     much better than what we had before.
 588          */
 589         err_pos = NULL;
 590         /* Iterate through errors */
 591         list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
 592                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 593
 594                 if((vme_err->address >= address) && (vme_err->address < bound)){
 595                         list_del(err_pos);
 596                         kfree(vme_err);
 597                 }
 598         }
 599 }
 600
 601 /*
 602  * Initialize a slave window with the requested attributes.
 603  */
 604 int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
 605         unsigned long long vme_base, unsigned long long size,
 606         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 607 {
 608         unsigned int i, addr = 0, granularity = 0;
 609         unsigned int temp_ctl = 0;
 610         unsigned int vme_base_low, vme_base_high;
 611         unsigned int vme_bound_low, vme_bound_high;
 612         unsigned int pci_offset_low, pci_offset_high;
 613         unsigned long long vme_bound, pci_offset;
 614
 615 #if 0
 616         printk("Set slave image %d to:\n", image->number);
 617         printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no");
 618         printk("\tVME Base:0x%llx\n", vme_base);
 619         printk("\tWindow Size:0x%llx\n", size);
 620         printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base);
 621         printk("\tAddress Space:0x%x\n", aspace);
 622         printk("\tTransfer Cycle Properties:0x%x\n", cycle);
 623 #endif
 624
 625         i = image->number;
 626
 627         switch (aspace) {
 628         case VME_A16:
 629                 granularity = 0x10;
 630                 addr |= TSI148_LCSR_ITAT_AS_A16;
 631                 break;
 632         case VME_A24:
 633                 granularity = 0x1000;
 634                 addr |= TSI148_LCSR_ITAT_AS_A24;
 635                 break;
 636         case VME_A32:
 637                 granularity = 0x10000;
 638                 addr |= TSI148_LCSR_ITAT_AS_A32;
 639                 break;
 640         case VME_A64:
 641                 granularity = 0x10000;
 642                 addr |= TSI148_LCSR_ITAT_AS_A64;
 643                 break;
 644         case VME_CRCSR:
 645         case VME_USER1:
 646         case VME_USER2:
 647         case VME_USER3:
 648         case VME_USER4:
 649         default:
 650                 printk("Invalid address space\n");
 651                 return -EINVAL;
 652                 break;
 653         }
 654
 655         /* Convert 64-bit variables to 2x 32-bit variables */
 656         reg_split(vme_base, &vme_base_high, &vme_base_low);
 657
 658         /*
 659          * Bound address is a valid address for the window, adjust
 660          * accordingly
 661          */
 662         vme_bound = vme_base + size - granularity;
 663         reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
 664         pci_offset = (unsigned long long)pci_base - vme_base;
 665         reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
 666
 667         if (vme_base_low & (granularity - 1)) {
 668                 printk("Invalid VME base alignment\n");
 669                 return -EINVAL;
 670         }
 671         if (vme_bound_low & (granularity - 1)) {
 672                 printk("Invalid VME bound alignment\n");
 673                 return -EINVAL;
 674         }
 675         if (pci_offset_low & (granularity - 1)) {
 676                 printk("Invalid PCI Offset alignment\n");
 677                 return -EINVAL;
 678         }
 679
 680 #if 0
 681         printk("\tVME Bound:0x%llx\n", vme_bound);
 682         printk("\tPCI Offset:0x%llx\n", pci_offset);
 683 #endif
 684
 685         /*  Disable while we are mucking around */
 686         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 687                 TSI148_LCSR_OFFSET_ITAT);
 688         temp_ctl &= ~TSI148_LCSR_ITAT_EN;
 689         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 690                 TSI148_LCSR_OFFSET_ITAT);
 691
 692         /* Setup mapping */
 693         iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 694                 TSI148_LCSR_OFFSET_ITSAU);
 695         iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 696                 TSI148_LCSR_OFFSET_ITSAL);
 697         iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 698                 TSI148_LCSR_OFFSET_ITEAU);
 699         iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 700                 TSI148_LCSR_OFFSET_ITEAL);
 701         iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 702                 TSI148_LCSR_OFFSET_ITOFU);
 703         iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 704                 TSI148_LCSR_OFFSET_ITOFL);
 705
 706 /* XXX Prefetch stuff currently unsupported */
 707 #if 0
 708
 709         for (x = 0; x < 4; x++) {
 710                 if ((64 << x) >= vmeIn->prefetchSize) {
 711                         break;
 712                 }
 713         }
 714         if (x == 4)
 715                 x--;
 716         temp_ctl |= (x << 16);
 717
 718         if (vmeIn->prefetchThreshold)
 719                 if (vmeIn->prefetchThreshold)
 720                         temp_ctl |= 0x40000;
 721 #endif
 722
 723         /* Setup 2eSST speeds */
 724         temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
 725         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 726         case VME_2eSST160:
 727                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
 728                 break;
 729         case VME_2eSST267:
 730                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
 731                 break;
 732         case VME_2eSST320:
 733                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
 734                 break;
 735         }
 736
 737         /* Setup cycle types */
 738         temp_ctl &= ~(0x1F << 7);
 739         if (cycle & VME_BLT)
 740                 temp_ctl |= TSI148_LCSR_ITAT_BLT;
 741         if (cycle & VME_MBLT)
 742                 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
 743         if (cycle & VME_2eVME)
 744                 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
 745         if (cycle & VME_2eSST)
 746                 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
 747         if (cycle & VME_2eSSTB)
 748                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
 749
 750         /* Setup address space */
 751         temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
 752         temp_ctl |= addr;
 753
 754         temp_ctl &= ~0xF;
 755         if (cycle & VME_SUPER)
 756                 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
 757         if (cycle & VME_USER)
 758                 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
 759         if (cycle & VME_PROG)
 760                 temp_ctl |= TSI148_LCSR_ITAT_PGM;
 761         if (cycle & VME_DATA)
 762                 temp_ctl |= TSI148_LCSR_ITAT_DATA;
 763
 764         /* Write ctl reg without enable */
 765         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 766                 TSI148_LCSR_OFFSET_ITAT);
 767
 768         if (enabled)
 769                 temp_ctl |= TSI148_LCSR_ITAT_EN;
 770
 771         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
 772                 TSI148_LCSR_OFFSET_ITAT);
 773
 774         return 0;
 775 }
 776
 777 /*
 778  * Get slave window configuration.
 779  *
 780  * XXX Prefetch currently unsupported.
 781  */
 782 int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
 783         unsigned long long *vme_base, unsigned long long *size,
 784         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 785 {
 786         unsigned int i, granularity = 0, ctl = 0;
 787         unsigned int vme_base_low, vme_base_high;
 788         unsigned int vme_bound_low, vme_bound_high;
 789         unsigned int pci_offset_low, pci_offset_high;
 790         unsigned long long vme_bound, pci_offset;
 791
 792
 793         i = image->number;
 794
 795         /* Read registers */
 796         ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 797                 TSI148_LCSR_OFFSET_ITAT);
 798
 799         vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 800                 TSI148_LCSR_OFFSET_ITSAU);
 801         vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 802                 TSI148_LCSR_OFFSET_ITSAL);
 803         vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 804                 TSI148_LCSR_OFFSET_ITEAU);
 805         vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 806                 TSI148_LCSR_OFFSET_ITEAL);
 807         pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 808                 TSI148_LCSR_OFFSET_ITOFU);
 809         pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
 810                 TSI148_LCSR_OFFSET_ITOFL);
 811
 812         /* Convert 64-bit variables to 2x 32-bit variables */
 813         reg_join(vme_base_high, vme_base_low, vme_base);
 814         reg_join(vme_bound_high, vme_bound_low, &vme_bound);
 815         reg_join(pci_offset_high, pci_offset_low, &pci_offset);
 816
 817         *pci_base = (dma_addr_t)vme_base + pci_offset;
 818
 819         *enabled = 0;
 820         *aspace = 0;
 821         *cycle = 0;
 822
 823         if (ctl & TSI148_LCSR_ITAT_EN)
 824                 *enabled = 1;
 825
 826         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
 827                 granularity = 0x10;
 828                 *aspace |= VME_A16;
 829         }
 830         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
 831                 granularity = 0x1000;
 832                 *aspace |= VME_A24;
 833         }
 834         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
 835                 granularity = 0x10000;
 836                 *aspace |= VME_A32;
 837         }
 838         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
 839                 granularity = 0x10000;
 840                 *aspace |= VME_A64;
 841         }
 842
 843         /* Need granularity before we set the size */
 844         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 845
 846
 847         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
 848                 *cycle |= VME_2eSST160;
 849         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
 850                 *cycle |= VME_2eSST267;
 851         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
 852                 *cycle |= VME_2eSST320;
 853
 854         if (ctl & TSI148_LCSR_ITAT_BLT)
 855                 *cycle |= VME_BLT;
 856         if (ctl & TSI148_LCSR_ITAT_MBLT)
 857                 *cycle |= VME_MBLT;
 858         if (ctl & TSI148_LCSR_ITAT_2eVME)
 859                 *cycle |= VME_2eVME;
 860         if (ctl & TSI148_LCSR_ITAT_2eSST)
 861                 *cycle |= VME_2eSST;
 862         if (ctl & TSI148_LCSR_ITAT_2eSSTB)
 863                 *cycle |= VME_2eSSTB;
 864
 865         if (ctl & TSI148_LCSR_ITAT_SUPR)
 866                 *cycle |= VME_SUPER;
 867         if (ctl & TSI148_LCSR_ITAT_NPRIV)
 868                 *cycle |= VME_USER;
 869         if (ctl & TSI148_LCSR_ITAT_PGM)
 870                 *cycle |= VME_PROG;
 871         if (ctl & TSI148_LCSR_ITAT_DATA)
 872                 *cycle |= VME_DATA;
 873
 874         return 0;
 875 }
 876
 877 /*
 878  * Allocate and map PCI Resource
 879  */
 880 static int tsi148_alloc_resource(struct vme_master_resource *image,
 881         unsigned long long size)
 882 {
 883         unsigned long long existing_size;
 884         int retval = 0;
 885         struct pci_dev *pdev;
 886
 887         /* Find pci_dev container of dev */
 888         if (tsi148_bridge->parent == NULL) {
 889                 printk("Dev entry NULL\n");
 890                 return -EINVAL;
 891         }
 892         pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 893
 894         existing_size = (unsigned long long)(image->pci_resource.end -
 895                 image->pci_resource.start);
 896
 897         /* If the existing size is OK, return */
 898         if (existing_size == (size - 1))
 899                 return 0;
 900
 901         if (existing_size != 0) {
 902                 iounmap(image->kern_base);
 903                 image->kern_base = NULL;
 904                 if (image->pci_resource.name != NULL)
 905                         kfree(image->pci_resource.name);
 906                 release_resource(&(image->pci_resource));
 907                 memset(&(image->pci_resource), 0, sizeof(struct resource));
 908         }
 909
 910         if (image->pci_resource.name == NULL) {
 911                 image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
 912                 if (image->pci_resource.name == NULL) {
 913                         printk(KERN_ERR "Unable to allocate memory for resource"
 914                                 " name\n");
 915                         retval = -ENOMEM;
 916                         goto err_name;
 917                 }
 918         }
 919
 920         sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name,
 921                 image->number);
 922
 923         image->pci_resource.start = 0;
 924         image->pci_resource.end = (unsigned long)size;
 925         image->pci_resource.flags = IORESOURCE_MEM;
 926
 927         retval = pci_bus_alloc_resource(pdev->bus,
 928                 &(image->pci_resource), size, size, PCIBIOS_MIN_MEM,
 929                 0, NULL, NULL);
 930         if (retval) {
 931                 printk(KERN_ERR "Failed to allocate mem resource for "
 932                         "window %d size 0x%lx start 0x%lx\n",
 933                         image->number, (unsigned long)size,
 934                         (unsigned long)image->pci_resource.start);
 935                 goto err_resource;
 936         }
 937
 938         image->kern_base = ioremap_nocache(
 939                 image->pci_resource.start, size);
 940         if (image->kern_base == NULL) {
 941                 printk(KERN_ERR "Failed to remap resource\n");
 942                 retval = -ENOMEM;
 943                 goto err_remap;
 944         }
 945
 946         return 0;
 947
 948         iounmap(image->kern_base);
 949         image->kern_base = NULL;
 950 err_remap:
 951         release_resource(&(image->pci_resource));
 952 err_resource:
 953         kfree(image->pci_resource.name);
 954         memset(&(image->pci_resource), 0, sizeof(struct resource));
 955 err_name:
 956         return retval;
 957 }
 958
 959 /*
 960  * Free and unmap PCI Resource
 961  */
 962 static void tsi148_free_resource(struct vme_master_resource *image)
 963 {
 964         iounmap(image->kern_base);
 965         image->kern_base = NULL;
 966         release_resource(&(image->pci_resource));
 967         kfree(image->pci_resource.name);
 968         memset(&(image->pci_resource), 0, sizeof(struct resource));
 969 }
 970
 971 /*
 972  * Set the attributes of an outbound window.
 973  */
 974 int tsi148_master_set( struct vme_master_resource *image, int enabled,
 975         unsigned long long vme_base, unsigned long long size,
 976         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 977 {
 978         int retval = 0;
 979         unsigned int i;
 980         unsigned int temp_ctl = 0;
 981         unsigned int pci_base_low, pci_base_high;
 982         unsigned int pci_bound_low, pci_bound_high;
 983         unsigned int vme_offset_low, vme_offset_high;
 984         unsigned long long pci_bound, vme_offset, pci_base;
 985
 986         /* Verify input data */
 987         if (vme_base & 0xFFFF) {
 988                 printk("Invalid VME Window alignment\n");
 989                 retval = -EINVAL;
 990                 goto err_window;
 991         }
 992         if (size < 0x10000) {
 993                 printk("Invalid VME Window size\n");
 994                 retval = -EINVAL;
 995                 goto err_window;
 996         }
 997
 998         spin_lock(&(image->lock));
 999
1000         /* Let's allocate the resource here rather than further up the stack as
1001          * it avoids pushing loads of bus dependant stuff up the stack
1002          */
1003         retval = tsi148_alloc_resource(image, size);
1004         if (retval) {
1005                 spin_unlock(&(image->lock));
1006                 printk(KERN_ERR "Unable to allocate memory for resource "
1007                         "name\n");
1008                 retval = -ENOMEM;
1009                 goto err_res;
1010         }
1011
1012         pci_base = (unsigned long long)image->pci_resource.start;
1013
1014
1015         /*
1016          * Bound address is a valid address for the window, adjust
1017          * according to window granularity.
1018          */
1019         pci_bound = pci_base + (size - 0x10000);
1020         vme_offset = vme_base - pci_base;
1021
1022         /* Convert 64-bit variables to 2x 32-bit variables */
1023         reg_split(pci_base, &pci_base_high, &pci_base_low);
1024         reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
1025         reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
1026
1027         if (pci_base_low & 0xFFFF) {
1028                 spin_unlock(&(image->lock));
1029                 printk("Invalid PCI base alignment\n");
1030                 retval = -EINVAL;
1031                 goto err_gran;
1032         }
1033         if (pci_bound_low & 0xFFFF) {
1034                 spin_unlock(&(image->lock));
1035                 printk("Invalid PCI bound alignment\n");
1036                 retval = -EINVAL;
1037                 goto err_gran;
1038         }
1039         if (vme_offset_low & 0xFFFF) {
1040                 spin_unlock(&(image->lock));
1041                 printk("Invalid VME Offset alignment\n");
1042                 retval = -EINVAL;
1043                 goto err_gran;
1044         }
1045
1046         i = image->number;
1047
1048         /* Disable while we are mucking around */
1049         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1050                 TSI148_LCSR_OFFSET_OTAT);
1051         temp_ctl &= ~TSI148_LCSR_OTAT_EN;
1052         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1053                 TSI148_LCSR_OFFSET_OTAT);
1054
1055 /* XXX Prefetch stuff currently unsupported */
1056 #if 0
1057         if (vmeOut->prefetchEnable) {
1058                 temp_ctl |= 0x40000;
1059                 for (x = 0; x < 4; x++) {
1060                         if ((2 << x) >= vmeOut->prefetchSize)
1061                                 break;
1062                 }
1063                 if (x == 4)
1064                         x = 3;
1065                 temp_ctl |= (x << 16);
1066         }
1067 #endif
1068
1069         /* Setup 2eSST speeds */
1070         temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
1071         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1072         case VME_2eSST160:
1073                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1074                 break;
1075         case VME_2eSST267:
1076                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1077                 break;
1078         case VME_2eSST320:
1079                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1080                 break;
1081         }
1082
1083         /* Setup cycle types */
1084         if (cycle & VME_BLT) {
1085                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1086                 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1087         }
1088         if (cycle & VME_MBLT) {
1089                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1090                 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1091         }
1092         if (cycle & VME_2eVME) {
1093                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1094                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1095         }
1096         if (cycle & VME_2eSST) {
1097                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1098                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1099         }
1100         if (cycle & VME_2eSSTB) {
1101                 printk("Currently not setting Broadcast Select Registers\n");
1102                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1103                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1104         }
1105
1106         /* Setup data width */
1107         temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1108         switch (dwidth) {
1109         case VME_D16:
1110                 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1111                 break;
1112         case VME_D32:
1113                 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1114                 break;
1115         default:
1116                 spin_unlock(&(image->lock));
1117                 printk("Invalid data width\n");
1118                 retval = -EINVAL;
1119                 goto err_dwidth;
1120         }
1121
1122         /* Setup address space */
1123         temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1124         switch (aspace) {
1125         case VME_A16:
1126                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1127                 break;
1128         case VME_A24:
1129                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1130                 break;
1131         case VME_A32:
1132                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1133                 break;
1134         case VME_A64:
1135                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1136                 break;
1137         case VME_CRCSR:
1138                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1139                 break;
1140         case VME_USER1:
1141                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1142                 break;
1143         case VME_USER2:
1144                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1145                 break;
1146         case VME_USER3:
1147                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1148                 break;
1149         case VME_USER4:
1150                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1151                 break;
1152         default:
1153                 spin_unlock(&(image->lock));
1154                 printk("Invalid address space\n");
1155                 retval = -EINVAL;
1156                 goto err_aspace;
1157                 break;
1158         }
1159
1160         temp_ctl &= ~(3<<4);
1161         if (cycle & VME_SUPER)
1162                 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1163         if (cycle & VME_PROG)
1164                 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1165
1166         /* Setup mapping */
1167         iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1168                 TSI148_LCSR_OFFSET_OTSAU);
1169         iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1170                 TSI148_LCSR_OFFSET_OTSAL);
1171         iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1172                 TSI148_LCSR_OFFSET_OTEAU);
1173         iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1174                 TSI148_LCSR_OFFSET_OTEAL);
1175         iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1176                 TSI148_LCSR_OFFSET_OTOFU);
1177         iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1178                 TSI148_LCSR_OFFSET_OTOFL);
1179
1180 /* XXX We need to deal with OTBS */
1181 #if 0
1182         iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base +
1183                 TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS);
1184 #endif
1185
1186         /* Write ctl reg without enable */
1187         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1188                 TSI148_LCSR_OFFSET_OTAT);
1189
1190         if (enabled)
1191                 temp_ctl |= TSI148_LCSR_OTAT_EN;
1192
1193         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1194                 TSI148_LCSR_OFFSET_OTAT);
1195
1196         spin_unlock(&(image->lock));
1197         return 0;
1198
1199 err_aspace:
1200 err_dwidth:
1201 err_gran:
1202         tsi148_free_resource(image);
1203 err_res:
1204 err_window:
1205         return retval;
1206
1207 }
1208
1209 /*
1210  * Set the attributes of an outbound window.
1211  *
1212  * XXX Not parsing prefetch information.
1213  */
1214 int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
1215         unsigned long long *vme_base, unsigned long long *size,
1216         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1217 {
1218         unsigned int i, ctl;
1219         unsigned int pci_base_low, pci_base_high;
1220         unsigned int pci_bound_low, pci_bound_high;
1221         unsigned int vme_offset_low, vme_offset_high;
1222
1223         unsigned long long pci_base, pci_bound, vme_offset;
1224
1225         i = image->number;
1226
1227         ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1228                 TSI148_LCSR_OFFSET_OTAT);
1229
1230         pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1231                 TSI148_LCSR_OFFSET_OTSAU);
1232         pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1233                 TSI148_LCSR_OFFSET_OTSAL);
1234         pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1235                 TSI148_LCSR_OFFSET_OTEAU);
1236         pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1237                 TSI148_LCSR_OFFSET_OTEAL);
1238         vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1239                 TSI148_LCSR_OFFSET_OTOFU);
1240         vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1241                 TSI148_LCSR_OFFSET_OTOFL);
1242
1243         /* Convert 64-bit variables to 2x 32-bit variables */
1244         reg_join(pci_base_high, pci_base_low, &pci_base);
1245         reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1246         reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1247
1248         *vme_base = pci_base + vme_offset;
1249         *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1250
1251         *enabled = 0;
1252         *aspace = 0;
1253         *cycle = 0;
1254         *dwidth = 0;
1255
1256         if (ctl & TSI148_LCSR_OTAT_EN)
1257                 *enabled = 1;
1258
1259         /* Setup address space */
1260         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1261                 *aspace |= VME_A16;
1262         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1263                 *aspace |= VME_A24;
1264         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1265                 *aspace |= VME_A32;
1266         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1267                 *aspace |= VME_A64;
1268         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1269                 *aspace |= VME_CRCSR;
1270         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1271                 *aspace |= VME_USER1;
1272         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1273                 *aspace |= VME_USER2;
1274         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1275                 *aspace |= VME_USER3;
1276         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1277                 *aspace |= VME_USER4;
1278
1279         /* Setup 2eSST speeds */
1280         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1281                 *cycle |= VME_2eSST160;
1282         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1283                 *cycle |= VME_2eSST267;
1284         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1285                 *cycle |= VME_2eSST320;
1286
1287         /* Setup cycle types */
1288         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
1289                 *cycle |= VME_SCT;
1290         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
1291                 *cycle |= VME_BLT;
1292         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
1293                 *cycle |= VME_MBLT;
1294         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
1295                 *cycle |= VME_2eVME;
1296         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
1297                 *cycle |= VME_2eSST;
1298         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
1299                 *cycle |= VME_2eSSTB;
1300
1301         if (ctl & TSI148_LCSR_OTAT_SUP)
1302                 *cycle |= VME_SUPER;
1303         else
1304                 *cycle |= VME_USER;
1305
1306         if (ctl & TSI148_LCSR_OTAT_PGM)
1307                 *cycle |= VME_PROG;
1308         else
1309                 *cycle |= VME_DATA;
1310
1311         /* Setup data width */
1312         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1313                 *dwidth = VME_D16;
1314         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1315                 *dwidth = VME_D32;
1316
1317         return 0;
1318 }
1319
1320
1321 int tsi148_master_get( struct vme_master_resource *image, int *enabled,
1322         unsigned long long *vme_base, unsigned long long *size,
1323         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1324 {
1325         int retval;
1326
1327         spin_lock(&(image->lock));
1328
1329         retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1330                 cycle, dwidth);
1331
1332         spin_unlock(&(image->lock));
1333
1334         return retval;
1335 }
1336
1337 ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1338         size_t count, loff_t offset)
1339 {
1340         int retval, enabled;
1341         unsigned long long vme_base, size;
1342         vme_address_t aspace;
1343         vme_cycle_t cycle;
1344         vme_width_t dwidth;
1345         struct vme_bus_error *vme_err = NULL;
1346
1347         spin_lock(&(image->lock));
1348
1349         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1350         retval = count;
1351
1352         if (!err_chk)
1353                 goto skip_chk;
1354
1355         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1356                 &dwidth);
1357
1358         vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1359         if(vme_err != NULL) {
1360                 dev_err(image->parent->parent, "First VME read error detected "
1361                         "an at address 0x%llx\n", vme_err->address);
1362                 retval = vme_err->address - (vme_base + offset);
1363                 /* Clear down save errors in this address range */
1364                 tsi148_clear_errors(aspace, vme_base + offset, count);
1365         }
1366
1367 skip_chk:
1368         spin_unlock(&(image->lock));
1369
1370         return retval;
1371 }
1372
1373
1374 /* XXX We need to change vme_master_resource->mtx to a spinlock so that read
1375  *     and write functions can be used in an interrupt context
1376  */
1377 ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1378         size_t count, loff_t offset)
1379 {
1380         int retval = 0, enabled;
1381         unsigned long long vme_base, size;
1382         vme_address_t aspace;
1383         vme_cycle_t cycle;
1384         vme_width_t dwidth;
1385
1386         struct vme_bus_error *vme_err = NULL;
1387
1388         spin_lock(&(image->lock));
1389
1390         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1391         retval = count;
1392
1393         /*
1394          * Writes are posted. We need to do a read on the VME bus to flush out
1395          * all of the writes before we check for errors. We can't guarentee
1396          * that reading the data we have just written is safe. It is believed
1397          * that there isn't any read, write re-ordering, so we can read any
1398          * location in VME space, so lets read the Device ID from the tsi148's
1399          * own registers as mapped into CR/CSR space.
1400          *
1401          * We check for saved errors in the written address range/space.
1402          */
1403
1404         if (!err_chk)
1405                 goto skip_chk;
1406
1407         /*
1408          * Get window info first, to maximise the time that the buffers may
1409          * fluch on their own
1410          */
1411         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1412                 &dwidth);
1413
1414         ioread16(flush_image->kern_base + 0x7F000);
1415
1416         vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1417         if(vme_err != NULL) {
1418                 printk("First VME write error detected an at address 0x%llx\n",
1419                         vme_err->address);
1420                 retval = vme_err->address - (vme_base + offset);
1421                 /* Clear down save errors in this address range */
1422                 tsi148_clear_errors(aspace, vme_base + offset, count);
1423         }
1424
1425 skip_chk:
1426         spin_unlock(&(image->lock));
1427
1428         return retval;
1429 }
1430
1431 /*
1432  * Perform an RMW cycle on the VME bus.
1433  *
1434  * Requires a previously configured master window, returns final value.
1435  */
1436 unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1437         unsigned int mask, unsigned int compare, unsigned int swap,
1438         loff_t offset)
1439 {
1440         unsigned long long pci_addr;
1441         unsigned int pci_addr_high, pci_addr_low;
1442         u32 tmp, result;
1443         int i;
1444
1445
1446         /* Find the PCI address that maps to the desired VME address */
1447         i = image->number;
1448
1449         /* Locking as we can only do one of these at a time */
1450         mutex_lock(&(vme_rmw));
1451
1452         /* Lock image */
1453         spin_lock(&(image->lock));
1454
1455         pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1456                 TSI148_LCSR_OFFSET_OTSAU);
1457         pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1458                 TSI148_LCSR_OFFSET_OTSAL);
1459
1460         reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1461         reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1462
1463         /* Configure registers */
1464         iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN);
1465         iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC);
1466         iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS);
1467         iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU);
1468         iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL);
1469
1470         /* Enable RMW */
1471         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1472         tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1473         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1474
1475         /* Kick process off with a read to the required address. */
1476         result = ioread32be(image->kern_base + offset);
1477
1478         /* Disable RMW */
1479         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1480         tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1481         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1482
1483         spin_unlock(&(image->lock));
1484
1485         mutex_unlock(&(vme_rmw));
1486
1487         return result;
1488 }
1489
1490 static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace,
1491         vme_cycle_t cycle, vme_width_t dwidth)
1492 {
1493         /* Setup 2eSST speeds */
1494         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1495         case VME_2eSST160:
1496                 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1497                 break;
1498         case VME_2eSST267:
1499                 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1500                 break;
1501         case VME_2eSST320:
1502                 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1503                 break;
1504         }
1505
1506         /* Setup cycle types */
1507         if (cycle & VME_SCT) {
1508                 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1509         }
1510         if (cycle & VME_BLT) {
1511                 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1512         }
1513         if (cycle & VME_MBLT) {
1514                 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1515         }
1516         if (cycle & VME_2eVME) {
1517                 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1518         }
1519         if (cycle & VME_2eSST) {
1520                 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1521         }
1522         if (cycle & VME_2eSSTB) {
1523                 printk("Currently not setting Broadcast Select Registers\n");
1524                 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1525         }
1526
1527         /* Setup data width */
1528         switch (dwidth) {
1529         case VME_D16:
1530                 *attr |= TSI148_LCSR_DSAT_DBW_16;
1531                 break;
1532         case VME_D32:
1533                 *attr |= TSI148_LCSR_DSAT_DBW_32;
1534                 break;
1535         default:
1536                 printk("Invalid data width\n");
1537                 return -EINVAL;
1538         }
1539
1540         /* Setup address space */
1541         switch (aspace) {
1542         case VME_A16:
1543                 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1544                 break;
1545         case VME_A24:
1546                 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1547                 break;
1548         case VME_A32:
1549                 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1550                 break;
1551         case VME_A64:
1552                 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1553                 break;
1554         case VME_CRCSR:
1555                 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1556                 break;
1557         case VME_USER1:
1558                 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1559                 break;
1560         case VME_USER2:
1561                 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1562                 break;
1563         case VME_USER3:
1564                 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1565                 break;
1566         case VME_USER4:
1567                 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1568                 break;
1569         default:
1570                 printk("Invalid address space\n");
1571                 return -EINVAL;
1572                 break;
1573         }
1574
1575         if (cycle & VME_SUPER)
1576                 *attr |= TSI148_LCSR_DSAT_SUP;
1577         if (cycle & VME_PROG)
1578                 *attr |= TSI148_LCSR_DSAT_PGM;
1579
1580         return 0;
1581 }
1582
1583 static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace,
1584         vme_cycle_t cycle, vme_width_t dwidth)
1585 {
1586         /* Setup 2eSST speeds */
1587         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1588         case VME_2eSST160:
1589                 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1590                 break;
1591         case VME_2eSST267:
1592                 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1593                 break;
1594         case VME_2eSST320:
1595                 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1596                 break;
1597         }
1598
1599         /* Setup cycle types */
1600         if (cycle & VME_SCT) {
1601                 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1602         }
1603         if (cycle & VME_BLT) {
1604                 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1605         }
1606         if (cycle & VME_MBLT) {
1607                 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1608         }
1609         if (cycle & VME_2eVME) {
1610                 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1611         }
1612         if (cycle & VME_2eSST) {
1613                 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1614         }
1615         if (cycle & VME_2eSSTB) {
1616                 printk("Currently not setting Broadcast Select Registers\n");
1617                 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1618         }
1619
1620         /* Setup data width */
1621         switch (dwidth) {
1622         case VME_D16:
1623                 *attr |= TSI148_LCSR_DDAT_DBW_16;
1624                 break;
1625         case VME_D32:
1626                 *attr |= TSI148_LCSR_DDAT_DBW_32;
1627                 break;
1628         default:
1629                 printk("Invalid data width\n");
1630                 return -EINVAL;
1631         }
1632
1633         /* Setup address space */
1634         switch (aspace) {
1635         case VME_A16:
1636                 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1637                 break;
1638         case VME_A24:
1639                 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1640                 break;
1641         case VME_A32:
1642                 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1643                 break;
1644         case VME_A64:
1645                 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1646                 break;
1647         case VME_CRCSR:
1648                 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1649                 break;
1650         case VME_USER1:
1651                 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1652                 break;
1653         case VME_USER2:
1654                 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1655                 break;
1656         case VME_USER3:
1657                 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1658                 break;
1659         case VME_USER4:
1660                 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1661                 break;
1662         default:
1663                 printk("Invalid address space\n");
1664                 return -EINVAL;
1665                 break;
1666         }
1667
1668         if (cycle & VME_SUPER)
1669                 *attr |= TSI148_LCSR_DDAT_SUP;
1670         if (cycle & VME_PROG)
1671                 *attr |= TSI148_LCSR_DDAT_PGM;
1672
1673         return 0;
1674 }
1675
1676 /*
1677  * Add a link list descriptor to the list
1678  *
1679  * XXX Need to handle 2eSST Broadcast select bits
1680  */
1681 int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
1682         struct vme_dma_attr *dest, size_t count)
1683 {
1684         struct tsi148_dma_entry *entry, *prev;
1685         u32 address_high, address_low;
1686         struct vme_dma_pattern *pattern_attr;
1687         struct vme_dma_pci *pci_attr;
1688         struct vme_dma_vme *vme_attr;
1689         dma_addr_t desc_ptr;
1690         int retval = 0;
1691
1692         /* XXX descriptor must be aligned on 64-bit boundaries */
1693         entry = (struct tsi148_dma_entry *)kmalloc(
1694                 sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1695         if (entry == NULL) {
1696                 printk("Failed to allocate memory for dma resource "
1697                         "structure\n");
1698                 retval = -ENOMEM;
1699                 goto err_mem;
1700         }
1701
1702         /* Test descriptor alignment */
1703         if ((unsigned long)&(entry->descriptor) & 0x7) {
1704                 printk("Descriptor not aligned to 8 byte boundary as "
1705                         "required: %p\n", &(entry->descriptor));
1706                 retval = -EINVAL;
1707                 goto err_align;
1708         }
1709
1710         /* Given we are going to fill out the structure, we probably don't
1711          * need to zero it, but better safe than sorry for now.
1712          */
1713         memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1714
1715         /* Fill out source part */
1716         switch (src->type) {
1717         case VME_DMA_PATTERN:
1718                 pattern_attr = (struct vme_dma_pattern *)src->private;
1719
1720                 entry->descriptor.dsal = pattern_attr->pattern;
1721                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1722                 /* Default behaviour is 32 bit pattern */
1723                 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
1724                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1725                 }
1726                 /* It seems that the default behaviour is to increment */
1727                 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
1728                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1729                 }
1730                 break;
1731         case VME_DMA_PCI:
1732                 pci_attr = (struct vme_dma_pci *)src->private;
1733
1734                 reg_split((unsigned long long)pci_attr->address, &address_high,
1735                         &address_low);
1736                 entry->descriptor.dsau = address_high;
1737                 entry->descriptor.dsal = address_low;
1738                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1739                 break;
1740         case VME_DMA_VME:
1741                 vme_attr = (struct vme_dma_vme *)src->private;
1742
1743                 reg_split((unsigned long long)vme_attr->address, &address_high,
1744                         &address_low);
1745                 entry->descriptor.dsau = address_high;
1746                 entry->descriptor.dsal = address_low;
1747                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1748
1749                 retval = tsi148_dma_set_vme_src_attributes(
1750                         &(entry->descriptor.dsat), vme_attr->aspace,
1751                         vme_attr->cycle, vme_attr->dwidth);
1752                 if(retval < 0 )
1753                         goto err_source;
1754                 break;
1755         default:
1756                 printk("Invalid source type\n");
1757                 retval = -EINVAL;
1758                 goto err_source;
1759                 break;
1760         }
1761
1762         /* Assume last link - this will be over-written by adding another */
1763         entry->descriptor.dnlau = 0;
1764         entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1765
1766
1767         /* Fill out destination part */
1768         switch (dest->type) {
1769         case VME_DMA_PCI:
1770                 pci_attr = (struct vme_dma_pci *)dest->private;
1771
1772                 reg_split((unsigned long long)pci_attr->address, &address_high,
1773                         &address_low);
1774                 entry->descriptor.ddau = address_high;
1775                 entry->descriptor.ddal = address_low;
1776                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1777                 break;
1778         case VME_DMA_VME:
1779                 vme_attr = (struct vme_dma_vme *)dest->private;
1780
1781                 reg_split((unsigned long long)vme_attr->address, &address_high,
1782                         &address_low);
1783                 entry->descriptor.ddau = address_high;
1784                 entry->descriptor.ddal = address_low;
1785                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1786
1787                 retval = tsi148_dma_set_vme_dest_attributes(
1788                         &(entry->descriptor.ddat), vme_attr->aspace,
1789                         vme_attr->cycle, vme_attr->dwidth);
1790                 if(retval < 0 )
1791                         goto err_dest;
1792                 break;
1793         default:
1794                 printk("Invalid destination type\n");
1795                 retval = -EINVAL;
1796                 goto err_dest;
1797                 break;
1798         }
1799
1800         /* Fill out count */
1801         entry->descriptor.dcnt = (u32)count;
1802
1803         /* Add to list */
1804         list_add_tail(&(entry->list), &(list->entries));
1805
1806         /* Fill out previous descriptors "Next Address" */
1807         if(entry->list.prev != &(list->entries)){
1808                 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1809                         list);
1810                 /* We need the bus address for the pointer */
1811                 desc_ptr = virt_to_bus(&(entry->descriptor));
1812                 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1813                         &(prev->descriptor.dnlal));
1814         }
1815
1816         return 0;
1817
1818 err_dest:
1819 err_source:
1820 err_align:
1821                 kfree(entry);
1822 err_mem:
1823         return retval;
1824 }
1825
1826 /*
1827  * Check to see if the provided DMA channel is busy.
1828  */
1829 static int tsi148_dma_busy(int channel)
1830 {
1831         u32 tmp;
1832
1833         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1834                 TSI148_LCSR_OFFSET_DSTA);
1835
1836         if (tmp & TSI148_LCSR_DSTA_BSY)
1837                 return 0;
1838         else
1839                 return 1;
1840
1841 }
1842
1843 /*
1844  * Execute a previously generated link list
1845  *
1846  * XXX Need to provide control register configuration.
1847  */
1848 int tsi148_dma_list_exec(struct vme_dma_list *list)
1849 {
1850         struct vme_dma_resource *ctrlr;
1851         int channel, retval = 0;
1852         struct tsi148_dma_entry *entry;
1853         dma_addr_t bus_addr;
1854         u32 bus_addr_high, bus_addr_low;
1855         u32 val, dctlreg = 0;
1856 #if 0
1857         int x;
1858 #endif
1859
1860         ctrlr = list->parent;
1861
1862         mutex_lock(&(ctrlr->mtx));
1863
1864         channel = ctrlr->number;
1865
1866         if (! list_empty(&(ctrlr->running))) {
1867                 /*
1868                  * XXX We have an active DMA transfer and currently haven't
1869                  *     sorted out the mechanism for "pending" DMA transfers.
1870                  *     Return busy.
1871                  */
1872                 /* Need to add to pending here */
1873                 mutex_unlock(&(ctrlr->mtx));
1874                 return -EBUSY;
1875         } else {
1876                 list_add(&(list->list), &(ctrlr->running));
1877         }
1878 #if 0
1879         /* XXX Still todo */
1880         for (x = 0; x < 8; x++) {       /* vme block size */
1881                 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
1882                         break;
1883                 }
1884         }
1885         if (x == 8)
1886                 x = 7;
1887         dctlreg |= (x << 12);
1888
1889         for (x = 0; x < 8; x++) {       /* pci block size */
1890                 if ((32 << x) >= vmeDma->maxPciBlockSize) {
1891                         break;
1892                 }
1893         }
1894         if (x == 8)
1895                 x = 7;
1896         dctlreg |= (x << 4);
1897
1898         if (vmeDma->vmeBackOffTimer) {
1899                 for (x = 1; x < 8; x++) {       /* vme timer */
1900                         if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
1901                                 break;
1902                         }
1903                 }
1904                 if (x == 8)
1905                         x = 7;
1906                 dctlreg |= (x << 8);
1907         }
1908
1909         if (vmeDma->pciBackOffTimer) {
1910                 for (x = 1; x < 8; x++) {       /* pci timer */
1911                         if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
1912                                 break;
1913                         }
1914                 }
1915                 if (x == 8)
1916                         x = 7;
1917                 dctlreg |= (x << 0);
1918         }
1919 #endif
1920
1921         /* Get first bus address and write into registers */
1922         entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1923                 list);
1924
1925         bus_addr = virt_to_bus(&(entry->descriptor));
1926
1927         mutex_unlock(&(ctrlr->mtx));
1928
1929         reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1930
1931         iowrite32be(bus_addr_high, tsi148_bridge->base +
1932                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1933         iowrite32be(bus_addr_low, tsi148_bridge->base +
1934                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1935
1936         /* Start the operation */
1937         iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base +
1938                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1939
1940         wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel));
1941         /*
1942          * Read status register, this register is valid until we kick off a
1943          * new transfer.
1944          */
1945         val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1946                 TSI148_LCSR_OFFSET_DSTA);
1947
1948         if (val & TSI148_LCSR_DSTA_VBE) {
1949                 printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val);
1950                 retval = -EIO;
1951         }
1952
1953         /* Remove list from running list */
1954         mutex_lock(&(ctrlr->mtx));
1955         list_del(&(list->list));
1956         mutex_unlock(&(ctrlr->mtx));
1957
1958         return retval;
1959 }
1960
1961 /*
1962  * Clean up a previously generated link list
1963  *
1964  * We have a separate function, don't assume that the chain can't be reused.
1965  */
1966 int tsi148_dma_list_empty(struct vme_dma_list *list)
1967 {
1968         struct list_head *pos, *temp;
1969         struct tsi148_dma_entry *entry;
1970
1971         /* detach and free each entry */
1972         list_for_each_safe(pos, temp, &(list->entries)) {
1973                 list_del(pos);
1974                 entry = list_entry(pos, struct tsi148_dma_entry, list);
1975                 kfree(entry);
1976         }
1977
1978         return (0);
1979 }
1980
1981 /*
1982  * All 4 location monitors reside at the same base - this is therefore a
1983  * system wide configuration.
1984  *
1985  * This does not enable the LM monitor - that should be done when the first
1986  * callback is attached and disabled when the last callback is removed.
1987  */
1988 int tsi148_lm_set(unsigned long long lm_base, vme_address_t aspace,
1989         vme_cycle_t cycle)
1990 {
1991         u32 lm_base_high, lm_base_low, lm_ctl = 0;
1992         int i;
1993
1994         mutex_lock(&(vme_lm));
1995
1996         /* If we already have a callback attached, we can't move it! */
1997         for (i = 0; i < 4; i++) {
1998                 if(lm_callback[i] != NULL) {
1999                         mutex_unlock(&(vme_lm));
2000                         printk("Location monitor callback attached, can't "
2001                                 "reset\n");
2002                         return -EBUSY;
2003                 }
2004         }
2005
2006         switch (aspace) {
2007         case VME_A16:
2008                 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
2009                 break;
2010         case VME_A24:
2011                 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
2012                 break;
2013         case VME_A32:
2014                 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
2015                 break;
2016         case VME_A64:
2017                 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
2018                 break;
2019         default:
2020                 mutex_unlock(&(vme_lm));
2021                 printk("Invalid address space\n");
2022                 return -EINVAL;
2023                 break;
2024         }
2025
2026         if (cycle & VME_SUPER)
2027                 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
2028         if (cycle & VME_USER)
2029                 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
2030         if (cycle & VME_PROG)
2031                 lm_ctl |= TSI148_LCSR_LMAT_PGM;
2032         if (cycle & VME_DATA)
2033                 lm_ctl |= TSI148_LCSR_LMAT_DATA;
2034
2035         reg_split(lm_base, &lm_base_high, &lm_base_low);
2036
2037         iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU);
2038         iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL);
2039         iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2040
2041         mutex_unlock(&(vme_lm));
2042
2043         return 0;
2044 }
2045
2046 /* Get configuration of the callback monitor and return whether it is enabled
2047  * or disabled.
2048  */
2049 int tsi148_lm_get(unsigned long long *lm_base, vme_address_t *aspace,
2050         vme_cycle_t *cycle)
2051 {
2052         u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2053
2054         mutex_lock(&(vme_lm));
2055
2056         lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU);
2057         lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL);
2058         lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2059
2060         reg_join(lm_base_high, lm_base_low, lm_base);
2061
2062         if (lm_ctl & TSI148_LCSR_LMAT_EN)
2063                 enabled = 1;
2064
2065         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
2066                 *aspace |= VME_A16;
2067         }
2068         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
2069                 *aspace |= VME_A24;
2070         }
2071         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
2072                 *aspace |= VME_A32;
2073         }
2074         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
2075                 *aspace |= VME_A64;
2076         }
2077
2078         if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2079                 *cycle |= VME_SUPER;
2080         if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2081                 *cycle |= VME_USER;
2082         if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2083                 *cycle |= VME_PROG;
2084         if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2085                 *cycle |= VME_DATA;
2086
2087         mutex_unlock(&(vme_lm));
2088
2089         return enabled;
2090 }
2091
2092 /*
2093  * Attach a callback to a specific location monitor.
2094  *
2095  * Callback will be passed the monitor triggered.
2096  */
2097 int tsi148_lm_attach(int monitor, void (*callback)(int))
2098 {
2099         u32 lm_ctl, tmp;
2100
2101         mutex_lock(&(vme_lm));
2102
2103         /* Ensure that the location monitor is configured - need PGM or DATA */
2104         lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2105         if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2106                 mutex_unlock(&(vme_lm));
2107                 printk("Location monitor not properly configured\n");
2108                 return -EINVAL;
2109         }
2110
2111         /* Check that a callback isn't already attached */
2112         if (lm_callback[monitor] != NULL) {
2113                 mutex_unlock(&(vme_lm));
2114                 printk("Existing callback attached\n");
2115                 return -EBUSY;
2116         }
2117
2118         /* Attach callback */
2119         lm_callback[monitor] = callback;
2120
2121         /* Enable Location Monitor interrupt */
2122         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2123         tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2124         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
2125
2126         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2127         tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2128         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2129
2130         /* Ensure that global Location Monitor Enable set */
2131         if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2132                 lm_ctl |= TSI148_LCSR_LMAT_EN;
2133                 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2134         }
2135
2136         mutex_unlock(&(vme_lm));
2137
2138         return 0;
2139 }
2140
2141 /*
2142  * Detach a callback function forn a specific location monitor.
2143  */
2144 int tsi148_lm_detach(int monitor)
2145 {
2146         u32 lm_en, tmp;
2147
2148         mutex_lock(&(vme_lm));
2149
2150         /* Disable Location Monitor and ensure previous interrupts are clear */
2151         lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2152         lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2153         iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN);
2154
2155         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2156         tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2157         iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2158
2159         iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2160                  tsi148_bridge->base + TSI148_LCSR_INTEO);
2161
2162         /* Detach callback */
2163         lm_callback[monitor] = NULL;
2164
2165         /* If all location monitors disabled, disable global Location Monitor */
2166         if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2167                         TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2168                 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2169                 tmp &= ~TSI148_LCSR_LMAT_EN;
2170                 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT);
2171         }
2172
2173         mutex_unlock(&(vme_lm));
2174
2175         return 0;
2176 }
2177
2178 /*
2179  * Determine Geographical Addressing
2180  */
2181 int tsi148_slot_get(void)
2182 {
2183         u32 slot = 0;
2184
2185         slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2186         slot = slot & TSI148_LCSR_VSTAT_GA_M;
2187         return (int)slot;
2188 }
2189
2190 static int __init tsi148_init(void)
2191 {
2192         return pci_register_driver(&tsi148_driver);
2193 }
2194
2195 /*
2196  * Configure CR/CSR space
2197  *
2198  * Access to the CR/CSR can be configured at power-up. The location of the
2199  * CR/CSR registers in the CR/CSR address space is determined by the boards
2200  * Auto-ID or Geographic address. This function ensures that the window is
2201  * enabled at an offset consistent with the boards geopgraphic address.
2202  *
2203  * Each board has a 512kB window, with the highest 4kB being used for the
2204  * boards registers, this means there is a fix length 508kB window which must
2205  * be mapped onto PCI memory.
2206  */
2207 static int tsi148_crcsr_init(struct pci_dev *pdev)
2208 {
2209         u32 cbar, crat, vstat;
2210         u32 crcsr_bus_high, crcsr_bus_low;
2211         int retval;
2212
2213         /* Allocate mem for CR/CSR image */
2214         crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2215                 &crcsr_bus);
2216         if (crcsr_kernel == NULL) {
2217                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
2218                         "image\n");
2219                 return -ENOMEM;
2220         }
2221
2222         memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2223
2224         reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2225
2226         iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU);
2227         iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL);
2228
2229         /* Ensure that the CR/CSR is configured at the correct offset */
2230         cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR);
2231         cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2232
2233         vstat = tsi148_slot_get();
2234
2235         if (cbar != vstat) {
2236                 dev_info(&pdev->dev, "Setting CR/CSR offset\n");
2237                 iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR);
2238         }
2239         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar);
2240
2241         crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2242         if (crat & TSI148_LCSR_CRAT_EN) {
2243                 dev_info(&pdev->dev, "Enabling CR/CSR space\n");
2244                 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2245                         tsi148_bridge->base + TSI148_LCSR_CRAT);
2246         } else
2247                 dev_info(&pdev->dev, "CR/CSR already enabled\n");
2248
2249         /* If we want flushed, error-checked writes, set up a window
2250          * over the CR/CSR registers. We read from here to safely flush
2251          * through VME writes.
2252          */
2253         if(err_chk) {
2254                 retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000),
2255                         0x80000, VME_CRCSR, VME_SCT, VME_D16);
2256                 if (retval)
2257                         dev_err(&pdev->dev, "Configuring flush image failed\n");
2258         }
2259
2260         return 0;
2261
2262 }
2263
2264 static void tsi148_crcsr_exit(struct pci_dev *pdev)
2265 {
2266         u32 crat;
2267
2268         /* Turn off CR/CSR space */
2269         crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2270         iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2271                 tsi148_bridge->base + TSI148_LCSR_CRAT);
2272
2273         /* Free image */
2274         iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU);
2275         iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL);
2276
2277         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus);
2278 }
2279
2280 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2281 {
2282         int retval, i, master_num;
2283         u32 data;
2284         struct list_head *pos = NULL;
2285         struct vme_master_resource *master_image;
2286         struct vme_slave_resource *slave_image;
2287         struct vme_dma_resource *dma_ctrlr;
2288
2289         /* If we want to support more than one of each bridge, we need to
2290          * dynamically generate this so we get one per device
2291          */
2292         tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
2293                 GFP_KERNEL);
2294         if (tsi148_bridge == NULL) {
2295                 dev_err(&pdev->dev, "Failed to allocate memory for device "
2296                         "structure\n");
2297                 retval = -ENOMEM;
2298                 goto err_struct;
2299         }
2300
2301         memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2302
2303         /* Enable the device */
2304         retval = pci_enable_device(pdev);
2305         if (retval) {
2306                 dev_err(&pdev->dev, "Unable to enable device\n");
2307                 goto err_enable;
2308         }
2309
2310         /* Map Registers */
2311         retval = pci_request_regions(pdev, driver_name);
2312         if (retval) {
2313                 dev_err(&pdev->dev, "Unable to reserve resources\n");
2314                 goto err_resource;
2315         }
2316
2317         /* map registers in BAR 0 */
2318         tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096);
2319         if (!tsi148_bridge->base) {
2320                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2321                 retval = -EIO;
2322                 goto err_remap;
2323         }
2324
2325         /* Check to see if the mapping worked out */
2326         data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF;
2327         if (data != PCI_VENDOR_ID_TUNDRA) {
2328                 dev_err(&pdev->dev, "CRG region check failed\n");
2329                 retval = -EIO;
2330                 goto err_test;
2331         }
2332
2333         /* Initialize wait queues & mutual exclusion flags */
2334         /* XXX These need to be moved to the vme_bridge structure */
2335         init_waitqueue_head(&dma_queue[0]);
2336         init_waitqueue_head(&dma_queue[1]);
2337         init_waitqueue_head(&iack_queue);
2338         mutex_init(&(vme_int));
2339         mutex_init(&(vme_irq));
2340         mutex_init(&(vme_rmw));
2341         mutex_init(&(vme_lm));
2342
2343         tsi148_bridge->parent = &(pdev->dev);
2344         strcpy(tsi148_bridge->name, driver_name);
2345
2346         /* Setup IRQ */
2347         retval = tsi148_irq_init(tsi148_bridge);
2348         if (retval != 0) {
2349                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2350                 goto err_irq;
2351         }
2352
2353         /* If we are going to flush writes, we need to read from the VME bus.
2354          * We need to do this safely, thus we read the devices own CR/CSR
2355          * register. To do this we must set up a window in CR/CSR space and
2356          * hence have one less master window resource available.
2357          */
2358         master_num = TSI148_MAX_MASTER;
2359         if(err_chk){
2360                 master_num--;
2361                 /* XXX */
2362                 flush_image = (struct vme_master_resource *)kmalloc(
2363                         sizeof(struct vme_master_resource), GFP_KERNEL);
2364                 if (flush_image == NULL) {
2365                         dev_err(&pdev->dev, "Failed to allocate memory for "
2366                         "flush resource structure\n");
2367                         retval = -ENOMEM;
2368                         goto err_master;
2369                 }
2370                 flush_image->parent = tsi148_bridge;
2371                 spin_lock_init(&(flush_image->lock));
2372                 flush_image->locked = 1;
2373                 flush_image->number = master_num;
2374                 flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2375                         VME_A64;
2376                 flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2377                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2378                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2379                         VME_PROG | VME_DATA;
2380                 flush_image->width_attr = VME_D16 | VME_D32;
2381                 memset(&(flush_image->pci_resource), 0,
2382                         sizeof(struct resource));
2383                 flush_image->kern_base  = NULL;
2384         }
2385
2386         /* Add master windows to list */
2387         INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2388         for (i = 0; i < master_num; i++) {
2389                 master_image = (struct vme_master_resource *)kmalloc(
2390                         sizeof(struct vme_master_resource), GFP_KERNEL);
2391                 if (master_image == NULL) {
2392                         dev_err(&pdev->dev, "Failed to allocate memory for "
2393                         "master resource structure\n");
2394                         retval = -ENOMEM;
2395                         goto err_master;
2396                 }
2397                 master_image->parent = tsi148_bridge;
2398                 spin_lock_init(&(master_image->lock));
2399                 master_image->locked = 0;
2400                 master_image->number = i;
2401                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2402                         VME_A64;
2403                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2404                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2405                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2406                         VME_PROG | VME_DATA;
2407                 master_image->width_attr = VME_D16 | VME_D32;
2408                 memset(&(master_image->pci_resource), 0,
2409                         sizeof(struct resource));
2410                 master_image->kern_base  = NULL;
2411                 list_add_tail(&(master_image->list),
2412                         &(tsi148_bridge->master_resources));
2413         }
2414
2415         /* Add slave windows to list */
2416         INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2417         for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2418                 slave_image = (struct vme_slave_resource *)kmalloc(
2419                         sizeof(struct vme_slave_resource), GFP_KERNEL);
2420                 if (slave_image == NULL) {
2421                         dev_err(&pdev->dev, "Failed to allocate memory for "
2422                         "slave resource structure\n");
2423                         retval = -ENOMEM;
2424                         goto err_slave;
2425                 }
2426                 slave_image->parent = tsi148_bridge;
2427                 mutex_init(&(slave_image->mtx));
2428                 slave_image->locked = 0;
2429                 slave_image->number = i;
2430                 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2431                         VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2432                         VME_USER3 | VME_USER4;
2433                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2434                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2435                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2436                         VME_PROG | VME_DATA;
2437                 list_add_tail(&(slave_image->list),
2438                         &(tsi148_bridge->slave_resources));
2439         }
2440
2441         /* Add dma engines to list */
2442         INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2443         for (i = 0; i < TSI148_MAX_DMA; i++) {
2444                 dma_ctrlr = (struct vme_dma_resource *)kmalloc(
2445                         sizeof(struct vme_dma_resource), GFP_KERNEL);
2446                 if (dma_ctrlr == NULL) {
2447                         dev_err(&pdev->dev, "Failed to allocate memory for "
2448                         "dma resource structure\n");
2449                         retval = -ENOMEM;
2450                         goto err_dma;
2451                 }
2452                 dma_ctrlr->parent = tsi148_bridge;
2453                 mutex_init(&(dma_ctrlr->mtx));
2454                 dma_ctrlr->locked = 0;
2455                 dma_ctrlr->number = i;
2456                 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2457                 INIT_LIST_HEAD(&(dma_ctrlr->running));
2458                 list_add_tail(&(dma_ctrlr->list),
2459                         &(tsi148_bridge->dma_resources));
2460         }
2461
2462         tsi148_bridge->slave_get = tsi148_slave_get;
2463         tsi148_bridge->slave_set = tsi148_slave_set;
2464         tsi148_bridge->master_get = tsi148_master_get;
2465         tsi148_bridge->master_set = tsi148_master_set;
2466         tsi148_bridge->master_read = tsi148_master_read;
2467         tsi148_bridge->master_write = tsi148_master_write;
2468         tsi148_bridge->master_rmw = tsi148_master_rmw;
2469         tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2470         tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2471         tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2472         tsi148_bridge->request_irq = tsi148_request_irq;
2473         tsi148_bridge->free_irq = tsi148_free_irq;
2474         tsi148_bridge->generate_irq = tsi148_generate_irq;
2475         tsi148_bridge->lm_set = tsi148_lm_set;
2476         tsi148_bridge->lm_get = tsi148_lm_get;
2477         tsi148_bridge->lm_attach = tsi148_lm_attach;
2478         tsi148_bridge->lm_detach = tsi148_lm_detach;
2479         tsi148_bridge->slot_get = tsi148_slot_get;
2480
2481         data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2482         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2483                 (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
2484         dev_info(&pdev->dev, "VME geographical address is %d\n",
2485                 data & TSI148_LCSR_VSTAT_GA_M);
2486         dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2487                 err_chk ? "enabled" : "disabled");
2488
2489         if(tsi148_crcsr_init(pdev)) {
2490                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2491                 goto err_crcsr;
2492
2493         }
2494
2495         /* Need to save tsi148_bridge pointer locally in link list for use in
2496          * tsi148_remove()
2497          */
2498         retval = vme_register_bridge(tsi148_bridge);
2499         if (retval != 0) {
2500                 dev_err(&pdev->dev, "Chip Registration failed.\n");
2501                 goto err_reg;
2502         }
2503
2504         /* Clear VME bus "board fail", and "power-up reset" lines */
2505         data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2506         data &= ~TSI148_LCSR_VSTAT_BRDFL;
2507         data |= TSI148_LCSR_VSTAT_CPURST;
2508         iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT);
2509
2510         return 0;
2511
2512         vme_unregister_bridge(tsi148_bridge);
2513 err_reg:
2514         tsi148_crcsr_exit(pdev);
2515 err_crcsr:
2516 err_dma:
2517         /* resources are stored in link list */
2518         list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2519                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2520                 list_del(pos);
2521                 kfree(dma_ctrlr);
2522         }
2523 err_slave:
2524         /* resources are stored in link list */
2525         list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2526                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2527                 list_del(pos);
2528                 kfree(slave_image);
2529         }
2530 err_master:
2531         /* resources are stored in link list */
2532         list_for_each(pos, &(tsi148_bridge->master_resources)) {
2533                 master_image = list_entry(pos, struct vme_master_resource,                              list);
2534                 list_del(pos);
2535                 kfree(master_image);
2536         }
2537
2538         tsi148_irq_exit(pdev);
2539 err_irq:
2540 err_test:
2541         iounmap(tsi148_bridge->base);
2542 err_remap:
2543         pci_release_regions(pdev);
2544 err_resource:
2545         pci_disable_device(pdev);
2546 err_enable:
2547         kfree(tsi148_bridge);
2548 err_struct:
2549         return retval;
2550
2551 }
2552
2553 static void tsi148_remove(struct pci_dev *pdev)
2554 {
2555         struct list_head *pos = NULL;
2556         struct vme_master_resource *master_image;
2557         struct vme_slave_resource *slave_image;
2558         struct vme_dma_resource *dma_ctrlr;
2559         int i;
2560
2561         dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2562
2563         /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */
2564
2565         /*
2566          *  Shutdown all inbound and outbound windows.
2567          */
2568         for (i = 0; i < 8; i++) {
2569                 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] +
2570                         TSI148_LCSR_OFFSET_ITAT);
2571                 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] +
2572                         TSI148_LCSR_OFFSET_OTAT);
2573         }
2574
2575         /*
2576          *  Shutdown Location monitor.
2577          */
2578         iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT);
2579
2580         /*
2581          *  Shutdown CRG map.
2582          */
2583         iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT);
2584
2585         /*
2586          *  Clear error status.
2587          */
2588         iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT);
2589         iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT);
2590         iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT);
2591
2592         /*
2593          *  Remove VIRQ interrupt (if any)
2594          */
2595         if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) {
2596                 iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR);
2597         }
2598
2599         /*
2600          *  Disable and clear all interrupts.
2601          */
2602         iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
2603         iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
2604         iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTEN);
2605
2606         /*
2607          *  Map all Interrupts to PCI INTA
2608          */
2609         iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1);
2610         iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2);
2611
2612         tsi148_irq_exit(pdev);
2613
2614         vme_unregister_bridge(tsi148_bridge);
2615
2616         tsi148_crcsr_exit(pdev);
2617
2618         /* resources are stored in link list */
2619         list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2620                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2621                 list_del(pos);
2622                 kfree(dma_ctrlr);
2623         }
2624
2625         /* resources are stored in link list */
2626         list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2627                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2628                 list_del(pos);
2629                 kfree(slave_image);
2630         }
2631
2632         /* resources are stored in link list */
2633         list_for_each(pos, &(tsi148_bridge->master_resources)) {
2634                 master_image = list_entry(pos, struct vme_master_resource,                              list);
2635                 list_del(pos);
2636                 kfree(master_image);
2637         }
2638
2639         tsi148_irq_exit(pdev);
2640
2641         iounmap(tsi148_bridge->base);
2642
2643         pci_release_regions(pdev);
2644
2645         pci_disable_device(pdev);
2646
2647         kfree(tsi148_bridge);
2648 }
2649
2650 static void __exit tsi148_exit(void)
2651 {
2652         pci_unregister_driver(&tsi148_driver);
2653
2654         printk(KERN_DEBUG "Driver removed.\n");
2655 }
2656
2657 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2658 module_param(err_chk, bool, 0);
2659
2660 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2661 MODULE_LICENSE("GPL");
2662
2663 module_init(tsi148_init);
2664 module_exit(tsi148_exit);
2665
2666 /*----------------------------------------------------------------------------
2667  * STAGING
2668  *--------------------------------------------------------------------------*/
2669
2670 #if 0
2671 /*
2672  * Direct Mode DMA transfer
2673  *
2674  * XXX Not looking at direct mode for now, we can always use link list mode
2675  *     with a single entry.
2676  */
2677 int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src,
2678         struct vme_dma_attr dest, size_t count)
2679 {
2680         u32 dctlreg = 0;
2681         unsigned int tmp;
2682         int val;
2683         int channel, x;
2684         struct vmeDmaPacket *cur_dma;
2685         struct tsi148_dma_descriptor *dmaLL;
2686
2687         /* direct mode */
2688         dctlreg = 0x800000;
2689
2690         for (x = 0; x < 8; x++) {       /* vme block size */
2691                 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
2692                         break;
2693                 }
2694         }
2695         if (x == 8)
2696                 x = 7;
2697         dctlreg |= (x << 12);
2698
2699         for (x = 0; x < 8; x++) {       /* pci block size */
2700                 if ((32 << x) >= vmeDma->maxPciBlockSize) {
2701                         break;
2702                 }
2703         }
2704         if (x == 8)
2705                 x = 7;
2706         dctlreg |= (x << 4);
2707
2708         if (vmeDma->vmeBackOffTimer) {
2709                 for (x = 1; x < 8; x++) {       /* vme timer */
2710                         if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
2711                                 break;
2712                         }
2713                 }
2714                 if (x == 8)
2715                         x = 7;
2716                 dctlreg |= (x << 8);
2717         }
2718
2719         if (vmeDma->pciBackOffTimer) {
2720                 for (x = 1; x < 8; x++) {       /* pci timer */
2721                         if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
2722                                 break;
2723                         }
2724                 }
2725                 if (x == 8)
2726                         x = 7;
2727                 dctlreg |= (x << 0);
2728         }
2729
2730         /* Program registers for DMA transfer */
2731         iowrite32be(dmaLL->dsau, tsi148_bridge->base +
2732                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU);
2733         iowrite32be(dmaLL->dsal, tsi148_bridge->base +
2734                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL);
2735         iowrite32be(dmaLL->ddau, tsi148_bridge->base +
2736                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU);
2737         iowrite32be(dmaLL->ddal, tsi148_bridge->base +
2738                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL);
2739         iowrite32be(dmaLL->dsat, tsi148_bridge->base +
2740                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT);
2741         iowrite32be(dmaLL->ddat, tsi148_bridge->base +
2742                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT);
2743         iowrite32be(dmaLL->dcnt, tsi148_bridge->base +
2744                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT);
2745         iowrite32be(dmaLL->ddbs, tsi148_bridge->base +
2746                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS);
2747
2748         /* Start the operation */
2749         iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base +
2750                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
2751
2752         tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2753                 TSI148_LCSR_OFFSET_DSTA);
2754         wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0);
2755
2756         /*
2757          * Read status register, we should probably do this in some error
2758          * handler rather than here so that we can be sure we haven't kicked off
2759          * another DMA transfer.
2760          */
2761         val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2762                 TSI148_LCSR_OFFSET_DSTA);
2763
2764         vmeDma->vmeDmaStatus = 0;
2765         if (val & 0x10000000) {
2766                 printk(KERN_ERR
2767                         "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n",
2768                         val);
2769                 vmeDma->vmeDmaStatus = val;
2770
2771         }
2772         return (0);
2773 }
2774 #endif
2775
2776 #if 0
2777
2778 /* Global VME controller information */
2779 struct pci_dev *vme_pci_dev;
2780
2781 /*
2782  * Set the VME bus arbiter with the requested attributes
2783  */
2784 int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb)
2785 {
2786         int temp_ctl = 0;
2787         int gto = 0;
2788
2789         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2790         temp_ctl &= 0xFFEFFF00;
2791
2792         if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
2793                 gto = 8;
2794         } else if (vmeArb->globalTimeoutTimer > 2048) {
2795                 return (-EINVAL);
2796         } else if (vmeArb->globalTimeoutTimer == 0) {
2797                 gto = 0;
2798         } else {
2799                 gto = 1;
2800                 while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) {
2801                         gto += 1;
2802                 }
2803         }
2804         temp_ctl |= gto;
2805
2806         if (vmeArb->arbiterMode != VME_PRIORITY_MODE) {
2807                 temp_ctl |= 1 << 6;
2808         }
2809
2810         if (vmeArb->arbiterTimeoutFlag) {
2811                 temp_ctl |= 1 << 7;
2812         }
2813
2814         if (vmeArb->noEarlyReleaseFlag) {
2815                 temp_ctl |= 1 << 20;
2816         }
2817         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL);
2818
2819         return (0);
2820 }
2821
2822 /*
2823  * Return the attributes of the VME bus arbiter.
2824  */
2825 int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb)
2826 {
2827         int temp_ctl = 0;
2828         int gto = 0;
2829
2830
2831         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2832
2833         gto = temp_ctl & 0xF;
2834         if (gto != 0) {
2835                 vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1)));
2836         }
2837
2838         if (temp_ctl & (1 << 6)) {
2839                 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
2840         } else {
2841                 vmeArb->arbiterMode = VME_PRIORITY_MODE;
2842         }
2843
2844         if (temp_ctl & (1 << 7)) {
2845                 vmeArb->arbiterTimeoutFlag = 1;
2846         }
2847
2848         if (temp_ctl & (1 << 20)) {
2849                 vmeArb->noEarlyReleaseFlag = 1;
2850         }
2851
2852         return (0);
2853 }
2854
2855 /*
2856  * Set the VME bus requestor with the requested attributes
2857  */
2858 int tempe_set_requestor(vmeRequesterCfg_t * vmeReq)
2859 {
2860         int temp_ctl = 0;
2861
2862         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2863         temp_ctl &= 0xFFFF0000;
2864
2865         if (vmeReq->releaseMode == 1) {
2866                 temp_ctl |= (1 << 3);
2867         }
2868
2869         if (vmeReq->fairMode == 1) {
2870                 temp_ctl |= (1 << 2);
2871         }
2872
2873         temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8;
2874         temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12;
2875         temp_ctl |= vmeReq->requestLevel;
2876
2877         iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2878         return (0);
2879 }
2880
2881 /*
2882  * Return the attributes of the VME bus requestor
2883  */
2884 int tempe_get_requestor(vmeRequesterCfg_t * vmeReq)
2885 {
2886         int temp_ctl = 0;
2887
2888         temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2889
2890         if (temp_ctl & 0x18) {
2891                 vmeReq->releaseMode = 1;
2892         }
2893
2894         if (temp_ctl & (1 << 2)) {
2895                 vmeReq->fairMode = 1;
2896         }
2897
2898         vmeReq->requestLevel = temp_ctl & 3;
2899         vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7;
2900         vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7;
2901
2902         return (0);
2903 }
2904
2905
2906 #endif