SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/vme/bridges/vme_tsi148.c

   1 /*
   2  * Support for the Tundra TSI148 VME-PCI Bridge Chip
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/mm.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/pci.h>
  23 #include <linux/poll.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <asm/time.h>
  29 #include <asm/io.h>
  30 #include <asm/uaccess.h>
  31
  32 #include "../vme.h"
  33 #include "../vme_bridge.h"
  34 #include "vme_tsi148.h"
  35
  36 static int __init tsi148_init(void);
  37 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  38 static void tsi148_remove(struct pci_dev *);
  39 static void __exit tsi148_exit(void);
  40
  41
  42 int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
  43         unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
  44 int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
  45         unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
  46
  47 int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
  48         unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
  49 int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
  50         unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
  51 ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
  52         loff_t);
  53 ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
  54         loff_t);
  55 unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
  56         unsigned int, unsigned int, loff_t);
  57 int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
  58         struct vme_dma_attr *, size_t);
  59 int tsi148_dma_list_exec(struct vme_dma_list *);
  60 int tsi148_dma_list_empty(struct vme_dma_list *);
  61 int tsi148_generate_irq(int, int);
  62
  63 /* Module parameter */
  64 static int err_chk;
  65 static int geoid;
  66
  67 static char driver_name[] = "vme_tsi148";
  68
  69 static const struct pci_device_id tsi148_ids[] = {
  70         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  71         { },
  72 };
  73
  74 static struct pci_driver tsi148_driver = {
  75         .name = driver_name,
  76         .id_table = tsi148_ids,
  77         .probe = tsi148_probe,
  78         .remove = tsi148_remove,
  79 };
  80
  81 static void reg_join(unsigned int high, unsigned int low,
  82         unsigned long long *variable)
  83 {
  84         *variable = (unsigned long long)high << 32;
  85         *variable |= (unsigned long long)low;
  86 }
  87
  88 static void reg_split(unsigned long long variable, unsigned int *high,
  89         unsigned int *low)
  90 {
  91         *low = (unsigned int)variable & 0xFFFFFFFF;
  92         *high = (unsigned int)(variable >> 32);
  93 }
  94
  95 /*
  96  * Wakes up DMA queue.
  97  */
  98 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
  99         int channel_mask)
 100 {
 101         u32 serviced = 0;
 102
 103         if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
 104                 wake_up(&(bridge->dma_queue[0]));
 105                 serviced |= TSI148_LCSR_INTC_DMA0C;
 106         }
 107         if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
 108                 wake_up(&(bridge->dma_queue[1]));
 109                 serviced |= TSI148_LCSR_INTC_DMA1C;
 110         }
 111
 112         return serviced;
 113 }
 114
 115 /*
 116  * Wake up location monitor queue
 117  */
 118 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
 119 {
 120         int i;
 121         u32 serviced = 0;
 122
 123         for (i = 0; i < 4; i++) {
 124                 if(stat & TSI148_LCSR_INTS_LMS[i]) {
 125                         /* We only enable interrupts if the callback is set */
 126                         bridge->lm_callback[i](i);
 127                         serviced |= TSI148_LCSR_INTC_LMC[i];
 128                 }
 129         }
 130
 131         return serviced;
 132 }
 133
 134 /*
 135  * Wake up mail box queue.
 136  *
 137  * XXX This functionality is not exposed up though API.
 138  */
 139 static u32 tsi148_MB_irqhandler(struct tsi148_driver *bridge, u32 stat)
 140 {
 141         int i;
 142         u32 val;
 143         u32 serviced = 0;
 144
 145         for (i = 0; i < 4; i++) {
 146                 if(stat & TSI148_LCSR_INTS_MBS[i]) {
 147                         val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
 148                         printk("VME Mailbox %d received: 0x%x\n", i, val);
 149                         serviced |= TSI148_LCSR_INTC_MBC[i];
 150                 }
 151         }
 152
 153         return serviced;
 154 }
 155
 156 /*
 157  * Display error & status message when PERR (PCI) exception interrupt occurs.
 158  */
 159 static u32 tsi148_PERR_irqhandler(struct tsi148_driver *bridge)
 160 {
 161         printk(KERN_ERR
 162                 "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
 163                 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
 164                 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
 165                 ioread32be(bridge->base + TSI148_LCSR_EDPAT)
 166                 );
 167         printk(KERN_ERR
 168                 "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
 169                 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
 170                 ioread32be(bridge->base + TSI148_LCSR_EDPXS)
 171                 );
 172
 173         iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
 174
 175         return TSI148_LCSR_INTC_PERRC;
 176 }
 177
 178 /*
 179  * Save address and status when VME error interrupt occurs.
 180  */
 181 static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
 182 {
 183         unsigned int error_addr_high, error_addr_low;
 184         unsigned long long error_addr;
 185         u32 error_attrib;
 186         struct vme_bus_error *error;
 187         struct tsi148_driver *bridge;
 188
 189         bridge = tsi148_bridge->driver_priv;
 190
 191         error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
 192         error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
 193         error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
 194
 195         reg_join(error_addr_high, error_addr_low, &error_addr);
 196
 197         /* Check for exception register overflow (we have lost error data) */
 198         if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
 199                 printk(KERN_ERR "VME Bus Exception Overflow Occurred\n");
 200         }
 201
 202         error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
 203                 GFP_ATOMIC);
 204         if (error) {
 205                 error->address = error_addr;
 206                 error->attributes = error_attrib;
 207                 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
 208         } else {
 209                 printk(KERN_ERR
 210                         "Unable to alloc memory for VMEbus Error reporting\n");
 211                 printk(KERN_ERR
 212                         "VME Bus Error at address: 0x%llx, attributes: %08x\n",
 213                         error_addr, error_attrib);
 214         }
 215
 216         /* Clear Status */
 217         iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
 218
 219         return TSI148_LCSR_INTC_VERRC;
 220 }
 221
 222 /*
 223  * Wake up IACK queue.
 224  */
 225 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
 226 {
 227         wake_up(&(bridge->iack_queue));
 228
 229         return TSI148_LCSR_INTC_IACKC;
 230 }
 231
 232 /*
 233  * Calling VME bus interrupt callback if provided.
 234  */
 235 static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
 236         u32 stat)
 237 {
 238         int vec, i, serviced = 0;
 239         struct tsi148_driver *bridge;
 240
 241         bridge = tsi148_bridge->driver_priv;
 242
 243         for (i = 7; i > 0; i--) {
 244                 if (stat & (1 << i)) {
 245                         /*
 246                          *      Note:   Even though the registers are defined
 247                          *      as 32-bits in the spec, we only want to issue
 248                          *      8-bit IACK cycles on the bus, read from offset
 249                          *      3.
 250                          */
 251                         vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
 252
 253                         vme_irq_handler(tsi148_bridge, i, vec);
 254
 255                         serviced |= (1 << i);
 256                 }
 257         }
 258
 259         return serviced;
 260 }
 261
 262 /*
 263  * Top level interrupt handler.  Clears appropriate interrupt status bits and
 264  * then calls appropriate sub handler(s).
 265  */
 266 static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
 267 {
 268         u32 stat, enable, serviced = 0;
 269         struct vme_bridge *tsi148_bridge;
 270         struct tsi148_driver *bridge;
 271
 272         tsi148_bridge = ptr;
 273
 274         bridge = tsi148_bridge->driver_priv;
 275
 276         /* Determine which interrupts are unmasked and set */
 277         enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 278         stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
 279
 280         /* Only look at unmasked interrupts */
 281         stat &= enable;
 282
 283         if (unlikely(!stat)) {
 284                 return IRQ_NONE;
 285         }
 286
 287         /* Call subhandlers as appropriate */
 288         /* DMA irqs */
 289         if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
 290                 serviced |= tsi148_DMA_irqhandler(bridge, stat);
 291
 292         /* Location monitor irqs */
 293         if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
 294                         TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
 295                 serviced |= tsi148_LM_irqhandler(bridge, stat);
 296
 297         /* Mail box irqs */
 298         if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
 299                         TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
 300                 serviced |= tsi148_MB_irqhandler(bridge, stat);
 301
 302         /* PCI bus error */
 303         if (stat & TSI148_LCSR_INTS_PERRS)
 304                 serviced |= tsi148_PERR_irqhandler(bridge);
 305
 306         /* VME bus error */
 307         if (stat & TSI148_LCSR_INTS_VERRS)
 308                 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
 309
 310         /* IACK irq */
 311         if (stat & TSI148_LCSR_INTS_IACKS)
 312                 serviced |= tsi148_IACK_irqhandler(bridge);
 313
 314         /* VME bus irqs */
 315         if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
 316                         TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
 317                         TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
 318                         TSI148_LCSR_INTS_IRQ1S))
 319                 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
 320
 321         /* Clear serviced interrupts */
 322         iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
 323
 324         return IRQ_HANDLED;
 325 }
 326
 327 static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
 328 {
 329         int result;
 330         unsigned int tmp;
 331         struct pci_dev *pdev;
 332         struct tsi148_driver *bridge;
 333
 334         pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 335
 336         bridge = tsi148_bridge->driver_priv;
 337
 338         /* Initialise list for VME bus errors */
 339         INIT_LIST_HEAD(&(tsi148_bridge->vme_errors));
 340
 341         mutex_init(&(tsi148_bridge->irq_mtx));
 342
 343         result = request_irq(pdev->irq,
 344                              tsi148_irqhandler,
 345                              IRQF_SHARED,
 346                              driver_name, tsi148_bridge);
 347         if (result) {
 348                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 349                         pdev->irq);
 350                 return result;
 351         }
 352
 353         /* Enable and unmask interrupts */
 354         tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
 355                 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
 356                 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
 357                 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
 358                 TSI148_LCSR_INTEO_IACKEO;
 359
 360         /* This leaves the following interrupts masked.
 361          * TSI148_LCSR_INTEO_VIEEO
 362          * TSI148_LCSR_INTEO_SYSFLEO
 363          * TSI148_LCSR_INTEO_ACFLEO
 364          */
 365
 366         /* Don't enable Location Monitor interrupts here - they will be
 367          * enabled when the location monitors are properly configured and
 368          * a callback has been attached.
 369          * TSI148_LCSR_INTEO_LM0EO
 370          * TSI148_LCSR_INTEO_LM1EO
 371          * TSI148_LCSR_INTEO_LM2EO
 372          * TSI148_LCSR_INTEO_LM3EO
 373          */
 374
 375         /* Don't enable VME interrupts until we add a handler, else the board
 376          * will respond to it and we don't want that unless it knows how to
 377          * properly deal with it.
 378          * TSI148_LCSR_INTEO_IRQ7EO
 379          * TSI148_LCSR_INTEO_IRQ6EO
 380          * TSI148_LCSR_INTEO_IRQ5EO
 381          * TSI148_LCSR_INTEO_IRQ4EO
 382          * TSI148_LCSR_INTEO_IRQ3EO
 383          * TSI148_LCSR_INTEO_IRQ2EO
 384          * TSI148_LCSR_INTEO_IRQ1EO
 385          */
 386
 387         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 388         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 389
 390         return 0;
 391 }
 392
 393 static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev)
 394 {
 395         /* Turn off interrupts */
 396         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
 397         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
 398
 399         /* Clear all interrupts */
 400         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
 401
 402         /* Detach interrupt handler */
 403         free_irq(pdev->irq, pdev);
 404 }
 405
 406 /*
 407  * Check to see if an IACk has been received, return true (1) or false (0).
 408  */
 409 int tsi148_iack_received(struct tsi148_driver *bridge)
 410 {
 411         u32 tmp;
 412
 413         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 414
 415         if (tmp & TSI148_LCSR_VICR_IRQS)
 416                 return 0;
 417         else
 418                 return 1;
 419 }
 420
 421 /*
 422  * Configure VME interrupt
 423  */
 424 void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
 425         int state, int sync)
 426 {
 427         struct pci_dev *pdev;
 428         u32 tmp;
 429         struct tsi148_driver *bridge;
 430
 431         bridge = tsi148_bridge->driver_priv;
 432
 433         /* We need to do the ordering differently for enabling and disabling */
 434         if (state == 0) {
 435                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 436                 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
 437                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 438
 439                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 440                 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
 441                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 442
 443                 if (sync != 0) {
 444                         pdev = container_of(tsi148_bridge->parent,
 445                                 struct pci_dev, dev);
 446
 447                         synchronize_irq(pdev->irq);
 448                 }
 449         } else {
 450                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 451                 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
 452                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 453
 454                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 455                 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
 456                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 457         }
 458 }
 459
 460 /*
 461  * Generate a VME bus interrupt at the requested level & vector. Wait for
 462  * interrupt to be acked.
 463  */
 464 int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid)
 465 {
 466         u32 tmp;
 467         struct tsi148_driver *bridge;
 468
 469         bridge = tsi148_bridge->driver_priv;
 470
 471         mutex_lock(&(bridge->vme_int));
 472
 473         /* Read VICR register */
 474         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 475
 476         /* Set Status/ID */
 477         tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
 478                 (statid & TSI148_LCSR_VICR_STID_M);
 479         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 480
 481         /* Assert VMEbus IRQ */
 482         tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
 483         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 484
 485         /* XXX Consider implementing a timeout? */
 486         wait_event_interruptible(bridge->iack_queue,
 487                 tsi148_iack_received(bridge));
 488
 489         mutex_unlock(&(bridge->vme_int));
 490
 491         return 0;
 492 }
 493
 494 /*
 495  * Find the first error in this address range
 496  */
 497 static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
 498         vme_address_t aspace, unsigned long long address, size_t count)
 499 {
 500         struct list_head *err_pos;
 501         struct vme_bus_error *vme_err, *valid = NULL;
 502         unsigned long long bound;
 503
 504         bound = address + count;
 505
 506         /*
 507          * XXX We are currently not looking at the address space when parsing
 508          *     for errors. This is because parsing the Address Modifier Codes
 509          *     is going to be quite resource intensive to do properly. We
 510          *     should be OK just looking at the addresses and this is certainly
 511          *     much better than what we had before.
 512          */
 513         err_pos = NULL;
 514         /* Iterate through errors */
 515         list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
 516                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 517                 if((vme_err->address >= address) && (vme_err->address < bound)){
 518                         valid = vme_err;
 519                         break;
 520                 }
 521         }
 522
 523         return valid;
 524 }
 525
 526 /*
 527  * Clear errors in the provided address range.
 528  */
 529 static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
 530         vme_address_t aspace, unsigned long long address, size_t count)
 531 {
 532         struct list_head *err_pos, *temp;
 533         struct vme_bus_error *vme_err;
 534         unsigned long long bound;
 535
 536         bound = address + count;
 537
 538         /*
 539          * XXX We are currently not looking at the address space when parsing
 540          *     for errors. This is because parsing the Address Modifier Codes
 541          *     is going to be quite resource intensive to do properly. We
 542          *     should be OK just looking at the addresses and this is certainly
 543          *     much better than what we had before.
 544          */
 545         err_pos = NULL;
 546         /* Iterate through errors */
 547         list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
 548                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 549
 550                 if((vme_err->address >= address) && (vme_err->address < bound)){
 551                         list_del(err_pos);
 552                         kfree(vme_err);
 553                 }
 554         }
 555 }
 556
 557 /*
 558  * Initialize a slave window with the requested attributes.
 559  */
 560 int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
 561         unsigned long long vme_base, unsigned long long size,
 562         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 563 {
 564         unsigned int i, addr = 0, granularity = 0;
 565         unsigned int temp_ctl = 0;
 566         unsigned int vme_base_low, vme_base_high;
 567         unsigned int vme_bound_low, vme_bound_high;
 568         unsigned int pci_offset_low, pci_offset_high;
 569         unsigned long long vme_bound, pci_offset;
 570         struct tsi148_driver *bridge;
 571
 572         bridge = image->parent->driver_priv;
 573
 574 #if 0
 575         printk("Set slave image %d to:\n", image->number);
 576         printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no");
 577         printk("\tVME Base:0x%llx\n", vme_base);
 578         printk("\tWindow Size:0x%llx\n", size);
 579         printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base);
 580         printk("\tAddress Space:0x%x\n", aspace);
 581         printk("\tTransfer Cycle Properties:0x%x\n", cycle);
 582 #endif
 583
 584         i = image->number;
 585
 586         switch (aspace) {
 587         case VME_A16:
 588                 granularity = 0x10;
 589                 addr |= TSI148_LCSR_ITAT_AS_A16;
 590                 break;
 591         case VME_A24:
 592                 granularity = 0x1000;
 593                 addr |= TSI148_LCSR_ITAT_AS_A24;
 594                 break;
 595         case VME_A32:
 596                 granularity = 0x10000;
 597                 addr |= TSI148_LCSR_ITAT_AS_A32;
 598                 break;
 599         case VME_A64:
 600                 granularity = 0x10000;
 601                 addr |= TSI148_LCSR_ITAT_AS_A64;
 602                 break;
 603         case VME_CRCSR:
 604         case VME_USER1:
 605         case VME_USER2:
 606         case VME_USER3:
 607         case VME_USER4:
 608         default:
 609                 printk("Invalid address space\n");
 610                 return -EINVAL;
 611                 break;
 612         }
 613
 614         /* Convert 64-bit variables to 2x 32-bit variables */
 615         reg_split(vme_base, &vme_base_high, &vme_base_low);
 616
 617         /*
 618          * Bound address is a valid address for the window, adjust
 619          * accordingly
 620          */
 621         vme_bound = vme_base + size - granularity;
 622         reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
 623         pci_offset = (unsigned long long)pci_base - vme_base;
 624         reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
 625
 626         if (vme_base_low & (granularity - 1)) {
 627                 printk("Invalid VME base alignment\n");
 628                 return -EINVAL;
 629         }
 630         if (vme_bound_low & (granularity - 1)) {
 631                 printk("Invalid VME bound alignment\n");
 632                 return -EINVAL;
 633         }
 634         if (pci_offset_low & (granularity - 1)) {
 635                 printk("Invalid PCI Offset alignment\n");
 636                 return -EINVAL;
 637         }
 638
 639 #if 0
 640         printk("\tVME Bound:0x%llx\n", vme_bound);
 641         printk("\tPCI Offset:0x%llx\n", pci_offset);
 642 #endif
 643
 644         /*  Disable while we are mucking around */
 645         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 646                 TSI148_LCSR_OFFSET_ITAT);
 647         temp_ctl &= ~TSI148_LCSR_ITAT_EN;
 648         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 649                 TSI148_LCSR_OFFSET_ITAT);
 650
 651         /* Setup mapping */
 652         iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
 653                 TSI148_LCSR_OFFSET_ITSAU);
 654         iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
 655                 TSI148_LCSR_OFFSET_ITSAL);
 656         iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
 657                 TSI148_LCSR_OFFSET_ITEAU);
 658         iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
 659                 TSI148_LCSR_OFFSET_ITEAL);
 660         iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
 661                 TSI148_LCSR_OFFSET_ITOFU);
 662         iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
 663                 TSI148_LCSR_OFFSET_ITOFL);
 664
 665 /* XXX Prefetch stuff currently unsupported */
 666 #if 0
 667
 668         for (x = 0; x < 4; x++) {
 669                 if ((64 << x) >= vmeIn->prefetchSize) {
 670                         break;
 671                 }
 672         }
 673         if (x == 4)
 674                 x--;
 675         temp_ctl |= (x << 16);
 676
 677         if (vmeIn->prefetchThreshold)
 678                 if (vmeIn->prefetchThreshold)
 679                         temp_ctl |= 0x40000;
 680 #endif
 681
 682         /* Setup 2eSST speeds */
 683         temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
 684         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 685         case VME_2eSST160:
 686                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
 687                 break;
 688         case VME_2eSST267:
 689                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
 690                 break;
 691         case VME_2eSST320:
 692                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
 693                 break;
 694         }
 695
 696         /* Setup cycle types */
 697         temp_ctl &= ~(0x1F << 7);
 698         if (cycle & VME_BLT)
 699                 temp_ctl |= TSI148_LCSR_ITAT_BLT;
 700         if (cycle & VME_MBLT)
 701                 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
 702         if (cycle & VME_2eVME)
 703                 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
 704         if (cycle & VME_2eSST)
 705                 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
 706         if (cycle & VME_2eSSTB)
 707                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
 708
 709         /* Setup address space */
 710         temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
 711         temp_ctl |= addr;
 712
 713         temp_ctl &= ~0xF;
 714         if (cycle & VME_SUPER)
 715                 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
 716         if (cycle & VME_USER)
 717                 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
 718         if (cycle & VME_PROG)
 719                 temp_ctl |= TSI148_LCSR_ITAT_PGM;
 720         if (cycle & VME_DATA)
 721                 temp_ctl |= TSI148_LCSR_ITAT_DATA;
 722
 723         /* Write ctl reg without enable */
 724         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 725                 TSI148_LCSR_OFFSET_ITAT);
 726
 727         if (enabled)
 728                 temp_ctl |= TSI148_LCSR_ITAT_EN;
 729
 730         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 731                 TSI148_LCSR_OFFSET_ITAT);
 732
 733         return 0;
 734 }
 735
 736 /*
 737  * Get slave window configuration.
 738  *
 739  * XXX Prefetch currently unsupported.
 740  */
 741 int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
 742         unsigned long long *vme_base, unsigned long long *size,
 743         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 744 {
 745         unsigned int i, granularity = 0, ctl = 0;
 746         unsigned int vme_base_low, vme_base_high;
 747         unsigned int vme_bound_low, vme_bound_high;
 748         unsigned int pci_offset_low, pci_offset_high;
 749         unsigned long long vme_bound, pci_offset;
 750         struct tsi148_driver *bridge;
 751
 752         bridge = image->parent->driver_priv;
 753
 754         i = image->number;
 755
 756         /* Read registers */
 757         ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 758                 TSI148_LCSR_OFFSET_ITAT);
 759
 760         vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 761                 TSI148_LCSR_OFFSET_ITSAU);
 762         vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 763                 TSI148_LCSR_OFFSET_ITSAL);
 764         vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 765                 TSI148_LCSR_OFFSET_ITEAU);
 766         vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 767                 TSI148_LCSR_OFFSET_ITEAL);
 768         pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 769                 TSI148_LCSR_OFFSET_ITOFU);
 770         pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 771                 TSI148_LCSR_OFFSET_ITOFL);
 772
 773         /* Convert 64-bit variables to 2x 32-bit variables */
 774         reg_join(vme_base_high, vme_base_low, vme_base);
 775         reg_join(vme_bound_high, vme_bound_low, &vme_bound);
 776         reg_join(pci_offset_high, pci_offset_low, &pci_offset);
 777
 778         *pci_base = (dma_addr_t)vme_base + pci_offset;
 779
 780         *enabled = 0;
 781         *aspace = 0;
 782         *cycle = 0;
 783
 784         if (ctl & TSI148_LCSR_ITAT_EN)
 785                 *enabled = 1;
 786
 787         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
 788                 granularity = 0x10;
 789                 *aspace |= VME_A16;
 790         }
 791         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
 792                 granularity = 0x1000;
 793                 *aspace |= VME_A24;
 794         }
 795         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
 796                 granularity = 0x10000;
 797                 *aspace |= VME_A32;
 798         }
 799         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
 800                 granularity = 0x10000;
 801                 *aspace |= VME_A64;
 802         }
 803
 804         /* Need granularity before we set the size */
 805         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 806
 807
 808         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
 809                 *cycle |= VME_2eSST160;
 810         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
 811                 *cycle |= VME_2eSST267;
 812         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
 813                 *cycle |= VME_2eSST320;
 814
 815         if (ctl & TSI148_LCSR_ITAT_BLT)
 816                 *cycle |= VME_BLT;
 817         if (ctl & TSI148_LCSR_ITAT_MBLT)
 818                 *cycle |= VME_MBLT;
 819         if (ctl & TSI148_LCSR_ITAT_2eVME)
 820                 *cycle |= VME_2eVME;
 821         if (ctl & TSI148_LCSR_ITAT_2eSST)
 822                 *cycle |= VME_2eSST;
 823         if (ctl & TSI148_LCSR_ITAT_2eSSTB)
 824                 *cycle |= VME_2eSSTB;
 825
 826         if (ctl & TSI148_LCSR_ITAT_SUPR)
 827                 *cycle |= VME_SUPER;
 828         if (ctl & TSI148_LCSR_ITAT_NPRIV)
 829                 *cycle |= VME_USER;
 830         if (ctl & TSI148_LCSR_ITAT_PGM)
 831                 *cycle |= VME_PROG;
 832         if (ctl & TSI148_LCSR_ITAT_DATA)
 833                 *cycle |= VME_DATA;
 834
 835         return 0;
 836 }
 837
 838 /*
 839  * Allocate and map PCI Resource
 840  */
 841 static int tsi148_alloc_resource(struct vme_master_resource *image,
 842         unsigned long long size)
 843 {
 844         unsigned long long existing_size;
 845         int retval = 0;
 846         struct pci_dev *pdev;
 847         struct vme_bridge *tsi148_bridge;
 848
 849         tsi148_bridge = image->parent;
 850
 851         /* Find pci_dev container of dev */
 852         if (tsi148_bridge->parent == NULL) {
 853                 printk("Dev entry NULL\n");
 854                 return -EINVAL;
 855         }
 856         pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 857
 858         existing_size = (unsigned long long)(image->bus_resource.end -
 859                 image->bus_resource.start);
 860
 861         /* If the existing size is OK, return */
 862         if ((size != 0) && (existing_size == (size - 1)))
 863                 return 0;
 864
 865         if (existing_size != 0) {
 866                 iounmap(image->kern_base);
 867                 image->kern_base = NULL;
 868                 if (image->bus_resource.name != NULL)
 869                         kfree(image->bus_resource.name);
 870                 release_resource(&(image->bus_resource));
 871                 memset(&(image->bus_resource), 0, sizeof(struct resource));
 872         }
 873
 874         /* Exit here if size is zero */
 875         if (size == 0) {
 876                 return 0;
 877         }
 878
 879         if (image->bus_resource.name == NULL) {
 880                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
 881                 if (image->bus_resource.name == NULL) {
 882                         printk(KERN_ERR "Unable to allocate memory for resource"
 883                                 " name\n");
 884                         retval = -ENOMEM;
 885                         goto err_name;
 886                 }
 887         }
 888
 889         sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
 890                 image->number);
 891
 892         image->bus_resource.start = 0;
 893         image->bus_resource.end = (unsigned long)size;
 894         image->bus_resource.flags = IORESOURCE_MEM;
 895
 896         retval = pci_bus_alloc_resource(pdev->bus,
 897                 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
 898                 0, NULL, NULL);
 899         if (retval) {
 900                 printk(KERN_ERR "Failed to allocate mem resource for "
 901                         "window %d size 0x%lx start 0x%lx\n",
 902                         image->number, (unsigned long)size,
 903                         (unsigned long)image->bus_resource.start);
 904                 goto err_resource;
 905         }
 906
 907         image->kern_base = ioremap_nocache(
 908                 image->bus_resource.start, size);
 909         if (image->kern_base == NULL) {
 910                 printk(KERN_ERR "Failed to remap resource\n");
 911                 retval = -ENOMEM;
 912                 goto err_remap;
 913         }
 914
 915         return 0;
 916
 917         iounmap(image->kern_base);
 918         image->kern_base = NULL;
 919 err_remap:
 920         release_resource(&(image->bus_resource));
 921 err_resource:
 922         kfree(image->bus_resource.name);
 923         memset(&(image->bus_resource), 0, sizeof(struct resource));
 924 err_name:
 925         return retval;
 926 }
 927
 928 /*
 929  * Free and unmap PCI Resource
 930  */
 931 static void tsi148_free_resource(struct vme_master_resource *image)
 932 {
 933         iounmap(image->kern_base);
 934         image->kern_base = NULL;
 935         release_resource(&(image->bus_resource));
 936         kfree(image->bus_resource.name);
 937         memset(&(image->bus_resource), 0, sizeof(struct resource));
 938 }
 939
 940 /*
 941  * Set the attributes of an outbound window.
 942  */
 943 int tsi148_master_set( struct vme_master_resource *image, int enabled,
 944         unsigned long long vme_base, unsigned long long size,
 945         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 946 {
 947         int retval = 0;
 948         unsigned int i;
 949         unsigned int temp_ctl = 0;
 950         unsigned int pci_base_low, pci_base_high;
 951         unsigned int pci_bound_low, pci_bound_high;
 952         unsigned int vme_offset_low, vme_offset_high;
 953         unsigned long long pci_bound, vme_offset, pci_base;
 954         struct tsi148_driver *bridge;
 955
 956         bridge = image->parent->driver_priv;
 957
 958         /* Verify input data */
 959         if (vme_base & 0xFFFF) {
 960                 printk(KERN_ERR "Invalid VME Window alignment\n");
 961                 retval = -EINVAL;
 962                 goto err_window;
 963         }
 964
 965         if ((size == 0) && (enabled != 0)) {
 966                 printk(KERN_ERR "Size must be non-zero for enabled windows\n");
 967                 retval = -EINVAL;
 968                 goto err_window;
 969         }
 970
 971         spin_lock(&(image->lock));
 972
 973         /* Let's allocate the resource here rather than further up the stack as
 974          * it avoids pushing loads of bus dependant stuff up the stack. If size
 975          * is zero, any existing resource will be freed.
 976          */
 977         retval = tsi148_alloc_resource(image, size);
 978         if (retval) {
 979                 spin_unlock(&(image->lock));
 980                 printk(KERN_ERR "Unable to allocate memory for "
 981                         "resource\n");
 982                 goto err_res;
 983         }
 984
 985         if (size == 0) {
 986                 pci_base = 0;
 987                 pci_bound = 0;
 988                 vme_offset = 0;
 989         } else {
 990                 pci_base = (unsigned long long)image->bus_resource.start;
 991
 992                 /*
 993                  * Bound address is a valid address for the window, adjust
 994                  * according to window granularity.
 995                  */
 996                 pci_bound = pci_base + (size - 0x10000);
 997                 vme_offset = vme_base - pci_base;
 998         }
 999
1000         /* Convert 64-bit variables to 2x 32-bit variables */
1001         reg_split(pci_base, &pci_base_high, &pci_base_low);
1002         reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
1003         reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
1004
1005         if (pci_base_low & 0xFFFF) {
1006                 spin_unlock(&(image->lock));
1007                 printk(KERN_ERR "Invalid PCI base alignment\n");
1008                 retval = -EINVAL;
1009                 goto err_gran;
1010         }
1011         if (pci_bound_low & 0xFFFF) {
1012                 spin_unlock(&(image->lock));
1013                 printk(KERN_ERR "Invalid PCI bound alignment\n");
1014                 retval = -EINVAL;
1015                 goto err_gran;
1016         }
1017         if (vme_offset_low & 0xFFFF) {
1018                 spin_unlock(&(image->lock));
1019                 printk(KERN_ERR "Invalid VME Offset alignment\n");
1020                 retval = -EINVAL;
1021                 goto err_gran;
1022         }
1023
1024         i = image->number;
1025
1026         /* Disable while we are mucking around */
1027         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1028                 TSI148_LCSR_OFFSET_OTAT);
1029         temp_ctl &= ~TSI148_LCSR_OTAT_EN;
1030         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1031                 TSI148_LCSR_OFFSET_OTAT);
1032
1033 /* XXX Prefetch stuff currently unsupported */
1034 #if 0
1035         if (vmeOut->prefetchEnable) {
1036                 temp_ctl |= 0x40000;
1037                 for (x = 0; x < 4; x++) {
1038                         if ((2 << x) >= vmeOut->prefetchSize)
1039                                 break;
1040                 }
1041                 if (x == 4)
1042                         x = 3;
1043                 temp_ctl |= (x << 16);
1044         }
1045 #endif
1046
1047         /* Setup 2eSST speeds */
1048         temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
1049         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1050         case VME_2eSST160:
1051                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1052                 break;
1053         case VME_2eSST267:
1054                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1055                 break;
1056         case VME_2eSST320:
1057                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1058                 break;
1059         }
1060
1061         /* Setup cycle types */
1062         if (cycle & VME_BLT) {
1063                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1064                 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1065         }
1066         if (cycle & VME_MBLT) {
1067                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1068                 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1069         }
1070         if (cycle & VME_2eVME) {
1071                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1072                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1073         }
1074         if (cycle & VME_2eSST) {
1075                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1076                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1077         }
1078         if (cycle & VME_2eSSTB) {
1079                 printk(KERN_WARNING "Currently not setting Broadcast Select "
1080                         "Registers\n");
1081                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1082                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1083         }
1084
1085         /* Setup data width */
1086         temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1087         switch (dwidth) {
1088         case VME_D16:
1089                 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1090                 break;
1091         case VME_D32:
1092                 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1093                 break;
1094         default:
1095                 spin_unlock(&(image->lock));
1096                 printk(KERN_ERR "Invalid data width\n");
1097                 retval = -EINVAL;
1098                 goto err_dwidth;
1099         }
1100
1101         /* Setup address space */
1102         temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1103         switch (aspace) {
1104         case VME_A16:
1105                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1106                 break;
1107         case VME_A24:
1108                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1109                 break;
1110         case VME_A32:
1111                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1112                 break;
1113         case VME_A64:
1114                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1115                 break;
1116         case VME_CRCSR:
1117                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1118                 break;
1119         case VME_USER1:
1120                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1121                 break;
1122         case VME_USER2:
1123                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1124                 break;
1125         case VME_USER3:
1126                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1127                 break;
1128         case VME_USER4:
1129                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1130                 break;
1131         default:
1132                 spin_unlock(&(image->lock));
1133                 printk(KERN_ERR "Invalid address space\n");
1134                 retval = -EINVAL;
1135                 goto err_aspace;
1136                 break;
1137         }
1138
1139         temp_ctl &= ~(3<<4);
1140         if (cycle & VME_SUPER)
1141                 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1142         if (cycle & VME_PROG)
1143                 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1144
1145         /* Setup mapping */
1146         iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1147                 TSI148_LCSR_OFFSET_OTSAU);
1148         iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1149                 TSI148_LCSR_OFFSET_OTSAL);
1150         iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1151                 TSI148_LCSR_OFFSET_OTEAU);
1152         iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1153                 TSI148_LCSR_OFFSET_OTEAL);
1154         iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1155                 TSI148_LCSR_OFFSET_OTOFU);
1156         iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1157                 TSI148_LCSR_OFFSET_OTOFL);
1158
1159 /* XXX We need to deal with OTBS */
1160 #if 0
1161         iowrite32be(vmeOut->bcastSelect2esst, bridge->base +
1162                 TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS);
1163 #endif
1164
1165         /* Write ctl reg without enable */
1166         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1167                 TSI148_LCSR_OFFSET_OTAT);
1168
1169         if (enabled)
1170                 temp_ctl |= TSI148_LCSR_OTAT_EN;
1171
1172         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1173                 TSI148_LCSR_OFFSET_OTAT);
1174
1175         spin_unlock(&(image->lock));
1176         return 0;
1177
1178 err_aspace:
1179 err_dwidth:
1180 err_gran:
1181         tsi148_free_resource(image);
1182 err_res:
1183 err_window:
1184         return retval;
1185
1186 }
1187
1188 /*
1189  * Set the attributes of an outbound window.
1190  *
1191  * XXX Not parsing prefetch information.
1192  */
1193 int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
1194         unsigned long long *vme_base, unsigned long long *size,
1195         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1196 {
1197         unsigned int i, ctl;
1198         unsigned int pci_base_low, pci_base_high;
1199         unsigned int pci_bound_low, pci_bound_high;
1200         unsigned int vme_offset_low, vme_offset_high;
1201
1202         unsigned long long pci_base, pci_bound, vme_offset;
1203         struct tsi148_driver *bridge;
1204
1205         bridge = image->parent->driver_priv;
1206
1207         i = image->number;
1208
1209         ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1210                 TSI148_LCSR_OFFSET_OTAT);
1211
1212         pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1213                 TSI148_LCSR_OFFSET_OTSAU);
1214         pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1215                 TSI148_LCSR_OFFSET_OTSAL);
1216         pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1217                 TSI148_LCSR_OFFSET_OTEAU);
1218         pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1219                 TSI148_LCSR_OFFSET_OTEAL);
1220         vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1221                 TSI148_LCSR_OFFSET_OTOFU);
1222         vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1223                 TSI148_LCSR_OFFSET_OTOFL);
1224
1225         /* Convert 64-bit variables to 2x 32-bit variables */
1226         reg_join(pci_base_high, pci_base_low, &pci_base);
1227         reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1228         reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1229
1230         *vme_base = pci_base + vme_offset;
1231         *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1232
1233         *enabled = 0;
1234         *aspace = 0;
1235         *cycle = 0;
1236         *dwidth = 0;
1237
1238         if (ctl & TSI148_LCSR_OTAT_EN)
1239                 *enabled = 1;
1240
1241         /* Setup address space */
1242         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1243                 *aspace |= VME_A16;
1244         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1245                 *aspace |= VME_A24;
1246         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1247                 *aspace |= VME_A32;
1248         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1249                 *aspace |= VME_A64;
1250         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1251                 *aspace |= VME_CRCSR;
1252         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1253                 *aspace |= VME_USER1;
1254         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1255                 *aspace |= VME_USER2;
1256         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1257                 *aspace |= VME_USER3;
1258         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1259                 *aspace |= VME_USER4;
1260
1261         /* Setup 2eSST speeds */
1262         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1263                 *cycle |= VME_2eSST160;
1264         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1265                 *cycle |= VME_2eSST267;
1266         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1267                 *cycle |= VME_2eSST320;
1268
1269         /* Setup cycle types */
1270         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
1271                 *cycle |= VME_SCT;
1272         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
1273                 *cycle |= VME_BLT;
1274         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
1275                 *cycle |= VME_MBLT;
1276         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
1277                 *cycle |= VME_2eVME;
1278         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
1279                 *cycle |= VME_2eSST;
1280         if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
1281                 *cycle |= VME_2eSSTB;
1282
1283         if (ctl & TSI148_LCSR_OTAT_SUP)
1284                 *cycle |= VME_SUPER;
1285         else
1286                 *cycle |= VME_USER;
1287
1288         if (ctl & TSI148_LCSR_OTAT_PGM)
1289                 *cycle |= VME_PROG;
1290         else
1291                 *cycle |= VME_DATA;
1292
1293         /* Setup data width */
1294         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1295                 *dwidth = VME_D16;
1296         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1297                 *dwidth = VME_D32;
1298
1299         return 0;
1300 }
1301
1302
1303 int tsi148_master_get( struct vme_master_resource *image, int *enabled,
1304         unsigned long long *vme_base, unsigned long long *size,
1305         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1306 {
1307         int retval;
1308
1309         spin_lock(&(image->lock));
1310
1311         retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1312                 cycle, dwidth);
1313
1314         spin_unlock(&(image->lock));
1315
1316         return retval;
1317 }
1318
1319 ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1320         size_t count, loff_t offset)
1321 {
1322         int retval, enabled;
1323         unsigned long long vme_base, size;
1324         vme_address_t aspace;
1325         vme_cycle_t cycle;
1326         vme_width_t dwidth;
1327         struct vme_bus_error *vme_err = NULL;
1328         struct vme_bridge *tsi148_bridge;
1329
1330         tsi148_bridge = image->parent;
1331
1332         spin_lock(&(image->lock));
1333
1334         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1335         retval = count;
1336
1337         if (!err_chk)
1338                 goto skip_chk;
1339
1340         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1341                 &dwidth);
1342
1343         vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1344                 count);
1345         if(vme_err != NULL) {
1346                 dev_err(image->parent->parent, "First VME read error detected "
1347                         "an at address 0x%llx\n", vme_err->address);
1348                 retval = vme_err->address - (vme_base + offset);
1349                 /* Clear down save errors in this address range */
1350                 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1351                         count);
1352         }
1353
1354 skip_chk:
1355         spin_unlock(&(image->lock));
1356
1357         return retval;
1358 }
1359
1360
1361 ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1362         size_t count, loff_t offset)
1363 {
1364         int retval = 0, enabled;
1365         unsigned long long vme_base, size;
1366         vme_address_t aspace;
1367         vme_cycle_t cycle;
1368         vme_width_t dwidth;
1369
1370         struct vme_bus_error *vme_err = NULL;
1371         struct vme_bridge *tsi148_bridge;
1372         struct tsi148_driver *bridge;
1373
1374         tsi148_bridge = image->parent;
1375
1376         bridge = tsi148_bridge->driver_priv;
1377
1378         spin_lock(&(image->lock));
1379
1380         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1381         retval = count;
1382
1383         /*
1384          * Writes are posted. We need to do a read on the VME bus to flush out
1385          * all of the writes before we check for errors. We can't guarentee
1386          * that reading the data we have just written is safe. It is believed
1387          * that there isn't any read, write re-ordering, so we can read any
1388          * location in VME space, so lets read the Device ID from the tsi148's
1389          * own registers as mapped into CR/CSR space.
1390          *
1391          * We check for saved errors in the written address range/space.
1392          */
1393
1394         if (!err_chk)
1395                 goto skip_chk;
1396
1397         /*
1398          * Get window info first, to maximise the time that the buffers may
1399          * fluch on their own
1400          */
1401         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1402                 &dwidth);
1403
1404         ioread16(bridge->flush_image->kern_base + 0x7F000);
1405
1406         vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1407                 count);
1408         if(vme_err != NULL) {
1409                 printk("First VME write error detected an at address 0x%llx\n",
1410                         vme_err->address);
1411                 retval = vme_err->address - (vme_base + offset);
1412                 /* Clear down save errors in this address range */
1413                 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1414                         count);
1415         }
1416
1417 skip_chk:
1418         spin_unlock(&(image->lock));
1419
1420         return retval;
1421 }
1422
1423 /*
1424  * Perform an RMW cycle on the VME bus.
1425  *
1426  * Requires a previously configured master window, returns final value.
1427  */
1428 unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1429         unsigned int mask, unsigned int compare, unsigned int swap,
1430         loff_t offset)
1431 {
1432         unsigned long long pci_addr;
1433         unsigned int pci_addr_high, pci_addr_low;
1434         u32 tmp, result;
1435         int i;
1436         struct tsi148_driver *bridge;
1437
1438         bridge = image->parent->driver_priv;
1439
1440         /* Find the PCI address that maps to the desired VME address */
1441         i = image->number;
1442
1443         /* Locking as we can only do one of these at a time */
1444         mutex_lock(&(bridge->vme_rmw));
1445
1446         /* Lock image */
1447         spin_lock(&(image->lock));
1448
1449         pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1450                 TSI148_LCSR_OFFSET_OTSAU);
1451         pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1452                 TSI148_LCSR_OFFSET_OTSAL);
1453
1454         reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1455         reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1456
1457         /* Configure registers */
1458         iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1459         iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1460         iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1461         iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1462         iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1463
1464         /* Enable RMW */
1465         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1466         tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1467         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1468
1469         /* Kick process off with a read to the required address. */
1470         result = ioread32be(image->kern_base + offset);
1471
1472         /* Disable RMW */
1473         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1474         tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1475         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1476
1477         spin_unlock(&(image->lock));
1478
1479         mutex_unlock(&(bridge->vme_rmw));
1480
1481         return result;
1482 }
1483
1484 static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace,
1485         vme_cycle_t cycle, vme_width_t dwidth)
1486 {
1487         /* Setup 2eSST speeds */
1488         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1489         case VME_2eSST160:
1490                 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1491                 break;
1492         case VME_2eSST267:
1493                 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1494                 break;
1495         case VME_2eSST320:
1496                 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1497                 break;
1498         }
1499
1500         /* Setup cycle types */
1501         if (cycle & VME_SCT) {
1502                 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1503         }
1504         if (cycle & VME_BLT) {
1505                 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1506         }
1507         if (cycle & VME_MBLT) {
1508                 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1509         }
1510         if (cycle & VME_2eVME) {
1511                 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1512         }
1513         if (cycle & VME_2eSST) {
1514                 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1515         }
1516         if (cycle & VME_2eSSTB) {
1517                 printk("Currently not setting Broadcast Select Registers\n");
1518                 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1519         }
1520
1521         /* Setup data width */
1522         switch (dwidth) {
1523         case VME_D16:
1524                 *attr |= TSI148_LCSR_DSAT_DBW_16;
1525                 break;
1526         case VME_D32:
1527                 *attr |= TSI148_LCSR_DSAT_DBW_32;
1528                 break;
1529         default:
1530                 printk("Invalid data width\n");
1531                 return -EINVAL;
1532         }
1533
1534         /* Setup address space */
1535         switch (aspace) {
1536         case VME_A16:
1537                 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1538                 break;
1539         case VME_A24:
1540                 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1541                 break;
1542         case VME_A32:
1543                 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1544                 break;
1545         case VME_A64:
1546                 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1547                 break;
1548         case VME_CRCSR:
1549                 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1550                 break;
1551         case VME_USER1:
1552                 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1553                 break;
1554         case VME_USER2:
1555                 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1556                 break;
1557         case VME_USER3:
1558                 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1559                 break;
1560         case VME_USER4:
1561                 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1562                 break;
1563         default:
1564                 printk("Invalid address space\n");
1565                 return -EINVAL;
1566                 break;
1567         }
1568
1569         if (cycle & VME_SUPER)
1570                 *attr |= TSI148_LCSR_DSAT_SUP;
1571         if (cycle & VME_PROG)
1572                 *attr |= TSI148_LCSR_DSAT_PGM;
1573
1574         return 0;
1575 }
1576
1577 static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace,
1578         vme_cycle_t cycle, vme_width_t dwidth)
1579 {
1580         /* Setup 2eSST speeds */
1581         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1582         case VME_2eSST160:
1583                 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1584                 break;
1585         case VME_2eSST267:
1586                 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1587                 break;
1588         case VME_2eSST320:
1589                 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1590                 break;
1591         }
1592
1593         /* Setup cycle types */
1594         if (cycle & VME_SCT) {
1595                 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1596         }
1597         if (cycle & VME_BLT) {
1598                 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1599         }
1600         if (cycle & VME_MBLT) {
1601                 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1602         }
1603         if (cycle & VME_2eVME) {
1604                 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1605         }
1606         if (cycle & VME_2eSST) {
1607                 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1608         }
1609         if (cycle & VME_2eSSTB) {
1610                 printk("Currently not setting Broadcast Select Registers\n");
1611                 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1612         }
1613
1614         /* Setup data width */
1615         switch (dwidth) {
1616         case VME_D16:
1617                 *attr |= TSI148_LCSR_DDAT_DBW_16;
1618                 break;
1619         case VME_D32:
1620                 *attr |= TSI148_LCSR_DDAT_DBW_32;
1621                 break;
1622         default:
1623                 printk("Invalid data width\n");
1624                 return -EINVAL;
1625         }
1626
1627         /* Setup address space */
1628         switch (aspace) {
1629         case VME_A16:
1630                 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1631                 break;
1632         case VME_A24:
1633                 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1634                 break;
1635         case VME_A32:
1636                 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1637                 break;
1638         case VME_A64:
1639                 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1640                 break;
1641         case VME_CRCSR:
1642                 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1643                 break;
1644         case VME_USER1:
1645                 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1646                 break;
1647         case VME_USER2:
1648                 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1649                 break;
1650         case VME_USER3:
1651                 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1652                 break;
1653         case VME_USER4:
1654                 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1655                 break;
1656         default:
1657                 printk("Invalid address space\n");
1658                 return -EINVAL;
1659                 break;
1660         }
1661
1662         if (cycle & VME_SUPER)
1663                 *attr |= TSI148_LCSR_DDAT_SUP;
1664         if (cycle & VME_PROG)
1665                 *attr |= TSI148_LCSR_DDAT_PGM;
1666
1667         return 0;
1668 }
1669
1670 /*
1671  * Add a link list descriptor to the list
1672  *
1673  * XXX Need to handle 2eSST Broadcast select bits
1674  */
1675 int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
1676         struct vme_dma_attr *dest, size_t count)
1677 {
1678         struct tsi148_dma_entry *entry, *prev;
1679         u32 address_high, address_low;
1680         struct vme_dma_pattern *pattern_attr;
1681         struct vme_dma_pci *pci_attr;
1682         struct vme_dma_vme *vme_attr;
1683         dma_addr_t desc_ptr;
1684         int retval = 0;
1685
1686         /* XXX descriptor must be aligned on 64-bit boundaries */
1687         entry = (struct tsi148_dma_entry *)kmalloc(
1688                 sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1689         if (entry == NULL) {
1690                 printk("Failed to allocate memory for dma resource "
1691                         "structure\n");
1692                 retval = -ENOMEM;
1693                 goto err_mem;
1694         }
1695
1696         /* Test descriptor alignment */
1697         if ((unsigned long)&(entry->descriptor) & 0x7) {
1698                 printk("Descriptor not aligned to 8 byte boundary as "
1699                         "required: %p\n", &(entry->descriptor));
1700                 retval = -EINVAL;
1701                 goto err_align;
1702         }
1703
1704         /* Given we are going to fill out the structure, we probably don't
1705          * need to zero it, but better safe than sorry for now.
1706          */
1707         memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1708
1709         /* Fill out source part */
1710         switch (src->type) {
1711         case VME_DMA_PATTERN:
1712                 pattern_attr = (struct vme_dma_pattern *)src->private;
1713
1714                 entry->descriptor.dsal = pattern_attr->pattern;
1715                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1716                 /* Default behaviour is 32 bit pattern */
1717                 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
1718                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1719                 }
1720                 /* It seems that the default behaviour is to increment */
1721                 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
1722                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1723                 }
1724                 break;
1725         case VME_DMA_PCI:
1726                 pci_attr = (struct vme_dma_pci *)src->private;
1727
1728                 reg_split((unsigned long long)pci_attr->address, &address_high,
1729                         &address_low);
1730                 entry->descriptor.dsau = address_high;
1731                 entry->descriptor.dsal = address_low;
1732                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1733                 break;
1734         case VME_DMA_VME:
1735                 vme_attr = (struct vme_dma_vme *)src->private;
1736
1737                 reg_split((unsigned long long)vme_attr->address, &address_high,
1738                         &address_low);
1739                 entry->descriptor.dsau = address_high;
1740                 entry->descriptor.dsal = address_low;
1741                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1742
1743                 retval = tsi148_dma_set_vme_src_attributes(
1744                         &(entry->descriptor.dsat), vme_attr->aspace,
1745                         vme_attr->cycle, vme_attr->dwidth);
1746                 if(retval < 0 )
1747                         goto err_source;
1748                 break;
1749         default:
1750                 printk("Invalid source type\n");
1751                 retval = -EINVAL;
1752                 goto err_source;
1753                 break;
1754         }
1755
1756         /* Assume last link - this will be over-written by adding another */
1757         entry->descriptor.dnlau = 0;
1758         entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1759
1760
1761         /* Fill out destination part */
1762         switch (dest->type) {
1763         case VME_DMA_PCI:
1764                 pci_attr = (struct vme_dma_pci *)dest->private;
1765
1766                 reg_split((unsigned long long)pci_attr->address, &address_high,
1767                         &address_low);
1768                 entry->descriptor.ddau = address_high;
1769                 entry->descriptor.ddal = address_low;
1770                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1771                 break;
1772         case VME_DMA_VME:
1773                 vme_attr = (struct vme_dma_vme *)dest->private;
1774
1775                 reg_split((unsigned long long)vme_attr->address, &address_high,
1776                         &address_low);
1777                 entry->descriptor.ddau = address_high;
1778                 entry->descriptor.ddal = address_low;
1779                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1780
1781                 retval = tsi148_dma_set_vme_dest_attributes(
1782                         &(entry->descriptor.ddat), vme_attr->aspace,
1783                         vme_attr->cycle, vme_attr->dwidth);
1784                 if(retval < 0 )
1785                         goto err_dest;
1786                 break;
1787         default:
1788                 printk("Invalid destination type\n");
1789                 retval = -EINVAL;
1790                 goto err_dest;
1791                 break;
1792         }
1793
1794         /* Fill out count */
1795         entry->descriptor.dcnt = (u32)count;
1796
1797         /* Add to list */
1798         list_add_tail(&(entry->list), &(list->entries));
1799
1800         /* Fill out previous descriptors "Next Address" */
1801         if(entry->list.prev != &(list->entries)){
1802                 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1803                         list);
1804                 /* We need the bus address for the pointer */
1805                 desc_ptr = virt_to_bus(&(entry->descriptor));
1806                 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1807                         &(prev->descriptor.dnlal));
1808         }
1809
1810         return 0;
1811
1812 err_dest:
1813 err_source:
1814 err_align:
1815                 kfree(entry);
1816 err_mem:
1817         return retval;
1818 }
1819
1820 /*
1821  * Check to see if the provided DMA channel is busy.
1822  */
1823 static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1824 {
1825         u32 tmp;
1826         struct tsi148_driver *bridge;
1827
1828         bridge = tsi148_bridge->driver_priv;
1829
1830         tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1831                 TSI148_LCSR_OFFSET_DSTA);
1832
1833         if (tmp & TSI148_LCSR_DSTA_BSY)
1834                 return 0;
1835         else
1836                 return 1;
1837
1838 }
1839
1840 /*
1841  * Execute a previously generated link list
1842  *
1843  * XXX Need to provide control register configuration.
1844  */
1845 int tsi148_dma_list_exec(struct vme_dma_list *list)
1846 {
1847         struct vme_dma_resource *ctrlr;
1848         int channel, retval = 0;
1849         struct tsi148_dma_entry *entry;
1850         dma_addr_t bus_addr;
1851         u32 bus_addr_high, bus_addr_low;
1852         u32 val, dctlreg = 0;
1853 #if 0
1854         int x;
1855 #endif
1856         struct tsi148_driver *bridge;
1857
1858         ctrlr = list->parent;
1859
1860         bridge = ctrlr->parent->driver_priv;
1861
1862         mutex_lock(&(ctrlr->mtx));
1863
1864         channel = ctrlr->number;
1865
1866         if (! list_empty(&(ctrlr->running))) {
1867                 /*
1868                  * XXX We have an active DMA transfer and currently haven't
1869                  *     sorted out the mechanism for "pending" DMA transfers.
1870                  *     Return busy.
1871                  */
1872                 /* Need to add to pending here */
1873                 mutex_unlock(&(ctrlr->mtx));
1874                 return -EBUSY;
1875         } else {
1876                 list_add(&(list->list), &(ctrlr->running));
1877         }
1878 #if 0
1879         /* XXX Still todo */
1880         for (x = 0; x < 8; x++) {       /* vme block size */
1881                 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
1882                         break;
1883                 }
1884         }
1885         if (x == 8)
1886                 x = 7;
1887         dctlreg |= (x << 12);
1888
1889         for (x = 0; x < 8; x++) {       /* pci block size */
1890                 if ((32 << x) >= vmeDma->maxPciBlockSize) {
1891                         break;
1892                 }
1893         }
1894         if (x == 8)
1895                 x = 7;
1896         dctlreg |= (x << 4);
1897
1898         if (vmeDma->vmeBackOffTimer) {
1899                 for (x = 1; x < 8; x++) {       /* vme timer */
1900                         if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
1901                                 break;
1902                         }
1903                 }
1904                 if (x == 8)
1905                         x = 7;
1906                 dctlreg |= (x << 8);
1907         }
1908
1909         if (vmeDma->pciBackOffTimer) {
1910                 for (x = 1; x < 8; x++) {       /* pci timer */
1911                         if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
1912                                 break;
1913                         }
1914                 }
1915                 if (x == 8)
1916                         x = 7;
1917                 dctlreg |= (x << 0);
1918         }
1919 #endif
1920
1921         /* Get first bus address and write into registers */
1922         entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1923                 list);
1924
1925         bus_addr = virt_to_bus(&(entry->descriptor));
1926
1927         mutex_unlock(&(ctrlr->mtx));
1928
1929         reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1930
1931         iowrite32be(bus_addr_high, bridge->base +
1932                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1933         iowrite32be(bus_addr_low, bridge->base +
1934                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1935
1936         /* Start the operation */
1937         iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1938                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1939
1940         wait_event_interruptible(bridge->dma_queue[channel],
1941                 tsi148_dma_busy(ctrlr->parent, channel));
1942         /*
1943          * Read status register, this register is valid until we kick off a
1944          * new transfer.
1945          */
1946         val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1947                 TSI148_LCSR_OFFSET_DSTA);
1948
1949         if (val & TSI148_LCSR_DSTA_VBE) {
1950                 printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val);
1951                 retval = -EIO;
1952         }
1953
1954         /* Remove list from running list */
1955         mutex_lock(&(ctrlr->mtx));
1956         list_del(&(list->list));
1957         mutex_unlock(&(ctrlr->mtx));
1958
1959         return retval;
1960 }
1961
1962 /*
1963  * Clean up a previously generated link list
1964  *
1965  * We have a separate function, don't assume that the chain can't be reused.
1966  */
1967 int tsi148_dma_list_empty(struct vme_dma_list *list)
1968 {
1969         struct list_head *pos, *temp;
1970         struct tsi148_dma_entry *entry;
1971
1972         /* detach and free each entry */
1973         list_for_each_safe(pos, temp, &(list->entries)) {
1974                 list_del(pos);
1975                 entry = list_entry(pos, struct tsi148_dma_entry, list);
1976                 kfree(entry);
1977         }
1978
1979         return (0);
1980 }
1981
1982 /*
1983  * All 4 location monitors reside at the same base - this is therefore a
1984  * system wide configuration.
1985  *
1986  * This does not enable the LM monitor - that should be done when the first
1987  * callback is attached and disabled when the last callback is removed.
1988  */
1989 int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1990         vme_address_t aspace, vme_cycle_t cycle)
1991 {
1992         u32 lm_base_high, lm_base_low, lm_ctl = 0;
1993         int i;
1994         struct tsi148_driver *bridge;
1995
1996         bridge = lm->parent->driver_priv;
1997
1998         mutex_lock(&(lm->mtx));
1999
2000         /* If we already have a callback attached, we can't move it! */
2001         for (i = 0; i < lm->monitors; i++) {
2002                 if (bridge->lm_callback[i] != NULL) {
2003                         mutex_unlock(&(lm->mtx));
2004                         printk("Location monitor callback attached, can't "
2005                                 "reset\n");
2006                         return -EBUSY;
2007                 }
2008         }
2009
2010         switch (aspace) {
2011         case VME_A16:
2012                 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
2013                 break;
2014         case VME_A24:
2015                 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
2016                 break;
2017         case VME_A32:
2018                 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
2019                 break;
2020         case VME_A64:
2021                 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
2022                 break;
2023         default:
2024                 mutex_unlock(&(lm->mtx));
2025                 printk("Invalid address space\n");
2026                 return -EINVAL;
2027                 break;
2028         }
2029
2030         if (cycle & VME_SUPER)
2031                 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
2032         if (cycle & VME_USER)
2033                 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
2034         if (cycle & VME_PROG)
2035                 lm_ctl |= TSI148_LCSR_LMAT_PGM;
2036         if (cycle & VME_DATA)
2037                 lm_ctl |= TSI148_LCSR_LMAT_DATA;
2038
2039         reg_split(lm_base, &lm_base_high, &lm_base_low);
2040
2041         iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
2042         iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
2043         iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2044
2045         mutex_unlock(&(lm->mtx));
2046
2047         return 0;
2048 }
2049
2050 /* Get configuration of the callback monitor and return whether it is enabled
2051  * or disabled.
2052  */
2053 int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
2054         vme_address_t *aspace, vme_cycle_t *cycle)
2055 {
2056         u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2057         struct tsi148_driver *bridge;
2058
2059         bridge = lm->parent->driver_priv;
2060
2061         mutex_lock(&(lm->mtx));
2062
2063         lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2064         lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2065         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2066
2067         reg_join(lm_base_high, lm_base_low, lm_base);
2068
2069         if (lm_ctl & TSI148_LCSR_LMAT_EN)
2070                 enabled = 1;
2071
2072         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
2073                 *aspace |= VME_A16;
2074         }
2075         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
2076                 *aspace |= VME_A24;
2077         }
2078         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
2079                 *aspace |= VME_A32;
2080         }
2081         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
2082                 *aspace |= VME_A64;
2083         }
2084
2085         if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2086                 *cycle |= VME_SUPER;
2087         if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2088                 *cycle |= VME_USER;
2089         if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2090                 *cycle |= VME_PROG;
2091         if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2092                 *cycle |= VME_DATA;
2093
2094         mutex_unlock(&(lm->mtx));
2095
2096         return enabled;
2097 }
2098
2099 /*
2100  * Attach a callback to a specific location monitor.
2101  *
2102  * Callback will be passed the monitor triggered.
2103  */
2104 int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2105         void (*callback)(int))
2106 {
2107         u32 lm_ctl, tmp;
2108         struct tsi148_driver *bridge;
2109
2110         bridge = lm->parent->driver_priv;
2111
2112         mutex_lock(&(lm->mtx));
2113
2114         /* Ensure that the location monitor is configured - need PGM or DATA */
2115         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2116         if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2117                 mutex_unlock(&(lm->mtx));
2118                 printk("Location monitor not properly configured\n");
2119                 return -EINVAL;
2120         }
2121
2122         /* Check that a callback isn't already attached */
2123         if (bridge->lm_callback[monitor] != NULL) {
2124                 mutex_unlock(&(lm->mtx));
2125                 printk("Existing callback attached\n");
2126                 return -EBUSY;
2127         }
2128
2129         /* Attach callback */
2130         bridge->lm_callback[monitor] = callback;
2131
2132         /* Enable Location Monitor interrupt */
2133         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2134         tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2135         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2136
2137         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2138         tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2139         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2140
2141         /* Ensure that global Location Monitor Enable set */
2142         if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2143                 lm_ctl |= TSI148_LCSR_LMAT_EN;
2144                 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2145         }
2146
2147         mutex_unlock(&(lm->mtx));
2148
2149         return 0;
2150 }
2151
2152 /*
2153  * Detach a callback function forn a specific location monitor.
2154  */
2155 int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2156 {
2157         u32 lm_en, tmp;
2158         struct tsi148_driver *bridge;
2159
2160         bridge = lm->parent->driver_priv;
2161
2162         mutex_lock(&(lm->mtx));
2163
2164         /* Disable Location Monitor and ensure previous interrupts are clear */
2165         lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2166         lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2167         iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2168
2169         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2170         tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2171         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2172
2173         iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2174                  bridge->base + TSI148_LCSR_INTC);
2175
2176         /* Detach callback */
2177         bridge->lm_callback[monitor] = NULL;
2178
2179         /* If all location monitors disabled, disable global Location Monitor */
2180         if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2181                         TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2182                 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2183                 tmp &= ~TSI148_LCSR_LMAT_EN;
2184                 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2185         }
2186
2187         mutex_unlock(&(lm->mtx));
2188
2189         return 0;
2190 }
2191
2192 /*
2193  * Determine Geographical Addressing
2194  */
2195 int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2196 {
2197         u32 slot = 0;
2198         struct tsi148_driver *bridge;
2199
2200         bridge = tsi148_bridge->driver_priv;
2201
2202         if (!geoid) {
2203                 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2204                 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2205         } else
2206                 slot = geoid;
2207
2208         return (int)slot;
2209 }
2210
2211 static int __init tsi148_init(void)
2212 {
2213         return pci_register_driver(&tsi148_driver);
2214 }
2215
2216 /*
2217  * Configure CR/CSR space
2218  *
2219  * Access to the CR/CSR can be configured at power-up. The location of the
2220  * CR/CSR registers in the CR/CSR address space is determined by the boards
2221  * Auto-ID or Geographic address. This function ensures that the window is
2222  * enabled at an offset consistent with the boards geopgraphic address.
2223  *
2224  * Each board has a 512kB window, with the highest 4kB being used for the
2225  * boards registers, this means there is a fix length 508kB window which must
2226  * be mapped onto PCI memory.
2227  */
2228 static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2229         struct pci_dev *pdev)
2230 {
2231         u32 cbar, crat, vstat;
2232         u32 crcsr_bus_high, crcsr_bus_low;
2233         int retval;
2234         struct tsi148_driver *bridge;
2235
2236         bridge = tsi148_bridge->driver_priv;
2237
2238         /* Allocate mem for CR/CSR image */
2239         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2240                 &(bridge->crcsr_bus));
2241         if (bridge->crcsr_kernel == NULL) {
2242                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
2243                         "image\n");
2244                 return -ENOMEM;
2245         }
2246
2247         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2248
2249         reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2250
2251         iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2252         iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2253
2254         /* Ensure that the CR/CSR is configured at the correct offset */
2255         cbar = ioread32be(bridge->base + TSI148_CBAR);
2256         cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2257
2258         vstat = tsi148_slot_get(tsi148_bridge);
2259
2260         if (cbar != vstat) {
2261                 cbar = vstat;
2262                 dev_info(&pdev->dev, "Setting CR/CSR offset\n");
2263                 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2264         }
2265         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar);
2266
2267         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2268         if (crat & TSI148_LCSR_CRAT_EN) {
2269                 dev_info(&pdev->dev, "Enabling CR/CSR space\n");
2270                 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2271                         bridge->base + TSI148_LCSR_CRAT);
2272         } else
2273                 dev_info(&pdev->dev, "CR/CSR already enabled\n");
2274
2275         /* If we want flushed, error-checked writes, set up a window
2276          * over the CR/CSR registers. We read from here to safely flush
2277          * through VME writes.
2278          */
2279         if(err_chk) {
2280                 retval = tsi148_master_set(bridge->flush_image, 1,
2281                         (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2282                         VME_D16);
2283                 if (retval)
2284                         dev_err(&pdev->dev, "Configuring flush image failed\n");
2285         }
2286
2287         return 0;
2288
2289 }
2290
2291 static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2292         struct pci_dev *pdev)
2293 {
2294         u32 crat;
2295         struct tsi148_driver *bridge;
2296
2297         bridge = tsi148_bridge->driver_priv;
2298
2299         /* Turn off CR/CSR space */
2300         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2301         iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2302                 bridge->base + TSI148_LCSR_CRAT);
2303
2304         /* Free image */
2305         iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2306         iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2307
2308         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2309                 bridge->crcsr_bus);
2310 }
2311
2312 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2313 {
2314         int retval, i, master_num;
2315         u32 data;
2316         struct list_head *pos = NULL;
2317         struct vme_bridge *tsi148_bridge;
2318         struct tsi148_driver *tsi148_device;
2319         struct vme_master_resource *master_image;
2320         struct vme_slave_resource *slave_image;
2321         struct vme_dma_resource *dma_ctrlr;
2322         struct vme_lm_resource *lm;
2323
2324         /* If we want to support more than one of each bridge, we need to
2325          * dynamically generate this so we get one per device
2326          */
2327         tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
2328                 GFP_KERNEL);
2329         if (tsi148_bridge == NULL) {
2330                 dev_err(&pdev->dev, "Failed to allocate memory for device "
2331                         "structure\n");
2332                 retval = -ENOMEM;
2333                 goto err_struct;
2334         }
2335
2336         memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2337
2338         tsi148_device = kmalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2339         if (tsi148_device == NULL) {
2340                 dev_err(&pdev->dev, "Failed to allocate memory for device "
2341                         "structure\n");
2342                 retval = -ENOMEM;
2343                 goto err_driver;
2344         }
2345
2346         memset(tsi148_device, 0, sizeof(struct tsi148_driver));
2347
2348         tsi148_bridge->driver_priv = tsi148_device;
2349
2350         /* Enable the device */
2351         retval = pci_enable_device(pdev);
2352         if (retval) {
2353                 dev_err(&pdev->dev, "Unable to enable device\n");
2354                 goto err_enable;
2355         }
2356
2357         /* Map Registers */
2358         retval = pci_request_regions(pdev, driver_name);
2359         if (retval) {
2360                 dev_err(&pdev->dev, "Unable to reserve resources\n");
2361                 goto err_resource;
2362         }
2363
2364         /* map registers in BAR 0 */
2365         tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2366                 4096);
2367         if (!tsi148_device->base) {
2368                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2369                 retval = -EIO;
2370                 goto err_remap;
2371         }
2372
2373         /* Check to see if the mapping worked out */
2374         data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2375         if (data != PCI_VENDOR_ID_TUNDRA) {
2376                 dev_err(&pdev->dev, "CRG region check failed\n");
2377                 retval = -EIO;
2378                 goto err_test;
2379         }
2380
2381         /* Initialize wait queues & mutual exclusion flags */
2382         init_waitqueue_head(&(tsi148_device->dma_queue[0]));
2383         init_waitqueue_head(&(tsi148_device->dma_queue[1]));
2384         init_waitqueue_head(&(tsi148_device->iack_queue));
2385         mutex_init(&(tsi148_device->vme_int));
2386         mutex_init(&(tsi148_device->vme_rmw));
2387
2388         tsi148_bridge->parent = &(pdev->dev);
2389         strcpy(tsi148_bridge->name, driver_name);
2390
2391         /* Setup IRQ */
2392         retval = tsi148_irq_init(tsi148_bridge);
2393         if (retval != 0) {
2394                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2395                 goto err_irq;
2396         }
2397
2398         /* If we are going to flush writes, we need to read from the VME bus.
2399          * We need to do this safely, thus we read the devices own CR/CSR
2400          * register. To do this we must set up a window in CR/CSR space and
2401          * hence have one less master window resource available.
2402          */
2403         master_num = TSI148_MAX_MASTER;
2404         if(err_chk){
2405                 master_num--;
2406
2407                 tsi148_device->flush_image = (struct vme_master_resource *)
2408                         kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2409                 if (tsi148_device->flush_image == NULL) {
2410                         dev_err(&pdev->dev, "Failed to allocate memory for "
2411                         "flush resource structure\n");
2412                         retval = -ENOMEM;
2413                         goto err_master;
2414                 }
2415                 tsi148_device->flush_image->parent = tsi148_bridge;
2416                 spin_lock_init(&(tsi148_device->flush_image->lock));
2417                 tsi148_device->flush_image->locked = 1;
2418                 tsi148_device->flush_image->number = master_num;
2419                 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2420                         VME_A32 | VME_A64;
2421                 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2422                         VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2423                         VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2424                         VME_USER | VME_PROG | VME_DATA;
2425                 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2426                 memset(&(tsi148_device->flush_image->bus_resource), 0,
2427                         sizeof(struct resource));
2428                 tsi148_device->flush_image->kern_base  = NULL;
2429         }
2430
2431         /* Add master windows to list */
2432         INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2433         for (i = 0; i < master_num; i++) {
2434                 master_image = (struct vme_master_resource *)kmalloc(
2435                         sizeof(struct vme_master_resource), GFP_KERNEL);
2436                 if (master_image == NULL) {
2437                         dev_err(&pdev->dev, "Failed to allocate memory for "
2438                         "master resource structure\n");
2439                         retval = -ENOMEM;
2440                         goto err_master;
2441                 }
2442                 master_image->parent = tsi148_bridge;
2443                 spin_lock_init(&(master_image->lock));
2444                 master_image->locked = 0;
2445                 master_image->number = i;
2446                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2447                         VME_A64;
2448                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2449                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2450                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2451                         VME_PROG | VME_DATA;
2452                 master_image->width_attr = VME_D16 | VME_D32;
2453                 memset(&(master_image->bus_resource), 0,
2454                         sizeof(struct resource));
2455                 master_image->kern_base  = NULL;
2456                 list_add_tail(&(master_image->list),
2457                         &(tsi148_bridge->master_resources));
2458         }
2459
2460         /* Add slave windows to list */
2461         INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2462         for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2463                 slave_image = (struct vme_slave_resource *)kmalloc(
2464                         sizeof(struct vme_slave_resource), GFP_KERNEL);
2465                 if (slave_image == NULL) {
2466                         dev_err(&pdev->dev, "Failed to allocate memory for "
2467                         "slave resource structure\n");
2468                         retval = -ENOMEM;
2469                         goto err_slave;
2470                 }
2471                 slave_image->parent = tsi148_bridge;
2472                 mutex_init(&(slave_image->mtx));
2473                 slave_image->locked = 0;
2474                 slave_image->number = i;
2475                 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2476                         VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2477                         VME_USER3 | VME_USER4;
2478                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2479                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2480                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2481                         VME_PROG | VME_DATA;
2482                 list_add_tail(&(slave_image->list),
2483                         &(tsi148_bridge->slave_resources));
2484         }
2485
2486         /* Add dma engines to list */
2487         INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2488         for (i = 0; i < TSI148_MAX_DMA; i++) {
2489                 dma_ctrlr = (struct vme_dma_resource *)kmalloc(
2490                         sizeof(struct vme_dma_resource), GFP_KERNEL);
2491                 if (dma_ctrlr == NULL) {
2492                         dev_err(&pdev->dev, "Failed to allocate memory for "
2493                         "dma resource structure\n");
2494                         retval = -ENOMEM;
2495                         goto err_dma;
2496                 }
2497                 dma_ctrlr->parent = tsi148_bridge;
2498                 mutex_init(&(dma_ctrlr->mtx));
2499                 dma_ctrlr->locked = 0;
2500                 dma_ctrlr->number = i;
2501                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2502                         VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2503                         VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2504                         VME_DMA_PATTERN_TO_MEM;
2505                 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2506                 INIT_LIST_HEAD(&(dma_ctrlr->running));
2507                 list_add_tail(&(dma_ctrlr->list),
2508                         &(tsi148_bridge->dma_resources));
2509         }
2510
2511         /* Add location monitor to list */
2512         INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2513         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2514         if (lm == NULL) {
2515                 dev_err(&pdev->dev, "Failed to allocate memory for "
2516                 "location monitor resource structure\n");
2517                 retval = -ENOMEM;
2518                 goto err_lm;
2519         }
2520         lm->parent = tsi148_bridge;
2521         mutex_init(&(lm->mtx));
2522         lm->locked = 0;
2523         lm->number = 1;
2524         lm->monitors = 4;
2525         list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2526
2527         tsi148_bridge->slave_get = tsi148_slave_get;
2528         tsi148_bridge->slave_set = tsi148_slave_set;
2529         tsi148_bridge->master_get = tsi148_master_get;
2530         tsi148_bridge->master_set = tsi148_master_set;
2531         tsi148_bridge->master_read = tsi148_master_read;
2532         tsi148_bridge->master_write = tsi148_master_write;
2533         tsi148_bridge->master_rmw = tsi148_master_rmw;
2534         tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2535         tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2536         tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2537         tsi148_bridge->irq_set = tsi148_irq_set;
2538         tsi148_bridge->irq_generate = tsi148_irq_generate;
2539         tsi148_bridge->lm_set = tsi148_lm_set;
2540         tsi148_bridge->lm_get = tsi148_lm_get;
2541         tsi148_bridge->lm_attach = tsi148_lm_attach;
2542         tsi148_bridge->lm_detach = tsi148_lm_detach;
2543         tsi148_bridge->slot_get = tsi148_slot_get;
2544
2545         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2546         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2547                 (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
2548         if (!geoid)
2549                 dev_info(&pdev->dev, "VME geographical address is %d\n",
2550                         data & TSI148_LCSR_VSTAT_GA_M);
2551         else
2552                 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2553                         geoid);
2554
2555         dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2556                 err_chk ? "enabled" : "disabled");
2557
2558         if (tsi148_crcsr_init(tsi148_bridge, pdev))
2559                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2560                 goto err_crcsr;
2561
2562         retval = vme_register_bridge(tsi148_bridge);
2563         if (retval != 0) {
2564                 dev_err(&pdev->dev, "Chip Registration failed.\n");
2565                 goto err_reg;
2566         }
2567
2568         pci_set_drvdata(pdev, tsi148_bridge);
2569
2570         /* Clear VME bus "board fail", and "power-up reset" lines */
2571         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2572         data &= ~TSI148_LCSR_VSTAT_BRDFL;
2573         data |= TSI148_LCSR_VSTAT_CPURST;
2574         iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2575
2576         return 0;
2577
2578         vme_unregister_bridge(tsi148_bridge);
2579 err_reg:
2580         tsi148_crcsr_exit(tsi148_bridge, pdev);
2581 err_crcsr:
2582 err_lm:
2583         /* resources are stored in link list */
2584         list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2585                 lm = list_entry(pos, struct vme_lm_resource, list);
2586                 list_del(pos);
2587                 kfree(lm);
2588         }
2589 err_dma:
2590         /* resources are stored in link list */
2591         list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2592                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2593                 list_del(pos);
2594                 kfree(dma_ctrlr);
2595         }
2596 err_slave:
2597         /* resources are stored in link list */
2598         list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2599                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2600                 list_del(pos);
2601                 kfree(slave_image);
2602         }
2603 err_master:
2604         /* resources are stored in link list */
2605         list_for_each(pos, &(tsi148_bridge->master_resources)) {
2606                 master_image = list_entry(pos, struct vme_master_resource,                              list);
2607                 list_del(pos);
2608                 kfree(master_image);
2609         }
2610
2611         tsi148_irq_exit(tsi148_device, pdev);
2612 err_irq:
2613 err_test:
2614         iounmap(tsi148_device->base);
2615 err_remap:
2616         pci_release_regions(pdev);
2617 err_resource:
2618         pci_disable_device(pdev);
2619 err_enable:
2620         kfree(tsi148_device);
2621 err_driver:
2622         kfree(tsi148_bridge);
2623 err_struct:
2624         return retval;
2625
2626 }
2627
2628 static void tsi148_remove(struct pci_dev *pdev)
2629 {
2630         struct list_head *pos = NULL;
2631         struct vme_master_resource *master_image;
2632         struct vme_slave_resource *slave_image;
2633         struct vme_dma_resource *dma_ctrlr;
2634         int i;
2635         struct tsi148_driver *bridge;
2636         struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2637
2638         bridge = tsi148_bridge->driver_priv;
2639
2640
2641         dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2642
2643         /*
2644          *  Shutdown all inbound and outbound windows.
2645          */
2646         for (i = 0; i < 8; i++) {
2647                 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2648                         TSI148_LCSR_OFFSET_ITAT);
2649                 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2650                         TSI148_LCSR_OFFSET_OTAT);
2651         }
2652
2653         /*
2654          *  Shutdown Location monitor.
2655          */
2656         iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2657
2658         /*
2659          *  Shutdown CRG map.
2660          */
2661         iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2662
2663         /*
2664          *  Clear error status.
2665          */
2666         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2667         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2668         iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2669
2670         /*
2671          *  Remove VIRQ interrupt (if any)
2672          */
2673         if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2674                 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2675
2676         /*
2677          *  Map all Interrupts to PCI INTA
2678          */
2679         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2680         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2681
2682         tsi148_irq_exit(bridge, pdev);
2683
2684         vme_unregister_bridge(tsi148_bridge);
2685
2686         tsi148_crcsr_exit(tsi148_bridge, pdev);
2687
2688         /* resources are stored in link list */
2689         list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2690                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2691                 list_del(pos);
2692                 kfree(dma_ctrlr);
2693         }
2694
2695         /* resources are stored in link list */
2696         list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2697                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2698                 list_del(pos);
2699                 kfree(slave_image);
2700         }
2701
2702         /* resources are stored in link list */
2703         list_for_each(pos, &(tsi148_bridge->master_resources)) {
2704                 master_image = list_entry(pos, struct vme_master_resource,
2705                         list);
2706                 list_del(pos);
2707                 kfree(master_image);
2708         }
2709
2710         tsi148_irq_exit(bridge, pdev);
2711
2712         iounmap(bridge->base);
2713
2714         pci_release_regions(pdev);
2715
2716         pci_disable_device(pdev);
2717
2718         kfree(tsi148_bridge->driver_priv);
2719
2720         kfree(tsi148_bridge);
2721 }
2722
2723 static void __exit tsi148_exit(void)
2724 {
2725         pci_unregister_driver(&tsi148_driver);
2726
2727         printk(KERN_DEBUG "Driver removed.\n");
2728 }
2729
2730 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2731 module_param(err_chk, bool, 0);
2732
2733 MODULE_PARM_DESC(geoid, "Override geographical addressing");
2734 module_param(geoid, int, 0);
2735
2736 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2737 MODULE_LICENSE("GPL");
2738
2739 module_init(tsi148_init);
2740 module_exit(tsi148_exit);
2741
2742 /*----------------------------------------------------------------------------
2743  * STAGING
2744  *--------------------------------------------------------------------------*/
2745
2746 #if 0
2747 /*
2748  * Direct Mode DMA transfer
2749  *
2750  * XXX Not looking at direct mode for now, we can always use link list mode
2751  *     with a single entry.
2752  */
2753 int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src,
2754         struct vme_dma_attr dest, size_t count)
2755 {
2756         u32 dctlreg = 0;
2757         unsigned int tmp;
2758         int val;
2759         int channel, x;
2760         struct vmeDmaPacket *cur_dma;
2761         struct tsi148_dma_descriptor *dmaLL;
2762
2763         /* direct mode */
2764         dctlreg = 0x800000;
2765
2766         for (x = 0; x < 8; x++) {       /* vme block size */
2767                 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
2768                         break;
2769                 }
2770         }
2771         if (x == 8)
2772                 x = 7;
2773         dctlreg |= (x << 12);
2774
2775         for (x = 0; x < 8; x++) {       /* pci block size */
2776                 if ((32 << x) >= vmeDma->maxPciBlockSize) {
2777                         break;
2778                 }
2779         }
2780         if (x == 8)
2781                 x = 7;
2782         dctlreg |= (x << 4);
2783
2784         if (vmeDma->vmeBackOffTimer) {
2785                 for (x = 1; x < 8; x++) {       /* vme timer */
2786                         if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
2787                                 break;
2788                         }
2789                 }
2790                 if (x == 8)
2791                         x = 7;
2792                 dctlreg |= (x << 8);
2793         }
2794
2795         if (vmeDma->pciBackOffTimer) {
2796                 for (x = 1; x < 8; x++) {       /* pci timer */
2797                         if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
2798                                 break;
2799                         }
2800                 }
2801                 if (x == 8)
2802                         x = 7;
2803                 dctlreg |= (x << 0);
2804         }
2805
2806         /* Program registers for DMA transfer */
2807         iowrite32be(dmaLL->dsau, tsi148_bridge->driver_priv->base +
2808                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU);
2809         iowrite32be(dmaLL->dsal, tsi148_bridge->driver_priv->base +
2810                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL);
2811         iowrite32be(dmaLL->ddau, tsi148_bridge->driver_priv->base +
2812                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU);
2813         iowrite32be(dmaLL->ddal, tsi148_bridge->driver_priv->base +
2814                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL);
2815         iowrite32be(dmaLL->dsat, tsi148_bridge->driver_priv->base +
2816                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT);
2817         iowrite32be(dmaLL->ddat, tsi148_bridge->driver_priv->base +
2818                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT);
2819         iowrite32be(dmaLL->dcnt, tsi148_bridge->driver_priv->base +
2820                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT);
2821         iowrite32be(dmaLL->ddbs, tsi148_bridge->driver_priv->base +
2822                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS);
2823
2824         /* Start the operation */
2825         iowrite32be(dctlreg | 0x2000000, tsi148_bridge->driver_priv->base +
2826                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
2827
2828         tmp = ioread32be(tsi148_bridge->driver_priv->base +
2829                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA);
2830         wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0);
2831
2832         /*
2833          * Read status register, we should probably do this in some error
2834          * handler rather than here so that we can be sure we haven't kicked off
2835          * another DMA transfer.
2836          */
2837         val = ioread32be(tsi148_bridge->driver_priv->base +
2838                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSTA);
2839
2840         vmeDma->vmeDmaStatus = 0;
2841         if (val & 0x10000000) {
2842                 printk(KERN_ERR
2843                         "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n",
2844                         val);
2845                 vmeDma->vmeDmaStatus = val;
2846
2847         }
2848         return (0);
2849 }
2850 #endif
2851
2852 #if 0
2853
2854 /* Global VME controller information */
2855 struct pci_dev *vme_pci_dev;
2856
2857 /*
2858  * Set the VME bus arbiter with the requested attributes
2859  */
2860 int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb)
2861 {
2862         int temp_ctl = 0;
2863         int gto = 0;
2864
2865         temp_ctl = ioread32be(tsi148_bridge->driver_priv->base +
2866                 TSI148_LCSR_VCTRL);
2867         temp_ctl &= 0xFFEFFF00;
2868
2869         if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
2870                 gto = 8;
2871         } else if (vmeArb->globalTimeoutTimer > 2048) {
2872                 return (-EINVAL);
2873         } else if (vmeArb->globalTimeoutTimer == 0) {
2874                 gto = 0;
2875         } else {
2876                 gto = 1;
2877                 while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) {
2878                         gto += 1;
2879                 }
2880         }
2881         temp_ctl |= gto;
2882
2883         if (vmeArb->arbiterMode != VME_PRIORITY_MODE) {
2884                 temp_ctl |= 1 << 6;
2885         }
2886
2887         if (vmeArb->arbiterTimeoutFlag) {
2888                 temp_ctl |= 1 << 7;
2889         }
2890
2891         if (vmeArb->noEarlyReleaseFlag) {
2892                 temp_ctl |= 1 << 20;
2893         }
2894         iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base +
2895                 TSI148_LCSR_VCTRL);
2896
2897         return (0);
2898 }
2899
2900 /*
2901  * Return the attributes of the VME bus arbiter.
2902  */
2903 int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb)
2904 {
2905         int temp_ctl = 0;
2906         int gto = 0;
2907
2908
2909         temp_ctl = ioread32be(tsi148_bridge->driver_priv->base +
2910                 TSI148_LCSR_VCTRL);
2911
2912         gto = temp_ctl & 0xF;
2913         if (gto != 0) {
2914                 vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1)));
2915         }
2916
2917         if (temp_ctl & (1 << 6)) {
2918                 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
2919         } else {
2920                 vmeArb->arbiterMode = VME_PRIORITY_MODE;
2921         }
2922
2923         if (temp_ctl & (1 << 7)) {
2924                 vmeArb->arbiterTimeoutFlag = 1;
2925         }
2926
2927         if (temp_ctl & (1 << 20)) {
2928                 vmeArb->noEarlyReleaseFlag = 1;
2929         }
2930
2931         return (0);
2932 }
2933
2934 /*
2935  * Set the VME bus requestor with the requested attributes
2936  */
2937 int tempe_set_requestor(vmeRequesterCfg_t * vmeReq)
2938 {
2939         int temp_ctl = 0;
2940
2941         temp_ctl = ioread32be(tsi148_bridge->driver_priv->base +
2942                 TSI148_LCSR_VMCTRL);
2943         temp_ctl &= 0xFFFF0000;
2944
2945         if (vmeReq->releaseMode == 1) {
2946                 temp_ctl |= (1 << 3);
2947         }
2948
2949         if (vmeReq->fairMode == 1) {
2950                 temp_ctl |= (1 << 2);
2951         }
2952
2953         temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8;
2954         temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12;
2955         temp_ctl |= vmeReq->requestLevel;
2956
2957         iowrite32be(temp_ctl, tsi148_bridge->driver_priv->base +
2958                 TSI148_LCSR_VMCTRL);
2959         return (0);
2960 }
2961
2962 /*
2963  * Return the attributes of the VME bus requestor
2964  */
2965 int tempe_get_requestor(vmeRequesterCfg_t * vmeReq)
2966 {
2967         int temp_ctl = 0;
2968
2969         temp_ctl = ioread32be(tsi148_bridge->driver_priv->base +
2970                 TSI148_LCSR_VMCTRL);
2971
2972         if (temp_ctl & 0x18) {
2973                 vmeReq->releaseMode = 1;
2974         }
2975
2976         if (temp_ctl & (1 << 2)) {
2977                 vmeReq->fairMode = 1;
2978         }
2979
2980         vmeReq->requestLevel = temp_ctl & 3;
2981         vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7;
2982         vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7;
2983
2984         return (0);
2985 }
2986
2987
2988 #endif