1 /*******************************************************************
2 * Copyright © 1997-2007 Alacritech, Inc. All rights reserved
4 * $Id: sxghif.h,v 1.5 2008/07/24 19:18:22 chris Exp $
8 * This file contains structures and definitions for the
9 * Alacritech Sahara host interface
10 ******************************************************************/
15 struct sxg_ucode_regs {
16 /* Address 0 - 0x3F = Command codes 0-15 for TCB 0. Excode 0 */
17 u32 Icr; /* Code = 0 (extended), ExCode = 0 - Int control */
18 u32 RsvdReg1; /* Code = 1 - TOE -NA */
19 u32 RsvdReg2; /* Code = 2 - TOE -NA */
20 u32 RsvdReg3; /* Code = 3 - TOE -NA */
21 u32 RsvdReg4; /* Code = 4 - TOE -NA */
22 u32 RsvdReg5; /* Code = 5 - TOE -NA */
23 u32 CardUp; /* Code = 6 - Microcode initialized when 1 */
24 u32 RsvdReg7; /* Code = 7 - TOE -NA */
25 u32 ConfigStat; /* Code = 8 - Configuration data load status */
26 u32 RsvdReg9; /* Code = 9 - TOE -NA */
27 u32 CodeNotUsed[6]; /* Codes 10-15 not used. ExCode = 0 */
28 /* This brings us to ExCode 1 at address 0x40 = Interrupt status pointer */
29 u32 Isp; /* Code = 0 (extended), ExCode = 1 */
30 u32 PadEx1[15]; /* Codes 1-15 not used with extended codes */
31 /* ExCode 2 = Interrupt Status Register */
32 u32 Isr; /* Code = 0 (extended), ExCode = 2 */
34 /* ExCode 3 = Event base register. Location of event rings */
35 u32 EventBase; /* Code = 0 (extended), ExCode = 3 */
37 /* ExCode 4 = Event ring size */
38 u32 EventSize; /* Code = 0 (extended), ExCode = 4 */
40 /* ExCode 5 = TCB Buffers base address */
41 u32 TcbBase; /* Code = 0 (extended), ExCode = 5 */
43 /* ExCode 6 = TCB Composite Buffers base address */
44 u32 TcbCompBase; /* Code = 0 (extended), ExCode = 6 */
46 /* ExCode 7 = Transmit ring base address */
47 u32 XmtBase; /* Code = 0 (extended), ExCode = 7 */
49 /* ExCode 8 = Transmit ring size */
50 u32 XmtSize; /* Code = 0 (extended), ExCode = 8 */
52 /* ExCode 9 = Receive ring base address */
53 u32 RcvBase; /* Code = 0 (extended), ExCode = 9 */
55 /* ExCode 10 = Receive ring size */
56 u32 RcvSize; /* Code = 0 (extended), ExCode = 10 */
58 /* ExCode 11 = Read EEPROM/Flash Config */
59 u32 Config; /* Code = 0 (extended), ExCode = 11 */
61 /* ExCode 12 = Multicast bits 31:0 */
62 u32 McastLow; /* Code = 0 (extended), ExCode = 12 */
64 /* ExCode 13 = Multicast bits 63:32 */
65 u32 McastHigh; /* Code = 0 (extended), ExCode = 13 */
67 /* ExCode 14 = Ping */
68 u32 Ping; /* Code = 0 (extended), ExCode = 14 */
70 /* ExCode 15 = Link MTU */
71 u32 LinkMtu; /* Code = 0 (extended), ExCode = 15 */
73 /* ExCode 16 = Download synchronization */
74 u32 LoadSync; /* Code = 0 (extended), ExCode = 16 */
76 /* ExCode 17 = Upper DRAM address bits on 32-bit systems */
77 u32 Upper; /* Code = 0 (extended), ExCode = 17 */
79 /* ExCode 18 = Slowpath Send Index Address */
80 u32 SPSendIndex; /* Code = 0 (extended), ExCode = 18 */
82 /* ExCode 19 = Get ucode statistics */
83 u32 GetUcodeStats; /* Code = 0 (extended), ExCode = 19 */
85 /* ExCode 20 = Aggregation - See sxgmisc.c:SxgSetInterruptAggregation */
86 u32 Aggregation; /* Code = 0 (extended), ExCode = 20 */
88 /* ExCode 21 = Receive MDL push timer */
89 u32 PushTicks; /* Code = 0 (extended), ExCode = 21 */
91 /* ExCode 22 = ACK Frequency */
92 u32 AckFrequency; /* Code = 0 (extended), ExCode = 22 */
94 /* ExCode 23 = TOE NA */
97 /* ExCode 24 = TOE NA */
100 /* ExCode 25 = TOE NA */
101 u32 RsvdReg25; /* Code = 0 (extended), ExCode = 25 */
103 /* ExCode 26 = Receive checksum requirements */
104 u32 ReceiveChecksum; /* Code = 0 (extended), ExCode = 26 */
106 /* ExCode 27 = RSS Requirements */
107 u32 Rss; /* Code = 0 (extended), ExCode = 27 */
109 /* ExCode 28 = RSS Table */
110 u32 RssTable; /* Code = 0 (extended), ExCode = 28 */
112 /* ExCode 29 = Event ring release entries */
113 u32 EventRelease; /* Code = 0 (extended), ExCode = 29 */
115 /* ExCode 30 = Number of receive bufferlist commands on ring 0 */
116 u32 RcvCmd; /* Code = 0 (extended), ExCode = 30 */
118 /* ExCode 31 = slowpath transmit command - Data[31:0] = 1 */
119 u32 XmtCmd; /* Code = 0 (extended), ExCode = 31 */
121 /* ExCode 32 = Dump command */
122 u32 DumpCmd; /* Code = 0 (extended), ExCode = 32 */
124 /* ExCode 33 = Debug command */
125 u32 DebugCmd; /* Code = 0 (extended), ExCode = 33 */
128 * There are 128 possible extended commands - each of account for 16
129 * words (including the non-relevent base command codes 1-15).
130 * Pad for the remainder of these here to bring us to the next CPU
131 * base. As extended codes are added, reduce the first array value in
132 * the following field
134 u32 PadToNextCpu[94][16]; /* 94 = 128 - 34 (34 = Excodes 0 - 33)*/
137 /* Interrupt control register (0) values */
138 #define SXG_ICR_DISABLE 0x00000000
139 #define SXG_ICR_ENABLE 0x00000001
140 #define SXG_ICR_MASK 0x00000002
141 #define SXG_ICR_MSGID_MASK 0xFFFF0000
142 #define SXG_ICR_MSGID_SHIFT 16
143 #define SXG_ICR(_MessageId, _Data) \
144 ((((_MessageId) << SXG_ICR_MSGID_SHIFT) & \
145 SXG_ICR_MSGID_MASK) | (_Data))
147 #define SXG_MIN_AGG_DEFAULT 0x0010 /* Minimum aggregation default */
148 #define SXG_MAX_AGG_DEFAULT 0x0040 /* Maximum aggregation default */
149 #define SXG_MAX_AGG_SHIFT 16 /* Maximum in top 16 bits of register */
150 /* Disable interrupt aggregation on xmt */
151 #define SXG_AGG_XMT_DISABLE 0x80000000
153 /* The Microcode supports up to 8 RSS queues */
154 #define SXG_MAX_RSS 8
156 #define SXG_MAX_RSS_TABLE_SIZE 256 /* 256-byte max */
158 #define SXG_RSS_TCP6 0x00000001 /* RSS TCP over IPv6 */
159 #define SXG_RSS_TCP4 0x00000002 /* RSS TCP over IPv4 */
160 #define SXG_RSS_LEGACY 0x00000004 /* Line-base interrupts */
161 #define SXG_RSS_TABLE_SIZE 0x0000FF00 /* Table size mask */
163 #define SXG_RSS_TABLE_SHIFT 8
164 #define SXG_RSS_BASE_CPU 0x00FF0000 /* Base CPU (not used) */
165 #define SXG_RSS_BASE_SHIFT 16
167 #define SXG_RCV_IP_CSUM_ENABLED 0x00000001 /* ExCode 26 (ReceiveChecksum) */
168 #define SXG_RCV_TCP_CSUM_ENABLED 0x00000002 /* ExCode 26 (ReceiveChecksum) */
170 #define SXG_XMT_CPUID_SHIFT 16
173 * Status returned by ucode in the ConfigStat reg (see above) when attempted
174 * to load configuration data from the EEPROM/Flash.
176 #define SXG_CFG_TIMEOUT 1 /* init value - timeout if unchanged */
177 #define SXG_CFG_LOAD_EEPROM 2 /* config data loaded from EEPROM */
178 #define SXG_CFG_LOAD_FLASH 3 /* config data loaded from flash */
179 #define SXG_CFG_LOAD_INVALID 4 /* no valid config data found */
180 #define SXG_CFG_LOAD_ERROR 5 /* hardware error */
182 #define SXG_CHECK_FOR_HANG_TIME 5
185 * TCB registers - This is really the same register memory area as UCODE_REGS
186 * above, but defined differently. Bits 17:06 of the address define the TCB,
187 * which means each TCB area occupies 0x40 (64) bytes, or 16 u32S. What really
188 * is happening is that these registers occupy the "PadEx[15]" areas in the
189 * struct sxg_ucode_regs definition above
191 struct sxg_tcb_regs {
192 u32 ExCode; /* Extended codes - see SXG_UCODE_REGS */
193 u32 Xmt; /* Code = 1 - # of Xmt descriptors added to ring */
194 u32 Rcv; /* Code = 2 - # of Rcv descriptors added to ring */
195 u32 Rsvd1; /* Code = 3 - TOE NA */
196 u32 Rsvd2; /* Code = 4 - TOE NA */
197 u32 Rsvd3; /* Code = 5 - TOE NA */
198 u32 Invalid1; /* Code = 6 - Reserved for "CardUp" see above */
199 u32 Rsvd4; /* Code = 7 - TOE NA */
200 u32 Invalid2; /* Code = 8 - Reserved for "ConfigStat" see above */
201 u32 Rsvd5; /* Code = 9 - TOE NA */
202 u32 Pad[6]; /* Codes 10-15 - Not used. */
205 /***************************************************************************
208 * _______________________________________
210 * |____|____|____|____|____|____|____|____|
211 * ^^^^ ^^^^ ^^^^ ^^^^ \ /
212 * ERR --|||| |||| |||| |||| -----------------
213 * EVENT ---||| |||| |||| |||| |
214 * ----|| |||| |||| |||| |-- Crash Address
215 * UPC -----| |||| |||| ||||
216 * LEVENT -------|||| |||| ||||
217 * PDQF --------||| |||| ||||
218 * RMISS ---------|| |||| ||||
219 * BREAK ----------| |||| ||||
220 * HBEATOK ------------|||| ||||
221 * NOHBEAT -------------||| ||||
222 * ERFULL --------------|| ||||
223 * XDROP ---------------| ||||
224 * -----------------||||
225 * -----------------||||--\
226 * ||---|-CpuId of crash
228 ***************************************************************************/
229 #define SXG_ISR_ERR 0x80000000 /* Error */
230 #define SXG_ISR_EVENT 0x40000000 /* Event ring event */
231 #define SXG_ISR_NONE1 0x20000000 /* Not used */
232 #define SXG_ISR_UPC 0x10000000 /* Dump/debug command complete*/
233 #define SXG_ISR_LINK 0x08000000 /* Link event */
234 #define SXG_ISR_PDQF 0x04000000 /* Processed data queue full */
235 #define SXG_ISR_RMISS 0x02000000 /* Drop - no host buf */
236 #define SXG_ISR_BREAK 0x01000000 /* Breakpoint hit */
237 #define SXG_ISR_PING 0x00800000 /* Heartbeat response */
238 #define SXG_ISR_DEAD 0x00400000 /* Card crash */
239 #define SXG_ISR_ERFULL 0x00200000 /* Event ring full */
240 #define SXG_ISR_XDROP 0x00100000 /* XMT Drop - no DRAM bufs or XMT err */
241 #define SXG_ISR_SPSEND 0x00080000 /* Slow send complete */
242 #define SXG_ISR_CPU 0x00070000 /* Dead CPU mask */
243 #define SXG_ISR_CPU_SHIFT 16 /* Dead CPU shift */
244 #define SXG_ISR_CRASH 0x0000FFFF /* Crash address mask */
246 /***************************************************************************
250 * .___________________.___________________.
251 * |<------------ Pad 0 ------------>|
252 * |_________|_________|_________|_________|0 0x00
253 * |<------------ Pad 1 ------------>|
254 * |_________|_________|_________|_________|4 0x04
255 * |<------------ Pad 2 ------------>|
256 * |_________|_________|_________|_________|8 0x08
257 * |<----------- Event Word 0 ------------>|
258 * |_________|_________|_________|_________|12 0x0c
259 * |<----------- Event Word 1 ------------>|
260 * |_________|_________|_________|_________|16 0x10
261 * |<------------- Toeplitz ------------>|
262 * |_________|_________|_________|_________|20 0x14
263 * |<----- Length ---->|<------ TCB Id --->|
264 * |_________|_________|_________|_________|24 0x18
265 * |<----- Status ---->|Evnt Code|Flsh Code|
266 * |_________|_________|_________|_________|28 0x1c
268 * |- VALID |||| ||||- RBUFC
278 * _______________________________________
279 * |<----- Status ---->|Evnt Code|Flsh Code|
280 * |_________|Cmd Index|_________|_________|28 0x1c
290 ************************************************************************/
291 #pragma pack(push, 1)
293 u32 Pad[1]; /* not used */
294 u32 SndUna; /* SndUna value */
295 u32 Resid; /* receive MDL resid */
297 void * HostHandle; /* Receive host handle */
298 u32 Rsvd1; /* TOE NA */
301 u32 Rsvd2; /* TOE NA */
304 u32 Toeplitz; /* RSS Toeplitz hash */
306 ushort Rsvd3; /* TOE NA */
307 ushort HdrOffset; /* Slowpath */
310 unsigned char Rsvd4; /* TOE NA */
311 unsigned char Code; /* Event code */
312 unsigned char CommandIndex; /* New ring index */
313 unsigned char Status; /* Event status */
317 /* Event code definitions */
318 #define EVENT_CODE_BUFFERS 0x01 /* Receive buffer list command (ring 0) */
319 #define EVENT_CODE_SLOWRCV 0x02 /* Slowpath receive */
320 #define EVENT_CODE_UNUSED 0x04 /* Was slowpath commands complete */
323 #define EVENT_STATUS_VALID 0x80 /* Entry valid */
325 /* Slowpath status */
326 #define EVENT_STATUS_ERROR 0x40 /* Completed with error. Index in next byte */
327 #define EVENT_STATUS_TCPIP4 0x20 /* TCPIPv4 frame */
328 #define EVENT_STATUS_TCPBAD 0x10 /* Bad TCP checksum */
329 #define EVENT_STATUS_IPBAD 0x08 /* Bad IP checksum */
330 #define EVENT_STATUS_RCVERR 0x04 /* Slowpath receive error */
331 #define EVENT_STATUS_IPONLY 0x02 /* IP frame */
332 #define EVENT_STATUS_TCPIP6 0x01 /* TCPIPv6 frame */
333 #define EVENT_STATUS_TCPIP 0x21 /* Combination of v4 and v6 */
337 * Size must be power of 2, between 128 and 16k
339 #define EVENT_RING_SIZE 4096
340 #define EVENT_RING_BATCH 16 /* Hand entries back 16 at a time. */
341 /* Stop processing events after 4096 (256 * 16) */
342 #define EVENT_BATCH_LIMIT 256
344 struct sxg_event_ring {
345 struct sxg_event Ring[EVENT_RING_SIZE];
349 /* Maximum number of TCBS supported by hardware/microcode */
350 #define SXG_MAX_TCB 4096
351 /* Minimum TCBs before we fail initialization */
352 #define SXG_MIN_TCB 512
355 * The bucket is determined by bits 11:4 of the toeplitz if we support 4k
356 * offloaded connections, 10:4 if we support 2k and so on.
358 #define SXG_TCB_BUCKET_SHIFT 4
359 #define SXG_TCB_PER_BUCKET 16
360 #define SXG_TCB_BUCKET_MASK 0xFF0 /* Bucket portion of TCB ID */
361 #define SXG_TCB_ELEMENT_MASK 0x00F /* Element within bucket */
362 #define SXG_TCB_BUCKETS 256 /* 256 * 16 = 4k */
364 #define SXG_TCB_BUFFER_SIZE 512 /* ASSERT format is correct */
366 #define SXG_TCB_RCVQ_SIZE 736
368 #define SXG_TCB_COMPOSITE_BUFFER_SIZE 1024
370 #define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
371 (((_TcpObject)->VlanId) ? \
372 ((_IPv6) ? /* Vlan frame header = yes */ \
373 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp: \
374 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp): \
375 ((_IPv6) ? /* Vlan frame header = No */ \
376 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
377 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
379 #define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
380 (_TcpObject)->VlanId ? \
381 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip: \
382 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
384 #define SXG_LOCATE_IP6_FRAME_HDR(TcpObject) \
385 (_TcpObject)->VlanId ? \
386 &(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip: \
387 &(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
391 * Horrible kludge to distinguish dumb-nic, slowpath, and
392 * fastpath traffic. Decrement the HopLimit by one
393 * for slowpath, two for fastpath. This assumes the limit is measurably
394 * greater than two, which I think is reasonable.
395 * Obviously this is DBG only. Maybe remove later, or #if 0 so we
396 * can set it when needed
398 #define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
399 PIPV6_HDR _Ip6FrameHdr; \
400 if ((_TcpObject)->IPv6) { \
401 _Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
403 _Ip6FrameHdr->HopLimit = \
404 (_TcpObject)->Cached.TtlOrHopLimit - 2; \
406 _Ip6FrameHdr->HopLimit = \
407 (_TcpObject)->Cached.TtlOrHopLimit - 1; \
412 /* Do nothing with free build */
413 #define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath)
416 /* Receive and transmit rings */
417 #define SXG_MAX_RING_SIZE 256
418 #define SXG_XMT_RING_SIZE 128 /* Start with 128 */
419 #define SXG_RCV_RING_SIZE 128 /* Start with 128 */
420 #define SXG_MAX_ENTRIES 4096
421 #define SXG_JUMBO_RCV_RING_SIZE 32
423 /* Structure and macros to manage a ring */
424 struct sxg_ring_info {
425 /* Where we add entries - Note unsigned char:RING_SIZE */
427 unsigned char Tail; /* Where we pull off completed entries */
428 ushort Size; /* Ring size - Must be multiple of 2 */
429 void * Context[SXG_MAX_RING_SIZE]; /* Shadow ring */
432 #define SXG_INITIALIZE_RING(_ring, _size) { \
435 (_ring).Size = (_size); \
438 #define SXG_ADVANCE_INDEX(_index, _size) \
439 ((_index) = ((_index) + 1) & ((_size) - 1))
440 #define SXG_PREVIOUS_INDEX(_index, _size) \
441 (((_index) - 1) &((_size) - 1))
442 #define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
443 #define SXG_RING_FULL(_ring) \
444 ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
445 #define SXG_RING_ADVANCE_HEAD(_ring) \
446 SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
447 #define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
448 SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
449 #define SXG_RING_ADVANCE_TAIL(_ring) { \
450 ASSERT((_ring)->Tail != (_ring)->Head); \
451 SXG_ADVANCE_INDEX((_ring)->Tail, ((_ring)->Size)); \
454 * Set cmd to the next available ring entry, set the shadow context
455 * entry and advance the ring.
456 * The appropriate lock must be held when calling this macro
458 #define SXG_GET_CMD(_ring, _ringinfo, _cmd, _context) { \
459 if(SXG_RING_FULL(_ringinfo)) { \
462 (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Head]; \
463 (_ringinfo)->Context[(_ringinfo)->Head] = (void *)(_context);\
464 SXG_RING_ADVANCE_HEAD(_ringinfo); \
469 * Abort the previously allocated command by retreating the head.
470 * NOTE - The appopriate lock MUST NOT BE DROPPED between the SXG_GET_CMD
471 * and SXG_ABORT_CMD calls.
473 #define SXG_ABORT_CMD(_ringinfo) { \
474 ASSERT(!(SXG_RING_EMPTY(_ringinfo))); \
475 SXG_RING_RETREAT_HEAD(_ringinfo); \
476 (_ringinfo)->Context[(_ringinfo)->Head] = NULL; \
480 * For the given ring, return a pointer to the tail cmd and context,
481 * clear the context and advance the tail
483 #define SXG_RETURN_CMD(_ring, _ringinfo, _cmd, _context) { \
484 (_cmd) = &(_ring)->Descriptors[(_ringinfo)->Tail]; \
485 (_context) = (_ringinfo)->Context[(_ringinfo)->Tail]; \
486 (_ringinfo)->Context[(_ringinfo)->Tail] = NULL; \
487 SXG_RING_ADVANCE_TAIL(_ringinfo); \
491 * For a given ring find out how much the first pointer is ahead of
492 * the second pointer. "ahead" recognises the fact that the ring can wrap
494 static inline int sxg_ring_get_forward_diff (struct sxg_ring_info *ringinfo,
496 if ((a < 0 || a > ringinfo->Size ) || (b < 0 || b > ringinfo->Size))
498 if (a > b) /* _a is lagging _b and _b has not wrapped around */
501 return ((ringinfo->Size - (b - a)));
504 /***************************************************************
505 * Host Command Buffer - commands to INIC via the Cmd Rings
508 * .___________________.___________________.
509 * |<-------------- Sgl Low -------------->|
510 * |_________|_________|_________|_________|0 0x00
511 * |<-------------- Sgl High ------------->|
512 * |_________|_________|_________|_________|4 0x04
513 * |<------------- Sge 0 Low ----------->|
514 * |_________|_________|_________|_________|8 0x08
515 * |<------------- Sge 0 High ----------->|
516 * |_________|_________|_________|_________|12 0x0c
517 * |<------------ Sge 0 Length ---------->|
518 * |_________|_________|_________|_________|16 0x10
519 * |<----------- Window Update ----------->|
520 * |<-------- SP 1st SGE offset ---------->|
521 * |_________|_________|_________|_________|20 0x14
522 * |<----------- Total Length ------------>|
523 * |_________|_________|_________|_________|24 0x18
524 * |<----- LCnt ------>|<----- Flags ----->|
525 * |_________|_________|_________|_________|28 0x1c
526 ****************************************************************/
527 #pragma pack(push, 1)
529 dma64_addr_t Sgl; /* Physical address of SGL */
532 dma64_addr_t FirstSgeAddress; /* Address of first SGE */
533 u32 FirstSgeLength; /* Length of first SGE */
535 u32 Rsvd1; /* TOE NA */
536 u32 SgeOffset; /* Slowpath - 2nd SGE offset */
537 /* MDL completion - clobbers update */
541 u32 TotalLength; /* Total transfer length */
542 u32 Mss; /* LSO MSS */
548 unsigned char Flags:4; /* slowpath flags */
549 unsigned char IpHl:4; /* Ip header length (>>2) */
550 unsigned char MacLen; /* Mac header len */
553 ushort Flags:4; /* slowpath flags */
554 ushort TcpHdrOff:7; /* TCP */
555 ushort MacLen:5; /* Mac header len */
557 ushort Flags; /* flags */
560 ushort SgEntries; /* SG entry count including first sge */
562 unsigned char Status; /* Copied from event status */
563 unsigned char NotUsed;
569 #pragma pack(push, 1)
576 /********************************************************************
582 * /.--- TCP Large segment send
587 * .___________________.____________vvvv.
589 * | LCnt |hlen|hdroff|Flgs|
590 * |___________________|||||||||||||____|
597 * //.--- Checksum TCP
598 * ///.--- Checksum IP
599 * 3 1 //// No bits - normal send
601 * .___________________._______________vvvv.
602 * | | Offload | IP | |
603 * | LCnt |MAC hlen |Hlen|Flgs|
604 * |___________________|____|____|____|____|
606 *****************************************************************/
607 /* Slowpath CMD flags */
608 #define SXG_SLOWCMD_CSUM_IP 0x01 /* Checksum IP */
609 #define SXG_SLOWCMD_CSUM_TCP 0x02 /* Checksum TCP */
610 #define SXG_SLOWCMD_LSO 0x04 /* Large segment send */
612 struct sxg_xmt_ring {
613 struct sxg_cmd Descriptors[SXG_XMT_RING_SIZE];
616 struct sxg_rcv_ring {
617 struct sxg_cmd Descriptors[SXG_RCV_RING_SIZE];
621 * Share memory buffer types - Used to identify asynchronous
622 * shared memory allocation
624 enum sxg_buffer_type {
625 SXG_BUFFER_TYPE_RCV, /* Receive buffer */
626 SXG_BUFFER_TYPE_SGL /* SGL buffer */
629 /* State for SXG buffers */
630 #define SXG_BUFFER_FREE 0x01
631 #define SXG_BUFFER_BUSY 0x02
632 #define SXG_BUFFER_ONCARD 0x04
633 #define SXG_BUFFER_UPSTREAM 0x08
636 * Receive data buffers
638 * Receive data buffers are given to the Sahara card 128 at a time.
639 * This is accomplished by filling in a "receive descriptor block"
640 * with 128 "receive descriptors". Each descriptor consists of
641 * a physical address, which the card uses as the address to
642 * DMA data into, and a virtual address, which is given back
643 * to the host in the "HostHandle" portion of an event.
644 * The receive descriptor data structure is defined below
645 * as sxg_rcv_data_descriptor, and the corresponding block
646 * is defined as sxg_rcv_descriptor_block.
648 * This receive descriptor block is given to the card by filling
649 * in the Sgl field of a sxg_cmd entry from pAdapt->RcvRings[0]
650 * with the physical address of the receive descriptor block.
652 * Both the receive buffers and the receive descriptor blocks
653 * require additional data structures to maintain them
654 * on a free queue and contain other information associated with them.
655 * Those data structures are defined as the sxg_rcv_data_buffer_hdr
656 * and sxg_rcv_descriptor_block_hdr respectively.
658 * Since both the receive buffers and the receive descriptor block
659 * must be accessible by the card, both must be allocated out of
660 * shared memory. To ensure that we always have a descriptor
661 * block available for every 128 buffers, we allocate all of
662 * these resources together in a single block. This entire
663 * block is managed by a struct sxg_rcv_block_hdr, who's sole purpose
664 * is to maintain address information so that the entire block
667 * Further complicating matters is the fact that the receive
668 * buffers must be variable in length in order to accomodate
669 * jumbo frame configurations. We configure the buffer
670 * length so that the buffer and it's corresponding struct
671 * sxg_rcv_data_buffer_hdr structure add up to an even
672 * boundary. Then we place the remaining data structures after 128
673 * of them as shown in the following diagram:
675 * _________________________________________
677 * | Variable length receive buffer #1 |
678 * |_________________________________________|
680 * | sxg_rcv_data_buffer_hdr #1 |
681 * |_________________________________________| <== Even 2k or 10k boundary
683 * | ... repeat 2-128 .. |
684 * |_________________________________________|
686 * | struct sxg_rcv_descriptor_block |
687 * | Contains sxg_rcv_data_descriptor * 128 |
688 * |_________________________________________|
690 * | struct sxg_rcv_descriptor_block_hdr |
691 * |_________________________________________|
693 * | struct sxg_rcv_block_hdr |
694 * |_________________________________________|
696 * Memory consumption:
698 * Buffers and sxg_rcv_data_buffer_hdr = 2k * 128 = 256k
699 * + struct sxg_rcv_descriptor_block = 2k
700 * + struct sxg_rcv_descriptor_block_hdr = ~32
701 * + struct sxg_rcv_block_hdr = ~32
702 * => Total = ~258k/block
705 * Buffers and sxg_rcv_data_buffer_hdr = 10k * 128 = 1280k
706 * + struct sxg_rcv_descriptor_block = 2k
707 * + struct sxg_rcv_descriptor_block_hdr = ~32
708 * + struct sxg_rcv_block_hdr = ~32
709 * => Total = ~1282k/block
712 #define SXG_RCV_DATA_BUFFERS 8192 /* Amount to give to the card */
713 #define SXG_INITIAL_RCV_DATA_BUFFERS 16384 /* Initial pool of buffers */
714 /* Minimum amount and when to get more */
715 #define SXG_MIN_RCV_DATA_BUFFERS 4096
716 #define SXG_MAX_RCV_BLOCKS 256 /* = 32k receive buffers */
717 /* Amount to give to the card in case of jumbo frames */
718 #define SXG_JUMBO_RCV_DATA_BUFFERS 2048
719 /* Initial pool of buffers in case of jumbo buffers */
720 #define SXG_INITIAL_JUMBO_RCV_DATA_BUFFERS 4096
721 #define SXG_MIN_JUMBO_RCV_DATA_BUFFERS 1024
723 /* Receive buffer header */
724 struct sxg_rcv_data_buffer_hdr {
725 dma64_addr_t PhysicalAddress; /* Buffer physical address */
727 * Note - DO NOT USE the VirtualAddress field to locate data.
728 * Use the sxg.h:SXG_RECEIVE_DATA_LOCATION macro instead.
730 struct list_entry FreeList; /* Free queue of buffers */
731 unsigned char State; /* See SXG_BUFFER state above */
732 struct sk_buff * skb; /* Double mapped (nbl and pkt)*/
736 * SxgSlowReceive uses the PACKET (skb) contained
737 * in the struct sxg_rcv_data_buffer_hdr when indicating dumb-nic data
739 #define SxgDumbRcvPacket skb
741 /* Space for struct sxg_rcv_data_buffer_hdr */
742 #define SXG_RCV_DATA_HDR_SIZE sizeof(struct sxg_rcv_data_buffer_hdr)
743 /* Non jumbo = 2k including HDR */
744 #define SXG_RCV_DATA_BUFFER_SIZE 2048
745 /* jumbo = 10k including HDR */
746 #define SXG_RCV_JUMBO_BUFFER_SIZE 10240
748 /* Receive data descriptor */
749 struct sxg_rcv_data_descriptor {
751 struct sk_buff *VirtualAddress; /* Host handle */
752 u64 ForceTo8Bytes; /*Force x86 to 8-byte boundary*/
754 dma64_addr_t PhysicalAddress;
757 /* Receive descriptor block */
758 #define SXG_RCV_DESCRIPTORS_PER_BLOCK 128
759 #define SXG_RCV_DESCRIPTOR_BLOCK_SIZE 2048 /* For sanity check */
761 struct sxg_rcv_descriptor_block {
762 struct sxg_rcv_data_descriptor Descriptors[SXG_RCV_DESCRIPTORS_PER_BLOCK];
765 /* Receive descriptor block header */
766 struct sxg_rcv_descriptor_block_hdr {
767 void *VirtualAddress; /* start of 2k buffer */
768 dma64_addr_t PhysicalAddress;/* and it's physical address */
769 struct list_entry FreeList;/* free queue of descriptor blocks */
770 unsigned char State; /* see sxg_buffer state above */
773 /* Receive block header */
774 struct sxg_rcv_block_hdr {
775 void *VirtualAddress; /* Start of virtual memory */
776 dma64_addr_t PhysicalAddress;/* ..and it's physical address*/
777 struct list_entry AllList; /* Queue of all SXG_RCV_BLOCKS*/
780 /* Macros to determine data structure offsets into receive block */
781 #define SXG_RCV_BLOCK_SIZE(_Buffersize) \
782 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
783 (sizeof(struct sxg_rcv_descriptor_block)) + \
784 (sizeof(struct sxg_rcv_descriptor_block_hdr)) + \
785 (sizeof(struct sxg_rcv_block_hdr)))
786 #define SXG_RCV_BUFFER_DATA_SIZE(_Buffersize) \
787 ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
788 #define SXG_RCV_DATA_BUFFER_HDR_OFFSET(_Buffersize) \
789 ((_Buffersize) - SXG_RCV_DATA_HDR_SIZE)
790 #define SXG_RCV_DESCRIPTOR_BLOCK_OFFSET(_Buffersize) \
791 ((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK)
792 #define SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET(_Buffersize) \
793 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
794 (sizeof(struct sxg_rcv_descriptor_block)))
795 #define SXG_RCV_BLOCK_HDR_OFFSET(_Buffersize) \
796 (((_Buffersize) * SXG_RCV_DESCRIPTORS_PER_BLOCK) + \
797 (sizeof(struct sxg_rcv_descriptor_block)) + \
798 (sizeof(struct sxg_rcv_descriptor_block_hdr)))
800 /* Scatter gather list buffer */
801 #define SXG_INITIAL_SGL_BUFFERS 8192 /* Initial pool of SGL buffers */
802 #define SXG_MIN_SGL_BUFFERS 2048 /* Minimum amount and when to get more*/
803 /* Maximum to allocate (note ADAPT:ushort) */
804 #define SXG_MAX_SGL_BUFFERS 16384
807 * SXG_SGL_POOL_PROPERTIES - This structure is used to define a pool of SGL
808 * buffers. These buffers are allocated out of shared memory and used to
809 * contain a physical scatter gather list structure that is shared
812 * We split our SGL buffers into multiple pools based on size. The motivation
813 * is that some applications perform very large I/Os (1MB for example), so
814 * we need to be able to allocate an SGL to accommodate such a request.
815 * But such an SGL would require 256 24-byte SG entries - ~6k.
816 * Given that the vast majority of I/Os are much smaller than 1M, allocating
817 * a single pool of SGL buffers would be a horribly inefficient use of
820 * The following structure includes two fields relating to its size.
821 * The NBSize field specifies the largest NET_BUFFER that can be handled
822 * by the particular pool. The SGEntries field defines the size, in
823 * entries, of the SGL for that pool. The SGEntries is determined by
824 * dividing the NBSize by the expected page size (4k), and then padding
825 * it by some appropriate amount as insurance (20% or so..??).
827 struct sxg_sgl_pool_properties {
828 u32 NBSize; /* Largest NET_BUFFER size for this pool */
829 ushort SGEntries; /* Number of entries in SGL */
830 ushort InitialBuffers; /* Number to allocate at initializationtime */
831 ushort MinBuffers; /* When to get more */
832 ushort MaxBuffers; /* When to stop */
833 ushort PerCpuThreshold;/* See sxgh.h:SXG_RESOURCES */
837 * At the moment I'm going to statically initialize 4 pools:
838 * 100k buffer pool: The vast majority of the expected buffers are expected
839 * to be less than or equal to 100k. At 30 entries per and
840 * 8k initial buffers amounts to ~4MB of memory
841 * NOTE - This used to be 64K with 20 entries, but during
842 * WHQL NDIS 6.0 Testing (2c_mini6stress) MS does their
843 * best to send absurd NBL's with ridiculous SGLs, we
844 * have received 400byte sends contained in SGL's that
846 * 1M buffer pool: Buffers between 64k and 1M. Allocate 256 initial
847 * buffers with 300 entries each => ~2MB of memory
848 * 5M buffer pool: Not expected often, if at all. 32 initial buffers
849 * at 1500 entries each => ~1MB of memory
850 * 10M buffer pool: Not expected at all, except under pathelogical conditions.
851 * Allocate one at initialization time.
852 * Note - 10M is the current limit of what we can realistically
853 * support due to the sahara SGL bug described in the
854 * SAHARA SGL WORKAROUND below. We will likely adjust the
855 * number of pools and/or pool properties over time.
857 #define SXG_NUM_SGL_POOLS 4
858 #define INITIALIZE_SGL_POOL_PROPERTIES \
859 struct sxg_sgl_pool_properties SxgSglPoolProperties[SXG_NUM_SGL_POOLS] =\
861 { 102400, 30, 8192, 2048, 16384, 256}, \
862 { 1048576, 300, 256, 128, 1024, 16}, \
863 { 5252880, 1500, 32, 16, 512, 0}, \
864 {10485760, 2700, 2, 4, 32, 0}, \
867 extern struct sxg_sgl_pool_properties SxgSglPoolProperties[];
869 #define SXG_MAX_SGL_BUFFER_SIZE \
870 SxgSglPoolProperties[SXG_NUM_SGL_POOLS - 1].NBSize
873 * SAHARA SGL WORKAROUND!!
874 * The current Sahara card uses a 16-bit counter when advancing
875 * SGL address locations. This means that if an SGL crosses
876 * a 64k boundary, the hardware will actually skip back to
877 * the start of the previous 64k boundary, with obviously
878 * undesirable results.
880 * We currently workaround this issue by allocating SGL buffers
881 * in 64k blocks and skipping over buffers that straddle the boundary.
883 #define SXG_INVALID_SGL(phys_addr,len) \
884 (((phys_addr >> 16) != ( (phys_addr + len) >> 16 )))
887 * Allocate SGLs in blocks so we can skip over invalid entries.
888 * We allocation 64k worth of SGL buffers, including the
889 * struct sxg_sgl_block_hdr, plus one for padding
891 #define SXG_SGL_BLOCK_SIZE 65536
892 #define SXG_SGL_ALLOCATION_SIZE(_Pool) \
893 SXG_SGL_BLOCK_SIZE + SXG_SGL_SIZE(_Pool)
895 struct sxg_sgl_block_hdr {
896 ushort Pool; /* Associated SGL pool */
897 /* struct sxg_scatter_gather blocks */
898 struct list_entry List;
899 dma64_addr_t PhysicalAddress;/* physical address */
903 * The following definition denotes the maximum block of memory that the
904 * card can DMA to.It is specified in the call to NdisMRegisterScatterGatherDma.
905 * For now, use the same value as used in the Slic/Oasis driver, which
906 * is 128M. That should cover any expected MDL that I can think of.
908 #define SXG_MAX_PHYS_MAP (1024 * 1024 * 128)
910 /* Self identifying structure type */
912 SXG_SGL_DUMB, /* Dumb NIC SGL */
913 SXG_SGL_SLOW, /* Slowpath protocol header - see below */
914 SXG_SGL_CHIMNEY /* Chimney offload SGL */
918 * The ucode expects an NDIS SGL structure that
919 * is formatted for an x64 system. When running
920 * on an x64 system, we can simply hand the NDIS SGL
921 * to the card directly. For x86 systems we must reconstruct
922 * the SGL. The following structure defines an x64
923 * formatted SGL entry
926 dma64_addr_t Address; /* same as wdm.h */
927 u32 Length; /* same as wdm.h */
928 u32 CompilerPad; /* The compiler pads to 8-bytes */
929 u64 Reserved; /* u32 * in wdm.h. Force to 8 bytes */
933 * Our SGL structure - Essentially the same as
934 * wdm.h:SCATTER_GATHER_LIST. Note the variable number of
935 * elements based on the pool specified above
938 u32 NumberOfElements;
940 struct sxg_x64_sge Elements[1]; /* Variable */
943 struct sxg_scatter_gather {
944 enum SXG_SGL_TYPE Type; /* FIRST! Dumb-nic or offload */
945 ushort Pool; /* Associated SGL pool */
946 ushort Entries; /* SGL total entries */
947 void * adapter; /* Back pointer to adapter */
948 /* Free struct sxg_scatter_gather blocks */
949 struct list_entry FreeList;
950 /* All struct sxg_scatter_gather blocks */
951 struct list_entry AllList;
952 dma64_addr_t PhysicalAddress;/* physical address */
953 unsigned char State; /* See SXG_BUFFER state above */
954 unsigned char CmdIndex; /* Command ring index */
955 struct sk_buff *DumbPacket; /* Associated Packet */
956 /* For asynchronous completions */
958 u32 CurOffset; /* Current SGL offset */
959 u32 SglRef; /* SGL reference count */
960 struct vlan_hdr VlanTag; /* VLAN tag to be inserted into SGL */
961 struct sxg_x64_sgl *pSgl; /* SGL Addr. Possibly &Sgl */
962 struct sxg_x64_sgl Sgl; /* SGL handed to card */
966 * Note - the "- 1" is because struct sxg_scatter_gather=>struct sxg_x64_sgl
969 #define SXG_SGL_SIZE(_Pool) \
970 (sizeof(struct sxg_scatter_gather) + \
971 ((SxgSglPoolProperties[_Pool].SGEntries - 1) * \
972 sizeof(struct sxg_x64_sge)))
974 /* Force NDIS to give us it's own buffer so we can reformat to our own */
975 #define SXG_SGL_BUFFER(_SxgSgl) NULL
976 #define SXG_SGL_BUFFER_LENGTH(_SxgSgl) 0
977 #define SXG_SGL_BUF_SIZE 0
980 #if defined(CONFIG_X86_64)
981 #define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
982 #define SXG_SGL_BUFFER_LENGTH(_SxgSgl) ((_SxgSgl)->Entries * \
983 sizeof(struct sxg_x64_sge))
984 #define SXG_SGL_BUF_SIZE sizeof(struct sxg_x64_sgl)
985 #elif defined(CONFIG_X86)
986 // Force NDIS to give us it's own buffer so we can reformat to our own
987 #define SXG_SGL_BUFFER(_SxgSgl) NULL
988 #define SXG_SGL_BUFFER_LENGTH(_SxgSgl) 0
989 #define SXG_SGL_BUF_SIZE 0
991 #error staging: sxg: driver is for X86 only!
994 /* Microcode statistics */
995 struct sxg_ucode_stats {
996 u32 RPDQOflow; /* PDQ overflow (unframed ie dq & drop 1st) */
997 u32 XDrops; /* Xmt drops due to no xmt buffer */
998 u32 ERDrops; /* Rcv drops due to ER full */
999 u32 NBDrops; /* Rcv drops due to out of host buffers */
1000 u32 PQDrops; /* Rcv drops due to PDQ full */
1001 /* Rcv drops due to bad frame: no link addr match, frlen > max */
1003 u32 UPDrops; /* Rcv drops due to UPFq full */
1004 u32 XNoBufs; /* Xmt drop due to no DRAM Xmit buffer or PxyBuf */
1008 * Macros for handling the Offload engine values
1010 /* Number of positions to shift Network Header Length before passing to card */
1011 #define SXG_NW_HDR_LEN_SHIFT 2