1 /**************************************************************************
3 * Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
5 * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * The views and conclusions contained in the software and documentation
32 * are those of the authors and should not be interpreted as representing
33 * official policies, either expressed or implied, of Alacritech, Inc.
35 **************************************************************************/
40 * This is the base set of header definitions for the SXG driver.
42 #ifndef __SXG_DRIVER_H__
43 #define __SXG_DRIVER_H__
45 #define p_net_device struct net_device *
46 // SXG_STATS - Probably move these to someplace where
47 // the slicstat (sxgstat?) program can get them.
50 u32 XmtNBL; // Offload send NBL count
51 u64 DumbXmtBytes; // Dumbnic send bytes
52 u64 SlowXmtBytes; // Slowpath send bytes
53 u64 FastXmtBytes; // Fastpath send bytes
54 u64 DumbXmtPkts; // Dumbnic send packets
55 u64 SlowXmtPkts; // Slowpath send packets
56 u64 FastXmtPkts; // Fastpath send packets
57 u64 DumbXmtUcastPkts; // directed packets
58 u64 DumbXmtMcastPkts; // Multicast packets
59 u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
60 u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT
61 u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT
62 u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT
63 u64 XmtErrors; // OID_GEN_XMIT_ERROR
64 u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS
65 u64 XmtOk; // OID_GEN_XMIT_OK
66 u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH
67 u64 XmtZeroFull; // Transmit ring zero full
69 u32 RcvNBL; // Offload recieve NBL count
70 u64 DumbRcvBytes; // dumbnic recv bytes
71 u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV
72 u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV
73 u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV
74 u64 SlowRcvBytes; // Slowpath recv bytes
75 u64 FastRcvBytes; // Fastpath recv bytes
76 u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
77 u64 DumbRcvTcpPkts; // See SxgCollectStats
78 u64 DumbRcvUcastPkts; // directed packets
79 u64 DumbRcvMcastPkts; // Multicast packets
80 u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
81 u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
82 u64 RcvErrors; // OID_GEN_RCV_ERROR
83 u64 RcvDiscards; // OID_GEN_RCV_DISCARDS
84 u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER
85 u64 PdqFull; // Processed Data Queue Full
86 u64 EventRingFull; // Event ring full
88 u64 MaxSends; // Max sends outstanding
89 u64 NoSglBuf; // SGL buffer allocation failure
90 u64 SglFail; // NDIS SGL failure
91 u64 SglAsync; // NDIS SGL failure
92 u64 NoMem; // Memory allocation failure
93 u64 NumInts; // Interrupts
94 u64 FalseInts; // Interrupt with ISR == 0
95 u64 XmtDrops; // No sahara DRAM buffer for xmt
96 // Sahara receive status
97 u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM
98 u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW
99 u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN
100 u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM:
101 u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW:
102 u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN:
103 u64 Parity; // SXG_RCV_STATUS_PARITY
104 u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY:
105 u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY:
106 u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW:
107 u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE:
108 u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE:
109 u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC:
110 u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW:
111 u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW:
115 /****************************************************************************
116 * DUMB-NIC Send path definitions
117 ****************************************************************************/
119 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
121 dev_kfree_skb_irq(_skb); \
124 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
126 dev_kfree_skb(_skb); \
129 // Locate current receive header buffer location. Use this
130 // instead of RcvDataHdr->VirtualAddress since the data
131 // may have been offset by SXG_ADVANCE_MDL_OFFSET
132 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
134 /************************************************************************
135 * Dumb-NIC receive processing
136 ************************************************************************/
137 // Define an SXG_PACKET as an NDIS_PACKET
138 #define PSXG_PACKET struct sk_buff *
139 // Indications array size
140 #define SXG_RCV_ARRAYSIZE 64
142 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \
143 struct sk_buff * skb; \
144 skb = netdev_alloc_skb(_pAdapt->netdev, 2048); \
146 (_RcvDataBufferHdr)->skb = skb; \
149 (_RcvDataBufferHdr)->skb = NULL; \
153 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
154 if((_RcvDataBufferHdr)->skb) { \
155 dev_kfree_skb((_RcvDataBufferHdr)->skb); \
159 // Macro to add a NDIS_PACKET to an indication array
160 // If we fill up our array of packet pointers, then indicate this
161 // block up now and start on a new one.
162 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
163 (_IndicationList)[_NumPackets] = (_Packet); \
165 if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
166 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
167 (_NumPackets), 0, 0, 0); \
168 netif_rx((_IndicationList),(_NumPackets)); \
173 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
175 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
176 (_NumPackets), 0, 0, 0); \
177 netif_rx((_IndicationList),(_NumPackets)); \
182 #define SXG_REINIATIALIZE_PACKET(_Packet) \
183 {} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
185 // Definitions to initialize Dumb-nic Receive NBLs
186 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
188 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
189 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
191 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
192 NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
193 NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
194 NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
197 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
198 NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
199 _Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
200 _Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
201 NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
202 _Packet8021qInfo.Value; \
205 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
206 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
207 (_RcvDataBufferHdr), (_Packet), \
208 (_Event)->Status, 0); \
209 ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); \
210 skb_put(Packet, (_Event)->Length); \
213 ///////////////////////////////////////////////////////////////////////////////
214 // Macros to free a receive data buffer and receive data descriptor block
215 ///////////////////////////////////////////////////////////////////////////////
216 // NOTE - Lock must be held with RCV macros
217 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
218 struct LIST_ENTRY *_ple; \
220 if((_pAdapt)->FreeRcvBufferCount) { \
221 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
222 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
223 (_Hdr) = container_of(_ple, struct SXG_RCV_DATA_BUFFER_HDR, FreeList); \
224 (_pAdapt)->FreeRcvBufferCount--; \
225 ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
229 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
230 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
231 (_Hdr), (_pAdapt)->FreeRcvBufferCount, \
232 (_Hdr)->State, (_Hdr)->VirtualAddress); \
233 /* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
234 (_pAdapt)->FreeRcvBufferCount++; \
235 ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
236 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
237 (_Hdr)->State = SXG_BUFFER_FREE; \
238 InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
241 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
242 ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
243 (_Hdr)->State = SXG_BUFFER_FREE; \
244 (_pAdapt)->FreeRcvBlockCount++; \
245 ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
246 InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
250 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
251 spin_lock(&(_pAdapt)->SglQLock); \
252 (_pAdapt)->FreeSglBufferCount++; \
253 ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
254 ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
255 (_Sgl)->State = SXG_BUFFER_FREE; \
256 InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
257 spin_unlock(&(_pAdapt)->SglQLock); \
260 // Get an SGL buffer from the free queue. The first part of this macro
261 // attempts to keep ahead of buffer depletion by allocating more when
262 // we hit a minimum threshold. Note that we don't grab the lock
263 // until after that. We're dealing with round numbers here, so we don't need to,
264 // and not grabbing it avoids a possible double-trip.
265 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
266 struct LIST_ENTRY *_ple; \
267 if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
268 (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
269 (_pAdapt->AllocationsPending == 0)) { \
270 sxg_allocate_buffer_memory(_pAdapt, \
271 (sizeof(struct SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
272 SXG_BUFFER_TYPE_SGL); \
275 spin_lock(&(_pAdapt)->SglQLock); \
276 if((_pAdapt)->FreeSglBufferCount) { \
277 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
278 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
279 (_Sgl) = container_of(_ple, struct SXG_SCATTER_GATHER, FreeList); \
280 (_pAdapt)->FreeSglBufferCount--; \
281 ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
282 (_Sgl)->State = SXG_BUFFER_BUSY; \
283 (_Sgl)->pSgl = NULL; \
285 spin_unlock(&(_pAdapt)->SglQLock); \
289 // SXG_MULTICAST_ADDRESS
291 // Linked list of multicast addresses.
292 struct SXG_MULTICAST_ADDRESS {
293 unsigned char Address[6];
294 struct SXG_MULTICAST_ADDRESS *Next;
297 // Structure to maintain chimney send and receive buffer queues.
298 // This structure maintains NET_BUFFER_LIST queues that are
299 // given to us via the Chimney MiniportTcpOffloadSend and
300 // MiniportTcpOffloadReceive routines. This structure DOES NOT
301 // manage our data buffer queue
302 struct SXG_BUFFER_QUEUE {
303 u32 Type; // Slow or fast - See below
304 u32 Direction; // Xmt or Rcv
305 u32 Bytes; // Byte count
306 u32 * Head; // Send queue head
307 u32 * Tail; // Send queue tail
308 // PNET_BUFFER_LIST NextNBL; // Short cut - next NBL
309 // PNET_BUFFER NextNB; // Short cut - next NB
312 #define SXG_SLOW_SEND_BUFFER 0
313 #define SXG_FAST_SEND_BUFFER 1
314 #define SXG_RECEIVE_BUFFER 2
316 #define SXG_INIT_BUFFER(_Buffer, _Type) { \
317 (_Buffer)->Type = (_Type); \
318 if((_Type) == SXG_RECEIVE_BUFFER) { \
319 (_Buffer)->Direction = 0; \
321 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
323 (_Buffer)->Bytes = 0; \
324 (_Buffer)->Head = NULL; \
325 (_Buffer)->Tail = NULL; \
329 #define SXG_RSS_CPU_COUNT(_pAdapt) \
330 ((_pAdapt)->RssEnabled ? NR_CPUS : 1)
332 /****************************************************************************
333 * DRIVER and ADAPTER structures
334 ****************************************************************************/
336 // Adapter states - These states closely match the adapter states
337 // documented in the DDK (with a few exceptions).
339 SXG_STATE_INITIALIZING, // Initializing
340 SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode
341 SXG_STATE_PAUSING, // Pausing
342 SXG_STATE_PAUSED, // Paused
343 SXG_STATE_RUNNING, // Running
344 SXG_STATE_RESETTING, // Reset in progress
345 SXG_STATE_SLEEP, // Sleeping
346 SXG_STATE_DIAG, // Diagnostic mode
347 SXG_STATE_HALTING, // Halting
348 SXG_STATE_HALTED, // Down or not-initialized
349 SXG_STATE_SHUTDOWN // shutdown
353 enum SXG_LINK_STATE {
358 // Link initialization timeout in 100us units
359 #define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE!
362 // Microcode file selection codes
364 SXG_UCODE_SAHARA, // Sahara ucode
365 SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode
366 SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode
370 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
371 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
373 // This probably lives in a proto.h file. Move later
374 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
375 #define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
376 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
379 #define SXG_ID DPFLTR_IHVNETWORK_ID
380 #define SXG_ERROR DPFLTR_ERROR_LEVEL
383 // SXG_DRIVER structure -
385 // contains information about the sxg driver. There is only
386 // one of these, and it is defined as a global.
388 struct adapter_t *Adapters; // Linked list of adapters
389 ushort AdapterID; // Maintain unique adapter ID
392 #ifdef STATUS_SUCCESS
393 #undef STATUS_SUCCESS
396 #define STATUS_SUCCESS 0
397 #define STATUS_PENDING 0
398 #define STATUS_FAILURE -1
399 #define STATUS_ERROR -2
400 #define STATUS_NOT_SUPPORTED -3
401 #define STATUS_BUFFER_TOO_SHORT -4
402 #define STATUS_RESOURCES -5
404 #define SLIC_MAX_CARDS 32
405 #define SLIC_MAX_PORTS 4 /* Max # of ports per card */
406 #if SLIC_DUMP_ENABLED
409 // This cannot be bigger than the max DMA size the card supports,
410 // given the current code structure in the host and ucode.
411 // Mojave supports 16K, Oasis supports 16K-1, so
412 // just set this at 15K, shouldnt make that much of a diff.
413 #define DUMP_BUF_SIZE 0x3C00
416 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
417 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
419 struct mcast_address_t {
420 unsigned char address[6];
421 struct mcast_address_t *next;
424 #define CARD_DOWN 0x00000000
425 #define CARD_UP 0x00000001
426 #define CARD_FAIL 0x00000002
427 #define CARD_DIAG 0x00000003
428 #define CARD_SLEEP 0x00000004
430 #define ADAPT_DOWN 0x00
431 #define ADAPT_UP 0x01
432 #define ADAPT_FAIL 0x02
433 #define ADAPT_RESET 0x03
434 #define ADAPT_SLEEP 0x04
436 #define ADAPT_FLAGS_BOOTTIME 0x0001
437 #define ADAPT_FLAGS_IS64BIT 0x0002
438 #define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
439 #define ADAPT_FLAGS_FIBERMEDIA 0x0008
440 #define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
441 #define ADAPT_FLAGS_INT_REGISTERED 0x0020
442 #define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
443 #define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
444 #define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
446 #define LINK_DOWN 0x00
447 #define LINK_CONFIG 0x01
450 #define LINK_10MB 0x00
451 #define LINK_100MB 0x01
452 #define LINK_AUTOSPEED 0x02
453 #define LINK_1000MB 0x03
454 #define LINK_10000MB 0x04
456 #define LINK_HALFD 0x00
457 #define LINK_FULLD 0x01
458 #define LINK_AUTOD 0x02
460 #define MAC_DIRECTED 0x00000001
461 #define MAC_BCAST 0x00000002
462 #define MAC_MCAST 0x00000004
463 #define MAC_PROMISC 0x00000008
464 #define MAC_LOOPBACK 0x00000010
465 #define MAC_ALLMCAST 0x00000020
467 #define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
468 #define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
469 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
470 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
471 #define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
474 struct ether_header {
475 unsigned char ether_dhost[6];
476 unsigned char ether_shost[6];
481 #define NUM_CFG_SPACES 2
482 #define NUM_CFG_REGS 64
485 struct adapter_t *adapter[SLIC_MAX_PORTS];
486 struct physcard_t *next;
487 unsigned int adapters_allocd;
490 struct sxgbase_driver_t {
491 spinlock_t driver_lock;
492 unsigned long flags; /* irqsave for spinlock */
495 u32 num_sxg_ports_active;
497 struct physcard_t *phys_card;
504 struct physcard_t *physcard;
505 unsigned int physport;
506 unsigned int slotnumber;
507 unsigned int functionnumber;
513 void __iomem * base_addr;
517 unsigned int activated;
519 unsigned int isp_initialized;
521 unsigned char linkstate;
523 unsigned char macaddr[6];
524 unsigned char currmacaddr[6];
526 ushort devflags_prev;
528 struct mcast_address_t *mcastaddrs;
529 struct timer_list pingtimer;
531 struct timer_list statstimer;
533 struct timer_list vpci_timer;
535 struct timer_list loadtimer;
542 u32 error_interrupts;
543 u32 error_rmiss_interrupts;
548 u32 linkevent_interrupts;
551 u32 false_interrupts;
560 u32 rcv_interrupt_yields;
562 struct net_device_stats stats;
563 u32 * MiniportHandle; // Our miniport handle
564 enum SXG_STATE State; // Adapter state
565 enum SXG_LINK_STATE LinkState; // Link state
566 u64 LinkSpeed; // Link Speed
567 u32 PowerState; // NDIS power state
568 struct adapter_t *Next; // Linked list
569 ushort AdapterID; // 1..n
571 p_net_device next_netdevice;
572 struct pci_dev * pcidev;
574 struct SXG_MULTICAST_ADDRESS *MulticastAddrs; // Multicast list
575 u64 MulticastMask; // Multicast mask
576 u32 * InterruptHandle; // Register Interrupt handle
577 u32 InterruptLevel; // From Resource list
578 u32 InterruptVector; // From Resource list
579 spinlock_t AdapterLock; /* Serialize access adapter routines */
580 spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
581 struct SXG_HW_REGS *HwRegs; // Sahara HW Register Memory (BAR0/1)
582 struct SXG_UCODE_REGS *UcodeRegs; // Microcode Register Memory (BAR2/3)
583 struct SXG_TCB_REGS *TcbRegs; // Same as Ucode regs - See sxghw.h
584 ushort FrameSize; // Maximum frame size
585 u32 * DmaHandle; // NDIS DMA handle
586 u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
587 u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
588 u32 MacFilter; // NDIS MAC Filter
589 struct SXG_EVENT_RING *EventRings; // Host event rings. 1/CPU to 16 max
590 dma_addr_t PEventRings; // Physical address
591 u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
592 dma_addr_t PTcbBuffers; // TCB Buffers - physical address
593 dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
594 struct SXG_XMT_RING *XmtRings; // Transmit rings
595 dma_addr_t PXmtRings; // Transmit rings - physical address
596 struct SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
597 spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
598 u32 * XmtRingZeroIndex; // Shared XMT ring 0 index
599 dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical
600 struct LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
601 u32 FreeProtoHdrCount; // Count
602 void * ProtocolHeaders; // Block of protocol header
603 dma_addr_t PProtocolHeaders; // Block of protocol headers - phys
605 struct SXG_RCV_RING *RcvRings; // Receive rings
606 dma_addr_t PRcvRings; // Receive rings - physical address
607 struct SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
609 u32 * Isr; // Interrupt status register
610 dma_addr_t PIsr; // ISR - physical address
611 u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR
612 ushort InterruptsEnabled; // Bitmask of enabled vectors
613 unsigned char * IndirectionTable; // RSS indirection table
614 dma_addr_t PIndirectionTable; // Physical address
615 ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS
616 ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS
617 unsigned char HashSecretKey[40]; // rss key
619 // Receive buffer queues
620 spinlock_t RcvQLock; /* Receive Queue Lock */
621 struct LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
622 struct LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
623 struct LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
624 ushort FreeRcvBufferCount; // Number of free rcv data buffers
625 ushort FreeRcvBlockCount; // # of free rcv descriptor blocks
626 ushort AllRcvBlockCount; // Number of total receive blocks
627 ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only
628 u32 AllocationsPending; // Receive allocation pending
629 u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card
631 spinlock_t SglQLock; /* SGL Queue Lock */
632 struct LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
633 struct LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
634 ushort FreeSglBufferCount; // Number of free SGL buffers
635 ushort AllSglBufferCount; // Number of total SGL buffers
636 u32 CurrentTime; // Tick count
637 u32 FastpathConnections;// # of fastpath connections
638 // Various single-bit flags:
639 u32 BasicAllocations:1; // Locks and listheads
640 u32 IntRegistered:1; // Interrupt registered
641 u32 PingOutstanding:1; // Ping outstanding to card
642 u32 Dead:1; // Card dead
643 u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request
644 u32 DumpCard:1; // OID_SLIC_CARD_DUMP request
645 u32 DumpCmdRunning:1; // Dump command in progress
646 u32 DebugRunning:1; // AGDB debug in progress
647 u32 JumboEnabled:1; // Jumbo frames enabled
648 u32 MsiEnabled:1; // MSI interrupt enabled
649 u32 RssEnabled:1; // RSS Enabled
650 u32 FailOnBadEeprom:1; // Fail on Bad Eeprom
651 u32 DiagStart:1; // Init adapter for diagnostic start
653 u32 PendingRcvCount; // Outstanding rcv indications
654 u32 PendingXmtCount; // Outstanding send requests
655 struct SXG_STATS Stats; // Statistics
656 u32 ReassBufs; // Number of reassembly buffers
658 ushort CrashLocation; // Microcode crash location
659 unsigned char CrashCpu; // Sahara CPU ID
661 // PDIAG_CMD DiagCmds; // List of free diagnostic commands
662 // PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers
663 // PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests
664 // u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var?
665 // unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx)
667 /////////////////////////////////////////////////////////////////////
668 // Put preprocessor-conditional fields at the end so we don't
669 // have to recompile sxgdbg everytime we reconfigure the driver
670 /////////////////////////////////////////////////////////////////////
671 #if defined(CONFIG_X86)
672 u32 AddrUpper; // Upper 32 bits of 64-bit register
674 //#if SXG_FAILURE_DUMP
675 // NDIS_EVENT DumpThreadEvent; // syncronize dump thread
676 // BOOLEAN DumpThreadRunning; // termination flag
677 // PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer
678 // dma_addr_t PDumpBuffer; // Physical address
679 //#endif // SXG_FAILURE_DUMP
683 #if SLIC_DUMP_ENABLED
684 #define SLIC_DUMP_REQUESTED 1
685 #define SLIC_DUMP_IN_PROGRESS 2
686 #define SLIC_DUMP_DONE 3
688 /****************************************************************************
690 * Microcode crash information structure. This
691 * structure is written out to the card's SRAM when the microcode panic's.
693 ****************************************************************************/
694 struct slic_crash_info {
699 #define CRASH_INFO_OFFSET 0x155C
703 #define UPDATE_STATS(largestat, newstat, oldstat) \
705 if ((newstat) < (oldstat)) \
706 (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
708 (largestat) += ((newstat) - (oldstat)); \
711 #define UPDATE_STATS_GB(largestat, newstat, oldstat) \
713 (largestat) += ((newstat) - (oldstat)); \
716 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
719 if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
721 if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
725 #define ETHERMAXFRAME 1514
726 #define JUMBOMAXFRAME 9014
728 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
729 #define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
730 #define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
732 #define SXG_GET_ADDR_LOW(_addr) (u32)_addr
733 #define SXG_GET_ADDR_HIGH(_addr) (u32)0
737 #define DONT_FLUSH FALSE
739 #define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9
740 #define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10
741 #define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11
743 #endif /* __SXG_DRIVER_H__ */