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   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #include "r8192S_hw.h"
  39 #include "r8192S_phy.h"
  40 #include "r8192S_phyreg.h"
  41 #include "r8192SU_HWImg.h"
  42
  43 #include "ieee80211/dot11d.h"
  44
  45 /*---------------------------Define Local Constant---------------------------*/
  46 /* Channel switch:The size of command tables for switch channel*/
  47 #define MAX_PRECMD_CNT 16
  48 #define MAX_RFDEPENDCMD_CNT 16
  49 #define MAX_POSTCMD_CNT 16
  50 #define MAX_DOZE_WAITING_TIMES_9x 64
  51
  52 /*------------------------Define local variable------------------------------*/
  53 // 2004-05-11
  54
  55 static  u32
  56 phy_CalculateBitShift(u32 BitMask);
  57 static  RT_STATUS
  58 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  59 static void
  60 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  61 static  RT_STATUS
  62 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  63 static  RT_STATUS
  64 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  65 static bool
  66 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  67 void
  68 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  69 void
  70 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  71 void
  72 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
  73 static void
  74 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
  75 static bool
  76 phy_SwChnlStepByStep(
  77         struct net_device* dev,
  78         u8              channel,
  79         u8              *stage,
  80         u8              *step,
  81         u32             *delay
  82         );
  83 static RT_STATUS
  84 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
  85 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
  86 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
  87 void phy_SetFwCmdIOCallback(struct net_device* dev);
  88
  89 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
  90 //
  91 // Description:
  92 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
  93 //
  94 // Assumption:
  95 //              -       Only use on RTL8192S USB interface.
  96 //              -       PASSIVE LEVEL
  97 //
  98 // Created by Roger, 2008.09.06.
  99 //
 100 //use in phy only
 101 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 102 {
 103         struct r8192_priv *priv = ieee80211_priv(dev);
 104         u32     ReturnValue = 0xffffffff;
 105         u8      PollingCnt = 50;
 106         u8      BBWaitCounter = 0;
 107
 108
 109         //
 110         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 111         // We have to make sure that previous BB I/O has been done.
 112         // 2008.08.20.
 113         //
 114         while(priv->bChangeBBInProgress)
 115         {
 116                 BBWaitCounter ++;
 117                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 118                 msleep(1); // 1 ms
 119
 120                 // Wait too long, return FALSE to avoid to be stuck here.
 121                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 122                 {
 123                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 124                         return ReturnValue;
 125                 }
 126         }
 127
 128         priv->bChangeBBInProgress = true;
 129
 130         read_nic_dword(dev, RegAddr);
 131
 132         do
 133         {// Make sure that access could be done.
 134                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 135                         break;
 136         }while( --PollingCnt );
 137
 138         if(PollingCnt == 0)
 139         {
 140                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 141         }
 142         else
 143         {
 144                 // Data FW read back.
 145                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 146                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 147         }
 148
 149         priv->bChangeBBInProgress = false;
 150
 151         return ReturnValue;
 152 }
 153
 154
 155
 156 //
 157 // Description:
 158 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 159 //
 160 // Assumption:
 161 //              -       Only use on RTL8192S USB interface.
 162 //              -       PASSIVE LEVEL
 163 //
 164 // Created by Roger, 2008.09.06.
 165 //
 166 //use in phy only
 167 void
 168 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 169 {
 170         struct r8192_priv *priv = ieee80211_priv(dev);
 171         u8      BBWaitCounter = 0;
 172
 173         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 174
 175         //
 176         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 177         // We have to make sure that previous BB I/O has been done.
 178         // 2008.08.20.
 179         //
 180         while(priv->bChangeBBInProgress)
 181         {
 182                 BBWaitCounter ++;
 183                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 184                 msleep(1); // 1 ms
 185
 186                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 187                 {
 188                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 189                         return;
 190                 }
 191         }
 192
 193         priv->bChangeBBInProgress = true;
 194         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 195         write_nic_dword(dev, RegAddr, Data);
 196
 197         priv->bChangeBBInProgress = false;
 198 }
 199
 200
 201
 202 //
 203 // Description:
 204 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 205 //
 206 // Assumption:
 207 //              -       Only use on RTL8192S USB interface.
 208 //              -       PASSIVE LEVEL
 209 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 210 //
 211 // Created by Roger, 2008.09.06.
 212 //
 213 //use in phy only
 214 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 215 {
 216
 217         struct r8192_priv *priv = ieee80211_priv(dev);
 218         //u32   value  = 0, ReturnValue = 0;
 219         u32     ReturnValue = 0;
 220         //u32   tmplong,tmplong2;
 221         u8      PollingCnt = 50;
 222         u8      RFWaitCounter = 0;
 223
 224
 225         //
 226         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 227         // We have to make sure that previous RF I/O has been done.
 228         // 2008.08.20.
 229         //
 230         while(priv->bChangeRFInProgress)
 231         {
 232                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 233                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 234                 down(&priv->rf_sem);
 235
 236                 RFWaitCounter ++;
 237                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 238                 msleep(1); // 1 ms
 239
 240                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 241                 {
 242                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 243                         return 0xffffffff;
 244                 }
 245                 else
 246                 {
 247                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 248                 }
 249         }
 250
 251         priv->bChangeRFInProgress = true;
 252         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 253
 254
 255         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 256
 257         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 258                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 259                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 260
 261         do
 262         {// Make sure that access could be done.
 263                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 264                         break;
 265         }while( --PollingCnt );
 266
 267         // Data FW read back.
 268         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 269
 270         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 271         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 272         up(&priv->rf_sem);
 273         priv->bChangeRFInProgress = false;
 274
 275         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 276
 277         return ReturnValue;
 278
 279 }
 280
 281
 282 //
 283 // Description:
 284 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 285 //
 286 // Assumption:
 287 //              -       Only use on RTL8192S USB interface.
 288 //              -       PASSIVE LEVEL
 289 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 290 //
 291 // Created by Roger, 2008.09.06.
 292 //
 293 //use in phy only
 294 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 295 {
 296
 297         struct r8192_priv *priv = ieee80211_priv(dev);
 298         u8      PollingCnt = 50;
 299         u8      RFWaitCounter = 0;
 300
 301
 302         //
 303         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 304         // We have to make sure that previous BB I/O has been done.
 305         // 2008.08.20.
 306         //
 307         while(priv->bChangeRFInProgress)
 308         {
 309                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 310                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 311                 down(&priv->rf_sem);
 312
 313                 RFWaitCounter ++;
 314                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 315                 msleep(1); // 1 ms
 316
 317                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 318                 {
 319                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 320                         return;
 321                 }
 322                 else
 323                 {
 324                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 325                 }
 326         }
 327
 328         priv->bChangeRFInProgress = true;
 329         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 330
 331
 332         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 333
 334         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 335         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 336                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 337                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 338
 339         do
 340         {// Make sure that access could be done.
 341                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 342                                 break;
 343         }while( --PollingCnt );
 344
 345         if(PollingCnt == 0)
 346         {
 347                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 348         }
 349
 350         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 351         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 352         up(&priv->rf_sem);
 353         priv->bChangeRFInProgress = false;
 354
 355 }
 356
 357
 358 /*---------------------Define local function prototype-----------------------*/
 359
 360
 361 /*----------------------------Function Body----------------------------------*/
 362 //
 363 // 1. BB register R/W API
 364 //
 365 /**
 366 * Function:     PHY_QueryBBReg
 367 *
 368 * OverView:     Read "sepcific bits" from BB register
 369 *
 370 * Input:
 371 *                       PADAPTER                Adapter,
 372 *                       u32                     RegAddr,                //The target address to be readback
 373 *                       u32                     BitMask         //The target bit position in the target address
 374 *                                                                               //to be readback
 375 * Output:       None
 376 * Return:               u32                     Data                    //The readback register value
 377 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 378 */
 379 //use phy dm core 8225 8256 6052
 380 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 381 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 382 {
 383
 384         u32     ReturnValue = 0, OriginalValue, BitShift;
 385
 386
 387         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 388
 389         //
 390         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 391         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 392         // infinite cycle.
 393         // 2008.09.06.
 394         //
 395 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 396         if(IS_BB_REG_OFFSET_92S(RegAddr))
 397         {
 398                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 399
 400                 if((RegAddr & 0x03) != 0)
 401                 {
 402                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 403                         return 0;
 404                 }
 405
 406         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 407         }
 408         else
 409         {
 410         OriginalValue = read_nic_dword(dev, RegAddr);
 411         }
 412
 413         BitShift = phy_CalculateBitShift(BitMask);
 414         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 415
 416         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 417         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 418         return (ReturnValue);
 419 }
 420
 421 /**
 422 * Function:     PHY_SetBBReg
 423 *
 424 * OverView:     Write "Specific bits" to BB register (page 8~)
 425 *
 426 * Input:
 427 *                       PADAPTER                Adapter,
 428 *                       u32                     RegAddr,                //The target address to be modified
 429 *                       u32                     BitMask         //The target bit position in the target address
 430 *                                                                               //to be modified
 431 *                       u32                     Data                    //The new register value in the target bit position
 432 *                                                                               //of the target address
 433 *
 434 * Output:       None
 435 * Return:               None
 436 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 437 */
 438 //use phy dm core 8225 8256
 439 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 440 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 441 {
 442         u32     OriginalValue, BitShift, NewValue;
 443
 444
 445         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 446
 447         //
 448         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 449         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 450         // infinite cycle.
 451         // 2008.09.06.
 452         //
 453 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 454         if(IS_BB_REG_OFFSET_92S(RegAddr))
 455         {
 456                 if((RegAddr & 0x03) != 0)
 457                 {
 458                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 459                         return;
 460                 }
 461
 462                 if(BitMask!= bMaskDWord)
 463                 {//if not "double word" write
 464                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 465                         BitShift = phy_CalculateBitShift(BitMask);
 466             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 467                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 468                 }else
 469                         phy_SetUsbBBReg(dev, RegAddr, Data);
 470         }
 471         else
 472         {
 473                 if(BitMask!= bMaskDWord)
 474                 {//if not "double word" write
 475                         OriginalValue = read_nic_dword(dev, RegAddr);
 476                         BitShift = phy_CalculateBitShift(BitMask);
 477                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 478                         write_nic_dword(dev, RegAddr, NewValue);
 479                 }else
 480                         write_nic_dword(dev, RegAddr, Data);
 481         }
 482
 483         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 484
 485         return;
 486 }
 487
 488
 489 //
 490 // 2. RF register R/W API
 491 //
 492 /**
 493 * Function:     PHY_QueryRFReg
 494 *
 495 * OverView:     Query "Specific bits" to RF register (page 8~)
 496 *
 497 * Input:
 498 *                       PADAPTER                Adapter,
 499 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 500 *                       u32                     RegAddr,                //The target address to be read
 501 *                       u32                     BitMask         //The target bit position in the target address
 502 *                                                                               //to be read
 503 *
 504 * Output:       None
 505 * Return:               u32                     Readback value
 506 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 507 */
 508 //in dm 8256 and phy
 509 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 510 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 511 {
 512         u32 Original_Value, Readback_Value, BitShift;//, flags;
 513         struct r8192_priv *priv = ieee80211_priv(dev);
 514
 515
 516         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 517
 518         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 519         {
 520                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 521                 return 0;
 522         }
 523
 524         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 525         {
 526                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 527                 return 0;
 528         }
 529
 530         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 531         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 532         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 533         down(&priv->rf_sem);
 534         //
 535         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 536         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 537         // infinite cycle.
 538         // 2008.09.06.
 539         //
 540 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 541         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 542         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 543
 544         BitShift =  phy_CalculateBitShift(BitMask);
 545         Readback_Value = (Original_Value & BitMask) >> BitShift;
 546         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 547         up(&priv->rf_sem);
 548         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 549
 550         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 551
 552         return (Readback_Value);
 553 }
 554
 555 /**
 556 * Function:     PHY_SetRFReg
 557 *
 558 * OverView:     Write "Specific bits" to RF register (page 8~)
 559 *
 560 * Input:
 561 *                       PADAPTER                Adapter,
 562 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 563 *                       u32                     RegAddr,                //The target address to be modified
 564 *                       u32                     BitMask         //The target bit position in the target address
 565 *                                                                               //to be modified
 566 *                       u32                     Data                    //The new register Data in the target bit position
 567 *                                                                               //of the target address
 568 *
 569 * Output:       None
 570 * Return:               None
 571 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 572 */
 573 //use phy  8225 8256
 574 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 575 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 576 {
 577
 578         struct r8192_priv *priv = ieee80211_priv(dev);
 579         u32 Original_Value, BitShift, New_Value;//, flags;
 580
 581         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 582                 RegAddr, BitMask, Data, eRFPath);
 583
 584         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 585         {
 586                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 587                 return ;
 588         }
 589         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 590         {
 591                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 592                 return;
 593         }
 594
 595         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 596         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 597         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 598         down(&priv->rf_sem);
 599         //
 600         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 601         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 602         // infinite cycle.
 603         // 2008.09.06.
 604         //
 605 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 606                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 607
 608                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 609                 {
 610                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 611                         BitShift =  phy_CalculateBitShift(BitMask);
 612                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 613                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 614                 }
 615                 else
 616                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 617         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 618         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 619         up(&priv->rf_sem);
 620         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 621         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 622                         RegAddr, BitMask, Data, eRFPath);
 623
 624 }
 625
 626 /**
 627 * Function:     phy_CalculateBitShift
 628 *
 629 * OverView:     Get shifted position of the BitMask
 630 *
 631 * Input:
 632 *                       u32             BitMask,
 633 *
 634 * Output:       none
 635 * Return:               u32             Return the shift bit bit position of the mask
 636 */
 637 //use in phy only
 638 static u32 phy_CalculateBitShift(u32 BitMask)
 639 {
 640         u32 i;
 641
 642         for(i=0; i<=31; i++)
 643         {
 644                 if ( ((BitMask>>i) &  0x1 ) == 1)
 645                         break;
 646         }
 647
 648         return (i);
 649 }
 650
 651
 652 //
 653 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 654 //
 655 /*-----------------------------------------------------------------------------
 656  * Function:    PHY_MACConfig8192S
 657  *
 658  * Overview:    Condig MAC by header file or parameter file.
 659  *
 660  * Input:       NONE
 661  *
 662  * Output:      NONE
 663  *
 664  * Return:      NONE
 665  *
 666  * Revised History:
 667  *  When                Who             Remark
 668  *  08/12/2008  MHC             Create Version 0.
 669  *
 670  *---------------------------------------------------------------------------*/
 671 //adapter_start
 672 extern bool PHY_MACConfig8192S(struct net_device* dev)
 673 {
 674         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 675
 676         //
 677         // Config MAC
 678         //
 679         rtStatus = phy_ConfigMACWithHeaderFile(dev);
 680         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
 681
 682 }
 683
 684 //adapter_start
 685 extern  bool
 686 PHY_BBConfig8192S(struct net_device* dev)
 687 {
 688         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
 689
 690         u8 PathMap = 0, index = 0, rf_num = 0;
 691         struct r8192_priv       *priv = ieee80211_priv(dev);
 692         phy_InitBBRFRegisterDefinition(dev);
 693
 694         //
 695         // Config BB and AGC
 696         //
 697         //switch( Adapter->MgntInfo.bRegHwParaFile )
 698         //{
 699         //      case 0:
 700         //              phy_BB8190_Config_HardCode(dev);
 701         //              break;
 702
 703         //      case 1:
 704                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
 705         //              break;
 706
 707         //      case 2:
 708                         // Partial Modify.
 709         //              phy_BB8190_Config_HardCode(dev);
 710         //              phy_BB8192S_Config_ParaFile(dev);
 711         //              break;
 712
 713         //      default:
 714         //              phy_BB8190_Config_HardCode(dev);
 715         //              break;
 716         //}
 717         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
 718                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
 719         priv->rf_pathmap = PathMap;
 720         for(index = 0; index<4; index++)
 721         {
 722                 if((PathMap>>index)&0x1)
 723                         rf_num++;
 724         }
 725
 726         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
 727                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
 728                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
 729                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
 730                 (priv->rf_type==RF_2T4R && rf_num!=4))
 731         {
 732                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
 733         }
 734         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
 735 }
 736
 737 //adapter_start
 738 extern  bool
 739 PHY_RFConfig8192S(struct net_device* dev)
 740 {
 741         struct r8192_priv       *priv = ieee80211_priv(dev);
 742         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 743
 744         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
 745
 746         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
 747         priv->rf_chip = RF_6052;
 748
 749         //
 750         // RF config
 751         //
 752         switch(priv->rf_chip)
 753         {
 754         case RF_8225:
 755         case RF_6052:
 756                 rtStatus = PHY_RF6052_Config(dev);
 757                 break;
 758
 759         case RF_8256:
 760                 //rtStatus = PHY_RF8256_Config(dev);
 761                 break;
 762
 763         case RF_8258:
 764                 break;
 765
 766         case RF_PSEUDO_11N:
 767                 //rtStatus = PHY_RF8225_Config(dev);
 768                 break;
 769         default:
 770             break;
 771         }
 772
 773         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
 774 }
 775
 776
 777 // Joseph test: new initialize order!!
 778 // Test only!! This part need to be re-organized.
 779 // Now it is just for 8256.
 780 //use in phy only
 781 #ifdef TO_DO_LIST
 782 static RT_STATUS
 783 phy_BB8190_Config_HardCode(struct net_device* dev)
 784 {
 785         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
 786         return RT_STATUS_SUCCESS;
 787 }
 788 #endif
 789
 790 /*-----------------------------------------------------------------------------
 791  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
 792  *
 793  * Overview:    This function
 794  *
 795  *
 796  * Input:       PADAPTER                Adapter
 797  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
 798  *
 799  * Output:      NONE
 800  *
 801  * Return:      RT_STATUS_SUCCESS: configuration file exist
 802  * When                 Who             Remark
 803  * 2008/11/10   tynli
 804  * use in phy only
 805  *---------------------------------------------------------------------------*/
 806 static RT_STATUS
 807 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
 808 {
 809         int i;
 810         struct r8192_priv       *priv = ieee80211_priv(dev);
 811         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
 812         u16                             PHY_REGArraytoXTXRLen;
 813
 814 //#if (HAL_CODE_BASE != RTL8192_S)
 815
 816         if(priv->rf_type == RF_1T1R)
 817         {
 818                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
 819                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
 820         }
 821         else if(priv->rf_type == RF_1T2R)
 822         {
 823                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
 824                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
 825         }
 826         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
 827         //{
 828         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
 829         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
 830         //}
 831         else
 832         {
 833                 return RT_STATUS_FAILURE;
 834         }
 835
 836         if(ConfigType == BaseBand_Config_PHY_REG)
 837         {
 838                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
 839                 {
 840                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
 841                                 mdelay(50);
 842                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
 843                                 mdelay(5);
 844                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
 845                                 mdelay(1);
 846                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
 847                                 udelay(50);
 848                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
 849                                 udelay(5);
 850                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
 851                                 udelay(1);
 852                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
 853                         //RT_TRACE(COMP_SEND,
 854                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
 855                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
 856                 }
 857         }
 858         else {
 859                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
 860         }
 861 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
 862         return RT_STATUS_SUCCESS;
 863 }
 864
 865
 866 //use in phy only
 867 static  RT_STATUS
 868 phy_BB8192S_Config_ParaFile(struct net_device* dev)
 869 {
 870         struct r8192_priv       *priv = ieee80211_priv(dev);
 871         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
 872         //u8                            u2RegValue;
 873         //u16                           u4RegValue;
 874         //char                          szBBRegFile[] = RTL819X_PHY_REG;
 875         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
 876         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
 877         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
 878         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
 879         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
 880
 881         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
 882
 883         //
 884         // 1. Read PHY_REG.TXT BB INIT!!
 885         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
 886         //
 887         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
 888             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
 889         {
 890                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
 891                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
 892                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
 893                   //so we should reconfig BB reg with the right PHY parameters.
 894                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
 895                 }
 896         }else
 897                 rtStatus = RT_STATUS_FAILURE;
 898
 899         if(rtStatus != RT_STATUS_SUCCESS){
 900                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
 901                 goto phy_BB8190_Config_ParaFile_Fail;
 902         }
 903
 904         //
 905         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
 906         //
 907         if (priv->AutoloadFailFlag == false)
 908         {
 909                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
 910         }
 911         if(rtStatus != RT_STATUS_SUCCESS){
 912                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
 913                 goto phy_BB8190_Config_ParaFile_Fail;
 914         }
 915
 916         //
 917         // 3. BB AGC table Initialization
 918         //
 919         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
 920
 921         if(rtStatus != RT_STATUS_SUCCESS){
 922                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
 923                 goto phy_BB8190_Config_ParaFile_Fail;
 924         }
 925
 926
 927         // Check if the CCK HighPower is turned ON.
 928         // This is used to calculate PWDB.
 929         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
 930
 931
 932 phy_BB8190_Config_ParaFile_Fail:
 933         return rtStatus;
 934 }
 935
 936 /*-----------------------------------------------------------------------------
 937  * Function:    phy_ConfigMACWithHeaderFile()
 938  *
 939  * Overview:    This function read BB parameters from Header file we gen, and do register
 940  *                        Read/Write
 941  *
 942  * Input:       PADAPTER                Adapter
 943  *                      char*                   pFileName
 944  *
 945  * Output:      NONE
 946  *
 947  * Return:      RT_STATUS_SUCCESS: configuration file exist
 948  *
 949  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
 950  *                      [Register][Mask][Value]
 951  *---------------------------------------------------------------------------*/
 952 //use in phy only
 953 static  RT_STATUS
 954 phy_ConfigMACWithHeaderFile(struct net_device* dev)
 955 {
 956         u32                                     i = 0;
 957         u32                                     ArrayLength = 0;
 958         u32*                                    ptrArray;
 959         //struct r8192_priv     *priv = ieee80211_priv(dev);
 960
 961 //#if (HAL_CODE_BASE != RTL8192_S)
 962         /*if(Adapter->bInHctTest)
 963         {
 964                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
 965                 ArrayLength = MACPHY_ArrayLengthDTM;
 966                 ptrArray = Rtl819XMACPHY_ArrayDTM;
 967         }
 968         else if(pHalData->bTXPowerDataReadFromEEPORM)
 969         {
 970 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
 971 //              ArrayLength = MACPHY_Array_PGLength;
 972 //              ptrArray = Rtl819XMACPHY_Array_PG;
 973
 974         }else*/
 975         { //2008.11.06 Modified by tynli.
 976                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
 977                 ArrayLength = MAC_2T_ArrayLength;
 978                 ptrArray = Rtl819XMAC_Array;
 979         }
 980
 981         /*for(i = 0 ;i < ArrayLength;i=i+3){
 982                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
 983                 if(ptrArray[i] == 0x318)
 984                 {
 985                         ptrArray[i+2] = 0x00000800;
 986                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
 987                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
 988                 }
 989                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
 990         }*/
 991         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
 992                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
 993         }
 994 //#endif
 995         return RT_STATUS_SUCCESS;
 996 }
 997
 998 /*-----------------------------------------------------------------------------
 999  * Function:    phy_ConfigBBWithHeaderFile()
1000  *
1001  * Overview:    This function read BB parameters from general file format, and do register
1002  *                        Read/Write
1003  *
1004  * Input:       PADAPTER                Adapter
1005  *                      u8                      ConfigType     0 => PHY_CONFIG
1006  *                                                                               1 =>AGC_TAB
1007  *
1008  * Output:      NONE
1009  *
1010  * Return:      RT_STATUS_SUCCESS: configuration file exist
1011  *
1012  *---------------------------------------------------------------------------*/
1013 //use in phy only
1014 static  RT_STATUS
1015 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1016 {
1017         int             i;
1018         //u8            ArrayLength;
1019         u32*    Rtl819XPHY_REGArray_Table;
1020         u32*    Rtl819XAGCTAB_Array_Table;
1021         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1022         //struct r8192_priv *priv = ieee80211_priv(dev);
1023 //#if (HAL_CODE_BASE != RTL8192_S)
1024         /*if(Adapter->bInHctTest)
1025         {
1026
1027                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1028                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1029
1030                 if(pHalData->RF_Type == RF_2T4R)
1031                 {
1032                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1033                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1034                 }
1035                 else if (pHalData->RF_Type == RF_1T2R)
1036                 {
1037                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1038                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1039                 }
1040
1041         }
1042         else
1043         */
1044         //{
1045         //
1046         // 2008.11.06 Modified by tynli.
1047         //
1048         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1049         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1050         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1051         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1052         //}
1053
1054         if(ConfigType == BaseBand_Config_PHY_REG)
1055         {
1056                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1057                 {
1058                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1059                                 mdelay(50);
1060                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1061                                 mdelay(5);
1062                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1063                                 mdelay(1);
1064                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1065                                 udelay(50);
1066                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1067                                 udelay(5);
1068                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1069                                 udelay(1);
1070                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1071                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1072
1073                 }
1074         }
1075         else if(ConfigType == BaseBand_Config_AGC_TAB){
1076                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1077                 {
1078                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1079                 }
1080         }
1081 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1082         return RT_STATUS_SUCCESS;
1083 }
1084
1085 /*-----------------------------------------------------------------------------
1086  * Function:    phy_ConfigBBWithPgHeaderFile
1087  *
1088  * Overview:    Config PHY_REG_PG array
1089  *
1090  * Input:       NONE
1091  *
1092  * Output:      NONE
1093  *
1094  * Return:      NONE
1095  *
1096  * Revised History:
1097  * When                 Who             Remark
1098  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1099  * 11/10/2008   tynli           Modify to mew files.
1100  //use in phy only
1101  *---------------------------------------------------------------------------*/
1102 static RT_STATUS
1103 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1104 {
1105         int i;
1106         //u8 ArrayLength;
1107         u32*    Rtl819XPHY_REGArray_Table_PG;
1108         u16     PHY_REGArrayPGLen;
1109         //struct r8192_priv *priv = ieee80211_priv(dev);
1110 //#if (HAL_CODE_BASE != RTL8192_S)
1111         // Default: pHalData->RF_Type = RF_2T2R.
1112
1113         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1114         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1115
1116         if(ConfigType == BaseBand_Config_PHY_REG)
1117         {
1118                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1119                 {
1120                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1121                                 mdelay(50);
1122                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1123                                 mdelay(5);
1124                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1125                                 mdelay(1);
1126                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1127                                 udelay(50);
1128                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1129                                 udelay(5);
1130                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1131                                 udelay(1);
1132                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1133                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1134                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1135                 }
1136         }else{
1137                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1138         }
1139         return RT_STATUS_SUCCESS;
1140
1141 }       /* phy_ConfigBBWithPgHeaderFile */
1142
1143 /*-----------------------------------------------------------------------------
1144  * Function:    PHY_ConfigRFWithHeaderFile()
1145  *
1146  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1147  *
1148  * Input:       PADAPTER                        Adapter
1149  *                      char*                           pFileName
1150  *                      RF90_RADIO_PATH_E       eRFPath
1151  *
1152  * Output:      NONE
1153  *
1154  * Return:      RT_STATUS_SUCCESS: configuration file exist
1155  *
1156  * Note:                Delay may be required for RF configuration
1157  *---------------------------------------------------------------------------*/
1158 //in 8256 phy_RF8256_Config_ParaFile only
1159 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1160 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1161 {
1162
1163         struct r8192_priv *priv = ieee80211_priv(dev);
1164         int                     i;
1165         //u32*  pRFArray;
1166         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1167         u32                     *Rtl819XRadioA_Array_Table;
1168         u32                     *Rtl819XRadioB_Array_Table;
1169         //u32*  Rtl819XRadioC_Array_Table;
1170         //u32*  Rtl819XRadioD_Array_Table;
1171         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1172
1173         {       //2008.11.06 Modified by tynli
1174                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1175                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1176                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1177                 RadioB_ArrayLen = RadioB_ArrayLength;
1178         }
1179
1180         if( priv->rf_type == RF_2T2R_GREEN )
1181         {
1182                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1183                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1184         }
1185         else
1186         {
1187                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1188                 RadioB_ArrayLen = RadioB_ArrayLength;
1189         }
1190
1191         rtStatus = RT_STATUS_SUCCESS;
1192
1193         // When initialization, we want the delay function(mdelay(), delay_us()
1194         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1195         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1196         // to run at Dispatch level to achive it.
1197         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1198
1199         switch(eRFPath){
1200                 case RF90_PATH_A:
1201                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1202                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1203                                         { // Deay specific ms. Only RF configuration require delay.
1204 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1205                                                 mdelay(1000);
1206                                 }
1207                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1208                                                 mdelay(5);
1209                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1210                                                 mdelay(1);
1211                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1212                                                 udelay(50);
1213                                                 //PlatformStallExecution(50);
1214                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1215                                                 udelay(5);
1216                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1217                                                 udelay(1);
1218                                         else
1219                                         {
1220                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1221                                         }
1222                         }
1223                         break;
1224                 case RF90_PATH_B:
1225                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1226                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1227                                         { // Deay specific ms. Only RF configuration require delay.
1228 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1229                                                 mdelay(1000);
1230                                 }
1231                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1232                                                 mdelay(5);
1233                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1234                                                 mdelay(1);
1235                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1236                                                 udelay(50);
1237                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1238                                                 udelay(5);
1239                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1240                                                 udelay(1);
1241                                         else
1242                                         {
1243                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1244                                         }
1245                         }
1246                         break;
1247                 case RF90_PATH_C:
1248                         break;
1249                 case RF90_PATH_D:
1250                         break;
1251                 default:
1252                         break;
1253         }
1254
1255         return rtStatus;
1256
1257 }
1258
1259 /*-----------------------------------------------------------------------------
1260  * Function:    PHY_CheckBBAndRFOK()
1261  *
1262  * Overview:    This function is write register and then readback to make sure whether
1263  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1264  *
1265  * Input:       PADAPTER                        Adapter
1266  *                      HW90_BLOCK_E            CheckBlock
1267  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
1268  *
1269  * Output:      NONE
1270  *
1271  * Return:      RT_STATUS_SUCCESS: PHY is OK
1272  *
1273  * Note:                This function may be removed in the ASIC
1274  *---------------------------------------------------------------------------*/
1275 //in 8256 phy_RF8256_Config_HardCode
1276 //but we don't use it temp
1277 RT_STATUS
1278 PHY_CheckBBAndRFOK(
1279         struct net_device* dev,
1280         HW90_BLOCK_E            CheckBlock,
1281         RF90_RADIO_PATH_E       eRFPath
1282         )
1283 {
1284         //struct r8192_priv *priv = ieee80211_priv(dev);
1285         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1286         u32                             i, CheckTimes = 4,ulRegRead = 0;
1287         u32                             WriteAddr[4];
1288         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1289
1290         // Initialize register address offset to be checked
1291         WriteAddr[HW90_BLOCK_MAC] = 0x100;
1292         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1293         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1294         WriteAddr[HW90_BLOCK_RF] = 0x3;
1295
1296         for(i=0 ; i < CheckTimes ; i++)
1297         {
1298
1299                 //
1300                 // Write Data to register and readback
1301                 //
1302                 switch(CheckBlock)
1303                 {
1304                 case HW90_BLOCK_MAC:
1305                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
1306                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1307                         break;
1308
1309                 case HW90_BLOCK_PHY0:
1310                 case HW90_BLOCK_PHY1:
1311                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1312                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1313                         break;
1314
1315                 case HW90_BLOCK_RF:
1316                         // When initialization, we want the delay function(mdelay(), delay_us()
1317                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1318                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1319                         // to run at Dispatch level to achive it.
1320                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
1321                         WriteData[i] &= 0xfff;
1322                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
1323                         // TODO: we should not delay for such a long time. Ask SD3
1324                         mdelay(10);
1325                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1326                         mdelay(10);
1327                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
1328                         break;
1329
1330                 default:
1331                         rtStatus = RT_STATUS_FAILURE;
1332                         break;
1333                 }
1334
1335
1336                 //
1337                 // Check whether readback data is correct
1338                 //
1339                 if(ulRegRead != WriteData[i])
1340                 {
1341                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
1342                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1343                         rtStatus = RT_STATUS_FAILURE;
1344                         break;
1345                 }
1346         }
1347
1348         return rtStatus;
1349 }
1350
1351 //no use temp in windows driver
1352 #ifdef TO_DO_LIST
1353 void
1354 PHY_SetRFPowerState8192SUsb(
1355         struct net_device* dev,
1356         RF_POWER_STATE  RFPowerState
1357         )
1358 {
1359         struct r8192_priv *priv = ieee80211_priv(dev);
1360         bool                    WaitShutDown = FALSE;
1361         u32                     DWordContent;
1362         //RF90_RADIO_PATH_E     eRFPath;
1363         u8                              eRFPath;
1364         BB_REGISTER_DEFINITION_T        *pPhyReg;
1365
1366         if(priv->SetRFPowerStateInProgress == TRUE)
1367                 return;
1368
1369         priv->SetRFPowerStateInProgress = TRUE;
1370
1371         // TODO: Emily, 2006.11.21, we should rewrite this function
1372
1373         if(RFPowerState==RF_SHUT_DOWN)
1374         {
1375                 RFPowerState=RF_OFF;
1376                 WaitShutDown=TRUE;
1377         }
1378
1379
1380         priv->RFPowerState = RFPowerState;
1381         switch( priv->rf_chip )
1382         {
1383         case RF_8225:
1384         case RF_6052:
1385                 switch( RFPowerState )
1386                 {
1387                 case RF_ON:
1388                         break;
1389
1390                 case RF_SLEEP:
1391                         break;
1392
1393                 case RF_OFF:
1394                         break;
1395                 }
1396                 break;
1397
1398         case RF_8256:
1399                 switch( RFPowerState )
1400                 {
1401                 case RF_ON:
1402                         break;
1403
1404                 case RF_SLEEP:
1405                         break;
1406
1407                 case RF_OFF:
1408                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1409                         {
1410                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1411                                         continue;
1412
1413                                 pPhyReg = &priv->PHYRegDef[eRFPath];
1414                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1415                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1416                         }
1417                         break;
1418                 }
1419                 break;
1420
1421         case RF_8258:
1422                 break;
1423         }// switch( priv->rf_chip )
1424
1425         priv->SetRFPowerStateInProgress = FALSE;
1426 }
1427 #endif
1428
1429 #ifdef RTL8192U
1430 //no use temp in windows driver
1431 void
1432 PHY_UpdateInitialGain(
1433         struct net_device* dev
1434         )
1435 {
1436         struct r8192_priv       *priv = ieee80211_priv(dev);
1437         //unsigned char                 *IGTable;
1438         //u8                    DIG_CurrentInitialGain = 4;
1439
1440         switch(priv->rf_chip)
1441         {
1442         case RF_8225:
1443                 break;
1444         case RF_8256:
1445                 break;
1446         case RF_8258:
1447                 break;
1448         case RF_PSEUDO_11N:
1449                 break;
1450         case RF_6052:
1451                 break;
1452         default:
1453                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
1454                 break;
1455         }
1456 }
1457 #endif
1458
1459 //YJ,modified,090107
1460 void PHY_GetHWRegOriginalValue(struct net_device* dev)
1461 {
1462         struct r8192_priv *priv = ieee80211_priv(dev);
1463
1464         // read tx power offset
1465         // Simulate 8192
1466         priv->MCSTxPowerLevelOriginalOffset[0] =
1467                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1468         priv->MCSTxPowerLevelOriginalOffset[1] =
1469                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1470         priv->MCSTxPowerLevelOriginalOffset[2] =
1471                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1472         priv->MCSTxPowerLevelOriginalOffset[3] =
1473                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1474         priv->MCSTxPowerLevelOriginalOffset[4] =
1475                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1476         priv->MCSTxPowerLevelOriginalOffset[5] =
1477                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1478
1479         // Read CCK offset
1480         priv->MCSTxPowerLevelOriginalOffset[6] =
1481                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1482         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1483         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1484         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1485         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1486
1487         // read rx initial gain
1488         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1489         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1490         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1491         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1492         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1493                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1494                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1495
1496         // read framesync
1497         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1498         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1499         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1500                                 rOFDM0_RxDetector3, priv->framesync);
1501 }
1502 //YJ,modified,090107,end
1503
1504
1505
1506 /**
1507 * Function:     phy_InitBBRFRegisterDefinition
1508 *
1509 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
1510 *
1511 * Input:
1512 *                       PADAPTER                Adapter,
1513 *
1514 * Output:       None
1515 * Return:               None
1516 * Note:         The initialization value is constant and it should never be changes
1517 */
1518 //use in phy only
1519 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
1520 {
1521         struct r8192_priv *priv = ieee80211_priv(dev);
1522
1523         // RF Interface Sowrtware Control
1524         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1525         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1526         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1527         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1528
1529         // RF Interface Readback Value
1530         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1531         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1532         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1533         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1534
1535         // RF Interface Output (and Enable)
1536         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1537         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1538         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1539         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1540
1541         // RF Interface (Output and)  Enable
1542         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1543         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1544         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1545         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1546
1547         //Addr of LSSI. Wirte RF register by driver
1548         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1549         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1550         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1551         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1552
1553         // RF parameter
1554         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
1555         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1556         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1557         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1558
1559         // Tx AGC Gain Stage (same for all path. Should we remove this?)
1560         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1561         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1562         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1563         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1564
1565         // Tranceiver A~D HSSI Parameter-1
1566         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
1567         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
1568         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
1569         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
1570
1571         // Tranceiver A~D HSSI Parameter-2
1572         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
1573         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
1574         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
1575         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
1576
1577         // RF switch Control
1578         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1579         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1580         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1581         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1582
1583         // AGC control 1
1584         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1585         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1586         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1587         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1588
1589         // AGC control 2
1590         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1591         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1592         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1593         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1594
1595         // RX AFE control 1
1596         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1597         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1598         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1599         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1600
1601         // RX AFE control 1
1602         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1603         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1604         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1605         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1606
1607         // Tx AFE control 1
1608         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1609         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1610         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1611         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1612
1613         // Tx AFE control 2
1614         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1615         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1616         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1617         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1618
1619         // Tranceiver LSSI Readback  SI mode
1620         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1621         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1622         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1623         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1624
1625         // Tranceiver LSSI Readback PI mode
1626         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1627         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1628         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
1629         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
1630
1631 }
1632
1633
1634 //
1635 //      Description:  Change RF power state.
1636 //
1637 //      Assumption: This function must be executed in re-schdulable context,
1638 //              ie. PASSIVE_LEVEL.
1639 //
1640 //      050823, by rcnjko.
1641 //not understand it seem's use in init
1642 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
1643 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1644 {
1645         struct r8192_priv *priv = ieee80211_priv(dev);
1646         bool                    bResult = FALSE;
1647
1648         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1649
1650         if(eRFPowerState == priv->ieee80211->eRFPowerState)
1651         {
1652                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1653                 return bResult;
1654         }
1655
1656         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
1657
1658         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1659
1660         return bResult;
1661 }
1662
1663 //use in phy only
1664 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1665 {
1666         struct r8192_priv *priv = ieee80211_priv(dev);
1667         bool                    bResult = TRUE;
1668         //u8            eRFPath;
1669         //u8            i, QueueID;
1670         u8              u1bTmp;
1671
1672         if(priv->SetRFPowerStateInProgress == TRUE)
1673                 return FALSE;
1674
1675         priv->SetRFPowerStateInProgress = TRUE;
1676
1677         switch(priv->rf_chip )
1678         {
1679                 default:
1680                 switch( eRFPowerState )
1681                 {
1682                         case eRfOn:
1683                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
1684                                 write_nic_word(dev, CMDR, 0x37FC);
1685                                 write_nic_byte(dev, PHY_CCA, 0x3);
1686                                 write_nic_byte(dev, TXPAUSE, 0x00);
1687                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
1688                                 break;
1689
1690                         //
1691                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
1692                         // By Bruce, 2008-01-16.
1693                         //
1694                         case eRfSleep:
1695                         case eRfOff:
1696                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
1697                                                 break;
1698 #ifdef NOT_YET
1699                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
1700                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1701                                 {
1702                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
1703                                         {
1704                                                 QueueID++;
1705                                                 continue;
1706                                         }
1707                                         else
1708                                         {
1709                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1710                                                 udelay(10);
1711                                                 i++;
1712                                         }
1713
1714                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
1715                                         {
1716                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1717                                                 break;
1718                                         }
1719                                 }
1720 #endif
1721                                 //
1722                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
1723                                 // Added by Bruce, 2008-11-22.
1724                                 //
1725                                 //==================================================================
1726                                 // (0) Disable FW BB reset checking
1727                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
1728
1729                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
1730                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
1731                                 u1bTmp |= BIT0;
1732                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
1733
1734                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
1735                                 write_nic_byte(dev, TXPAUSE, 0xFF);
1736
1737                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
1738                                 write_nic_word(dev, CMDR, 0x77FC);
1739                                 write_nic_byte(dev, PHY_CCA, 0x0);
1740                                 udelay(100);
1741
1742                                 write_nic_word(dev, CMDR, 0x37FC);
1743                                 udelay(10);
1744
1745                                 write_nic_word(dev, CMDR, 0x77FC);
1746                                 udelay(10);
1747
1748                                 // (3) Reset BB TRX blocks
1749                                 write_nic_word(dev, CMDR, 0x57FC);
1750                                 break;
1751
1752                         default:
1753                                 bResult = FALSE;
1754                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
1755                                 break;
1756                 }
1757                 break;
1758
1759         }
1760         priv->ieee80211->eRFPowerState = eRFPowerState;
1761 #ifdef TO_DO_LIST
1762         if(bResult)
1763         {
1764                 // Update current RF state variable.
1765                 priv->ieee80211->eRFPowerState = eRFPowerState;
1766
1767                 switch(priv->rf_chip )
1768                 {
1769                         case RF_8256:
1770                         switch(priv->ieee80211->eRFPowerState)
1771                         {
1772                                 case eRfOff:
1773                                         //
1774                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1775                                         //
1776                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1777                                         {
1778                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1779                                         }
1780                                         else
1781                                         {
1782                                                 // Turn off LED if RF is not ON.
1783                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1784                                         }
1785                                         break;
1786
1787                                 case eRfOn:
1788                                         // Turn on RF we are still linked, which might happen when
1789                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1790                                         if( pMgntInfo->bMediaConnect == TRUE )
1791                                         {
1792                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
1793                                         }
1794                                         else
1795                                         {
1796                                                 // Turn off LED if RF is not ON.
1797                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
1798                                         }
1799                                         break;
1800
1801                                 default:
1802                                         // do nothing.
1803                                         break;
1804                         }// Switch RF state
1805
1806                                 break;
1807
1808                         default:
1809                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
1810                                 break;
1811                 }// Switch rf_chip
1812         }
1813 #endif
1814         priv->SetRFPowerStateInProgress = FALSE;
1815
1816         return bResult;
1817 }
1818
1819 /*-----------------------------------------------------------------------------
1820  * Function:    GetTxPowerLevel8190()
1821  *
1822  * Overview:    This function is export to "common" moudule
1823  *
1824  * Input:       PADAPTER                Adapter
1825  *                      psByte                  Power Level
1826  *
1827  * Output:      NONE
1828  *
1829  * Return:      NONE
1830  *
1831  *---------------------------------------------------------------------------*/
1832  // no use temp
1833  void
1834 PHY_GetTxPowerLevel8192S(
1835         struct net_device* dev,
1836          long*                  powerlevel
1837         )
1838 {
1839         struct r8192_priv *priv = ieee80211_priv(dev);
1840         u8                      TxPwrLevel = 0;
1841         long                    TxPwrDbm;
1842         //
1843         // Because the Tx power indexes are different, we report the maximum of them to
1844         // meet the CCX TPC request. By Bruce, 2008-01-31.
1845         //
1846
1847         // CCK
1848         TxPwrLevel = priv->CurrentCckTxPwrIdx;
1849         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
1850
1851         // Legacy OFDM
1852         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
1853
1854         // Compare with Legacy OFDM Tx power.
1855         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
1856                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
1857
1858         // HT OFDM
1859         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
1860
1861         // Compare with HT OFDM Tx power.
1862         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
1863                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
1864
1865         *powerlevel = TxPwrDbm;
1866 }
1867
1868 /*-----------------------------------------------------------------------------
1869  * Function:    SetTxPowerLevel8190()
1870  *
1871  * Overview:    This function is export to "HalCommon" moudule
1872  *
1873  * Input:       PADAPTER                Adapter
1874  *                      u1Byte          channel
1875  *
1876  * Output:      NONE
1877  *
1878  * Return:      NONE
1879  *      2008/11/04      MHC             We remove EEPROM_93C56.
1880  *                                              We need to move CCX relative code to independet file.
1881 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
1882   *---------------------------------------------------------------------------*/
1883  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
1884 {
1885         struct r8192_priv *priv = ieee80211_priv(dev);
1886         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
1887         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
1888         s8      ant_pwr_diff = 0;
1889         u32     u4RegValue;
1890         u8      index = (channel -1);
1891         // 2009/01/22 MH Add for new EEPROM format from SD3
1892         u8      pwrdiff[2] = {0};
1893         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
1894         u8      rfpath = 0, rfpathnum = 2;
1895
1896         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
1897                 return;
1898
1899         //
1900         // Read predefined TX power index in EEPROM
1901         //
1902 //      if(priv->epromtype == EPROM_93c46)
1903         {
1904                 //
1905                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
1906                 // Power must be calculated by the antenna diff.
1907                 // So we have to rewrite Antenna gain offset register here.
1908                 // Please refer to BB register 0x80c
1909                 // 1. For CCK.
1910                 // 2. For OFDM 1T or 2T
1911                 //
1912
1913                 // 1. CCK
1914                 powerlevel = priv->RfTxPwrLevelCck[0][index];
1915
1916                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1917                 {
1918                 // Read HT 40 OFDM TX power
1919                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
1920                 // RF B HT OFDM pwr-RFA HT OFDM pwr
1921                 // Only one RF we need not to decide B <-> A pwr diff
1922
1923                 // Legacy<->HT pwr diff, we only care about path A.
1924
1925                 // We only assume 1T as RF path A
1926                 rfpathnum = 1;
1927                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1928                 }
1929                 else if (priv->rf_type == RF_2T2R)
1930                 {
1931                 // Read HT 40 OFDM TX power
1932                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
1933                         // RF B HT OFDM pwr-RFA HT OFDM pwr
1934                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
1935                                                 priv->RfTxPwrLevelOfdm2T[0][index];
1936                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
1937                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
1938
1939                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
1940                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
1941                 //priv->RfTxPwrLevelOfdm2T[1][index],
1942                 //priv->RfTxPwrLevelOfdm2T[0][index],
1943                 //priv->RfTxPwrLevelOfdm2T[1][index]));
1944
1945                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1946                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1947         }
1948
1949         //
1950         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
1951         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
1952         //
1953         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
1954         {
1955                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1956                 {
1957                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1958                         {
1959                                 // HT 20<->40 pwr diff
1960                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
1961
1962                                 // Calculate Antenna pwr diff
1963                                 if (pwrdiff[rfpath] < 8)        // 0~+7
1964                                 {
1965                                         ht20pwr[rfpath] += pwrdiff[rfpath];
1966                                 }
1967                                 else                            // index8-15=-8~-1
1968                                 {
1969                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
1970                                 }
1971                         }
1972
1973                         // RF B HT OFDM pwr-RFA HT OFDM pwr
1974                         if (priv->rf_type == RF_2T2R)
1975                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1976
1977                         //RTPRINT(FPHY, PHY_TXPWR,
1978                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
1979                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
1980                 }
1981
1982                 // Band Edge scheme is enabled for FCC mode
1983                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
1984                 {
1985                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1986                         {
1987                                 pwrdiff[rfpath] = 0;
1988                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1989                                 {
1990                                         if (channel <= 3)
1991                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
1992                                         else if (channel >= 9)
1993                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
1994                                         else
1995                                                 pwrdiff[rfpath] = 0;
1996
1997                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
1998                                 }
1999                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2000                                 {
2001                                         if (channel == 1)
2002                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2003                                         else if (channel >= 11)
2004                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2005                                         else
2006                                                 pwrdiff[rfpath] = 0;
2007
2008                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2009                                 }
2010                         }
2011
2012                         if (priv->rf_type == RF_2T2R)
2013                         {
2014                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2015                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2016                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2017                                 else
2018                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2019                         }
2020                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2021                         {
2022                                 if (channel <= 1 || channel >= 11)
2023                                 {
2024                                         //RTPRINT(FPHY, PHY_TXPWR,
2025                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2026                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2027                                 }
2028                         }
2029                         else
2030                         {
2031                                 if (channel <= 3 || channel >= 9)
2032                                 {
2033                                         //RTPRINT(FPHY, PHY_TXPWR,
2034                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2035                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2036                                 }
2037                         }
2038                 }
2039                 }
2040
2041         //Cosa added for protection, the reg rFPGA0_TxGainStage
2042         // range is from 7~-8, index = 0x0~0xf
2043         if(ant_pwr_diff > 7)
2044                 ant_pwr_diff = 7;
2045         if(ant_pwr_diff < -8)
2046                 ant_pwr_diff = -8;
2047
2048                 //RTPRINT(FPHY, PHY_TXPWR,
2049                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2050                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2051
2052                 ant_pwr_diff &= 0xf;
2053
2054                 // Antenna TX power difference
2055                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2056                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2057                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2058
2059                 // Antenna gain offset from B/C/D to A
2060                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2061                                                 priv->AntennaTxPwDiff[1]<<4 |
2062                                                 priv->AntennaTxPwDiff[0]        );
2063
2064                 // Notify Tx power difference for B/C/D to A!!!
2065                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2066         }
2067
2068         //
2069         // CCX 2 S31, AP control of client transmit power:
2070         // 1. We shall not exceed Cell Power Limit as possible as we can.
2071         // 2. Tolerance is +/- 5dB.
2072         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2073         //
2074         // TODO:
2075         // 1. 802.11h power contraint
2076         //
2077         // 071011, by rcnjko.
2078         //
2079 #ifdef TODO //WB, 11h has not implemented now.
2080         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2081                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2082         {
2083                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2084                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2085                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2086
2087                 RT_TRACE(COMP_TXAGC,
2088                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2089                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2090                 RT_TRACE(COMP_TXAGC,
2091                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2092                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2093
2094                 // CCK
2095                 if(powerlevel > CckCellPwrIdx)
2096                         powerlevel = CckCellPwrIdx;
2097                 // Legacy OFDM, HT OFDM
2098                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2099                 {
2100                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2101                         {
2102                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2103                         }
2104                         else
2105                         {
2106                                 powerlevelOFDM24G = 0;
2107                         }
2108                 }
2109
2110                 RT_TRACE(COMP_TXAGC,
2111                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2112                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2113         }
2114 #endif
2115
2116         priv->CurrentCckTxPwrIdx = powerlevel;
2117         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2118
2119         switch(priv->rf_chip)
2120         {
2121                 case RF_8225:
2122                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2123                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2124                 break;
2125
2126                 case RF_8256:
2127                         break;
2128
2129                 case RF_6052:
2130                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2131                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2132                         break;
2133
2134                 case RF_8258:
2135                         break;
2136                 default:
2137                         break;
2138         }
2139
2140 }
2141
2142 //
2143 //      Description:
2144 //              Update transmit power level of all channel supported.
2145 //
2146 //      TODO:
2147 //              A mode.
2148 //      By Bruce, 2008-02-04.
2149 //    no use temp
2150 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2151 {
2152         struct r8192_priv       *priv = ieee80211_priv(dev);
2153         u8                              idx;
2154         u8                              rf_path;
2155
2156         // TODO: A mode Tx power.
2157         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2158         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2159
2160         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2161                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2162         else
2163                 OfdmTxPwrIdx = 0;
2164
2165         for(idx = 0; idx < 14; idx++)
2166         {
2167                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2168                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2169                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2170                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2171                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2172                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2173
2174                 for (rf_path = 0; rf_path < 2; rf_path++)
2175                 {
2176                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2177                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2178                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2179                 }
2180         }
2181
2182         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2183
2184         return TRUE;
2185 }
2186
2187 /*
2188         Description:
2189                 When beacon interval is changed, the values of the
2190                 hw registers should be modified.
2191         By tynli, 2008.10.24.
2192
2193 */
2194
2195 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2196 {
2197         u32 NewBeaconNum;
2198
2199         NewBeaconNum = BeaconInterval *32 - 64;
2200         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2201         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2202         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2203         write_nic_dword(dev, WFM3, 0xB026007C);
2204 }
2205
2206 //
2207 //      Description:
2208 //              Map dBm into Tx power index according to
2209 //              current HW model, for example, RF and PA, and
2210 //              current wireless mode.
2211 //      By Bruce, 2008-01-29.
2212 //    use in phy only
2213 static u8 phy_DbmToTxPwrIdx(
2214         struct net_device* dev,
2215         WIRELESS_MODE   WirelessMode,
2216         long                    PowerInDbm
2217         )
2218 {
2219         //struct r8192_priv *priv = ieee80211_priv(dev);
2220         u8                              TxPwrIdx = 0;
2221         long                            Offset = 0;
2222
2223
2224         //
2225         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2226         // 3dbm, and OFDM HT equals to 0dbm repectively.
2227         // Note:
2228         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2229         // By Bruce, 2008-01-29.
2230         //
2231         switch(WirelessMode)
2232         {
2233         case WIRELESS_MODE_B:
2234                 Offset = -7;
2235                 break;
2236
2237         case WIRELESS_MODE_G:
2238         case WIRELESS_MODE_N_24G:
2239                 Offset = -8;
2240                 break;
2241         default:
2242                 break;
2243         }
2244
2245         if((PowerInDbm - Offset) > 0)
2246         {
2247                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2248         }
2249         else
2250         {
2251                 TxPwrIdx = 0;
2252         }
2253
2254         // Tx Power Index is too large.
2255         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2256                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2257
2258         return TxPwrIdx;
2259 }
2260 //
2261 //      Description:
2262 //              Map Tx power index into dBm according to
2263 //              current HW model, for example, RF and PA, and
2264 //              current wireless mode.
2265 //      By Bruce, 2008-01-29.
2266 //    use in phy only
2267 static long phy_TxPwrIdxToDbm(
2268         struct net_device* dev,
2269         WIRELESS_MODE   WirelessMode,
2270         u8                      TxPwrIdx
2271         )
2272 {
2273         //struct r8192_priv *priv = ieee80211_priv(dev);
2274         long                            Offset = 0;
2275         long                            PwrOutDbm = 0;
2276
2277         //
2278         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2279         // 3dbm, and OFDM HT equals to 0dbm repectively.
2280         // Note:
2281         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2282         // By Bruce, 2008-01-29.
2283         //
2284         switch(WirelessMode)
2285         {
2286         case WIRELESS_MODE_B:
2287                 Offset = -7;
2288                 break;
2289
2290         case WIRELESS_MODE_G:
2291         case WIRELESS_MODE_N_24G:
2292                 Offset = -8;
2293                 break;
2294         default:
2295                 break;
2296         }
2297
2298         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2299
2300         return PwrOutDbm;
2301 }
2302
2303 #ifdef TO_DO_LIST
2304 extern  VOID
2305 PHY_ScanOperationBackup8192S(
2306         IN      PADAPTER        Adapter,
2307         IN      u1Byte          Operation
2308         )
2309 {
2310
2311         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
2312         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
2313         u4Byte                          BitMask;
2314         u1Byte                          initial_gain;
2315
2316
2317
2318
2319
2320         if(!Adapter->bDriverStopped)
2321         {
2322                 switch(Operation)
2323                 {
2324                         case SCAN_OPT_BACKUP:
2325                                 //
2326                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
2327                                 // and resume both two DMs while scan complete.
2328                                 // 2008.11.27.
2329                                 //
2330                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2331                                 break;
2332
2333                         case SCAN_OPT_RESTORE:
2334                                 //
2335                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
2336                                 // recover earlier DIG settings.
2337                                 // 2008.11.27.
2338                                 //
2339                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2340                                 break;
2341
2342                         default:
2343                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2344                                 break;
2345                 }
2346         }
2347 }
2348 #endif
2349
2350 //nouse temp
2351 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
2352 {
2353
2354         //struct r8192_priv *priv = ieee80211_priv(dev);
2355         //u32                                   BitMask;
2356         //u8                                    initial_gain;
2357 }
2358
2359 /*-----------------------------------------------------------------------------
2360  * Function:    SetBWModeCallback8190Pci()
2361  *
2362  * Overview:    Timer callback function for SetSetBWMode
2363  *
2364  * Input:               PRT_TIMER               pTimer
2365  *
2366  * Output:      NONE
2367  *
2368  * Return:      NONE
2369  *
2370  * Note:                (1) We do not take j mode into consideration now
2371  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2372  *                           concurrently?
2373  *---------------------------------------------------------------------------*/
2374 //    use in phy only (in win it's timer)
2375 void PHY_SetBWModeCallback8192S(struct net_device *dev)
2376 {
2377         struct r8192_priv *priv = ieee80211_priv(dev);
2378         u8                              regBwOpMode;
2379
2380         //return;
2381
2382         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2383         //u32                           NowL, NowH;
2384         //u8Byte                                BeginTime, EndTime;
2385         u8                              regRRSR_RSC;
2386
2387         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
2388                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2389
2390         if(priv->rf_chip == RF_PSEUDO_11N)
2391         {
2392                 priv->SetBWModeInProgress= FALSE;
2393                 return;
2394         }
2395
2396         if(!priv->up)
2397                 return;
2398
2399         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2400         //NowL = read_nic_dword(dev, TSFR);
2401         //NowH = read_nic_dword(dev, TSFR+4);
2402         //BeginTime = ((u8Byte)NowH << 32) + NowL;
2403
2404         //3//
2405         //3//<1>Set MAC register
2406         //3//
2407         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2408         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2409
2410         switch(priv->CurrentChannelBW)
2411         {
2412                 case HT_CHANNEL_WIDTH_20:
2413                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2414                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2415
2416                         regBwOpMode |= BW_OPMODE_20MHZ;
2417                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2418                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2419                         break;
2420
2421                 case HT_CHANNEL_WIDTH_20_40:
2422                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2423                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2424
2425                         regBwOpMode &= ~BW_OPMODE_20MHZ;
2426                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2427                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2428                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
2429                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
2430                         break;
2431
2432                 default:
2433                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
2434                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2435                         break;
2436         }
2437
2438         //3//
2439         //3//<2>Set PHY related register
2440         //3//
2441         switch(priv->CurrentChannelBW)
2442         {
2443                 /* 20 MHz channel*/
2444                 case HT_CHANNEL_WIDTH_20:
2445                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2446                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2447
2448                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2449                         // It is set in Tx descriptor for 8192x series
2450                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2451                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2452                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2453
2454                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2455                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2456
2457
2458                         break;
2459
2460                 /* 40 MHz channel*/
2461                 case HT_CHANNEL_WIDTH_20_40:
2462                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2463                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2464
2465                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2466                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2467                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2468                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2469
2470                         // Set Control channel to upper or lower. These settings are required only for 40MHz
2471                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2472                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2473
2474                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
2475                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2476                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2477
2478                         break;
2479
2480                 default:
2481                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
2482                                                 ,priv->CurrentChannelBW);
2483                         break;
2484
2485         }
2486         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2487
2488         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2489         //NowL = read_nic_dword(dev, TSFR);
2490         //NowH = read_nic_dword(dev, TSFR+4);
2491         //EndTime = ((u8Byte)NowH << 32) + NowL;
2492         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
2493
2494         //3<3>Set RF related register
2495         switch( priv->rf_chip )
2496         {
2497                 case RF_8225:
2498                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
2499                         break;
2500
2501                 case RF_8256:
2502                         // Please implement this function in Hal8190PciPhy8256.c
2503                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2504                         break;
2505
2506                 case RF_8258:
2507                         // Please implement this function in Hal8190PciPhy8258.c
2508                         // PHY_SetRF8258Bandwidth();
2509                         break;
2510
2511                 case RF_PSEUDO_11N:
2512                         // Do Nothing
2513                         break;
2514
2515                 case RF_6052:
2516                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2517                         break;
2518                 default:
2519                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
2520                         break;
2521         }
2522
2523         priv->SetBWModeInProgress= FALSE;
2524
2525         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
2526 }
2527
2528
2529  /*-----------------------------------------------------------------------------
2530  * Function:   SetBWMode8190Pci()
2531  *
2532  * Overview:  This function is export to "HalCommon" moudule
2533  *
2534  * Input:               PADAPTER                        Adapter
2535  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
2536  *
2537  * Output:      NONE
2538  *
2539  * Return:      NONE
2540  *
2541  * Note:                We do not take j mode into consideration now
2542  *---------------------------------------------------------------------------*/
2543 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
2544 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
2545 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
2546 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2547 {
2548         struct r8192_priv *priv = ieee80211_priv(dev);
2549         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
2550
2551
2552         // Modified it for 20/40 mhz switch by guangan 070531
2553
2554         //return;
2555
2556         //if(priv->SwChnlInProgress)
2557 //      if(pMgntInfo->bScanInProgress)
2558 //      {
2559 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
2560 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2561 //              return;
2562 //      }
2563
2564 //      if(priv->SetBWModeInProgress)
2565 //      {
2566 //              // Modified it for 20/40 mhz switch by guangan 070531
2567 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
2568 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2569 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
2570 //              //return;
2571 //      }
2572
2573         if(priv->SetBWModeInProgress)
2574                 return;
2575
2576         priv->SetBWModeInProgress= TRUE;
2577
2578         priv->CurrentChannelBW = Bandwidth;
2579
2580         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2581                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2582         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2583                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2584         else
2585                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2586
2587         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
2588         {
2589         SetBWModeCallback8192SUsbWorkItem(dev);
2590         }
2591         else
2592         {
2593                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
2594                 priv->SetBWModeInProgress= FALSE;
2595                 priv->CurrentChannelBW = tmpBW;
2596         }
2597 }
2598
2599 //    use in phy only (in win it's timer)
2600 void PHY_SwChnlCallback8192S(struct net_device *dev)
2601 {
2602
2603         struct r8192_priv *priv = ieee80211_priv(dev);
2604         u32             delay;
2605         //bool                  ret;
2606
2607         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2608
2609         if(!priv->up)
2610                 return;
2611
2612         if(priv->rf_chip == RF_PSEUDO_11N)
2613         {
2614                 priv->SwChnlInProgress=FALSE;
2615                 return;                                                                 //return immediately if it is peudo-phy
2616         }
2617
2618         do{
2619                 if(!priv->SwChnlInProgress)
2620                         break;
2621
2622                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2623                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2624                 {
2625                         if(delay>0)
2626                         {
2627                                 mdelay(delay);
2628                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
2629                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
2630                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
2631                                 //==>SwChnlCallback8192SUsb(dev) for 92su
2632                         }
2633                         else
2634                         continue;
2635                 }
2636                 else
2637                 {
2638                         priv->SwChnlInProgress=FALSE;
2639                         break;
2640                 }
2641         }while(true);
2642 }
2643
2644 // Call after initialization
2645 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
2646 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2647 {
2648         struct r8192_priv *priv = ieee80211_priv(dev);
2649         //u8                    tmpchannel =channel;
2650         //bool                  bResult = false;
2651
2652         if(!priv->up)
2653                 return false;
2654
2655         if(priv->SwChnlInProgress)
2656                 return false;
2657
2658         if(priv->SetBWModeInProgress)
2659                 return false;
2660
2661         //--------------------------------------------
2662         switch(priv->ieee80211->mode)
2663         {
2664         case WIRELESS_MODE_A:
2665         case WIRELESS_MODE_N_5G:
2666                 if (channel<=14){
2667                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2668                         return false;
2669                 }
2670                 break;
2671
2672         case WIRELESS_MODE_B:
2673                 if (channel>14){
2674                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2675                         return false;
2676                 }
2677                 break;
2678
2679         case WIRELESS_MODE_G:
2680         case WIRELESS_MODE_N_24G:
2681                 if (channel>14){
2682                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2683                         return false;
2684                 }
2685                 break;
2686
2687         default:
2688                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
2689                 break;
2690         }
2691         //--------------------------------------------
2692
2693         priv->SwChnlInProgress = TRUE;
2694         if( channel == 0)
2695                 channel = 1;
2696
2697         priv->chan=channel;
2698
2699         priv->SwChnlStage=0;
2700         priv->SwChnlStep=0;
2701
2702         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
2703         {
2704         SwChnlCallback8192SUsbWorkItem(dev);
2705 #ifdef TO_DO_LIST
2706         if(bResult)
2707                 {
2708                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
2709                 }
2710                 else
2711                 {
2712                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
2713                         priv->SwChnlInProgress = false;
2714                         priv->CurrentChannel = tmpchannel;
2715                 }
2716 #endif
2717         }
2718         else
2719         {
2720                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
2721                 priv->SwChnlInProgress = false;
2722                 //priv->CurrentChannel = tmpchannel;
2723         }
2724         return true;
2725 }
2726
2727
2728 //
2729 // Description:
2730 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
2731 //
2732 // Implemented by Bruce, 2008-02-14.
2733 // The following procedure is operted according to SwChanlCallback8190Pci().
2734 // However, this procedure is performed synchronously  which should be running under
2735 // passive level.
2736 //
2737 //not understant it
2738 void PHY_SwChnlPhy8192S(        // Only called during initialize
2739         struct net_device* dev,
2740         u8              channel
2741         )
2742 {
2743         struct r8192_priv *priv = ieee80211_priv(dev);
2744
2745         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
2746
2747 #ifdef TO_DO_LIST
2748         // Cannot IO.
2749         if(RT_CANNOT_IO(dev))
2750                 return;
2751 #endif
2752
2753         // Channel Switching is in progress.
2754         if(priv->SwChnlInProgress)
2755                 return;
2756
2757         //return immediately if it is peudo-phy
2758         if(priv->rf_chip == RF_PSEUDO_11N)
2759         {
2760                 priv->SwChnlInProgress=FALSE;
2761                 return;
2762         }
2763
2764         priv->SwChnlInProgress = TRUE;
2765         if( channel == 0)
2766                 channel = 1;
2767
2768         priv->chan=channel;
2769
2770         priv->SwChnlStage = 0;
2771         priv->SwChnlStep = 0;
2772
2773         phy_FinishSwChnlNow(dev,channel);
2774
2775         priv->SwChnlInProgress = FALSE;
2776 }
2777
2778 //    use in phy only
2779 static bool
2780 phy_SetSwChnlCmdArray(
2781         SwChnlCmd*              CmdTable,
2782         u32                     CmdTableIdx,
2783         u32                     CmdTableSz,
2784         SwChnlCmdID             CmdID,
2785         u32                     Para1,
2786         u32                     Para2,
2787         u32                     msDelay
2788         )
2789 {
2790         SwChnlCmd* pCmd;
2791
2792         if(CmdTable == NULL)
2793         {
2794                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
2795                 return FALSE;
2796         }
2797         if(CmdTableIdx >= CmdTableSz)
2798         {
2799                 //RT_ASSERT(FALSE,
2800                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2801                                 //CmdTableIdx, CmdTableSz));
2802                 return FALSE;
2803         }
2804
2805         pCmd = CmdTable + CmdTableIdx;
2806         pCmd->CmdID = CmdID;
2807         pCmd->Para1 = Para1;
2808         pCmd->Para2 = Para2;
2809         pCmd->msDelay = msDelay;
2810
2811         return TRUE;
2812 }
2813
2814 //    use in phy only
2815 static bool
2816 phy_SwChnlStepByStep(
2817         struct net_device* dev,
2818         u8              channel,
2819         u8              *stage,
2820         u8              *step,
2821         u32             *delay
2822         )
2823 {
2824         struct r8192_priv *priv = ieee80211_priv(dev);
2825         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
2826         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
2827         u32                                     PreCommonCmdCnt;
2828         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
2829         u32                                     PostCommonCmdCnt;
2830         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
2831         u32                                     RfDependCmdCnt;
2832         SwChnlCmd                               *CurrentCmd = NULL;
2833         u8                                      eRFPath;
2834
2835         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
2836         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
2837         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2838         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
2839         if (!IsLegalChannel(priv->ieee80211, channel))
2840         {
2841                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2842                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2843         }
2844
2845         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
2846         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
2847
2848         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
2849         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2850         //{
2851                 // <1> Fill up pre common command.
2852         PreCommonCmdCnt = 0;
2853         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2854                                 CmdID_SetTxPowerLevel, 0, 0, 0);
2855         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2856                                 CmdID_End, 0, 0, 0);
2857
2858                 // <2> Fill up post common command.
2859         PostCommonCmdCnt = 0;
2860
2861         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2862                                 CmdID_End, 0, 0, 0);
2863
2864                 // <3> Fill up RF dependent command.
2865         RfDependCmdCnt = 0;
2866         switch( priv->rf_chip )
2867         {
2868                 case RF_8225:
2869                 if (channel < 1 || channel > 14)
2870                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2871                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2872                 // 2008/09/04 MH Change channel.
2873                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2874                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
2875                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2876                 CmdID_End, 0, 0, 0);
2877                 break;
2878
2879         case RF_8256:
2880                 if (channel < 1 || channel > 14)
2881                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2882                 // TEST!! This is not the table for 8256!!
2883                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2884                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2885                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
2886                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2887                 CmdID_End, 0, 0, 0);
2888                 break;
2889
2890         case RF_6052:
2891                 if (channel < 1 || channel > 14)
2892                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2893                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2894                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
2895                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2896                         CmdID_End, 0, 0, 0);
2897                 break;
2898
2899         case RF_8258:
2900                 break;
2901
2902         default:
2903                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
2904                 return FALSE;
2905                 break;
2906         }
2907
2908
2909         do{
2910                 switch(*stage)
2911                 {
2912                 case 0:
2913                         CurrentCmd=&PreCommonCmd[*step];
2914                         break;
2915                 case 1:
2916                         CurrentCmd=&RfDependCmd[*step];
2917                         break;
2918                 case 2:
2919                         CurrentCmd=&PostCommonCmd[*step];
2920                         break;
2921                 }
2922
2923                 if(CurrentCmd->CmdID==CmdID_End)
2924                 {
2925                         if((*stage)==2)
2926                         {
2927                                 return TRUE;
2928                         }
2929                         else
2930                         {
2931                                 (*stage)++;
2932                                 (*step)=0;
2933                                 continue;
2934                         }
2935                 }
2936
2937                 switch(CurrentCmd->CmdID)
2938                 {
2939                 case CmdID_SetTxPowerLevel:
2940                         //if(priv->card_8192_version > VERSION_8190_BD)
2941                                 PHY_SetTxPowerLevel8192S(dev,channel);
2942                         break;
2943                 case CmdID_WritePortUlong:
2944                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2945                         break;
2946                 case CmdID_WritePortUshort:
2947                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2948                         break;
2949                 case CmdID_WritePortUchar:
2950                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2951                         break;
2952                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
2953                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2954                         {
2955                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
2956                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
2957                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
2958                         }
2959                         break;
2960                 default:
2961                         break;
2962                 }
2963
2964                 break;
2965         }while(TRUE);
2966         //cosa }/*for(Number of RF paths)*/
2967
2968         (*delay)=CurrentCmd->msDelay;
2969         (*step)++;
2970         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2971         return FALSE;
2972 }
2973
2974 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
2975 //    use in phy only
2976 static void
2977 phy_FinishSwChnlNow(    // We should not call this function directly
2978         struct net_device* dev,
2979         u8              channel
2980                 )
2981 {
2982         struct r8192_priv       *priv = ieee80211_priv(dev);
2983         u32                     delay;
2984
2985         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2986         {
2987                 if(delay>0)
2988                         mdelay(delay);
2989                 if(!priv->up)
2990                         break;
2991         }
2992 }
2993
2994
2995 /*-----------------------------------------------------------------------------
2996  * Function:    PHYCheckIsLegalRfPath8190Pci()
2997  *
2998  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
2999  *                      We will return false.
3000  *
3001  * Input:               NONE
3002  *
3003  * Output:              NONE
3004  *
3005  * Return:              NONE
3006  *
3007  * Revised History:
3008  *      When            Who             Remark
3009  *      11/15/2007      MHC             Create Version 0.
3010  *
3011  *---------------------------------------------------------------------------*/
3012  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3013 //extern        bool
3014 //PHY_CheckIsLegalRfPath8192S(
3015 //      struct net_device* dev,
3016 //      u32     eRFPath)
3017 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3018 {
3019 //      struct r8192_priv *priv = ieee80211_priv(dev);
3020         bool                            rtValue = TRUE;
3021
3022         // NOt check RF Path now.!
3023         return  rtValue;
3024
3025 }       /* PHY_CheckIsLegalRfPath8192S */
3026
3027
3028
3029 /*-----------------------------------------------------------------------------
3030  * Function:    PHY_IQCalibrate8192S()
3031  *
3032  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3033  *                      to improve RF EVM!!?
3034  *
3035  * Input:               IN      PADAPTER        pAdapter
3036  *
3037  * Output:              NONE
3038  *
3039  * Return:              NONE
3040  *
3041  * Revised History:
3042  *      When            Who             Remark
3043  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3044  *
3045  *---------------------------------------------------------------------------*/
3046  //called by InitializeAdapter8192SE
3047 void
3048 PHY_IQCalibrate(        struct net_device* dev)
3049 {
3050         //struct r8192_priv     *priv = ieee80211_priv(dev);
3051         u32                             i, reg;
3052         u32                             old_value;
3053         long                            X, Y, TX0[4];
3054         u32                             TXA[4];
3055
3056         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3057
3058         //
3059         // 2. QFN 68
3060         //
3061         // For 1T2R IQK only now !!!
3062         for (i = 0; i < 10; i++)
3063         {
3064                 // IQK
3065                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3066                 //PlatformStallExecution(5);
3067                 udelay(5);
3068                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3069                 udelay(5);
3070                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3071                 udelay(5);
3072                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3073                 udelay(5);
3074                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3075                 udelay(5);
3076                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3077                 udelay(5);
3078                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3079                 udelay(5);
3080                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3081                 udelay(5);
3082                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3083                 udelay(5);
3084                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3085                 udelay(5);
3086                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3087                 udelay(2000);
3088                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3089                 udelay(5);
3090                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3091                 udelay(5);
3092                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3093
3094
3095                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3096
3097                 // Readback IQK value and rewrite
3098                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3099                 {
3100                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3101
3102                         // Calibrate init gain for A path for TX0
3103                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3104                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3105                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3106                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3107                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3108                         udelay(5);
3109
3110                         // Calibrate init gain for C path for TX0
3111                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3112                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3113                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3114                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3115                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3116                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3117                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3118                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3119                         udelay(5);
3120
3121                         // Calibrate RX A and B for RX0
3122                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3123                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3124                         reg = (reg & 0xFFFFFC00) |X;
3125                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3126                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3127                         reg = (reg & 0xFFFF03FF) |Y<<10;
3128                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3129                         udelay(5);
3130                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3131
3132                         // Calibrate init gain for A path for TX1 !!!!!!
3133                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3134                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3135                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3136                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3137                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3138                         udelay(5);
3139
3140                         // Calibrate init gain for C path for TX1
3141                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3142                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3143                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3144                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3145                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3146                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3147                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3148                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3149                         udelay(5);
3150
3151                         // Calibrate RX A and B for RX1
3152                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3153                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3154                         reg = (reg & 0xFFFFFC00) |X;
3155                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3156
3157                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3158                         reg = (reg & 0xFFFF03FF) |Y<<10;
3159                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3160                         udelay(5);
3161
3162                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3163                         break;
3164                 }
3165
3166         }
3167
3168
3169         //
3170         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3171         //
3172
3173
3174 }
3175
3176 /*-----------------------------------------------------------------------------
3177  * Function:    PHY_IQCalibrateBcut()
3178  *
3179  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3180  *                      to improve RF EVM!!?
3181  *
3182  * Input:               IN      PADAPTER        pAdapter
3183  *
3184  * Output:              NONE
3185  *
3186  * Return:              NONE
3187  *
3188  * Revised History:
3189  *      When            Who             Remark
3190  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3191  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
3192  *
3193  *---------------------------------------------------------------------------*/
3194 extern void PHY_IQCalibrateBcut(struct net_device* dev)
3195 {
3196         //struct r8192_priv     *priv = ieee80211_priv(dev);
3197         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
3198         u32                             i, reg;
3199         u32                             old_value;
3200         long                            X, Y, TX0[4];
3201         u32                             TXA[4];
3202         u32                             calibrate_set[13] = {0};
3203         u32                             load_value[13];
3204         u8                              RfPiEnable=0;
3205
3206         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
3207
3208         //
3209         // 1. Save e70~ee0 register setting, and load calibration setting
3210         //
3211         /*
3212         0xee0[31:0]=0x3fed92fb;
3213         0xedc[31:0] =0x3fed92fb;
3214         0xe70[31:0] =0x3fed92fb;
3215         0xe74[31:0] =0x3fed92fb;
3216         0xe78[31:0] =0x3fed92fb;
3217         0xe7c[31:0]= 0x3fed92fb;
3218         0xe80[31:0]= 0x3fed92fb;
3219         0xe84[31:0]= 0x3fed92fb;
3220         0xe88[31:0]= 0x3fed92fb;
3221         0xe8c[31:0]= 0x3fed92fb;
3222         0xed0[31:0]= 0x3fed92fb;
3223         0xed4[31:0]= 0x3fed92fb;
3224         0xed8[31:0]= 0x3fed92fb;
3225         */
3226         calibrate_set [0] = 0xee0;
3227         calibrate_set [1] = 0xedc;
3228         calibrate_set [2] = 0xe70;
3229         calibrate_set [3] = 0xe74;
3230         calibrate_set [4] = 0xe78;
3231         calibrate_set [5] = 0xe7c;
3232         calibrate_set [6] = 0xe80;
3233         calibrate_set [7] = 0xe84;
3234         calibrate_set [8] = 0xe88;
3235         calibrate_set [9] = 0xe8c;
3236         calibrate_set [10] = 0xed0;
3237         calibrate_set [11] = 0xed4;
3238         calibrate_set [12] = 0xed8;
3239         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
3240         for (i = 0; i < 13; i++)
3241         {
3242                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
3243                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
3244
3245         }
3246
3247         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
3248
3249         //
3250         // 2. QFN 68
3251         //
3252         // For 1T2R IQK only now !!!
3253         for (i = 0; i < 10; i++)
3254         {
3255                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
3256                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
3257                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3258                 {
3259                         //DbgPrint("IQK Switch to PI mode\n");
3260                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
3261                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
3262                 }
3263
3264                 // IQK
3265                 // 2. IQ calibration & LO leakage calibration
3266                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3267                 udelay(5);
3268                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3269                 udelay(5);
3270                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3271                 udelay(5);
3272                 //path-A IQ K and LO K gain setting
3273                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
3274                 udelay(5);
3275                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
3276                 udelay(5);
3277                 //set LO calibration
3278                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3279                 udelay(5);
3280                 //path-B IQ K and LO K gain setting
3281                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
3282                 udelay(5);
3283                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
3284                 udelay(5);
3285                 //K idac_I & IQ
3286                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3287                 udelay(5);
3288                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3289                 udelay(5);
3290
3291                 // delay 2ms
3292                 udelay(2000);
3293
3294                 //idac_Q setting
3295                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
3296                 udelay(5);
3297                 //K idac_Q & IQ
3298                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3299                 udelay(5);
3300                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3301
3302                 // delay 2ms
3303                 udelay(2000);
3304
3305                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3306                 udelay(5);
3307                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3308                 udelay(5);
3309                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3310
3311                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3312                 {
3313                         //DbgPrint("IQK Switch back to SI mode\n");
3314                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
3315                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
3316                 }
3317
3318
3319                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3320
3321                 // 3.   check fail bit, and fill BB IQ matrix
3322                 // Readback IQK value and rewrite
3323                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3324                 {
3325                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3326
3327                         // Calibrate init gain for A path for TX0
3328                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3329                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3330                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3331                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3332                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3333                         udelay(5);
3334
3335                         // Calibrate init gain for C path for TX0
3336                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3337                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3338                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3339                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3340                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3341                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3342                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3343                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3344                         udelay(5);
3345
3346                         // Calibrate RX A and B for RX0
3347                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3348                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3349                         reg = (reg & 0xFFFFFC00) |X;
3350                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3351                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3352                         reg = (reg & 0xFFFF03FF) |Y<<10;
3353                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3354                         udelay(5);
3355                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3356
3357                         // Calibrate init gain for A path for TX1 !!!!!!
3358                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3359                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3360                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3361                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3362                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3363                         udelay(5);
3364
3365                         // Calibrate init gain for C path for TX1
3366                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3367                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3368                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3369                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3370                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3371                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3372                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3373                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3374                         udelay(5);
3375
3376                         // Calibrate RX A and B for RX1
3377                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3378                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3379                         reg = (reg & 0xFFFFFC00) |X;
3380                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3381
3382                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3383                         reg = (reg & 0xFFFF03FF) |Y<<10;
3384                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3385                         udelay(5);
3386
3387                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3388                         break;
3389                 }
3390
3391         }
3392
3393         //
3394         // 4. Reload e70~ee0 register setting.
3395         //
3396         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
3397         for (i = 0; i < 13; i++)
3398                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
3399
3400
3401         //
3402         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3403         //
3404
3405
3406
3407 }       // PHY_IQCalibrateBcut
3408
3409
3410 //
3411 // Move from phycfg.c to gen.c to be code independent later
3412 //
3413 //-------------------------Move to other DIR later----------------------------*/
3414 //#if (DEV_BUS_TYPE == USB_INTERFACE)
3415
3416 //    use in phy only (in win it's timer)
3417 void SwChnlCallback8192SUsb(struct net_device *dev)
3418 {
3419
3420         struct r8192_priv *priv = ieee80211_priv(dev);
3421         u32                     delay;
3422 //      bool                    ret;
3423
3424         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
3425                                 %d\n", priv->chan);
3426
3427
3428         if(!priv->up)
3429                 return;
3430
3431         if(priv->rf_chip == RF_PSEUDO_11N)
3432         {
3433                 priv->SwChnlInProgress=FALSE;
3434                 return;                                                                 //return immediately if it is peudo-phy
3435         }
3436
3437         do{
3438                 if(!priv->SwChnlInProgress)
3439                         break;
3440
3441                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3442                 {
3443                         if(delay>0)
3444                         {
3445                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3446
3447                         }
3448                         else
3449                         continue;
3450                 }
3451                 else
3452                 {
3453                         priv->SwChnlInProgress=FALSE;
3454                 }
3455                 break;
3456         }while(TRUE);
3457 }
3458
3459
3460 //
3461 // Callback routine of the work item for switch channel.
3462 //
3463 //    use in phy only (in win it's work)
3464 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
3465 {
3466         struct r8192_priv *priv = ieee80211_priv(dev);
3467
3468         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
3469 #ifdef TO_DO_LIST
3470         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
3471         {
3472                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
3473
3474                 pHalData->SwChnlInProgress = FALSE;
3475                 return;
3476         }
3477 #endif
3478         phy_FinishSwChnlNow(dev, priv->chan);
3479         priv->SwChnlInProgress = FALSE;
3480
3481         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
3482 }
3483
3484
3485 /*-----------------------------------------------------------------------------
3486  * Function:    SetBWModeCallback8192SUsb()
3487  *
3488  * Overview:    Timer callback function for SetSetBWMode
3489  *
3490  * Input:               PRT_TIMER               pTimer
3491  *
3492  * Output:      NONE
3493  *
3494  * Return:      NONE
3495  *
3496  * Note:                (1) We do not take j mode into consideration now
3497  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3498  *                           concurrently?
3499  *---------------------------------------------------------------------------*/
3500 //====>//rtl8192_SetBWMode
3501 //    use in phy only (in win it's timer)
3502 void SetBWModeCallback8192SUsb(struct net_device *dev)
3503 {
3504         struct r8192_priv *priv = ieee80211_priv(dev);
3505         u8                              regBwOpMode;
3506
3507         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3508         //u32                           NowL, NowH;
3509         //u8Byte                                BeginTime, EndTime;
3510         u8                              regRRSR_RSC;
3511
3512         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3513                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3514
3515         if(priv->rf_chip == RF_PSEUDO_11N)
3516         {
3517                 priv->SetBWModeInProgress= FALSE;
3518                 return;
3519         }
3520
3521         if(!priv->up)
3522                 return;
3523
3524         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3525         //NowL = read_nic_dword(dev, TSFR);
3526         //NowH = read_nic_dword(dev, TSFR+4);
3527         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3528
3529         //3<1>Set MAC register
3530         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3531         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3532
3533         switch(priv->CurrentChannelBW)
3534         {
3535                 case HT_CHANNEL_WIDTH_20:
3536                         regBwOpMode |= BW_OPMODE_20MHZ;
3537                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3538                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3539                         break;
3540
3541                 case HT_CHANNEL_WIDTH_20_40:
3542                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3543                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3544                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3545
3546                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3547                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3548                         break;
3549
3550                 default:
3551                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
3552                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3553                         break;
3554         }
3555
3556         //3 <2>Set PHY related register
3557         switch(priv->CurrentChannelBW)
3558         {
3559                 case HT_CHANNEL_WIDTH_20:
3560                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3561                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3562
3563                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3564                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3565
3566                         break;
3567                 case HT_CHANNEL_WIDTH_20_40:
3568                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3569                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3570                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3571                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3572
3573                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3574                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3575                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3576                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3577                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3578
3579                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3580                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3581
3582                         break;
3583                 default:
3584                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
3585                                                 ,priv->CurrentChannelBW);
3586                         break;
3587
3588         }
3589         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3590
3591         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3592         //NowL = read_nic_dword(dev, TSFR);
3593         //NowH = read_nic_dword(dev, TSFR+4);
3594         //EndTime = ((u8Byte)NowH << 32) + NowL;
3595         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3596
3597 #if 1
3598         //3<3>Set RF related register
3599         switch( priv->rf_chip )
3600         {
3601                 case RF_8225:
3602                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3603                         break;
3604
3605                 case RF_8256:
3606                         // Please implement this function in Hal8190PciPhy8256.c
3607                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3608                         break;
3609
3610                 case RF_6052:
3611                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3612                         break;
3613
3614                 case RF_8258:
3615                         // Please implement this function in Hal8190PciPhy8258.c
3616                         // PHY_SetRF8258Bandwidth();
3617                         break;
3618
3619                 case RF_PSEUDO_11N:
3620                         // Do Nothing
3621                         break;
3622
3623                 default:
3624                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3625                         break;
3626         }
3627 #endif
3628         priv->SetBWModeInProgress= FALSE;
3629
3630         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
3631 }
3632
3633 //
3634 // Callback routine of the work item for set bandwidth mode.
3635 //
3636 //    use in phy only (in win it's work)
3637 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
3638 {
3639         struct r8192_priv               *priv = ieee80211_priv(dev);
3640         u8                              regBwOpMode;
3641
3642         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3643         //u32                           NowL, NowH;
3644         //u8Byte                                BeginTime, EndTime;
3645         u8                      regRRSR_RSC;
3646
3647         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
3648                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3649
3650         if(priv->rf_chip == RF_PSEUDO_11N)
3651         {
3652                 priv->SetBWModeInProgress= FALSE;
3653                 return;
3654         }
3655
3656         if(!priv->up)
3657                 return;
3658
3659         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3660         //NowL = read_nic_dword(dev, TSFR);
3661         //NowH = read_nic_dword(dev, TSFR+4);
3662         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3663
3664         //3<1>Set MAC register
3665         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3666         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3667
3668         switch(priv->CurrentChannelBW)
3669         {
3670                 case HT_CHANNEL_WIDTH_20:
3671                         regBwOpMode |= BW_OPMODE_20MHZ;
3672                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3673                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3674                         break;
3675
3676                 case HT_CHANNEL_WIDTH_20_40:
3677                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3678                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3679                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3680                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3681                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3682
3683                         break;
3684
3685                 default:
3686                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
3687                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3688                         break;
3689         }
3690
3691         //3 <2>Set PHY related register
3692         switch(priv->CurrentChannelBW)
3693         {
3694                 case HT_CHANNEL_WIDTH_20:
3695                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3696                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3697
3698                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3699
3700                         break;
3701                 case HT_CHANNEL_WIDTH_20_40:
3702                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3703                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3704
3705                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3706                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3707                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3708
3709                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3710
3711                         break;
3712
3713
3714                 default:
3715                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
3716                                                 ,priv->CurrentChannelBW);
3717                         break;
3718
3719         }
3720         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3721
3722         //3<3>Set RF related register
3723         switch( priv->rf_chip )
3724         {
3725                 case RF_8225:
3726                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3727                         break;
3728
3729                 case RF_8256:
3730                         // Please implement this function in Hal8190PciPhy8256.c
3731                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3732                         break;
3733
3734                 case RF_6052:
3735                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3736                         break;
3737
3738                 case RF_8258:
3739                         // Please implement this function in Hal8190PciPhy8258.c
3740                         // PHY_SetRF8258Bandwidth();
3741                         break;
3742
3743                 case RF_PSEUDO_11N:
3744                         // Do Nothing
3745                         break;
3746
3747                 default:
3748                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3749                         break;
3750         }
3751
3752         priv->SetBWModeInProgress= FALSE;
3753
3754         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
3755 }
3756
3757 //--------------------------Move to oter DIR later-------------------------------*/
3758 void InitialGain8192S(struct net_device *dev,   u8 Operation)
3759 {
3760 #ifdef TO_DO_LIST
3761         struct r8192_priv *priv = ieee80211_priv(dev);
3762 #endif
3763
3764 }
3765
3766 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
3767 {
3768         struct r8192_priv *priv = ieee80211_priv(dev);
3769
3770         priv->InitialGainOperateType = Operation;
3771
3772         if(priv->up)
3773         {
3774                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
3775         }
3776 }
3777
3778 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
3779 {
3780         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3781        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
3782        struct net_device *dev = priv->ieee80211->dev;
3783 #define SCAN_RX_INITIAL_GAIN    0x17
3784 #define POWER_DETECTION_TH      0x08
3785         u32     BitMask;
3786         u8      initial_gain;
3787         u8      Operation;
3788
3789         Operation = priv->InitialGainOperateType;
3790
3791         switch(Operation)
3792         {
3793                 case IG_Backup:
3794                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3795                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
3796                         BitMask = bMaskByte0;
3797                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3798                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3799                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3800                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3801                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3802                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3803                         BitMask  = bMaskByte2;
3804                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3805
3806                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3807                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3808                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3809                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3810                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3811
3812                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3813                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3814                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3815                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3816                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3817                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3818                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3819                         break;
3820                 case IG_Restore:
3821                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3822                         BitMask = 0x7f; //Bit0~ Bit6
3823                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3824                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3825
3826                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3827                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3828                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3829                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3830                         BitMask  = bMaskByte2;
3831                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3832
3833                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3834                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3835                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3836                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3837                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3838
3839                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
3840
3841                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3842                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
3843                         break;
3844                 default:
3845                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3846                         break;
3847         }
3848 }
3849
3850
3851 //-----------------------------------------------------------------------------
3852 //      Description:
3853 //              Schedule workitem to send specific CMD IO to FW.
3854 //      Added by Roger, 2008.12.03.
3855 //
3856 //-----------------------------------------------------------------------------
3857 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
3858 {
3859         struct r8192_priv *priv = ieee80211_priv(dev);
3860         u16     FwCmdWaitCounter = 0;
3861
3862         u16     FwCmdWaitLimit = 1000;
3863
3864         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
3865         if(priv->bInHctTest)
3866                 return true;
3867
3868         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
3869
3870         // Will be done by high power respectively.
3871         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
3872         {
3873                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
3874                 return false;
3875         }
3876
3877 #if 1
3878         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
3879         {
3880                 //if(RT_USB_CANNOT_IO(Adapter))
3881                 //{
3882                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
3883                 //      return FALSE;
3884                 //}
3885
3886                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
3887                 return false;
3888                 FwCmdWaitCounter ++;
3889                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
3890                 udelay(100);
3891         }
3892
3893         if(FwCmdWaitCounter == FwCmdWaitLimit)
3894         {
3895                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
3896                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
3897                 //return false;
3898         }
3899 #endif
3900         if (priv->SetFwCmdInProgress)
3901         {
3902                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
3903                 return false;
3904         }
3905         priv->SetFwCmdInProgress = TRUE;
3906         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
3907
3908         phy_SetFwCmdIOCallback(dev);
3909         return true;
3910 }
3911 void ChkFwCmdIoDone(struct net_device* dev)
3912 {
3913         u16 PollingCnt = 1000;
3914         u32 tmpValue;
3915
3916         do
3917         {// Make sure that CMD IO has be accepted by FW.
3918 #ifdef TO_DO_LIST
3919                 if(RT_USB_CANNOT_IO(Adapter))
3920                 {
3921                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
3922                         return;
3923                 }
3924 #endif
3925                 udelay(10); // sleep 20us
3926                 tmpValue = read_nic_dword(dev, WFM5);
3927                 if(tmpValue == 0)
3928                 {
3929                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
3930                         break;
3931                 }
3932                 else
3933                 {
3934                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
3935                 }
3936         }while( --PollingCnt );
3937
3938         if(PollingCnt == 0)
3939         {
3940                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
3941         }
3942 }
3943 //      Callback routine of the timer callback for FW Cmd IO.
3944 //
3945 //      Description:
3946 //              This routine will send specific CMD IO to FW and check whether it is done.
3947 //
3948 void phy_SetFwCmdIOCallback(struct net_device* dev)
3949 {
3950         //struct net_device* dev = (struct net_device*) data;
3951         u32             input;
3952         static u32 ScanRegister;
3953         struct r8192_priv *priv = ieee80211_priv(dev);
3954         if(!priv->up)
3955         {
3956                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
3957                 return;
3958         }
3959
3960         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
3961
3962         switch(priv->CurrentFwCmdIO)
3963         {
3964                 case FW_CMD_HIGH_PWR_ENABLE:
3965                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3966                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
3967                         break;
3968
3969                 case FW_CMD_HIGH_PWR_DISABLE:
3970                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
3971                         break;
3972
3973                 case FW_CMD_DIG_RESUME:
3974                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3975                         break;
3976
3977                 case FW_CMD_DIG_HALT:
3978                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
3979                         break;
3980
3981                 //
3982                 // <Roger_Notes> The following FW CMD IO was combined into single operation
3983                 // (i.e., to prevent number of system workitem out of resource!!).
3984                 // 2008.12.04.
3985                 //
3986                 case FW_CMD_RESUME_DM_BY_SCAN:
3987                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
3988                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3989                         {
3990                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
3991                                 ChkFwCmdIoDone(dev);
3992                         }
3993                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3994                         break;
3995
3996                 case FW_CMD_PAUSE_DM_BY_SCAN:
3997                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
3998                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
3999                         ChkFwCmdIoDone(dev);
4000                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4001                         break;
4002
4003                 //
4004                 // <Roger_Notes> The following FW CMD IO should be checked
4005                 // (i.e., workitem schedule timing issue!!).
4006                 // 2008.12.04.
4007                 //
4008                 case FW_CMD_DIG_DISABLE:
4009                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4010                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4011                         break;
4012
4013                 case FW_CMD_DIG_ENABLE:
4014                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4015                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4016                         break;
4017
4018                 case FW_CMD_RA_RESET:
4019                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4020                         break;
4021
4022                 case FW_CMD_RA_ACTIVE:
4023                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4024                         break;
4025
4026                 case FW_CMD_RA_REFRESH_N:
4027                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4028                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4029                                 input = FW_RA_REFRESH;
4030                         else
4031                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4032                         write_nic_dword(dev, WFM5, input);
4033                         break;
4034                 case FW_CMD_RA_REFRESH_BG:
4035                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4036                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4037                         ChkFwCmdIoDone(dev);
4038                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4039                         break;
4040
4041                 case FW_CMD_IQK_ENABLE:
4042                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4043                         break;
4044
4045                 case FW_CMD_TXPWR_TRACK_ENABLE:
4046                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4047                         break;
4048
4049                 case FW_CMD_TXPWR_TRACK_DISABLE:
4050                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4051                         break;
4052
4053                 default:
4054                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4055                         break;
4056         }
4057
4058         ChkFwCmdIoDone(dev);
4059
4060         switch(priv->CurrentFwCmdIO)
4061         {
4062                 case FW_CMD_HIGH_PWR_DISABLE:
4063                         //if(pMgntInfo->bTurboScan)
4064                         {
4065                                 //Lower initial gain
4066                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4067                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4068                                 // CCA threshold
4069                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4070                                 // Disable OFDM Part
4071                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4072                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4073                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4074                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4075                         }
4076                         break;
4077
4078                 case FW_CMD_HIGH_PWR_ENABLE:
4079                         //if(pMgntInfo->bTurboScan)
4080                         {
4081                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4082                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4083
4084                                 // CCA threshold
4085                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4086                                 // Enable OFDM Part
4087                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4088
4089                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4090                                 if(ScanRegister != 0){
4091                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4092                                 }
4093
4094                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4095                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4096                                 else
4097                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4098                         }
4099                         break;
4100         }
4101
4102         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
4103         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
4104
4105 }
4106