SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_phy.c

   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #ifdef RTL8192SU
  39 #include "r8192S_hw.h"
  40 #include "r8192S_phy.h"
  41 #include "r8192S_phyreg.h"
  42 #include "r8192SU_HWImg.h"
  43 //#include "r8192S_FwImgDTM.h"
  44 #else
  45 #include "r8192U_hw.h"
  46 #include "r819xU_phy.h"
  47 #include "r819xU_phyreg.h"
  48 #endif
  49
  50 #include "ieee80211/dot11d.h"
  51
  52 /*---------------------------Define Local Constant---------------------------*/
  53 /* Channel switch:The size of command tables for switch channel*/
  54 #define MAX_PRECMD_CNT 16
  55 #define MAX_RFDEPENDCMD_CNT 16
  56 #define MAX_POSTCMD_CNT 16
  57 #define MAX_DOZE_WAITING_TIMES_9x 64
  58
  59 /*------------------------Define local variable------------------------------*/
  60 // 2004-05-11
  61 #ifndef RTL8192SU
  62 static u32      RF_CHANNEL_TABLE_ZEBRA[]={
  63                 0,
  64                 0x085c,//2412 1
  65                 0x08dc,//2417 2
  66                 0x095c,//2422 3
  67                 0x09dc,//2427 4
  68                 0x0a5c,//2432 5
  69                 0x0adc,//2437 6
  70                 0x0b5c,//2442 7
  71                 0x0bdc,//2447 8
  72                 0x0c5c,//2452 9
  73                 0x0cdc,//2457 10
  74                 0x0d5c,//2462 11
  75                 0x0ddc,//2467 12
  76                 0x0e5c,//2472 13
  77                 //0x0f5c,//2484
  78                 0x0f72,//2484  //20040810
  79 };
  80 #endif
  81
  82 static  u32
  83 phy_CalculateBitShift(u32 BitMask);
  84 static  RT_STATUS
  85 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  86 static void
  87 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  88 static  RT_STATUS
  89 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  90 static  RT_STATUS
  91 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  92 static bool
  93 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  94 void
  95 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  96 void
  97 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  98 void
  99 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
 100 static void
 101 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
 102 static bool
 103 phy_SwChnlStepByStep(
 104         struct net_device* dev,
 105         u8              channel,
 106         u8              *stage,
 107         u8              *step,
 108         u32             *delay
 109         );
 110 static RT_STATUS
 111 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
 112 #ifdef RTL8192SE
 113 static  u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
 114 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
 115 static  void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 116 static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 117 #endif
 118 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
 119 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
 120 void phy_SetFwCmdIOCallback(struct net_device* dev);
 121
 122 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 123 #ifdef RTL8192SU
 124 //
 125 // Description:
 126 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
 127 //
 128 // Assumption:
 129 //              -       Only use on RTL8192S USB interface.
 130 //              -       PASSIVE LEVEL
 131 //
 132 // Created by Roger, 2008.09.06.
 133 //
 134 //use in phy only
 135 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 136 {
 137         struct r8192_priv *priv = ieee80211_priv(dev);
 138         u32     ReturnValue = 0xffffffff;
 139         u8      PollingCnt = 50;
 140         u8      BBWaitCounter = 0;
 141
 142
 143         //
 144         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 145         // We have to make sure that previous BB I/O has been done.
 146         // 2008.08.20.
 147         //
 148         while(priv->bChangeBBInProgress)
 149         {
 150                 BBWaitCounter ++;
 151                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 152                 msleep(1); // 1 ms
 153
 154                 // Wait too long, return FALSE to avoid to be stuck here.
 155                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 156                 {
 157                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 158                         return ReturnValue;
 159                 }
 160         }
 161
 162         priv->bChangeBBInProgress = true;
 163
 164         read_nic_dword(dev, RegAddr);
 165
 166         do
 167         {// Make sure that access could be done.
 168                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 169                         break;
 170         }while( --PollingCnt );
 171
 172         if(PollingCnt == 0)
 173         {
 174                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 175         }
 176         else
 177         {
 178                 // Data FW read back.
 179                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 180                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 181         }
 182
 183         priv->bChangeBBInProgress = false;
 184
 185         return ReturnValue;
 186 }
 187
 188
 189
 190 //
 191 // Description:
 192 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 193 //
 194 // Assumption:
 195 //              -       Only use on RTL8192S USB interface.
 196 //              -       PASSIVE LEVEL
 197 //
 198 // Created by Roger, 2008.09.06.
 199 //
 200 //use in phy only
 201 void
 202 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 203 {
 204         struct r8192_priv *priv = ieee80211_priv(dev);
 205         u8      BBWaitCounter = 0;
 206
 207         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 208
 209         //
 210         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 211         // We have to make sure that previous BB I/O has been done.
 212         // 2008.08.20.
 213         //
 214         while(priv->bChangeBBInProgress)
 215         {
 216                 BBWaitCounter ++;
 217                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 218                 msleep(1); // 1 ms
 219
 220                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 221                 {
 222                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 223                         return;
 224                 }
 225         }
 226
 227         priv->bChangeBBInProgress = true;
 228         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 229         write_nic_dword(dev, RegAddr, Data);
 230
 231         priv->bChangeBBInProgress = false;
 232 }
 233
 234
 235
 236 //
 237 // Description:
 238 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 239 //
 240 // Assumption:
 241 //              -       Only use on RTL8192S USB interface.
 242 //              -       PASSIVE LEVEL
 243 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 244 //
 245 // Created by Roger, 2008.09.06.
 246 //
 247 //use in phy only
 248 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 249 {
 250
 251         struct r8192_priv *priv = ieee80211_priv(dev);
 252         //u32   value  = 0, ReturnValue = 0;
 253         u32     ReturnValue = 0;
 254         //u32   tmplong,tmplong2;
 255         u8      PollingCnt = 50;
 256         u8      RFWaitCounter = 0;
 257
 258
 259         //
 260         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 261         // We have to make sure that previous RF I/O has been done.
 262         // 2008.08.20.
 263         //
 264         while(priv->bChangeRFInProgress)
 265         {
 266                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 267                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 268                 down(&priv->rf_sem);
 269
 270                 RFWaitCounter ++;
 271                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 272                 msleep(1); // 1 ms
 273
 274                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 275                 {
 276                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 277                         return 0xffffffff;
 278                 }
 279                 else
 280                 {
 281                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 282                 }
 283         }
 284
 285         priv->bChangeRFInProgress = true;
 286         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 287
 288
 289         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 290
 291         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 292                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 293                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 294
 295         do
 296         {// Make sure that access could be done.
 297                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 298                         break;
 299         }while( --PollingCnt );
 300
 301         // Data FW read back.
 302         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 303
 304         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 305         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 306         up(&priv->rf_sem);
 307         priv->bChangeRFInProgress = false;
 308
 309         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 310
 311         return ReturnValue;
 312
 313 }
 314
 315
 316 //
 317 // Description:
 318 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 319 //
 320 // Assumption:
 321 //              -       Only use on RTL8192S USB interface.
 322 //              -       PASSIVE LEVEL
 323 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 324 //
 325 // Created by Roger, 2008.09.06.
 326 //
 327 //use in phy only
 328 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 329 {
 330
 331         struct r8192_priv *priv = ieee80211_priv(dev);
 332         u8      PollingCnt = 50;
 333         u8      RFWaitCounter = 0;
 334
 335
 336         //
 337         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 338         // We have to make sure that previous BB I/O has been done.
 339         // 2008.08.20.
 340         //
 341         while(priv->bChangeRFInProgress)
 342         {
 343                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 344                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 345                 down(&priv->rf_sem);
 346
 347                 RFWaitCounter ++;
 348                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 349                 msleep(1); // 1 ms
 350
 351                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 352                 {
 353                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 354                         return;
 355                 }
 356                 else
 357                 {
 358                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 359                 }
 360         }
 361
 362         priv->bChangeRFInProgress = true;
 363         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 364
 365
 366         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 367
 368         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 369         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 370                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 371                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 372
 373         do
 374         {// Make sure that access could be done.
 375                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 376                                 break;
 377         }while( --PollingCnt );
 378
 379         if(PollingCnt == 0)
 380         {
 381                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 382         }
 383
 384         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 385         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 386         up(&priv->rf_sem);
 387         priv->bChangeRFInProgress = false;
 388
 389 }
 390
 391 #endif
 392
 393 /*---------------------Define local function prototype-----------------------*/
 394
 395
 396 /*----------------------------Function Body----------------------------------*/
 397 //
 398 // 1. BB register R/W API
 399 //
 400 /**
 401 * Function:     PHY_QueryBBReg
 402 *
 403 * OverView:     Read "sepcific bits" from BB register
 404 *
 405 * Input:
 406 *                       PADAPTER                Adapter,
 407 *                       u32                     RegAddr,                //The target address to be readback
 408 *                       u32                     BitMask         //The target bit position in the target address
 409 *                                                                               //to be readback
 410 * Output:       None
 411 * Return:               u32                     Data                    //The readback register value
 412 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 413 */
 414 //use phy dm core 8225 8256 6052
 415 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 416 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 417 {
 418
 419         u32     ReturnValue = 0, OriginalValue, BitShift;
 420
 421 #if (DISABLE_BB_RF == 1)
 422         return 0;
 423 #endif
 424
 425         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 426
 427         //
 428         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 429         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 430         // infinite cycle.
 431         // 2008.09.06.
 432         //
 433 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 434 #ifdef RTL8192SU
 435         if(IS_BB_REG_OFFSET_92S(RegAddr))
 436         {
 437                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 438
 439                 if((RegAddr & 0x03) != 0)
 440                 {
 441                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 442                         return 0;
 443                 }
 444
 445         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 446         }
 447         else
 448 #endif
 449         {
 450         OriginalValue = read_nic_dword(dev, RegAddr);
 451         }
 452
 453         BitShift = phy_CalculateBitShift(BitMask);
 454         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 455
 456         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 457         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 458         return (ReturnValue);
 459 }
 460
 461 /**
 462 * Function:     PHY_SetBBReg
 463 *
 464 * OverView:     Write "Specific bits" to BB register (page 8~)
 465 *
 466 * Input:
 467 *                       PADAPTER                Adapter,
 468 *                       u32                     RegAddr,                //The target address to be modified
 469 *                       u32                     BitMask         //The target bit position in the target address
 470 *                                                                               //to be modified
 471 *                       u32                     Data                    //The new register value in the target bit position
 472 *                                                                               //of the target address
 473 *
 474 * Output:       None
 475 * Return:               None
 476 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 477 */
 478 //use phy dm core 8225 8256
 479 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 480 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 481 {
 482         u32     OriginalValue, BitShift, NewValue;
 483
 484 #if (DISABLE_BB_RF == 1)
 485         return;
 486 #endif
 487
 488         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 489
 490         //
 491         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 492         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 493         // infinite cycle.
 494         // 2008.09.06.
 495         //
 496 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 497 #ifdef RTL8192SU
 498         if(IS_BB_REG_OFFSET_92S(RegAddr))
 499         {
 500                 if((RegAddr & 0x03) != 0)
 501                 {
 502                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 503                         return;
 504                 }
 505
 506                 if(BitMask!= bMaskDWord)
 507                 {//if not "double word" write
 508                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 509                         BitShift = phy_CalculateBitShift(BitMask);
 510             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 511                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 512                 }else
 513                         phy_SetUsbBBReg(dev, RegAddr, Data);
 514         }
 515         else
 516 #endif
 517         {
 518                 if(BitMask!= bMaskDWord)
 519                 {//if not "double word" write
 520                         OriginalValue = read_nic_dword(dev, RegAddr);
 521                         BitShift = phy_CalculateBitShift(BitMask);
 522                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 523                         write_nic_dword(dev, RegAddr, NewValue);
 524                 }else
 525                         write_nic_dword(dev, RegAddr, Data);
 526         }
 527
 528         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 529
 530         return;
 531 }
 532
 533
 534 //
 535 // 2. RF register R/W API
 536 //
 537 /**
 538 * Function:     PHY_QueryRFReg
 539 *
 540 * OverView:     Query "Specific bits" to RF register (page 8~)
 541 *
 542 * Input:
 543 *                       PADAPTER                Adapter,
 544 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 545 *                       u32                     RegAddr,                //The target address to be read
 546 *                       u32                     BitMask         //The target bit position in the target address
 547 *                                                                               //to be read
 548 *
 549 * Output:       None
 550 * Return:               u32                     Readback value
 551 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 552 */
 553 //in dm 8256 and phy
 554 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 555 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 556 {
 557         u32 Original_Value, Readback_Value, BitShift;//, flags;
 558         struct r8192_priv *priv = ieee80211_priv(dev);
 559
 560 #if (DISABLE_BB_RF == 1)
 561         return 0;
 562 #endif
 563
 564         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 565
 566         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 567         {
 568                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 569                 return 0;
 570         }
 571
 572         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 573         {
 574                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 575                 return 0;
 576         }
 577
 578         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 579         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 580         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 581         down(&priv->rf_sem);
 582         //
 583         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 584         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 585         // infinite cycle.
 586         // 2008.09.06.
 587         //
 588 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 589 #ifdef RTL8192SU
 590         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 591         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 592 #else
 593         if (priv->Rf_Mode == RF_OP_By_FW)
 594         {
 595                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 596         }
 597         else
 598         {
 599                 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 600         }
 601 #endif
 602
 603         BitShift =  phy_CalculateBitShift(BitMask);
 604         Readback_Value = (Original_Value & BitMask) >> BitShift;
 605         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 606         up(&priv->rf_sem);
 607         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 608
 609         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 610
 611         return (Readback_Value);
 612 }
 613
 614 /**
 615 * Function:     PHY_SetRFReg
 616 *
 617 * OverView:     Write "Specific bits" to RF register (page 8~)
 618 *
 619 * Input:
 620 *                       PADAPTER                Adapter,
 621 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 622 *                       u32                     RegAddr,                //The target address to be modified
 623 *                       u32                     BitMask         //The target bit position in the target address
 624 *                                                                               //to be modified
 625 *                       u32                     Data                    //The new register Data in the target bit position
 626 *                                                                               //of the target address
 627 *
 628 * Output:       None
 629 * Return:               None
 630 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 631 */
 632 //use phy  8225 8256
 633 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 634 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 635 {
 636
 637         struct r8192_priv *priv = ieee80211_priv(dev);
 638         u32 Original_Value, BitShift, New_Value;//, flags;
 639 #if (DISABLE_BB_RF == 1)
 640         return;
 641 #endif
 642
 643         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 644                 RegAddr, BitMask, Data, eRFPath);
 645
 646         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 647         {
 648                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 649                 return ;
 650         }
 651         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 652         {
 653                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 654                 return;
 655         }
 656
 657         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 658         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 659         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 660         down(&priv->rf_sem);
 661         //
 662         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 663         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 664         // infinite cycle.
 665         // 2008.09.06.
 666         //
 667 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 668 #ifdef RTL8192SU
 669                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 670
 671                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 672                 {
 673                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 674                         BitShift =  phy_CalculateBitShift(BitMask);
 675                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 676                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 677                 }
 678                 else
 679                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 680 #else
 681         if (priv->Rf_Mode == RF_OP_By_FW)
 682         {
 683                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 684                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 685                 {
 686                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 687                         BitShift =  phy_CalculateBitShift(BitMask);
 688                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 689
 690                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 691                 }
 692                 else
 693                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 694         }
 695         else
 696         {
 697                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 698                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 699                 {
 700                         Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 701                         BitShift =  phy_CalculateBitShift(BitMask);
 702                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 703
 704                         phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 705                 }
 706                 else
 707                         phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 708
 709         }
 710 #endif
 711         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 712         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 713         up(&priv->rf_sem);
 714         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 715         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 716                         RegAddr, BitMask, Data, eRFPath);
 717
 718 }
 719
 720 #ifdef RTL8192SE
 721 /*-----------------------------------------------------------------------------
 722  * Function:    phy_FwRFSerialRead()
 723  *
 724  * Overview:    We support firmware to execute RF-R/W.
 725  *
 726  * Input:               NONE
 727  *
 728  * Output:              NONE
 729  *
 730  * Return:              NONE
 731  *
 732  * Revised History:
 733  *      When            Who             Remark
 734  *      01/21/2008      MHC             Create Version 0.
 735  *
 736  *---------------------------------------------------------------------------*/
 737 //use in phy only
 738 static  u32
 739 phy_FwRFSerialRead(
 740         struct net_device* dev,
 741         RF90_RADIO_PATH_E       eRFPath,
 742         u32                             Offset  )
 743 {
 744         u32             retValue = 0;
 745         //u32           Data = 0;
 746         //u8            time = 0;
 747 #if 0
 748         //DbgPrint("FW RF CTRL\n\r");
 749         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 750            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 751            much time. This is only for site survey. */
 752         // 1. Read operation need not insert data. bit 0-11
 753         //Data &= bMask12Bits;
 754         // 2. Write RF register address. Bit 12-19
 755         Data |= ((Offset&0xFF)<<12);
 756         // 3. Write RF path.  bit 20-21
 757         Data |= ((eRFPath&0x3)<<20);
 758         // 4. Set RF read indicator. bit 22=0
 759         //Data |= 0x00000;
 760         // 5. Trigger Fw to operate the command. bit 31
 761         Data |= 0x80000000;
 762         // 6. We can not execute read operation if bit 31 is 1.
 763         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 764         {
 765                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 766                 if (time++ < 100)
 767                 {
 768                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
 769                         delay_us(10);
 770                 }
 771                 else
 772                         break;
 773         }
 774         // 7. Execute read operation.
 775         PlatformIOWrite4Byte(dev, QPNR, Data);
 776         // 8. Check if firmawre send back RF content.
 777         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 778         {
 779                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 780                 if (time++ < 100)
 781                 {
 782                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 783                         delay_us(10);
 784                 }
 785                 else
 786                         return  (0);
 787         }
 788         retValue = PlatformIORead4Byte(dev, RF_DATA);
 789 #endif
 790         return  (retValue);
 791
 792 }       /* phy_FwRFSerialRead */
 793
 794 /*-----------------------------------------------------------------------------
 795  * Function:    phy_FwRFSerialWrite()
 796  *
 797  * Overview:    We support firmware to execute RF-R/W.
 798  *
 799  * Input:               NONE
 800  *
 801  * Output:              NONE
 802  *
 803  * Return:              NONE
 804  *
 805  * Revised History:
 806  *      When            Who             Remark
 807  *      01/21/2008      MHC             Create Version 0.
 808  *
 809  *---------------------------------------------------------------------------*/
 810 //use in phy only
 811 static  void
 812 phy_FwRFSerialWrite(
 813         struct net_device* dev,
 814         RF90_RADIO_PATH_E       eRFPath,
 815         u32                             Offset,
 816         u32                             Data    )
 817 {
 818 #if 0
 819         u8      time = 0;
 820         DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
 821         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 822            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 823            much time. This is only for site survey. */
 824
 825         // 1. Set driver write bit and 12 bit data. bit 0-11
 826         //Data &= bMask12Bits;  // Done by uper layer.
 827         // 2. Write RF register address. bit 12-19
 828         Data |= ((Offset&0xFF)<<12);
 829         // 3. Write RF path.  bit 20-21
 830         Data |= ((eRFPath&0x3)<<20);
 831         // 4. Set RF write indicator. bit 22=1
 832         Data |= 0x400000;
 833         // 5. Trigger Fw to operate the command. bit 31=1
 834         Data |= 0x80000000;
 835
 836         // 6. Write operation. We can not write if bit 31 is 1.
 837         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 838         {
 839                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 840                 if (time++ < 100)
 841                 {
 842                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 843                         delay_us(10);
 844                 }
 845                 else
 846                         break;
 847         }
 848         // 7. No matter check bit. We always force the write. Because FW will
 849         //    not accept the command.
 850         PlatformIOWrite4Byte(dev, QPNR, Data);
 851         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 852            to finish RF write operation. */
 853         /* 2008/01/17 MH We support delay in firmware side now. */
 854         //delay_us(20);
 855 #endif
 856 }       /* phy_FwRFSerialWrite */
 857
 858 /**
 859 * Function:     phy_RFSerialRead
 860 *
 861 * OverView:     Read regster from RF chips
 862 *
 863 * Input:
 864 *                       PADAPTER                Adapter,
 865 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 866 *                       u32                     Offset,         //The target address to be read
 867 *
 868 * Output:       None
 869 * Return:               u32                     reback value
 870 * Note:         Threre are three types of serial operations:
 871 *                       1. Software serial write
 872 *                       2. Hardware LSSI-Low Speed Serial Interface
 873 *                       3. Hardware HSSI-High speed
 874 *                       serial write. Driver need to implement (1) and (2).
 875 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 876 */
 877 //use in phy only
 878 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
 879 {
 880
 881         u32                                             retValue = 0;
 882         struct r8192_priv *priv = ieee80211_priv(dev);
 883         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 884         u32                                             NewOffset;
 885         u8                                              RfPiEnable=0;
 886
 887
 888         //
 889         // Make sure RF register offset is correct
 890         //
 891         Offset &= 0x3f;
 892
 893         //
 894         // Switch page for 8256 RF IC
 895         //
 896         if(     priv->rf_chip == RF_8256 ||
 897                 priv->rf_chip == RF_8225 ||
 898                 priv->rf_chip == RF_6052)
 899         {
 900                 //analog to digital off, for protection
 901                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
 902
 903                 if(Offset>=31)
 904                 {
 905                         priv->RFReadPageCnt[2]++;//cosa add for debug
 906                         priv->RfReg0Value[eRFPath] |= 0x140;
 907
 908                         // Switch to Reg_Mode2 for Reg31~45
 909                         rtl8192_setBBreg(dev,
 910                                 pPhyReg->rf3wireOffset,
 911                                 bMaskDWord,
 912                                 (priv->RfReg0Value[eRFPath] << 16)      );
 913
 914                         // Modified Offset
 915                         NewOffset = Offset - 30;
 916
 917                 }else if(Offset>=16)
 918                 {
 919                         priv->RFReadPageCnt[1]++;//cosa add for debug
 920                         priv->RfReg0Value[eRFPath] |= 0x100;
 921                         priv->RfReg0Value[eRFPath] &= (~0x40);
 922
 923                         // Switch to Reg_Mode1 for Reg16~30
 924                         rtl8192_setBBreg(dev,
 925                                 pPhyReg->rf3wireOffset,
 926                                 bMaskDWord,
 927                                 (priv->RfReg0Value[eRFPath] << 16)      );
 928
 929                         // Modified Offset
 930                         NewOffset = Offset - 15;
 931                 }
 932                 else
 933                 {
 934                         priv->RFReadPageCnt[0]++;//cosa add for debug
 935                         NewOffset = Offset;
 936         }
 937         }
 938         else
 939                 NewOffset = Offset;
 940
 941         //
 942         // Put desired read address to LSSI control register
 943         //
 944         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 945
 946         //
 947         // Issue a posedge trigger
 948         //
 949         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 950         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 951
 952         // TODO: we should not delay such a  long time. Ask help from SD3
 953         mdelay(1);
 954
 955         retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 956
 957         // Switch back to Reg_Mode0;
 958         if(     priv->rf_chip == RF_8256 ||
 959                 priv->rf_chip == RF_8225 ||
 960                 priv->rf_chip == RF_0222D)
 961         {
 962                 if (Offset >= 0x10)
 963                 {
 964                         priv->RfReg0Value[eRFPath] &= 0xebf;
 965
 966                         rtl8192_setBBreg(
 967                                 dev,
 968                                 pPhyReg->rf3wireOffset,
 969                                 bMaskDWord,
 970                                 (priv->RfReg0Value[eRFPath] << 16)      );
 971                 }
 972
 973                 //analog to digital on
 974                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
 975         }
 976
 977         return retValue;
 978 }
 979
 980
 981
 982 /**
 983 * Function:     phy_RFSerialWrite
 984 *
 985 * OverView:     Write data to RF register (page 8~)
 986 *
 987 * Input:
 988 *                       PADAPTER                Adapter,
 989 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 990 *                       u32                     Offset,         //The target address to be read
 991 *                       u32                     Data                    //The new register Data in the target bit position
 992 *                                                                               //of the target to be read
 993 *
 994 * Output:       None
 995 * Return:               None
 996 * Note:         Threre are three types of serial operations:
 997 *                       1. Software serial write
 998 *                       2. Hardware LSSI-Low Speed Serial Interface
 999 *                       3. Hardware HSSI-High speed
1000 *                       serial write. Driver need to implement (1) and (2).
1001 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1002  *
1003  * Note:                  For RF8256 only
1004  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1005  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1006  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1007  *                       programming guide" for more details.
1008  *                       Thus, we define a sub-finction for RTL8526 register address conversion
1009  *                     ===========================================================
1010  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
1011  *                                                              (Reg00[12])             (Reg00[10])
1012  *                     ===========================================================
1013  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1014  *                     ------------------------------------------------------------------
1015  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1016  *                     ------------------------------------------------------------------
1017  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1018  *                     ------------------------------------------------------------------
1019 */
1020 ////use in phy only
1021 static void
1022 phy_RFSerialWrite(
1023         struct net_device* dev,
1024         RF90_RADIO_PATH_E       eRFPath,
1025         u32                             Offset,
1026         u32                             Data
1027         )
1028 {
1029         u32                                     DataAndAddr = 0;
1030         struct r8192_priv                       *priv = ieee80211_priv(dev);
1031         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1032         u32                                     NewOffset;
1033
1034         Offset &= 0x3f;
1035
1036         // Shadow Update
1037         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1038
1039
1040         // Switch page for 8256 RF IC
1041         if(     priv->rf_chip == RF_8256 ||
1042                 priv->rf_chip == RF_8225 ||
1043                 priv->rf_chip == RF_0222D)
1044         {
1045                 //analog to digital off, for protection
1046                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1047
1048                 if(Offset>=31)
1049                 {
1050                         priv->RFWritePageCnt[2]++;//cosa add for debug
1051                         priv->RfReg0Value[eRFPath] |= 0x140;
1052
1053                         rtl8192_setBBreg(dev,
1054                                 pPhyReg->rf3wireOffset,
1055                                 bMaskDWord,
1056                                 (priv->RfReg0Value[eRFPath] << 16)      );
1057
1058                         NewOffset = Offset - 30;
1059
1060                 }else if(Offset>=16)
1061                 {
1062                         priv->RFWritePageCnt[1]++;//cosa add for debug
1063                         priv->RfReg0Value[eRFPath] |= 0x100;
1064                         priv->RfReg0Value[eRFPath] &= (~0x40);
1065
1066
1067                         rtl8192_setBBreg(dev,
1068                                 pPhyReg->rf3wireOffset,
1069                                 bMaskDWord,
1070                                 (priv->RfReg0Value[eRFPath] << 16)      );
1071
1072                         NewOffset = Offset - 15;
1073                 }
1074                 else
1075                 {
1076                         priv->RFWritePageCnt[0]++;//cosa add for debug
1077                         NewOffset = Offset;
1078         }
1079         }
1080         else
1081                 NewOffset = Offset;
1082
1083         //
1084         // Put write addr in [5:0]  and write data in [31:16]
1085         //
1086         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1087
1088         //
1089         // Write Operation
1090         //
1091         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1092
1093
1094         if(Offset==0x0)
1095                 priv->RfReg0Value[eRFPath] = Data;
1096
1097         // Switch back to Reg_Mode0;
1098         if(     priv->rf_chip == RF_8256 ||
1099                 priv->rf_chip == RF_8225 ||
1100                 priv->rf_chip == RF_0222D)
1101         {
1102                 if (Offset >= 0x10)
1103                 {
1104                         if(Offset != 0)
1105                         {
1106                                 priv->RfReg0Value[eRFPath] &= 0xebf;
1107                                 rtl8192_setBBreg(
1108                                 dev,
1109                                 pPhyReg->rf3wireOffset,
1110                                 bMaskDWord,
1111                                 (priv->RfReg0Value[eRFPath] << 16)      );
1112                         }
1113                 }
1114                 //analog to digital on
1115                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1116         }
1117
1118 }
1119 #else
1120 /**
1121 * Function:     phy_RFSerialRead
1122 *
1123 * OverView:     Read regster from RF chips
1124 *
1125 * Input:
1126 *                       PADAPTER                Adapter,
1127 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1128 *                       u4Byte                  Offset,         //The target address to be read
1129 *
1130 * Output:       None
1131 * Return:               u4Byte                  reback value
1132 * Note:         Threre are three types of serial operations:
1133 *                       1. Software serial write
1134 *                       2. Hardware LSSI-Low Speed Serial Interface
1135 *                       3. Hardware HSSI-High speed
1136 *                       serial write. Driver need to implement (1) and (2).
1137 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1138 */
1139 #if 0
1140 static  u32
1141 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
1142 {
1143
1144         u32                                             retValue = 0;
1145         struct r8192_priv *priv = ieee80211_priv(dev);
1146         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1147         u32                                             NewOffset;
1148         //u32                                           value  = 0;
1149         u32                                             tmplong,tmplong2;
1150         u32                                             RfPiEnable=0;
1151 #if 0
1152         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1153                 return  retValue;
1154         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1155                 return  retValue;
1156 #endif
1157         //
1158         // Make sure RF register offset is correct
1159         //
1160         Offset &= 0x3f;
1161
1162         //
1163         // Switch page for 8256 RF IC
1164         //
1165         NewOffset = Offset;
1166
1167         // For 92S LSSI Read RFLSSIRead
1168         // For RF A/B write 0x824/82c(does not work in the future)
1169         // We must use 0x824 for RF A and B to execute read trigger
1170         tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
1171         tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
1172         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF
1173
1174         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
1175         mdelay(1);
1176
1177         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
1178         mdelay(1);
1179
1180         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
1181         mdelay(1);
1182
1183         if(eRFPath == RF90_PATH_A)
1184                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
1185         else if(eRFPath == RF90_PATH_B)
1186                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
1187
1188         if(RfPiEnable)
1189         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
1190                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
1191                 //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
1192         }
1193         else
1194         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
1195                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1196                 //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
1197         }
1198         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
1199
1200         return retValue;
1201
1202 }
1203 4
1204
1205
1206 /**
1207 * Function:     phy_RFSerialWrite
1208 *
1209 * OverView:     Write data to RF register (page 8~)
1210 *
1211 * Input:
1212 *                       PADAPTER                Adapter,
1213 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1214 *                       u4Byte                  Offset,         //The target address to be read
1215 *                       u4Byte                  Data                    //The new register Data in the target bit position
1216 *                                                                               //of the target to be read
1217 *
1218 * Output:       None
1219 * Return:               None
1220 * Note:         Threre are three types of serial operations:
1221 *                       1. Software serial write
1222 *                       2. Hardware LSSI-Low Speed Serial Interface
1223 *                       3. Hardware HSSI-High speed
1224 *                       serial write. Driver need to implement (1) and (2).
1225 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1226  *
1227  * Note:                  For RF8256 only
1228  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1229  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1230  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1231  *                       programming guide" for more details.
1232  *                       Thus, we define a sub-finction for RTL8526 register address conversion
1233  *                     ===========================================================
1234  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
1235  *                                                              (Reg00[12])             (Reg00[10])
1236  *                     ===========================================================
1237  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1238  *                     ------------------------------------------------------------------
1239  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1240  *                     ------------------------------------------------------------------
1241  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1242  *                     ------------------------------------------------------------------
1243  *
1244  *      2008/09/02      MH      Add 92S RF definition
1245  *
1246  *
1247  *
1248 */
1249 static  void
1250 phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32       Data)
1251 {
1252         u32                                             DataAndAddr = 0;
1253         struct r8192_priv *priv = ieee80211_priv(dev);
1254         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1255         u32                                             NewOffset;
1256
1257 #if 0
1258         //<Roger_TODO> We should check valid regs for RF_6052 case.
1259         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1260                 return;
1261         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1262                 return;
1263 #endif
1264
1265         Offset &= 0x3f;
1266
1267         //
1268         // Shadow Update
1269         //
1270         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1271
1272         //
1273         // Switch page for 8256 RF IC
1274         //
1275                 NewOffset = Offset;
1276
1277         //
1278         // Put write addr in [5:0]  and write data in [31:16]
1279         //
1280         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1281         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF
1282
1283         //
1284         // Write Operation
1285         //
1286         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1287         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
1288
1289 }
1290 #endif
1291 #endif
1292
1293 /**
1294 * Function:     phy_CalculateBitShift
1295 *
1296 * OverView:     Get shifted position of the BitMask
1297 *
1298 * Input:
1299 *                       u32             BitMask,
1300 *
1301 * Output:       none
1302 * Return:               u32             Return the shift bit bit position of the mask
1303 */
1304 //use in phy only
1305 static u32 phy_CalculateBitShift(u32 BitMask)
1306 {
1307         u32 i;
1308
1309         for(i=0; i<=31; i++)
1310         {
1311                 if ( ((BitMask>>i) &  0x1 ) == 1)
1312                         break;
1313         }
1314
1315         return (i);
1316 }
1317
1318
1319 //
1320 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
1321 //
1322 /*-----------------------------------------------------------------------------
1323  * Function:    PHY_MACConfig8192S
1324  *
1325  * Overview:    Condig MAC by header file or parameter file.
1326  *
1327  * Input:       NONE
1328  *
1329  * Output:      NONE
1330  *
1331  * Return:      NONE
1332  *
1333  * Revised History:
1334  *  When                Who             Remark
1335  *  08/12/2008  MHC             Create Version 0.
1336  *
1337  *---------------------------------------------------------------------------*/
1338 //adapter_start
1339 extern bool PHY_MACConfig8192S(struct net_device* dev)
1340 {
1341         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1342
1343         //
1344         // Config MAC
1345         //
1346 #if RTL8190_Download_Firmware_From_Header
1347         rtStatus = phy_ConfigMACWithHeaderFile(dev);
1348 #else
1349         // Not make sure EEPROM, add later
1350         RT_TRACE(COMP_INIT, "Read MACREG.txt\n");
1351         //rtStatus = phy_ConfigMACWithParaFile(dev, RTL819X_PHY_MACREG);// lzm del it temp
1352 #endif
1353         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
1354
1355 }
1356
1357 //adapter_start
1358 extern  bool
1359 PHY_BBConfig8192S(struct net_device* dev)
1360 {
1361         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1362
1363         u8 PathMap = 0, index = 0, rf_num = 0;
1364         struct r8192_priv       *priv = ieee80211_priv(dev);
1365         phy_InitBBRFRegisterDefinition(dev);
1366
1367         //
1368         // Config BB and AGC
1369         //
1370         //switch( Adapter->MgntInfo.bRegHwParaFile )
1371         //{
1372         //      case 0:
1373         //              phy_BB8190_Config_HardCode(dev);
1374         //              break;
1375
1376         //      case 1:
1377                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
1378         //              break;
1379
1380         //      case 2:
1381                         // Partial Modify.
1382         //              phy_BB8190_Config_HardCode(dev);
1383         //              phy_BB8192S_Config_ParaFile(dev);
1384         //              break;
1385
1386         //      default:
1387         //              phy_BB8190_Config_HardCode(dev);
1388         //              break;
1389         //}
1390         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
1391                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
1392         priv->rf_pathmap = PathMap;
1393         for(index = 0; index<4; index++)
1394         {
1395                 if((PathMap>>index)&0x1)
1396                         rf_num++;
1397         }
1398
1399         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
1400                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
1401                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
1402                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
1403                 (priv->rf_type==RF_2T4R && rf_num!=4))
1404         {
1405                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
1406         }
1407         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1408 }
1409
1410 //adapter_start
1411 extern  bool
1412 PHY_RFConfig8192S(struct net_device* dev)
1413 {
1414         struct r8192_priv       *priv = ieee80211_priv(dev);
1415         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1416
1417         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
1418
1419         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
1420         priv->rf_chip = RF_6052;
1421
1422         //
1423         // RF config
1424         //
1425         switch(priv->rf_chip)
1426         {
1427         case RF_8225:
1428         case RF_6052:
1429                 rtStatus = PHY_RF6052_Config(dev);
1430                 break;
1431
1432         case RF_8256:
1433                 //rtStatus = PHY_RF8256_Config(dev);
1434                 break;
1435
1436         case RF_8258:
1437                 break;
1438
1439         case RF_PSEUDO_11N:
1440                 //rtStatus = PHY_RF8225_Config(dev);
1441                 break;
1442         default:
1443             break;
1444         }
1445
1446         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1447 }
1448
1449
1450 // Joseph test: new initialize order!!
1451 // Test only!! This part need to be re-organized.
1452 // Now it is just for 8256.
1453 //use in phy only
1454 #ifdef TO_DO_LIST
1455 static RT_STATUS
1456 phy_BB8190_Config_HardCode(struct net_device* dev)
1457 {
1458         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1459         return RT_STATUS_SUCCESS;
1460 }
1461 #endif
1462
1463 /*-----------------------------------------------------------------------------
1464  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
1465  *
1466  * Overview:    This function
1467  *
1468  *
1469  * Input:       PADAPTER                Adapter
1470  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
1471  *
1472  * Output:      NONE
1473  *
1474  * Return:      RT_STATUS_SUCCESS: configuration file exist
1475  * When                 Who             Remark
1476  * 2008/11/10   tynli
1477  * use in phy only
1478  *---------------------------------------------------------------------------*/
1479 static RT_STATUS
1480 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
1481 {
1482         int i;
1483         struct r8192_priv       *priv = ieee80211_priv(dev);
1484         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
1485         u16                             PHY_REGArraytoXTXRLen;
1486
1487 //#if (HAL_CODE_BASE != RTL8192_S)
1488
1489         if(priv->rf_type == RF_1T1R)
1490         {
1491                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
1492                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
1493         }
1494         else if(priv->rf_type == RF_1T2R)
1495         {
1496                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
1497                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
1498         }
1499         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
1500         //{
1501         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
1502         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
1503         //}
1504         else
1505         {
1506                 return RT_STATUS_FAILURE;
1507         }
1508
1509         if(ConfigType == BaseBand_Config_PHY_REG)
1510         {
1511                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
1512                 {
1513                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
1514                                 mdelay(50);
1515                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
1516                                 mdelay(5);
1517                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
1518                                 mdelay(1);
1519                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
1520                                 udelay(50);
1521                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
1522                                 udelay(5);
1523                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
1524                                 udelay(1);
1525                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1526                         //RT_TRACE(COMP_SEND,
1527                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
1528                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1529                 }
1530         }
1531         else {
1532                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1533         }
1534 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1535         return RT_STATUS_SUCCESS;
1536 }
1537
1538
1539 //use in phy only
1540 static  RT_STATUS
1541 phy_BB8192S_Config_ParaFile(struct net_device* dev)
1542 {
1543         struct r8192_priv       *priv = ieee80211_priv(dev);
1544         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1545         //u8                            u2RegValue;
1546         //u16                           u4RegValue;
1547         //char                          szBBRegFile[] = RTL819X_PHY_REG;
1548         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
1549         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1550         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
1551         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
1552         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
1553
1554         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
1555
1556         //
1557         // 1. Read PHY_REG.TXT BB INIT!!
1558         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
1559         //
1560 #if RTL8190_Download_Firmware_From_Header
1561         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1562             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1563         {
1564                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1565                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1566                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1567                   //so we should reconfig BB reg with the right PHY parameters.
1568                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1569                 }
1570         }else
1571                 rtStatus = RT_STATUS_FAILURE;
1572 #else
1573         RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type);
1574         // No matter what kind of RF we always read PHY_REG.txt. We must copy different
1575         // type of parameter files to phy_reg.txt at first.
1576         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1577             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1578         {
1579                 rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile);
1580                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1581                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1582                   //so we should reconfig BB reg with the right PHY parameters.
1583                         if(priv->rf_type == RF_1T1R)
1584                                 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile);
1585                         else if(priv->rf_type == RF_1T2R)
1586                                 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile);
1587                 }
1588
1589         }else
1590                 rtStatus = RT_STATUS_FAILURE;
1591 #endif
1592
1593         if(rtStatus != RT_STATUS_SUCCESS){
1594                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
1595                 goto phy_BB8190_Config_ParaFile_Fail;
1596         }
1597
1598         //
1599         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1600         //
1601         if (priv->AutoloadFailFlag == false)
1602         {
1603 #if     RTL8190_Download_Firmware_From_Header
1604                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
1605 #else
1606                 rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile);
1607 #endif
1608         }
1609         if(rtStatus != RT_STATUS_SUCCESS){
1610                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
1611                 goto phy_BB8190_Config_ParaFile_Fail;
1612         }
1613
1614         //
1615         // 3. BB AGC table Initialization
1616         //
1617 #if RTL8190_Download_Firmware_From_Header
1618         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
1619 #else
1620         RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n");
1621         rtStatus = phy_ConfigBBWithParaFile(Adapter, (char* )&szAGCTableFile);
1622 #endif
1623
1624         if(rtStatus != RT_STATUS_SUCCESS){
1625                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
1626                 goto phy_BB8190_Config_ParaFile_Fail;
1627         }
1628
1629
1630 #if 0   // 2008/08/18 MH Disable for 92SE
1631         if(pHalData->VersionID > VERSION_8190_BD)
1632         {
1633                 //if(pHalData->RF_Type == RF_2T4R)
1634                 //{
1635                 // Antenna gain offset from B/C/D to A
1636                 u4RegValue = (  pHalData->AntennaTxPwDiff[2]<<8 |
1637                                                 pHalData->AntennaTxPwDiff[1]<<4 |
1638                                                 pHalData->AntennaTxPwDiff[0]);
1639                 //}
1640                 //else
1641                 //u4RegValue = 0;
1642
1643                 PHY_SetBBReg(dev, rFPGA0_TxGainStage,
1644                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1645
1646                 // CrystalCap
1647                 // Simulate 8192???
1648                 u4RegValue = pHalData->CrystalCap;
1649                 PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
1650                 // Simulate 8190??
1651                 //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2);       // bit2~3 of crystal cap
1652                 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
1653
1654         }
1655 #endif
1656
1657         // Check if the CCK HighPower is turned ON.
1658         // This is used to calculate PWDB.
1659         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1660
1661
1662 phy_BB8190_Config_ParaFile_Fail:
1663         return rtStatus;
1664 }
1665
1666 /*-----------------------------------------------------------------------------
1667  * Function:    phy_ConfigMACWithHeaderFile()
1668  *
1669  * Overview:    This function read BB parameters from Header file we gen, and do register
1670  *                        Read/Write
1671  *
1672  * Input:       PADAPTER                Adapter
1673  *                      char*                   pFileName
1674  *
1675  * Output:      NONE
1676  *
1677  * Return:      RT_STATUS_SUCCESS: configuration file exist
1678  *
1679  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
1680  *                      [Register][Mask][Value]
1681  *---------------------------------------------------------------------------*/
1682 //use in phy only
1683 static  RT_STATUS
1684 phy_ConfigMACWithHeaderFile(struct net_device* dev)
1685 {
1686         u32                                     i = 0;
1687         u32                                     ArrayLength = 0;
1688         u32*                                    ptrArray;
1689         //struct r8192_priv     *priv = ieee80211_priv(dev);
1690
1691 //#if (HAL_CODE_BASE != RTL8192_S)
1692         /*if(Adapter->bInHctTest)
1693         {
1694                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
1695                 ArrayLength = MACPHY_ArrayLengthDTM;
1696                 ptrArray = Rtl819XMACPHY_ArrayDTM;
1697         }
1698         else if(pHalData->bTXPowerDataReadFromEEPORM)
1699         {
1700 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
1701 //              ArrayLength = MACPHY_Array_PGLength;
1702 //              ptrArray = Rtl819XMACPHY_Array_PG;
1703
1704         }else*/
1705         { //2008.11.06 Modified by tynli.
1706                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
1707                 ArrayLength = MAC_2T_ArrayLength;
1708                 ptrArray = Rtl819XMAC_Array;
1709         }
1710
1711         /*for(i = 0 ;i < ArrayLength;i=i+3){
1712                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
1713                 if(ptrArray[i] == 0x318)
1714                 {
1715                         ptrArray[i+2] = 0x00000800;
1716                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1717                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1718                 }
1719                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1720         }*/
1721         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
1722                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
1723         }
1724 //#endif
1725         return RT_STATUS_SUCCESS;
1726 }
1727
1728 /*-----------------------------------------------------------------------------
1729  * Function:    phy_ConfigBBWithHeaderFile()
1730  *
1731  * Overview:    This function read BB parameters from general file format, and do register
1732  *                        Read/Write
1733  *
1734  * Input:       PADAPTER                Adapter
1735  *                      u8                      ConfigType     0 => PHY_CONFIG
1736  *                                                                               1 =>AGC_TAB
1737  *
1738  * Output:      NONE
1739  *
1740  * Return:      RT_STATUS_SUCCESS: configuration file exist
1741  *
1742  *---------------------------------------------------------------------------*/
1743 //use in phy only
1744 static  RT_STATUS
1745 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1746 {
1747         int             i;
1748         //u8            ArrayLength;
1749         u32*    Rtl819XPHY_REGArray_Table;
1750         u32*    Rtl819XAGCTAB_Array_Table;
1751         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1752         //struct r8192_priv *priv = ieee80211_priv(dev);
1753 //#if (HAL_CODE_BASE != RTL8192_S)
1754         /*if(Adapter->bInHctTest)
1755         {
1756
1757                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1758                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1759
1760                 if(pHalData->RF_Type == RF_2T4R)
1761                 {
1762                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1763                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1764                 }
1765                 else if (pHalData->RF_Type == RF_1T2R)
1766                 {
1767                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1768                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1769                 }
1770
1771         }
1772         else
1773         */
1774         //{
1775         //
1776         // 2008.11.06 Modified by tynli.
1777         //
1778         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1779         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1780         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1781         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1782         //}
1783
1784         if(ConfigType == BaseBand_Config_PHY_REG)
1785         {
1786                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1787                 {
1788                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1789                                 mdelay(50);
1790                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1791                                 mdelay(5);
1792                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1793                                 mdelay(1);
1794                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1795                                 udelay(50);
1796                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1797                                 udelay(5);
1798                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1799                                 udelay(1);
1800                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1801                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1802
1803                 }
1804         }
1805         else if(ConfigType == BaseBand_Config_AGC_TAB){
1806                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1807                 {
1808                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1809                 }
1810         }
1811 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1812         return RT_STATUS_SUCCESS;
1813 }
1814
1815 /*-----------------------------------------------------------------------------
1816  * Function:    phy_ConfigBBWithPgHeaderFile
1817  *
1818  * Overview:    Config PHY_REG_PG array
1819  *
1820  * Input:       NONE
1821  *
1822  * Output:      NONE
1823  *
1824  * Return:      NONE
1825  *
1826  * Revised History:
1827  * When                 Who             Remark
1828  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1829  * 11/10/2008   tynli           Modify to mew files.
1830  //use in phy only
1831  *---------------------------------------------------------------------------*/
1832 static RT_STATUS
1833 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1834 {
1835         int i;
1836         //u8 ArrayLength;
1837         u32*    Rtl819XPHY_REGArray_Table_PG;
1838         u16     PHY_REGArrayPGLen;
1839         //struct r8192_priv *priv = ieee80211_priv(dev);
1840 //#if (HAL_CODE_BASE != RTL8192_S)
1841         // Default: pHalData->RF_Type = RF_2T2R.
1842
1843         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1844         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1845
1846         if(ConfigType == BaseBand_Config_PHY_REG)
1847         {
1848                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1849                 {
1850                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1851                                 mdelay(50);
1852                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1853                                 mdelay(5);
1854                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1855                                 mdelay(1);
1856                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1857                                 udelay(50);
1858                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1859                                 udelay(5);
1860                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1861                                 udelay(1);
1862                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1863                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1864                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1865                 }
1866         }else{
1867                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1868         }
1869         return RT_STATUS_SUCCESS;
1870
1871 }       /* phy_ConfigBBWithPgHeaderFile */
1872
1873 /*-----------------------------------------------------------------------------
1874  * Function:    PHY_ConfigRFWithHeaderFile()
1875  *
1876  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1877  *
1878  * Input:       PADAPTER                        Adapter
1879  *                      char*                           pFileName
1880  *                      RF90_RADIO_PATH_E       eRFPath
1881  *
1882  * Output:      NONE
1883  *
1884  * Return:      RT_STATUS_SUCCESS: configuration file exist
1885  *
1886  * Note:                Delay may be required for RF configuration
1887  *---------------------------------------------------------------------------*/
1888 //in 8256 phy_RF8256_Config_ParaFile only
1889 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1890 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1891 {
1892
1893         struct r8192_priv *priv = ieee80211_priv(dev);
1894         int                     i;
1895         //u32*  pRFArray;
1896         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1897         u32                     *Rtl819XRadioA_Array_Table;
1898         u32                     *Rtl819XRadioB_Array_Table;
1899         //u32*  Rtl819XRadioC_Array_Table;
1900         //u32*  Rtl819XRadioD_Array_Table;
1901         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1902
1903         {       //2008.11.06 Modified by tynli
1904                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1905                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1906                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1907                 RadioB_ArrayLen = RadioB_ArrayLength;
1908         }
1909
1910         if( priv->rf_type == RF_2T2R_GREEN )
1911         {
1912                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1913                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1914         }
1915         else
1916         {
1917                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1918                 RadioB_ArrayLen = RadioB_ArrayLength;
1919         }
1920
1921         rtStatus = RT_STATUS_SUCCESS;
1922
1923         // When initialization, we want the delay function(mdelay(), delay_us()
1924         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1925         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1926         // to run at Dispatch level to achive it.
1927         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1928
1929         switch(eRFPath){
1930                 case RF90_PATH_A:
1931                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1932                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1933                                         { // Deay specific ms. Only RF configuration require delay.
1934 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1935 #ifdef RTL8192SU
1936                                                 mdelay(1000);
1937 #else
1938                                                 mdelay(50);
1939 #endif
1940                                 }
1941                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1942                                                 mdelay(5);
1943                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1944                                                 mdelay(1);
1945                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1946                                                 udelay(50);
1947                                                 //PlatformStallExecution(50);
1948                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1949                                                 udelay(5);
1950                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1951                                                 udelay(1);
1952                                         else
1953                                         {
1954                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1955                                         }
1956                         }
1957                         break;
1958                 case RF90_PATH_B:
1959                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1960                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1961                                         { // Deay specific ms. Only RF configuration require delay.
1962 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1963 #ifdef RTL8192SU
1964                                                 mdelay(1000);
1965 #else
1966                                                 mdelay(50);
1967 #endif
1968                                 }
1969                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1970                                                 mdelay(5);
1971                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1972                                                 mdelay(1);
1973                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1974                                                 udelay(50);
1975                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1976                                                 udelay(5);
1977                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1978                                                 udelay(1);
1979                                         else
1980                                         {
1981                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1982                                         }
1983                         }
1984                         break;
1985                 case RF90_PATH_C:
1986                         break;
1987                 case RF90_PATH_D:
1988                         break;
1989                 default:
1990                         break;
1991         }
1992
1993         return rtStatus;
1994
1995 }
1996
1997 /*-----------------------------------------------------------------------------
1998  * Function:    PHY_CheckBBAndRFOK()
1999  *
2000  * Overview:    This function is write register and then readback to make sure whether
2001  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
2002  *
2003  * Input:       PADAPTER                        Adapter
2004  *                      HW90_BLOCK_E            CheckBlock
2005  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
2006  *
2007  * Output:      NONE
2008  *
2009  * Return:      RT_STATUS_SUCCESS: PHY is OK
2010  *
2011  * Note:                This function may be removed in the ASIC
2012  *---------------------------------------------------------------------------*/
2013 //in 8256 phy_RF8256_Config_HardCode
2014 //but we don't use it temp
2015 RT_STATUS
2016 PHY_CheckBBAndRFOK(
2017         struct net_device* dev,
2018         HW90_BLOCK_E            CheckBlock,
2019         RF90_RADIO_PATH_E       eRFPath
2020         )
2021 {
2022         //struct r8192_priv *priv = ieee80211_priv(dev);
2023         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
2024         u32                             i, CheckTimes = 4,ulRegRead = 0;
2025         u32                             WriteAddr[4];
2026         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2027
2028         // Initialize register address offset to be checked
2029         WriteAddr[HW90_BLOCK_MAC] = 0x100;
2030         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2031         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2032         WriteAddr[HW90_BLOCK_RF] = 0x3;
2033
2034         for(i=0 ; i < CheckTimes ; i++)
2035         {
2036
2037                 //
2038                 // Write Data to register and readback
2039                 //
2040                 switch(CheckBlock)
2041                 {
2042                 case HW90_BLOCK_MAC:
2043                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
2044                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
2045                         break;
2046
2047                 case HW90_BLOCK_PHY0:
2048                 case HW90_BLOCK_PHY1:
2049                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2050                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2051                         break;
2052
2053                 case HW90_BLOCK_RF:
2054                         // When initialization, we want the delay function(mdelay(), delay_us()
2055                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
2056                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
2057                         // to run at Dispatch level to achive it.
2058                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
2059                         WriteData[i] &= 0xfff;
2060                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
2061                         // TODO: we should not delay for such a long time. Ask SD3
2062                         mdelay(10);
2063                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2064                         mdelay(10);
2065                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
2066                         break;
2067
2068                 default:
2069                         rtStatus = RT_STATUS_FAILURE;
2070                         break;
2071                 }
2072
2073
2074                 //
2075                 // Check whether readback data is correct
2076                 //
2077                 if(ulRegRead != WriteData[i])
2078                 {
2079                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
2080                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
2081                         rtStatus = RT_STATUS_FAILURE;
2082                         break;
2083                 }
2084         }
2085
2086         return rtStatus;
2087 }
2088
2089 //no use temp in windows driver
2090 #ifdef TO_DO_LIST
2091 void
2092 PHY_SetRFPowerState8192SUsb(
2093         struct net_device* dev,
2094         RF_POWER_STATE  RFPowerState
2095         )
2096 {
2097         struct r8192_priv *priv = ieee80211_priv(dev);
2098         bool                    WaitShutDown = FALSE;
2099         u32                     DWordContent;
2100         //RF90_RADIO_PATH_E     eRFPath;
2101         u8                              eRFPath;
2102         BB_REGISTER_DEFINITION_T        *pPhyReg;
2103
2104         if(priv->SetRFPowerStateInProgress == TRUE)
2105                 return;
2106
2107         priv->SetRFPowerStateInProgress = TRUE;
2108
2109         // TODO: Emily, 2006.11.21, we should rewrite this function
2110
2111         if(RFPowerState==RF_SHUT_DOWN)
2112         {
2113                 RFPowerState=RF_OFF;
2114                 WaitShutDown=TRUE;
2115         }
2116
2117
2118         priv->RFPowerState = RFPowerState;
2119         switch( priv->rf_chip )
2120         {
2121         case RF_8225:
2122         case RF_6052:
2123                 switch( RFPowerState )
2124                 {
2125                 case RF_ON:
2126                         break;
2127
2128                 case RF_SLEEP:
2129                         break;
2130
2131                 case RF_OFF:
2132                         break;
2133                 }
2134                 break;
2135
2136         case RF_8256:
2137                 switch( RFPowerState )
2138                 {
2139                 case RF_ON:
2140                         break;
2141
2142                 case RF_SLEEP:
2143                         break;
2144
2145                 case RF_OFF:
2146                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
2147                         {
2148                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2149                                         continue;
2150
2151                                 pPhyReg = &priv->PHYRegDef[eRFPath];
2152                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
2153                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
2154                         }
2155                         break;
2156                 }
2157                 break;
2158
2159         case RF_8258:
2160                 break;
2161         }// switch( priv->rf_chip )
2162
2163         priv->SetRFPowerStateInProgress = FALSE;
2164 }
2165 #endif
2166
2167 #ifdef RTL8192U
2168 //no use temp in windows driver
2169 void
2170 PHY_UpdateInitialGain(
2171         struct net_device* dev
2172         )
2173 {
2174         struct r8192_priv       *priv = ieee80211_priv(dev);
2175         //unsigned char                 *IGTable;
2176         //u8                    DIG_CurrentInitialGain = 4;
2177
2178         switch(priv->rf_chip)
2179         {
2180         case RF_8225:
2181                 break;
2182         case RF_8256:
2183                 break;
2184         case RF_8258:
2185                 break;
2186         case RF_PSEUDO_11N:
2187                 break;
2188         case RF_6052:
2189                 break;
2190         default:
2191                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
2192                 break;
2193         }
2194 }
2195 #endif
2196
2197 //YJ,modified,090107
2198 void PHY_GetHWRegOriginalValue(struct net_device* dev)
2199 {
2200         struct r8192_priv *priv = ieee80211_priv(dev);
2201
2202         // read tx power offset
2203         // Simulate 8192
2204         priv->MCSTxPowerLevelOriginalOffset[0] =
2205                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
2206         priv->MCSTxPowerLevelOriginalOffset[1] =
2207                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
2208         priv->MCSTxPowerLevelOriginalOffset[2] =
2209                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
2210         priv->MCSTxPowerLevelOriginalOffset[3] =
2211                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
2212         priv->MCSTxPowerLevelOriginalOffset[4] =
2213                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
2214         priv->MCSTxPowerLevelOriginalOffset[5] =
2215                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
2216
2217         // Read CCK offset
2218         priv->MCSTxPowerLevelOriginalOffset[6] =
2219                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
2220         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
2221         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
2222         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
2223         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
2224
2225         // read rx initial gain
2226         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
2227         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
2228         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
2229         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
2230         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2231                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2232                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2233
2234         // read framesync
2235         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
2236         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
2237         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2238                                 rOFDM0_RxDetector3, priv->framesync);
2239 }
2240 //YJ,modified,090107,end
2241
2242
2243
2244 /**
2245 * Function:     phy_InitBBRFRegisterDefinition
2246 *
2247 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
2248 *
2249 * Input:
2250 *                       PADAPTER                Adapter,
2251 *
2252 * Output:       None
2253 * Return:               None
2254 * Note:         The initialization value is constant and it should never be changes
2255 */
2256 //use in phy only
2257 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
2258 {
2259         struct r8192_priv *priv = ieee80211_priv(dev);
2260
2261         // RF Interface Sowrtware Control
2262         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2263         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2264         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2265         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2266
2267         // RF Interface Readback Value
2268         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2269         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2270         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2271         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2272
2273         // RF Interface Output (and Enable)
2274         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2275         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2276         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2277         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2278
2279         // RF Interface (Output and)  Enable
2280         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2281         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2282         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2283         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2284
2285         //Addr of LSSI. Wirte RF register by driver
2286         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2287         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2288         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2289         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2290
2291         // RF parameter
2292         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
2293         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2294         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2295         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2296
2297         // Tx AGC Gain Stage (same for all path. Should we remove this?)
2298         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2299         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2300         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2301         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2302
2303         // Tranceiver A~D HSSI Parameter-1
2304         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
2305         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
2306         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
2307         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
2308
2309         // Tranceiver A~D HSSI Parameter-2
2310         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
2311         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
2312         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
2313         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
2314
2315         // RF switch Control
2316         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2317         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2318         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2319         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2320
2321         // AGC control 1
2322         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2323         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2324         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2325         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2326
2327         // AGC control 2
2328         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2329         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2330         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2331         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2332
2333         // RX AFE control 1
2334         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2335         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2336         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2337         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2338
2339         // RX AFE control 1
2340         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2341         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2342         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2343         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2344
2345         // Tx AFE control 1
2346         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2347         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2348         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2349         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2350
2351         // Tx AFE control 2
2352         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2353         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2354         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2355         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2356
2357         // Tranceiver LSSI Readback  SI mode
2358         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2359         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2360         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2361         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2362
2363         // Tranceiver LSSI Readback PI mode
2364         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
2365         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
2366         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
2367         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
2368
2369 }
2370
2371
2372 //
2373 //      Description:  Change RF power state.
2374 //
2375 //      Assumption: This function must be executed in re-schdulable context,
2376 //              ie. PASSIVE_LEVEL.
2377 //
2378 //      050823, by rcnjko.
2379 //not understand it seem's use in init
2380 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
2381 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
2382 {
2383         struct r8192_priv *priv = ieee80211_priv(dev);
2384         bool                    bResult = FALSE;
2385
2386         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2387
2388         if(eRFPowerState == priv->ieee80211->eRFPowerState)
2389         {
2390                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2391                 return bResult;
2392         }
2393
2394         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
2395
2396         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
2397
2398         return bResult;
2399 }
2400
2401 //use in phy only
2402 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
2403 {
2404         struct r8192_priv *priv = ieee80211_priv(dev);
2405         bool                    bResult = TRUE;
2406         //u8            eRFPath;
2407         //u8            i, QueueID;
2408         u8              u1bTmp;
2409
2410         if(priv->SetRFPowerStateInProgress == TRUE)
2411                 return FALSE;
2412
2413         priv->SetRFPowerStateInProgress = TRUE;
2414
2415         switch(priv->rf_chip )
2416         {
2417                 default:
2418                 switch( eRFPowerState )
2419                 {
2420                         case eRfOn:
2421                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
2422                                 write_nic_word(dev, CMDR, 0x37FC);
2423                                 write_nic_byte(dev, PHY_CCA, 0x3);
2424                                 write_nic_byte(dev, TXPAUSE, 0x00);
2425                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
2426                                 break;
2427
2428                         //
2429                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
2430                         // By Bruce, 2008-01-16.
2431                         //
2432                         case eRfSleep:
2433                         case eRfOff:
2434                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
2435                                                 break;
2436 #ifdef NOT_YET
2437                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
2438                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
2439                                 {
2440                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
2441                                         {
2442                                                 QueueID++;
2443                                                 continue;
2444                                         }
2445                                         else
2446                                         {
2447                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
2448                                                 udelay(10);
2449                                                 i++;
2450                                         }
2451
2452                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
2453                                         {
2454                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
2455                                                 break;
2456                                         }
2457                                 }
2458 #endif
2459                                 //
2460                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
2461                                 // Added by Bruce, 2008-11-22.
2462                                 //
2463                                 //==================================================================
2464                                 // (0) Disable FW BB reset checking
2465                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
2466
2467                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
2468                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
2469                                 u1bTmp |= BIT0;
2470                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
2471
2472                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
2473                                 write_nic_byte(dev, TXPAUSE, 0xFF);
2474
2475                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
2476                                 write_nic_word(dev, CMDR, 0x77FC);
2477                                 write_nic_byte(dev, PHY_CCA, 0x0);
2478                                 udelay(100);
2479
2480                                 write_nic_word(dev, CMDR, 0x37FC);
2481                                 udelay(10);
2482
2483                                 write_nic_word(dev, CMDR, 0x77FC);
2484                                 udelay(10);
2485
2486                                 // (3) Reset BB TRX blocks
2487                                 write_nic_word(dev, CMDR, 0x57FC);
2488                                 break;
2489
2490                         default:
2491                                 bResult = FALSE;
2492                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
2493                                 break;
2494                 }
2495                 break;
2496
2497         }
2498         priv->ieee80211->eRFPowerState = eRFPowerState;
2499 #ifdef TO_DO_LIST
2500         if(bResult)
2501         {
2502                 // Update current RF state variable.
2503                 priv->ieee80211->eRFPowerState = eRFPowerState;
2504
2505                 switch(priv->rf_chip )
2506                 {
2507                         case RF_8256:
2508                         switch(priv->ieee80211->eRFPowerState)
2509                         {
2510                                 case eRfOff:
2511                                         //
2512                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
2513                                         //
2514                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
2515                                         {
2516                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
2517                                         }
2518                                         else
2519                                         {
2520                                                 // Turn off LED if RF is not ON.
2521                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
2522                                         }
2523                                         break;
2524
2525                                 case eRfOn:
2526                                         // Turn on RF we are still linked, which might happen when
2527                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
2528                                         if( pMgntInfo->bMediaConnect == TRUE )
2529                                         {
2530                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
2531                                         }
2532                                         else
2533                                         {
2534                                                 // Turn off LED if RF is not ON.
2535                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
2536                                         }
2537                                         break;
2538
2539                                 default:
2540                                         // do nothing.
2541                                         break;
2542                         }// Switch RF state
2543
2544                                 break;
2545
2546                         default:
2547                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
2548                                 break;
2549                 }// Switch rf_chip
2550         }
2551 #endif
2552         priv->SetRFPowerStateInProgress = FALSE;
2553
2554         return bResult;
2555 }
2556
2557 /*-----------------------------------------------------------------------------
2558  * Function:    GetTxPowerLevel8190()
2559  *
2560  * Overview:    This function is export to "common" moudule
2561  *
2562  * Input:       PADAPTER                Adapter
2563  *                      psByte                  Power Level
2564  *
2565  * Output:      NONE
2566  *
2567  * Return:      NONE
2568  *
2569  *---------------------------------------------------------------------------*/
2570  // no use temp
2571  void
2572 PHY_GetTxPowerLevel8192S(
2573         struct net_device* dev,
2574          long*                  powerlevel
2575         )
2576 {
2577         struct r8192_priv *priv = ieee80211_priv(dev);
2578         u8                      TxPwrLevel = 0;
2579         long                    TxPwrDbm;
2580         //
2581         // Because the Tx power indexes are different, we report the maximum of them to
2582         // meet the CCX TPC request. By Bruce, 2008-01-31.
2583         //
2584
2585         // CCK
2586         TxPwrLevel = priv->CurrentCckTxPwrIdx;
2587         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
2588
2589         // Legacy OFDM
2590         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
2591
2592         // Compare with Legacy OFDM Tx power.
2593         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2594                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
2595
2596         // HT OFDM
2597         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
2598
2599         // Compare with HT OFDM Tx power.
2600         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2601                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
2602
2603         *powerlevel = TxPwrDbm;
2604 }
2605
2606 /*-----------------------------------------------------------------------------
2607  * Function:    SetTxPowerLevel8190()
2608  *
2609  * Overview:    This function is export to "HalCommon" moudule
2610  *
2611  * Input:       PADAPTER                Adapter
2612  *                      u1Byte          channel
2613  *
2614  * Output:      NONE
2615  *
2616  * Return:      NONE
2617  *      2008/11/04      MHC             We remove EEPROM_93C56.
2618  *                                              We need to move CCX relative code to independet file.
2619 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
2620   *---------------------------------------------------------------------------*/
2621  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
2622 {
2623         struct r8192_priv *priv = ieee80211_priv(dev);
2624         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
2625         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
2626         s8      ant_pwr_diff = 0;
2627         u32     u4RegValue;
2628         u8      index = (channel -1);
2629         // 2009/01/22 MH Add for new EEPROM format from SD3
2630         u8      pwrdiff[2] = {0};
2631         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
2632         u8      rfpath = 0, rfpathnum = 2;
2633
2634         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
2635                 return;
2636
2637         //
2638         // Read predefined TX power index in EEPROM
2639         //
2640 //      if(priv->epromtype == EPROM_93c46)
2641         {
2642                 //
2643                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2644                 // Power must be calculated by the antenna diff.
2645                 // So we have to rewrite Antenna gain offset register here.
2646                 // Please refer to BB register 0x80c
2647                 // 1. For CCK.
2648                 // 2. For OFDM 1T or 2T
2649                 //
2650
2651                 // 1. CCK
2652                 powerlevel = priv->RfTxPwrLevelCck[0][index];
2653
2654                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
2655                 {
2656                 // Read HT 40 OFDM TX power
2657                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
2658                 // RF B HT OFDM pwr-RFA HT OFDM pwr
2659                 // Only one RF we need not to decide B <-> A pwr diff
2660
2661                 // Legacy<->HT pwr diff, we only care about path A.
2662
2663                 // We only assume 1T as RF path A
2664                 rfpathnum = 1;
2665                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
2666                 }
2667                 else if (priv->rf_type == RF_2T2R)
2668                 {
2669                 // Read HT 40 OFDM TX power
2670                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
2671                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2672                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
2673                                                 priv->RfTxPwrLevelOfdm2T[0][index];
2674                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
2675                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
2676
2677                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
2678                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
2679                 //priv->RfTxPwrLevelOfdm2T[1][index],
2680                 //priv->RfTxPwrLevelOfdm2T[0][index],
2681                 //priv->RfTxPwrLevelOfdm2T[1][index]));
2682
2683                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
2684                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
2685         }
2686
2687         //
2688         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
2689         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
2690         //
2691         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
2692         {
2693                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2694                 {
2695                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2696                         {
2697                                 // HT 20<->40 pwr diff
2698                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
2699
2700                                 // Calculate Antenna pwr diff
2701                                 if (pwrdiff[rfpath] < 8)        // 0~+7
2702                                 {
2703                                 #if 0//cosa, it doesn't need to add the offset here
2704                                         if (rfpath == 0)
2705                                                 powerlevelOFDM24G += pwrdiff[rfpath];
2706                                 #endif
2707                                         ht20pwr[rfpath] += pwrdiff[rfpath];
2708                                 }
2709                                 else                            // index8-15=-8~-1
2710                                 {
2711                                 #if 0//cosa, it doesn't need to add the offset here
2712                                         if (rfpath == 0)
2713                                                 powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
2714                                 #endif
2715                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
2716                                 }
2717                         }
2718
2719                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2720                         if (priv->rf_type == RF_2T2R)
2721                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2722
2723                         //RTPRINT(FPHY, PHY_TXPWR,
2724                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2725                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2726                 }
2727
2728                 // Band Edge scheme is enabled for FCC mode
2729                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
2730                 {
2731                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2732                         {
2733                                 pwrdiff[rfpath] = 0;
2734                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2735                                 {
2736                                         if (channel <= 3)
2737                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
2738                                         else if (channel >= 9)
2739                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
2740                                         else
2741                                                 pwrdiff[rfpath] = 0;
2742
2743                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
2744                                 }
2745                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2746                                 {
2747                                         if (channel == 1)
2748                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2749                                         else if (channel >= 11)
2750                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2751                                         else
2752                                                 pwrdiff[rfpath] = 0;
2753
2754                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2755                                 }
2756                         #if 0//cosa, it doesn't need to add the offset here
2757                                 if (rfpath == 0)
2758                                         powerlevelOFDM24G -= pwrdiff[rfpath];
2759                         #endif
2760                         }
2761
2762                         if (priv->rf_type == RF_2T2R)
2763                         {
2764                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2765                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2766                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2767                                 else
2768                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2769                         }
2770                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2771                         {
2772                                 if (channel <= 1 || channel >= 11)
2773                                 {
2774                                         //RTPRINT(FPHY, PHY_TXPWR,
2775                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2776                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2777                                 }
2778                         }
2779                         else
2780                         {
2781                                 if (channel <= 3 || channel >= 9)
2782                                 {
2783                                         //RTPRINT(FPHY, PHY_TXPWR,
2784                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2785                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2786                                 }
2787                         }
2788                 }
2789 #if 0//cosa, useless
2790                 // Read HT/Legacy OFDM diff
2791                 legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
2792 #endif
2793                 }
2794
2795         //Cosa added for protection, the reg rFPGA0_TxGainStage
2796         // range is from 7~-8, index = 0x0~0xf
2797         if(ant_pwr_diff > 7)
2798                 ant_pwr_diff = 7;
2799         if(ant_pwr_diff < -8)
2800                 ant_pwr_diff = -8;
2801
2802                 //RTPRINT(FPHY, PHY_TXPWR,
2803                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2804                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2805
2806                 ant_pwr_diff &= 0xf;
2807
2808                 // Antenna TX power difference
2809                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2810                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2811                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2812
2813                 // Antenna gain offset from B/C/D to A
2814                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2815                                                 priv->AntennaTxPwDiff[1]<<4 |
2816                                                 priv->AntennaTxPwDiff[0]        );
2817
2818                 // Notify Tx power difference for B/C/D to A!!!
2819                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2820         }
2821
2822         //
2823         // CCX 2 S31, AP control of client transmit power:
2824         // 1. We shall not exceed Cell Power Limit as possible as we can.
2825         // 2. Tolerance is +/- 5dB.
2826         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2827         //
2828         // TODO:
2829         // 1. 802.11h power contraint
2830         //
2831         // 071011, by rcnjko.
2832         //
2833 #ifdef TODO //WB, 11h has not implemented now.
2834         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2835                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2836         {
2837                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2838                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2839                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2840
2841                 RT_TRACE(COMP_TXAGC,
2842                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2843                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2844                 RT_TRACE(COMP_TXAGC,
2845                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2846                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2847
2848                 // CCK
2849                 if(powerlevel > CckCellPwrIdx)
2850                         powerlevel = CckCellPwrIdx;
2851                 // Legacy OFDM, HT OFDM
2852                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2853                 {
2854                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2855                         {
2856                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2857                         }
2858                         else
2859                         {
2860                                 powerlevelOFDM24G = 0;
2861                         }
2862                 }
2863
2864                 RT_TRACE(COMP_TXAGC,
2865                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2866                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2867         }
2868 #endif
2869
2870         priv->CurrentCckTxPwrIdx = powerlevel;
2871         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2872
2873         switch(priv->rf_chip)
2874         {
2875                 case RF_8225:
2876                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2877                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2878                 break;
2879
2880                 case RF_8256:
2881 #if 0
2882                         PHY_SetRF8256CCKTxPower(dev, powerlevel);
2883                         PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2884 #endif
2885                         break;
2886
2887                 case RF_6052:
2888                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2889                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2890                         break;
2891
2892                 case RF_8258:
2893                         break;
2894                 default:
2895                         break;
2896         }
2897
2898 }
2899
2900 //
2901 //      Description:
2902 //              Update transmit power level of all channel supported.
2903 //
2904 //      TODO:
2905 //              A mode.
2906 //      By Bruce, 2008-02-04.
2907 //    no use temp
2908 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2909 {
2910         struct r8192_priv       *priv = ieee80211_priv(dev);
2911         u8                              idx;
2912         u8                              rf_path;
2913
2914         // TODO: A mode Tx power.
2915         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2916         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2917
2918         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2919                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2920         else
2921                 OfdmTxPwrIdx = 0;
2922
2923         for(idx = 0; idx < 14; idx++)
2924         {
2925                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2926                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2927                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2928                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2929                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2930                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2931
2932                 for (rf_path = 0; rf_path < 2; rf_path++)
2933                 {
2934                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2935                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2936                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2937                 }
2938         }
2939
2940         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2941
2942         return TRUE;
2943 }
2944
2945 /*
2946         Description:
2947                 When beacon interval is changed, the values of the
2948                 hw registers should be modified.
2949         By tynli, 2008.10.24.
2950
2951 */
2952
2953 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2954 {
2955         u32 NewBeaconNum;
2956
2957         NewBeaconNum = BeaconInterval *32 - 64;
2958         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2959         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2960         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2961         write_nic_dword(dev, WFM3, 0xB026007C);
2962 }
2963
2964 //
2965 //      Description:
2966 //              Map dBm into Tx power index according to
2967 //              current HW model, for example, RF and PA, and
2968 //              current wireless mode.
2969 //      By Bruce, 2008-01-29.
2970 //    use in phy only
2971 static u8 phy_DbmToTxPwrIdx(
2972         struct net_device* dev,
2973         WIRELESS_MODE   WirelessMode,
2974         long                    PowerInDbm
2975         )
2976 {
2977         //struct r8192_priv *priv = ieee80211_priv(dev);
2978         u8                              TxPwrIdx = 0;
2979         long                            Offset = 0;
2980
2981
2982         //
2983         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2984         // 3dbm, and OFDM HT equals to 0dbm repectively.
2985         // Note:
2986         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2987         // By Bruce, 2008-01-29.
2988         //
2989         switch(WirelessMode)
2990         {
2991         case WIRELESS_MODE_B:
2992                 Offset = -7;
2993                 break;
2994
2995         case WIRELESS_MODE_G:
2996         case WIRELESS_MODE_N_24G:
2997                 Offset = -8;
2998                 break;
2999         default:
3000                 break;
3001         }
3002
3003         if((PowerInDbm - Offset) > 0)
3004         {
3005                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
3006         }
3007         else
3008         {
3009                 TxPwrIdx = 0;
3010         }
3011
3012         // Tx Power Index is too large.
3013         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
3014                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
3015
3016         return TxPwrIdx;
3017 }
3018 //
3019 //      Description:
3020 //              Map Tx power index into dBm according to
3021 //              current HW model, for example, RF and PA, and
3022 //              current wireless mode.
3023 //      By Bruce, 2008-01-29.
3024 //    use in phy only
3025 static long phy_TxPwrIdxToDbm(
3026         struct net_device* dev,
3027         WIRELESS_MODE   WirelessMode,
3028         u8                      TxPwrIdx
3029         )
3030 {
3031         //struct r8192_priv *priv = ieee80211_priv(dev);
3032         long                            Offset = 0;
3033         long                            PwrOutDbm = 0;
3034
3035         //
3036         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
3037         // 3dbm, and OFDM HT equals to 0dbm repectively.
3038         // Note:
3039         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
3040         // By Bruce, 2008-01-29.
3041         //
3042         switch(WirelessMode)
3043         {
3044         case WIRELESS_MODE_B:
3045                 Offset = -7;
3046                 break;
3047
3048         case WIRELESS_MODE_G:
3049         case WIRELESS_MODE_N_24G:
3050                 Offset = -8;
3051                 break;
3052         default:
3053                 break;
3054         }
3055
3056         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
3057
3058         return PwrOutDbm;
3059 }
3060
3061 #ifdef TO_DO_LIST
3062 extern  VOID
3063 PHY_ScanOperationBackup8192S(
3064         IN      PADAPTER        Adapter,
3065         IN      u1Byte          Operation
3066         )
3067 {
3068
3069         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
3070         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
3071         u4Byte                          BitMask;
3072         u1Byte                          initial_gain;
3073
3074
3075
3076
3077 #if(RTL8192S_DISABLE_FW_DM == 0)
3078
3079         if(!Adapter->bDriverStopped)
3080         {
3081                 switch(Operation)
3082                 {
3083                         case SCAN_OPT_BACKUP:
3084                                 //
3085                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
3086                                 // and resume both two DMs while scan complete.
3087                                 // 2008.11.27.
3088                                 //
3089                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
3090                                 break;
3091
3092                         case SCAN_OPT_RESTORE:
3093                                 //
3094                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
3095                                 // recover earlier DIG settings.
3096                                 // 2008.11.27.
3097                                 //
3098                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
3099                                 break;
3100
3101                         default:
3102                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
3103                                 break;
3104                 }
3105         }
3106 #endif
3107 }
3108 #endif
3109
3110 //nouse temp
3111 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
3112 {
3113
3114         //struct r8192_priv *priv = ieee80211_priv(dev);
3115         //u32                                   BitMask;
3116         //u8                                    initial_gain;
3117
3118 #if 0   // For 8192s test disable
3119         if(!dev->bDriverStopped)
3120         {
3121                 switch(Operation)
3122                 {
3123                         case IG_Backup:
3124                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
3125                                 initial_gain = priv->DefaultInitialGain[0];
3126                                 BitMask = bMaskByte0;
3127                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3128                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3129                                 pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3130                                 pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3131                                 pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3132                                 pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3133                                 BitMask  = bMaskByte2;
3134                                 pMgntInfo->InitGain_Backup.CCA          = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3135
3136                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3137                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3138                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3139                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3140                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3141
3142                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
3143                                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3144                                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3145                                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3146                                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3147                                 break;
3148                         case IG_Restore:
3149                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
3150                                 BitMask = 0x7f; //Bit0~ Bit6
3151                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3152                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3153
3154                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
3155                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
3156                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
3157                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
3158                                 BitMask  = (BIT22|BIT23);
3159                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
3160
3161                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3162                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3163                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3164                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3165                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3166
3167                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3168                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1);      // FW DIG ON
3169                                 break;
3170                         default:
3171                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
3172                                 break;
3173                 }
3174         }
3175 #endif
3176 }
3177
3178 /*-----------------------------------------------------------------------------
3179  * Function:    SetBWModeCallback8190Pci()
3180  *
3181  * Overview:    Timer callback function for SetSetBWMode
3182  *
3183  * Input:               PRT_TIMER               pTimer
3184  *
3185  * Output:      NONE
3186  *
3187  * Return:      NONE
3188  *
3189  * Note:                (1) We do not take j mode into consideration now
3190  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3191  *                           concurrently?
3192  *---------------------------------------------------------------------------*/
3193 //    use in phy only (in win it's timer)
3194 void PHY_SetBWModeCallback8192S(struct net_device *dev)
3195 {
3196         struct r8192_priv *priv = ieee80211_priv(dev);
3197         u8                              regBwOpMode;
3198
3199         //return;
3200
3201         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3202         //u32                           NowL, NowH;
3203         //u8Byte                                BeginTime, EndTime;
3204         u8                              regRRSR_RSC;
3205
3206         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3207                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3208
3209         if(priv->rf_chip == RF_PSEUDO_11N)
3210         {
3211                 priv->SetBWModeInProgress= FALSE;
3212                 return;
3213         }
3214
3215         if(!priv->up)
3216                 return;
3217
3218         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3219         //NowL = read_nic_dword(dev, TSFR);
3220         //NowH = read_nic_dword(dev, TSFR+4);
3221         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3222
3223         //3//
3224         //3//<1>Set MAC register
3225         //3//
3226         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3227         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3228
3229         switch(priv->CurrentChannelBW)
3230         {
3231                 case HT_CHANNEL_WIDTH_20:
3232                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3233                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3234
3235                         regBwOpMode |= BW_OPMODE_20MHZ;
3236                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3237                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3238                         break;
3239
3240                 case HT_CHANNEL_WIDTH_20_40:
3241                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3242                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3243
3244                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3245                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3246                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3247                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3248                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3249                         break;
3250
3251                 default:
3252                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
3253                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3254                         break;
3255         }
3256
3257         //3//
3258         //3//<2>Set PHY related register
3259         //3//
3260         switch(priv->CurrentChannelBW)
3261         {
3262                 /* 20 MHz channel*/
3263                 case HT_CHANNEL_WIDTH_20:
3264                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3265                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3266
3267                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3268                         // It is set in Tx descriptor for 8192x series
3269                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3270                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3271                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3272                         #if 0 //LZM 090219
3273                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
3274                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
3275                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
3276                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3277                         #endif
3278
3279                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3280                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3281
3282
3283                         break;
3284
3285                 /* 40 MHz channel*/
3286                 case HT_CHANNEL_WIDTH_20_40:
3287                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3288                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3289
3290                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3291                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3292                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3293                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3294                         #if 0 //LZM 090219
3295                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3296                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3297                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3298                         #endif
3299
3300                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3301                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3302                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3303
3304                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3305                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3306                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3307
3308                         break;
3309
3310                 default:
3311                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
3312                                                 ,priv->CurrentChannelBW);
3313                         break;
3314
3315         }
3316         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3317
3318         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3319         //NowL = read_nic_dword(dev, TSFR);
3320         //NowH = read_nic_dword(dev, TSFR+4);
3321         //EndTime = ((u8Byte)NowH << 32) + NowL;
3322         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3323
3324         //3<3>Set RF related register
3325         switch( priv->rf_chip )
3326         {
3327                 case RF_8225:
3328                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3329                         break;
3330
3331                 case RF_8256:
3332                         // Please implement this function in Hal8190PciPhy8256.c
3333                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3334                         break;
3335
3336                 case RF_8258:
3337                         // Please implement this function in Hal8190PciPhy8258.c
3338                         // PHY_SetRF8258Bandwidth();
3339                         break;
3340
3341                 case RF_PSEUDO_11N:
3342                         // Do Nothing
3343                         break;
3344
3345                 case RF_6052:
3346                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3347                         break;
3348                 default:
3349                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
3350                         break;
3351         }
3352
3353         priv->SetBWModeInProgress= FALSE;
3354
3355         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
3356 }
3357
3358
3359  /*-----------------------------------------------------------------------------
3360  * Function:   SetBWMode8190Pci()
3361  *
3362  * Overview:  This function is export to "HalCommon" moudule
3363  *
3364  * Input:               PADAPTER                        Adapter
3365  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
3366  *
3367  * Output:      NONE
3368  *
3369  * Return:      NONE
3370  *
3371  * Note:                We do not take j mode into consideration now
3372  *---------------------------------------------------------------------------*/
3373 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
3374 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
3375 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
3376 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3377 {
3378         struct r8192_priv *priv = ieee80211_priv(dev);
3379         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
3380
3381
3382         // Modified it for 20/40 mhz switch by guangan 070531
3383
3384         //return;
3385
3386         //if(priv->SwChnlInProgress)
3387 //      if(pMgntInfo->bScanInProgress)
3388 //      {
3389 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
3390 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3391 //              return;
3392 //      }
3393
3394 //      if(priv->SetBWModeInProgress)
3395 //      {
3396 //              // Modified it for 20/40 mhz switch by guangan 070531
3397 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
3398 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3399 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
3400 //              //return;
3401 //      }
3402
3403         if(priv->SetBWModeInProgress)
3404                 return;
3405
3406         priv->SetBWModeInProgress= TRUE;
3407
3408         priv->CurrentChannelBW = Bandwidth;
3409
3410         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3411                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3412         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3413                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3414         else
3415                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3416
3417 #if 0
3418         if(!priv->bDriverStopped)
3419         {
3420 #ifdef USE_WORKITEM
3421                 PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
3422 #else
3423                 PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
3424 #endif
3425         }
3426 #endif
3427         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
3428         {
3429 #ifdef RTL8192SE
3430         PHY_SetBWModeCallback8192S(dev);
3431 #elif defined(RTL8192SU)
3432         SetBWModeCallback8192SUsbWorkItem(dev);
3433 #endif
3434         }
3435         else
3436         {
3437                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
3438                 priv->SetBWModeInProgress= FALSE;
3439                 priv->CurrentChannelBW = tmpBW;
3440         }
3441 }
3442
3443 //    use in phy only (in win it's timer)
3444 void PHY_SwChnlCallback8192S(struct net_device *dev)
3445 {
3446
3447         struct r8192_priv *priv = ieee80211_priv(dev);
3448         u32             delay;
3449         //bool                  ret;
3450
3451         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
3452
3453         if(!priv->up)
3454                 return;
3455
3456         if(priv->rf_chip == RF_PSEUDO_11N)
3457         {
3458                 priv->SwChnlInProgress=FALSE;
3459                 return;                                                                 //return immediately if it is peudo-phy
3460         }
3461
3462         do{
3463                 if(!priv->SwChnlInProgress)
3464                         break;
3465
3466                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3467                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3468                 {
3469                         if(delay>0)
3470                         {
3471                                 mdelay(delay);
3472                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3473                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
3474                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
3475                                 //==>SwChnlCallback8192SUsb(dev) for 92su
3476                         }
3477                         else
3478                         continue;
3479                 }
3480                 else
3481                 {
3482                         priv->SwChnlInProgress=FALSE;
3483                         break;
3484                 }
3485         }while(true);
3486 }
3487
3488 // Call after initialization
3489 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
3490 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
3491 {
3492         struct r8192_priv *priv = ieee80211_priv(dev);
3493         //u8                    tmpchannel =channel;
3494         //bool                  bResult = false;
3495
3496         if(!priv->up)
3497                 return false;
3498
3499         if(priv->SwChnlInProgress)
3500                 return false;
3501
3502         if(priv->SetBWModeInProgress)
3503                 return false;
3504
3505         //--------------------------------------------
3506         switch(priv->ieee80211->mode)
3507         {
3508         case WIRELESS_MODE_A:
3509         case WIRELESS_MODE_N_5G:
3510                 if (channel<=14){
3511                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
3512                         return false;
3513                 }
3514                 break;
3515
3516         case WIRELESS_MODE_B:
3517                 if (channel>14){
3518                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
3519                         return false;
3520                 }
3521                 break;
3522
3523         case WIRELESS_MODE_G:
3524         case WIRELESS_MODE_N_24G:
3525                 if (channel>14){
3526                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
3527                         return false;
3528                 }
3529                 break;
3530
3531         default:
3532                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
3533                 break;
3534         }
3535         //--------------------------------------------
3536
3537         priv->SwChnlInProgress = TRUE;
3538         if( channel == 0)
3539                 channel = 1;
3540
3541         priv->chan=channel;
3542
3543         priv->SwChnlStage=0;
3544         priv->SwChnlStep=0;
3545
3546         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
3547         {
3548 #ifdef RTL8192SE
3549         PHY_SwChnlCallback8192S(dev);
3550 #elif defined(RTL8192SU)
3551         SwChnlCallback8192SUsbWorkItem(dev);
3552 #endif
3553 #ifdef TO_DO_LIST
3554         if(bResult)
3555                 {
3556                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
3557                 }
3558                 else
3559                 {
3560                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
3561                         priv->SwChnlInProgress = false;
3562                         priv->CurrentChannel = tmpchannel;
3563                 }
3564 #endif
3565         }
3566         else
3567         {
3568                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
3569                 priv->SwChnlInProgress = false;
3570                 //priv->CurrentChannel = tmpchannel;
3571         }
3572         return true;
3573 }
3574
3575
3576 //
3577 // Description:
3578 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
3579 //
3580 // Implemented by Bruce, 2008-02-14.
3581 // The following procedure is operted according to SwChanlCallback8190Pci().
3582 // However, this procedure is performed synchronously  which should be running under
3583 // passive level.
3584 //
3585 //not understant it
3586 void PHY_SwChnlPhy8192S(        // Only called during initialize
3587         struct net_device* dev,
3588         u8              channel
3589         )
3590 {
3591         struct r8192_priv *priv = ieee80211_priv(dev);
3592
3593         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
3594
3595 #ifdef TO_DO_LIST
3596         // Cannot IO.
3597         if(RT_CANNOT_IO(dev))
3598                 return;
3599 #endif
3600
3601         // Channel Switching is in progress.
3602         if(priv->SwChnlInProgress)
3603                 return;
3604
3605         //return immediately if it is peudo-phy
3606         if(priv->rf_chip == RF_PSEUDO_11N)
3607         {
3608                 priv->SwChnlInProgress=FALSE;
3609                 return;
3610         }
3611
3612         priv->SwChnlInProgress = TRUE;
3613         if( channel == 0)
3614                 channel = 1;
3615
3616         priv->chan=channel;
3617
3618         priv->SwChnlStage = 0;
3619         priv->SwChnlStep = 0;
3620
3621         phy_FinishSwChnlNow(dev,channel);
3622
3623         priv->SwChnlInProgress = FALSE;
3624 }
3625
3626 //    use in phy only
3627 static bool
3628 phy_SetSwChnlCmdArray(
3629         SwChnlCmd*              CmdTable,
3630         u32                     CmdTableIdx,
3631         u32                     CmdTableSz,
3632         SwChnlCmdID             CmdID,
3633         u32                     Para1,
3634         u32                     Para2,
3635         u32                     msDelay
3636         )
3637 {
3638         SwChnlCmd* pCmd;
3639
3640         if(CmdTable == NULL)
3641         {
3642                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3643                 return FALSE;
3644         }
3645         if(CmdTableIdx >= CmdTableSz)
3646         {
3647                 //RT_ASSERT(FALSE,
3648                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
3649                                 //CmdTableIdx, CmdTableSz));
3650                 return FALSE;
3651         }
3652
3653         pCmd = CmdTable + CmdTableIdx;
3654         pCmd->CmdID = CmdID;
3655         pCmd->Para1 = Para1;
3656         pCmd->Para2 = Para2;
3657         pCmd->msDelay = msDelay;
3658
3659         return TRUE;
3660 }
3661
3662 //    use in phy only
3663 static bool
3664 phy_SwChnlStepByStep(
3665         struct net_device* dev,
3666         u8              channel,
3667         u8              *stage,
3668         u8              *step,
3669         u32             *delay
3670         )
3671 {
3672         struct r8192_priv *priv = ieee80211_priv(dev);
3673         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
3674         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
3675         u32                                     PreCommonCmdCnt;
3676         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
3677         u32                                     PostCommonCmdCnt;
3678         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
3679         u32                                     RfDependCmdCnt;
3680         SwChnlCmd                               *CurrentCmd = NULL;
3681         u8                                      eRFPath;
3682
3683         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
3684         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
3685         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3686         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3687         if (!IsLegalChannel(priv->ieee80211, channel))
3688         {
3689                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
3690                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
3691         }
3692
3693         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3694         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3695
3696         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
3697         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3698         //{
3699                 // <1> Fill up pre common command.
3700         PreCommonCmdCnt = 0;
3701         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3702                                 CmdID_SetTxPowerLevel, 0, 0, 0);
3703         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3704                                 CmdID_End, 0, 0, 0);
3705
3706                 // <2> Fill up post common command.
3707         PostCommonCmdCnt = 0;
3708
3709         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3710                                 CmdID_End, 0, 0, 0);
3711
3712                 // <3> Fill up RF dependent command.
3713         RfDependCmdCnt = 0;
3714         switch( priv->rf_chip )
3715         {
3716                 case RF_8225:
3717                 if (channel < 1 || channel > 14)
3718                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3719                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3720                 // 2008/09/04 MH Change channel.
3721                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3722                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3723                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3724                 CmdID_End, 0, 0, 0);
3725                 break;
3726
3727         case RF_8256:
3728                 if (channel < 1 || channel > 14)
3729                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3730                 // TEST!! This is not the table for 8256!!
3731                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3732                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3733                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3734                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3735                 CmdID_End, 0, 0, 0);
3736                 break;
3737
3738         case RF_6052:
3739                 if (channel < 1 || channel > 14)
3740                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3741                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3742                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3743                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3744                         CmdID_End, 0, 0, 0);
3745                 break;
3746
3747         case RF_8258:
3748                 break;
3749
3750         default:
3751                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3752                 return FALSE;
3753                 break;
3754         }
3755
3756
3757         do{
3758                 switch(*stage)
3759                 {
3760                 case 0:
3761                         CurrentCmd=&PreCommonCmd[*step];
3762                         break;
3763                 case 1:
3764                         CurrentCmd=&RfDependCmd[*step];
3765                         break;
3766                 case 2:
3767                         CurrentCmd=&PostCommonCmd[*step];
3768                         break;
3769                 }
3770
3771                 if(CurrentCmd->CmdID==CmdID_End)
3772                 {
3773                         if((*stage)==2)
3774                         {
3775                                 return TRUE;
3776                         }
3777                         else
3778                         {
3779                                 (*stage)++;
3780                                 (*step)=0;
3781                                 continue;
3782                         }
3783                 }
3784
3785                 switch(CurrentCmd->CmdID)
3786                 {
3787                 case CmdID_SetTxPowerLevel:
3788                         //if(priv->card_8192_version > VERSION_8190_BD)
3789                                 PHY_SetTxPowerLevel8192S(dev,channel);
3790                         break;
3791                 case CmdID_WritePortUlong:
3792                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
3793                         break;
3794                 case CmdID_WritePortUshort:
3795                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
3796                         break;
3797                 case CmdID_WritePortUchar:
3798                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
3799                         break;
3800                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3801                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3802                         {
3803 #if (defined RTL8192SE ||defined RTL8192SU )
3804                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
3805                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
3806                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
3807 #else
3808                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
3809 #endif
3810                         }
3811                         break;
3812                 default:
3813                         break;
3814                 }
3815
3816                 break;
3817         }while(TRUE);
3818         //cosa }/*for(Number of RF paths)*/
3819
3820         (*delay)=CurrentCmd->msDelay;
3821         (*step)++;
3822         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3823         return FALSE;
3824 }
3825
3826 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
3827 //    use in phy only
3828 static void
3829 phy_FinishSwChnlNow(    // We should not call this function directly
3830         struct net_device* dev,
3831         u8              channel
3832                 )
3833 {
3834         struct r8192_priv       *priv = ieee80211_priv(dev);
3835         u32                     delay;
3836
3837         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
3838         {
3839                 if(delay>0)
3840                         mdelay(delay);
3841                 if(!priv->up)
3842                         break;
3843         }
3844 }
3845
3846
3847 /*-----------------------------------------------------------------------------
3848  * Function:    PHYCheckIsLegalRfPath8190Pci()
3849  *
3850  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3851  *                      We will return false.
3852  *
3853  * Input:               NONE
3854  *
3855  * Output:              NONE
3856  *
3857  * Return:              NONE
3858  *
3859  * Revised History:
3860  *      When            Who             Remark
3861  *      11/15/2007      MHC             Create Version 0.
3862  *
3863  *---------------------------------------------------------------------------*/
3864  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3865 //extern        bool
3866 //PHY_CheckIsLegalRfPath8192S(
3867 //      struct net_device* dev,
3868 //      u32     eRFPath)
3869 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3870 {
3871 //      struct r8192_priv *priv = ieee80211_priv(dev);
3872         bool                            rtValue = TRUE;
3873
3874         // NOt check RF Path now.!
3875 #if 0
3876         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3877         {
3878                 rtValue = FALSE;
3879         }
3880         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3881         {
3882
3883         }
3884 #endif
3885         return  rtValue;
3886
3887 }       /* PHY_CheckIsLegalRfPath8192S */
3888
3889
3890
3891 /*-----------------------------------------------------------------------------
3892  * Function:    PHY_IQCalibrate8192S()
3893  *
3894  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3895  *                      to improve RF EVM!!?
3896  *
3897  * Input:               IN      PADAPTER        pAdapter
3898  *
3899  * Output:              NONE
3900  *
3901  * Return:              NONE
3902  *
3903  * Revised History:
3904  *      When            Who             Remark
3905  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3906  *
3907  *---------------------------------------------------------------------------*/
3908  //called by InitializeAdapter8192SE
3909 void
3910 PHY_IQCalibrate(        struct net_device* dev)
3911 {
3912         //struct r8192_priv     *priv = ieee80211_priv(dev);
3913         u32                             i, reg;
3914         u32                             old_value;
3915         long                            X, Y, TX0[4];
3916         u32                             TXA[4];
3917
3918         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3919
3920         //
3921         // 2. QFN 68
3922         //
3923         // For 1T2R IQK only now !!!
3924         for (i = 0; i < 10; i++)
3925         {
3926                 // IQK
3927                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3928                 //PlatformStallExecution(5);
3929                 udelay(5);
3930                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3931                 udelay(5);
3932                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3933                 udelay(5);
3934                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3935                 udelay(5);
3936                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3937                 udelay(5);
3938                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3939                 udelay(5);
3940                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3941                 udelay(5);
3942                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3943                 udelay(5);
3944                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3945                 udelay(5);
3946                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3947                 udelay(5);
3948                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3949                 udelay(2000);
3950                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3951                 udelay(5);
3952                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3953                 udelay(5);
3954                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3955
3956
3957                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3958
3959                 // Readback IQK value and rewrite
3960                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3961                 {
3962                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3963
3964                         // Calibrate init gain for A path for TX0
3965                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3966                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3967                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3968                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3969                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3970                         udelay(5);
3971
3972                         // Calibrate init gain for C path for TX0
3973                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3974                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3975                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3976                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3977                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3978                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3979                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3980                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3981                         udelay(5);
3982
3983                         // Calibrate RX A and B for RX0
3984                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3985                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3986                         reg = (reg & 0xFFFFFC00) |X;
3987                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3988                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3989                         reg = (reg & 0xFFFF03FF) |Y<<10;
3990                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3991                         udelay(5);
3992                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3993
3994                         // Calibrate init gain for A path for TX1 !!!!!!
3995                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3996                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3997                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3998                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3999                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4000                         udelay(5);
4001
4002                         // Calibrate init gain for C path for TX1
4003                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4004                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4005                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4006                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4007                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4008                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4009                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4010                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4011                         udelay(5);
4012
4013                         // Calibrate RX A and B for RX1
4014                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4015                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4016                         reg = (reg & 0xFFFFFC00) |X;
4017                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4018
4019                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4020                         reg = (reg & 0xFFFF03FF) |Y<<10;
4021                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4022                         udelay(5);
4023
4024                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4025                         break;
4026                 }
4027
4028         }
4029
4030
4031         //
4032         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4033         //
4034
4035
4036 }
4037
4038 /*-----------------------------------------------------------------------------
4039  * Function:    PHY_IQCalibrateBcut()
4040  *
4041  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
4042  *                      to improve RF EVM!!?
4043  *
4044  * Input:               IN      PADAPTER        pAdapter
4045  *
4046  * Output:              NONE
4047  *
4048  * Return:              NONE
4049  *
4050  * Revised History:
4051  *      When            Who             Remark
4052  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
4053  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
4054  *
4055  *---------------------------------------------------------------------------*/
4056 extern void PHY_IQCalibrateBcut(struct net_device* dev)
4057 {
4058         //struct r8192_priv     *priv = ieee80211_priv(dev);
4059         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
4060         u32                             i, reg;
4061         u32                             old_value;
4062         long                            X, Y, TX0[4];
4063         u32                             TXA[4];
4064         u32                             calibrate_set[13] = {0};
4065         u32                             load_value[13];
4066         u8                              RfPiEnable=0;
4067
4068         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
4069
4070         //
4071         // 1. Save e70~ee0 register setting, and load calibration setting
4072         //
4073         /*
4074         0xee0[31:0]=0x3fed92fb;
4075         0xedc[31:0] =0x3fed92fb;
4076         0xe70[31:0] =0x3fed92fb;
4077         0xe74[31:0] =0x3fed92fb;
4078         0xe78[31:0] =0x3fed92fb;
4079         0xe7c[31:0]= 0x3fed92fb;
4080         0xe80[31:0]= 0x3fed92fb;
4081         0xe84[31:0]= 0x3fed92fb;
4082         0xe88[31:0]= 0x3fed92fb;
4083         0xe8c[31:0]= 0x3fed92fb;
4084         0xed0[31:0]= 0x3fed92fb;
4085         0xed4[31:0]= 0x3fed92fb;
4086         0xed8[31:0]= 0x3fed92fb;
4087         */
4088         calibrate_set [0] = 0xee0;
4089         calibrate_set [1] = 0xedc;
4090         calibrate_set [2] = 0xe70;
4091         calibrate_set [3] = 0xe74;
4092         calibrate_set [4] = 0xe78;
4093         calibrate_set [5] = 0xe7c;
4094         calibrate_set [6] = 0xe80;
4095         calibrate_set [7] = 0xe84;
4096         calibrate_set [8] = 0xe88;
4097         calibrate_set [9] = 0xe8c;
4098         calibrate_set [10] = 0xed0;
4099         calibrate_set [11] = 0xed4;
4100         calibrate_set [12] = 0xed8;
4101         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
4102         for (i = 0; i < 13; i++)
4103         {
4104                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
4105                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
4106
4107         }
4108
4109         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
4110
4111         //
4112         // 2. QFN 68
4113         //
4114         // For 1T2R IQK only now !!!
4115         for (i = 0; i < 10; i++)
4116         {
4117                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
4118                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
4119                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4120                 {
4121                         //DbgPrint("IQK Switch to PI mode\n");
4122                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
4123                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
4124                 }
4125
4126                 // IQK
4127                 // 2. IQ calibration & LO leakage calibration
4128                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
4129                 udelay(5);
4130                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
4131                 udelay(5);
4132                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
4133                 udelay(5);
4134                 //path-A IQ K and LO K gain setting
4135                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
4136                 udelay(5);
4137                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
4138                 udelay(5);
4139                 //set LO calibration
4140                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
4141                 udelay(5);
4142                 //path-B IQ K and LO K gain setting
4143                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
4144                 udelay(5);
4145                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
4146                 udelay(5);
4147                 //K idac_I & IQ
4148                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4149                 udelay(5);
4150                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4151                 udelay(5);
4152
4153                 // delay 2ms
4154                 udelay(2000);
4155
4156                 //idac_Q setting
4157                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
4158                 udelay(5);
4159                 //K idac_Q & IQ
4160                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4161                 udelay(5);
4162                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4163
4164                 // delay 2ms
4165                 udelay(2000);
4166
4167                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
4168                 udelay(5);
4169                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
4170                 udelay(5);
4171                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
4172
4173                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4174                 {
4175                         //DbgPrint("IQK Switch back to SI mode\n");
4176                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
4177                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
4178                 }
4179
4180
4181                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
4182
4183                 // 3.   check fail bit, and fill BB IQ matrix
4184                 // Readback IQK value and rewrite
4185                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
4186                 {
4187                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
4188
4189                         // Calibrate init gain for A path for TX0
4190                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
4191                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
4192                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4193                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
4194                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4195                         udelay(5);
4196
4197                         // Calibrate init gain for C path for TX0
4198                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
4199                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4200                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4201                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
4202                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4203                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
4204                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4205                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
4206                         udelay(5);
4207
4208                         // Calibrate RX A and B for RX0
4209                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
4210                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
4211                         reg = (reg & 0xFFFFFC00) |X;
4212                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4213                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
4214                         reg = (reg & 0xFFFF03FF) |Y<<10;
4215                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4216                         udelay(5);
4217                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4218
4219                         // Calibrate init gain for A path for TX1 !!!!!!
4220                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4221                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4222                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4223                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4224                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4225                         udelay(5);
4226
4227                         // Calibrate init gain for C path for TX1
4228                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4229                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4230                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4231                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4232                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4233                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4234                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4235                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4236                         udelay(5);
4237
4238                         // Calibrate RX A and B for RX1
4239                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4240                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4241                         reg = (reg & 0xFFFFFC00) |X;
4242                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4243
4244                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4245                         reg = (reg & 0xFFFF03FF) |Y<<10;
4246                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4247                         udelay(5);
4248
4249                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4250                         break;
4251                 }
4252
4253         }
4254
4255         //
4256         // 4. Reload e70~ee0 register setting.
4257         //
4258         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
4259         for (i = 0; i < 13; i++)
4260                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
4261
4262
4263         //
4264         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4265         //
4266
4267
4268
4269 }       // PHY_IQCalibrateBcut
4270
4271
4272 //
4273 // Move from phycfg.c to gen.c to be code independent later
4274 //
4275 //-------------------------Move to other DIR later----------------------------*/
4276 //#if (DEV_BUS_TYPE == USB_INTERFACE)
4277 #ifdef RTL8192SU
4278
4279 //    use in phy only (in win it's timer)
4280 void SwChnlCallback8192SUsb(struct net_device *dev)
4281 {
4282
4283         struct r8192_priv *priv = ieee80211_priv(dev);
4284         u32                     delay;
4285 //      bool                    ret;
4286
4287         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
4288                                 %d\n", priv->chan);
4289
4290
4291         if(!priv->up)
4292                 return;
4293
4294         if(priv->rf_chip == RF_PSEUDO_11N)
4295         {
4296                 priv->SwChnlInProgress=FALSE;
4297                 return;                                                                 //return immediately if it is peudo-phy
4298         }
4299
4300         do{
4301                 if(!priv->SwChnlInProgress)
4302                         break;
4303
4304                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
4305                 {
4306                         if(delay>0)
4307                         {
4308                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
4309
4310                         }
4311                         else
4312                         continue;
4313                 }
4314                 else
4315                 {
4316                         priv->SwChnlInProgress=FALSE;
4317                 }
4318                 break;
4319         }while(TRUE);
4320 }
4321
4322
4323 //
4324 // Callback routine of the work item for switch channel.
4325 //
4326 //    use in phy only (in win it's work)
4327 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
4328 {
4329         struct r8192_priv *priv = ieee80211_priv(dev);
4330
4331         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
4332 #ifdef TO_DO_LIST
4333         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
4334         {
4335                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
4336
4337                 pHalData->SwChnlInProgress = FALSE;
4338                 return;
4339         }
4340 #endif
4341         phy_FinishSwChnlNow(dev, priv->chan);
4342         priv->SwChnlInProgress = FALSE;
4343
4344         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
4345 }
4346
4347
4348 /*-----------------------------------------------------------------------------
4349  * Function:    SetBWModeCallback8192SUsb()
4350  *
4351  * Overview:    Timer callback function for SetSetBWMode
4352  *
4353  * Input:               PRT_TIMER               pTimer
4354  *
4355  * Output:      NONE
4356  *
4357  * Return:      NONE
4358  *
4359  * Note:                (1) We do not take j mode into consideration now
4360  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
4361  *                           concurrently?
4362  *---------------------------------------------------------------------------*/
4363 //====>//rtl8192_SetBWMode
4364 //    use in phy only (in win it's timer)
4365 void SetBWModeCallback8192SUsb(struct net_device *dev)
4366 {
4367         struct r8192_priv *priv = ieee80211_priv(dev);
4368         u8                              regBwOpMode;
4369
4370         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4371         //u32                           NowL, NowH;
4372         //u8Byte                                BeginTime, EndTime;
4373         u8                              regRRSR_RSC;
4374
4375         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
4376                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4377
4378         if(priv->rf_chip == RF_PSEUDO_11N)
4379         {
4380                 priv->SetBWModeInProgress= FALSE;
4381                 return;
4382         }
4383
4384         if(!priv->up)
4385                 return;
4386
4387         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4388         //NowL = read_nic_dword(dev, TSFR);
4389         //NowH = read_nic_dword(dev, TSFR+4);
4390         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4391
4392         //3<1>Set MAC register
4393         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4394         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4395
4396         switch(priv->CurrentChannelBW)
4397         {
4398                 case HT_CHANNEL_WIDTH_20:
4399                         regBwOpMode |= BW_OPMODE_20MHZ;
4400                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4401                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4402                         break;
4403
4404                 case HT_CHANNEL_WIDTH_20_40:
4405                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4406                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4407                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4408
4409                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4410                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4411                         break;
4412
4413                 default:
4414                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
4415                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4416                         break;
4417         }
4418
4419         //3 <2>Set PHY related register
4420         switch(priv->CurrentChannelBW)
4421         {
4422                 case HT_CHANNEL_WIDTH_20:
4423                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4424                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4425                         #if 0 //LZM090219
4426                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4427
4428                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4429                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
4430                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
4431                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
4432                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4433                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4434                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4435                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4436                         #endif
4437
4438                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4439                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4440
4441                         break;
4442                 case HT_CHANNEL_WIDTH_20_40:
4443                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4444                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4445                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4446                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4447
4448                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4449                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4450                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4451                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4452                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4453
4454                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4455                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4456
4457                         break;
4458                 default:
4459                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
4460                                                 ,priv->CurrentChannelBW);
4461                         break;
4462
4463         }
4464         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4465
4466         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4467         //NowL = read_nic_dword(dev, TSFR);
4468         //NowH = read_nic_dword(dev, TSFR+4);
4469         //EndTime = ((u8Byte)NowH << 32) + NowL;
4470         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
4471
4472 #if 1
4473         //3<3>Set RF related register
4474         switch( priv->rf_chip )
4475         {
4476                 case RF_8225:
4477                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4478                         break;
4479
4480                 case RF_8256:
4481                         // Please implement this function in Hal8190PciPhy8256.c
4482                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4483                         break;
4484
4485                 case RF_6052:
4486                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4487                         break;
4488
4489                 case RF_8258:
4490                         // Please implement this function in Hal8190PciPhy8258.c
4491                         // PHY_SetRF8258Bandwidth();
4492                         break;
4493
4494                 case RF_PSEUDO_11N:
4495                         // Do Nothing
4496                         break;
4497
4498                 default:
4499                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4500                         break;
4501         }
4502 #endif
4503         priv->SetBWModeInProgress= FALSE;
4504
4505         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
4506 }
4507
4508 //
4509 // Callback routine of the work item for set bandwidth mode.
4510 //
4511 //    use in phy only (in win it's work)
4512 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
4513 {
4514         struct r8192_priv               *priv = ieee80211_priv(dev);
4515         u8                              regBwOpMode;
4516
4517         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4518         //u32                           NowL, NowH;
4519         //u8Byte                                BeginTime, EndTime;
4520         u8                      regRRSR_RSC;
4521
4522         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
4523                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4524
4525         if(priv->rf_chip == RF_PSEUDO_11N)
4526         {
4527                 priv->SetBWModeInProgress= FALSE;
4528                 return;
4529         }
4530
4531         if(!priv->up)
4532                 return;
4533
4534         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4535         //NowL = read_nic_dword(dev, TSFR);
4536         //NowH = read_nic_dword(dev, TSFR+4);
4537         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4538
4539         //3<1>Set MAC register
4540         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4541         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4542
4543         switch(priv->CurrentChannelBW)
4544         {
4545                 case HT_CHANNEL_WIDTH_20:
4546                         regBwOpMode |= BW_OPMODE_20MHZ;
4547                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4548                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4549                         break;
4550
4551                 case HT_CHANNEL_WIDTH_20_40:
4552                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4553                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4554                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4555                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4556                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4557
4558                         break;
4559
4560                 default:
4561                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
4562                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4563                         break;
4564         }
4565
4566         //3 <2>Set PHY related register
4567         switch(priv->CurrentChannelBW)
4568         {
4569                 case HT_CHANNEL_WIDTH_20:
4570                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4571                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4572
4573                         #if 0 //LZM 090219
4574                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
4575
4576                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4577                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4578                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4579                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4580                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
4581                         #endif
4582
4583                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4584
4585                         break;
4586                 case HT_CHANNEL_WIDTH_20_40:
4587                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4588                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4589                         #if 0 //LZM 090219
4590                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4591
4592                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4593
4594                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4595                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4596                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4597                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4598                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4599                         #endif
4600
4601                         // Set Control channel to upper or lower. These settings are required only for 40MHz
4602                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4603                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4604
4605                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4606
4607                         break;
4608
4609
4610                 default:
4611                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
4612                                                 ,priv->CurrentChannelBW);
4613                         break;
4614
4615         }
4616         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4617
4618         //3<3>Set RF related register
4619         switch( priv->rf_chip )
4620         {
4621                 case RF_8225:
4622                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4623                         break;
4624
4625                 case RF_8256:
4626                         // Please implement this function in Hal8190PciPhy8256.c
4627                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4628                         break;
4629
4630                 case RF_6052:
4631                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4632                         break;
4633
4634                 case RF_8258:
4635                         // Please implement this function in Hal8190PciPhy8258.c
4636                         // PHY_SetRF8258Bandwidth();
4637                         break;
4638
4639                 case RF_PSEUDO_11N:
4640                         // Do Nothing
4641                         break;
4642
4643                 default:
4644                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4645                         break;
4646         }
4647
4648         priv->SetBWModeInProgress= FALSE;
4649
4650         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
4651 }
4652
4653 //--------------------------Move to oter DIR later-------------------------------*/
4654 #ifdef RTL8192SU
4655 void InitialGain8192S(struct net_device *dev,   u8 Operation)
4656 {
4657 #ifdef TO_DO_LIST
4658         struct r8192_priv *priv = ieee80211_priv(dev);
4659 #endif
4660
4661 }
4662 #endif
4663
4664 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
4665 {
4666         struct r8192_priv *priv = ieee80211_priv(dev);
4667
4668         priv->InitialGainOperateType = Operation;
4669
4670         if(priv->up)
4671         {
4672                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
4673         }
4674 }
4675
4676 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
4677 {
4678         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4679        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
4680        struct net_device *dev = priv->ieee80211->dev;
4681 #define SCAN_RX_INITIAL_GAIN    0x17
4682 #define POWER_DETECTION_TH      0x08
4683         u32     BitMask;
4684         u8      initial_gain;
4685         u8      Operation;
4686
4687         Operation = priv->InitialGainOperateType;
4688
4689         switch(Operation)
4690         {
4691                 case IG_Backup:
4692                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
4693                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
4694                         BitMask = bMaskByte0;
4695                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4696                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4697                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
4698                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
4699                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
4700                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
4701                         BitMask  = bMaskByte2;
4702                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
4703
4704                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4705                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4706                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4707                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4708                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
4709
4710                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
4711                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
4712                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
4713                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
4714                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
4715                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
4716                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
4717                         break;
4718                 case IG_Restore:
4719                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
4720                         BitMask = 0x7f; //Bit0~ Bit6
4721                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4722                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4723
4724                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
4725                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
4726                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
4727                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
4728                         BitMask  = bMaskByte2;
4729                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
4730
4731                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4732                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4733                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4734                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4735                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
4736
4737                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
4738
4739                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4740                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
4741                         break;
4742                 default:
4743                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
4744                         break;
4745         }
4746 }
4747
4748 #endif  // #if (DEV_BUS_TYPE == USB_INTERFACE)
4749
4750 //-----------------------------------------------------------------------------
4751 //      Description:
4752 //              Schedule workitem to send specific CMD IO to FW.
4753 //      Added by Roger, 2008.12.03.
4754 //
4755 //-----------------------------------------------------------------------------
4756 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
4757 {
4758         struct r8192_priv *priv = ieee80211_priv(dev);
4759         u16     FwCmdWaitCounter = 0;
4760
4761         u16     FwCmdWaitLimit = 1000;
4762
4763         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
4764         if(priv->bInHctTest)
4765                 return true;
4766
4767         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
4768
4769         // Will be done by high power respectively.
4770         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
4771         {
4772                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
4773                 return false;
4774         }
4775
4776 #if 1
4777         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
4778         {
4779                 //if(RT_USB_CANNOT_IO(Adapter))
4780                 //{
4781                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
4782                 //      return FALSE;
4783                 //}
4784
4785                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
4786                 return false;
4787                 FwCmdWaitCounter ++;
4788                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
4789                 udelay(100);
4790         }
4791
4792         if(FwCmdWaitCounter == FwCmdWaitLimit)
4793         {
4794                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
4795                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
4796                 //return false;
4797         }
4798 #endif
4799         if (priv->SetFwCmdInProgress)
4800         {
4801                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
4802                 return false;
4803         }
4804         priv->SetFwCmdInProgress = TRUE;
4805         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
4806
4807         phy_SetFwCmdIOCallback(dev);
4808         return true;
4809 }
4810 void ChkFwCmdIoDone(struct net_device* dev)
4811 {
4812         u16 PollingCnt = 1000;
4813         u32 tmpValue;
4814
4815         do
4816         {// Make sure that CMD IO has be accepted by FW.
4817 #ifdef TO_DO_LIST
4818                 if(RT_USB_CANNOT_IO(Adapter))
4819                 {
4820                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
4821                         return;
4822                 }
4823 #endif
4824                 udelay(10); // sleep 20us
4825                 tmpValue = read_nic_dword(dev, WFM5);
4826                 if(tmpValue == 0)
4827                 {
4828                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
4829                         break;
4830                 }
4831                 else
4832                 {
4833                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
4834                 }
4835         }while( --PollingCnt );
4836
4837         if(PollingCnt == 0)
4838         {
4839                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
4840         }
4841 }
4842 //      Callback routine of the timer callback for FW Cmd IO.
4843 //
4844 //      Description:
4845 //              This routine will send specific CMD IO to FW and check whether it is done.
4846 //
4847 void phy_SetFwCmdIOCallback(struct net_device* dev)
4848 {
4849         //struct net_device* dev = (struct net_device*) data;
4850         u32             input;
4851         static u32 ScanRegister;
4852         struct r8192_priv *priv = ieee80211_priv(dev);
4853         if(!priv->up)
4854         {
4855                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
4856                 return;
4857         }
4858
4859         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
4860
4861         switch(priv->CurrentFwCmdIO)
4862         {
4863                 case FW_CMD_HIGH_PWR_ENABLE:
4864                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4865                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
4866                         break;
4867
4868                 case FW_CMD_HIGH_PWR_DISABLE:
4869                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
4870                         break;
4871
4872                 case FW_CMD_DIG_RESUME:
4873                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4874                         break;
4875
4876                 case FW_CMD_DIG_HALT:
4877                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4878                         break;
4879
4880                 //
4881                 // <Roger_Notes> The following FW CMD IO was combined into single operation
4882                 // (i.e., to prevent number of system workitem out of resource!!).
4883                 // 2008.12.04.
4884                 //
4885                 case FW_CMD_RESUME_DM_BY_SCAN:
4886                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
4887                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4888                         {
4889                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
4890                                 ChkFwCmdIoDone(dev);
4891                         }
4892                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4893                         break;
4894
4895                 case FW_CMD_PAUSE_DM_BY_SCAN:
4896                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
4897                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4898                         ChkFwCmdIoDone(dev);
4899                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4900                         break;
4901
4902                 //
4903                 // <Roger_Notes> The following FW CMD IO should be checked
4904                 // (i.e., workitem schedule timing issue!!).
4905                 // 2008.12.04.
4906                 //
4907                 case FW_CMD_DIG_DISABLE:
4908                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4909                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4910                         break;
4911
4912                 case FW_CMD_DIG_ENABLE:
4913                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4914                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4915                         break;
4916
4917                 case FW_CMD_RA_RESET:
4918                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4919                         break;
4920
4921                 case FW_CMD_RA_ACTIVE:
4922                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4923                         break;
4924
4925                 case FW_CMD_RA_REFRESH_N:
4926                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4927                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4928                                 input = FW_RA_REFRESH;
4929                         else
4930                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4931                         write_nic_dword(dev, WFM5, input);
4932                         break;
4933                 case FW_CMD_RA_REFRESH_BG:
4934                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4935                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4936                         ChkFwCmdIoDone(dev);
4937                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4938                         break;
4939
4940                 case FW_CMD_IQK_ENABLE:
4941                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4942                         break;
4943
4944                 case FW_CMD_TXPWR_TRACK_ENABLE:
4945                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4946                         break;
4947
4948                 case FW_CMD_TXPWR_TRACK_DISABLE:
4949                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4950                         break;
4951
4952                 default:
4953                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4954                         break;
4955         }
4956
4957         ChkFwCmdIoDone(dev);
4958
4959         switch(priv->CurrentFwCmdIO)
4960         {
4961                 case FW_CMD_HIGH_PWR_DISABLE:
4962                         //if(pMgntInfo->bTurboScan)
4963                         {
4964                                 //Lower initial gain
4965                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4966                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4967                                 // CCA threshold
4968                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4969                                 // Disable OFDM Part
4970                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4971                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4972                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4973                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4974                         }
4975                         break;
4976
4977                 case FW_CMD_HIGH_PWR_ENABLE:
4978                         //if(pMgntInfo->bTurboScan)
4979                         {
4980                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4981                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4982
4983                                 // CCA threshold
4984                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4985                                 // Enable OFDM Part
4986                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4987
4988                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4989                                 if(ScanRegister != 0){
4990                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4991                                 }
4992
4993                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4994                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4995                                 else
4996                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4997                         }
4998                         break;
4999         }
5000
5001         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
5002         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
5003
5004 }
5005