SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_phy.c

   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #ifdef RTL8192SU
  39 #include "r8192S_hw.h"
  40 #include "r8192S_phy.h"
  41 #include "r8192S_phyreg.h"
  42 #include "r8192SU_HWImg.h"
  43 //#include "r8192S_FwImgDTM.h"
  44 #else
  45 #include "r8192U_hw.h"
  46 #include "r819xU_phy.h"
  47 #include "r819xU_phyreg.h"
  48 #endif
  49
  50 #include "ieee80211/dot11d.h"
  51
  52 /*---------------------------Define Local Constant---------------------------*/
  53 /* Channel switch:The size of command tables for switch channel*/
  54 #define MAX_PRECMD_CNT 16
  55 #define MAX_RFDEPENDCMD_CNT 16
  56 #define MAX_POSTCMD_CNT 16
  57 #define MAX_DOZE_WAITING_TIMES_9x 64
  58
  59 /*------------------------Define local variable------------------------------*/
  60 // 2004-05-11
  61 #ifndef RTL8192SU
  62 static u32      RF_CHANNEL_TABLE_ZEBRA[]={
  63                 0,
  64                 0x085c,//2412 1
  65                 0x08dc,//2417 2
  66                 0x095c,//2422 3
  67                 0x09dc,//2427 4
  68                 0x0a5c,//2432 5
  69                 0x0adc,//2437 6
  70                 0x0b5c,//2442 7
  71                 0x0bdc,//2447 8
  72                 0x0c5c,//2452 9
  73                 0x0cdc,//2457 10
  74                 0x0d5c,//2462 11
  75                 0x0ddc,//2467 12
  76                 0x0e5c,//2472 13
  77                 //0x0f5c,//2484
  78                 0x0f72,//2484  //20040810
  79 };
  80 #endif
  81
  82 static  u32
  83 phy_CalculateBitShift(u32 BitMask);
  84 static  RT_STATUS
  85 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  86 static void
  87 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  88 static  RT_STATUS
  89 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  90 static  RT_STATUS
  91 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  92 static bool
  93 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  94 void
  95 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  96 void
  97 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  98 void
  99 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
 100 static void
 101 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
 102 static bool
 103 phy_SwChnlStepByStep(
 104         struct net_device* dev,
 105         u8              channel,
 106         u8              *stage,
 107         u8              *step,
 108         u32             *delay
 109         );
 110 static RT_STATUS
 111 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
 112 #ifdef RTL8192SE
 113 static  u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
 114 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
 115 static  void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 116 static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 117 #endif
 118 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
 119 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
 120 void phy_SetFwCmdIOCallback(struct net_device* dev);
 121
 122 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 123 #ifdef RTL8192SU
 124 //
 125 // Description:
 126 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
 127 //
 128 // Assumption:
 129 //              -       Only use on RTL8192S USB interface.
 130 //              -       PASSIVE LEVEL
 131 //
 132 // Created by Roger, 2008.09.06.
 133 //
 134 //use in phy only
 135 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 136 {
 137         struct r8192_priv *priv = ieee80211_priv(dev);
 138         u32     ReturnValue = 0xffffffff;
 139         u8      PollingCnt = 50;
 140         u8      BBWaitCounter = 0;
 141
 142
 143         //
 144         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 145         // We have to make sure that previous BB I/O has been done.
 146         // 2008.08.20.
 147         //
 148         while(priv->bChangeBBInProgress)
 149         {
 150                 BBWaitCounter ++;
 151                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 152                 msleep(1); // 1 ms
 153
 154                 // Wait too long, return FALSE to avoid to be stuck here.
 155                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 156                 {
 157                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 158                         return ReturnValue;
 159                 }
 160         }
 161
 162         priv->bChangeBBInProgress = true;
 163
 164         read_nic_dword(dev, RegAddr);
 165
 166         do
 167         {// Make sure that access could be done.
 168                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 169                         break;
 170         }while( --PollingCnt );
 171
 172         if(PollingCnt == 0)
 173         {
 174                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 175         }
 176         else
 177         {
 178                 // Data FW read back.
 179                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 180                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 181         }
 182
 183         priv->bChangeBBInProgress = false;
 184
 185         return ReturnValue;
 186 }
 187
 188
 189
 190 //
 191 // Description:
 192 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 193 //
 194 // Assumption:
 195 //              -       Only use on RTL8192S USB interface.
 196 //              -       PASSIVE LEVEL
 197 //
 198 // Created by Roger, 2008.09.06.
 199 //
 200 //use in phy only
 201 void
 202 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 203 {
 204         struct r8192_priv *priv = ieee80211_priv(dev);
 205         u8      BBWaitCounter = 0;
 206
 207         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 208
 209         //
 210         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 211         // We have to make sure that previous BB I/O has been done.
 212         // 2008.08.20.
 213         //
 214         while(priv->bChangeBBInProgress)
 215         {
 216                 BBWaitCounter ++;
 217                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 218                 msleep(1); // 1 ms
 219
 220                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 221                 {
 222                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 223                         return;
 224                 }
 225         }
 226
 227         priv->bChangeBBInProgress = true;
 228         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 229         write_nic_dword(dev, RegAddr, Data);
 230
 231         priv->bChangeBBInProgress = false;
 232 }
 233
 234
 235
 236 //
 237 // Description:
 238 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 239 //
 240 // Assumption:
 241 //              -       Only use on RTL8192S USB interface.
 242 //              -       PASSIVE LEVEL
 243 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 244 //
 245 // Created by Roger, 2008.09.06.
 246 //
 247 //use in phy only
 248 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 249 {
 250
 251         struct r8192_priv *priv = ieee80211_priv(dev);
 252         //u32   value  = 0, ReturnValue = 0;
 253         u32     ReturnValue = 0;
 254         //u32   tmplong,tmplong2;
 255         u8      PollingCnt = 50;
 256         u8      RFWaitCounter = 0;
 257
 258
 259         //
 260         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 261         // We have to make sure that previous RF I/O has been done.
 262         // 2008.08.20.
 263         //
 264         while(priv->bChangeRFInProgress)
 265         {
 266                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 267                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 268                 down(&priv->rf_sem);
 269
 270                 RFWaitCounter ++;
 271                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 272                 msleep(1); // 1 ms
 273
 274                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 275                 {
 276                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 277                         return 0xffffffff;
 278                 }
 279                 else
 280                 {
 281                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 282                 }
 283         }
 284
 285         priv->bChangeRFInProgress = true;
 286         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 287
 288
 289         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 290
 291         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 292                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 293                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 294
 295         do
 296         {// Make sure that access could be done.
 297                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 298                         break;
 299         }while( --PollingCnt );
 300
 301         // Data FW read back.
 302         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 303
 304         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 305         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 306         up(&priv->rf_sem);
 307         priv->bChangeRFInProgress = false;
 308
 309         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 310
 311         return ReturnValue;
 312
 313 }
 314
 315
 316 //
 317 // Description:
 318 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 319 //
 320 // Assumption:
 321 //              -       Only use on RTL8192S USB interface.
 322 //              -       PASSIVE LEVEL
 323 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 324 //
 325 // Created by Roger, 2008.09.06.
 326 //
 327 //use in phy only
 328 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 329 {
 330
 331         struct r8192_priv *priv = ieee80211_priv(dev);
 332         u8      PollingCnt = 50;
 333         u8      RFWaitCounter = 0;
 334
 335
 336         //
 337         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 338         // We have to make sure that previous BB I/O has been done.
 339         // 2008.08.20.
 340         //
 341         while(priv->bChangeRFInProgress)
 342         {
 343                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 344                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 345                 down(&priv->rf_sem);
 346
 347                 RFWaitCounter ++;
 348                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 349                 msleep(1); // 1 ms
 350
 351                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 352                 {
 353                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 354                         return;
 355                 }
 356                 else
 357                 {
 358                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 359                 }
 360         }
 361
 362         priv->bChangeRFInProgress = true;
 363         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 364
 365
 366         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 367
 368         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 369         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 370                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 371                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 372
 373         do
 374         {// Make sure that access could be done.
 375                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 376                                 break;
 377         }while( --PollingCnt );
 378
 379         if(PollingCnt == 0)
 380         {
 381                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 382         }
 383
 384         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 385         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 386         up(&priv->rf_sem);
 387         priv->bChangeRFInProgress = false;
 388
 389 }
 390
 391 #endif
 392
 393 /*---------------------Define local function prototype-----------------------*/
 394
 395
 396 /*----------------------------Function Body----------------------------------*/
 397 //
 398 // 1. BB register R/W API
 399 //
 400 /**
 401 * Function:     PHY_QueryBBReg
 402 *
 403 * OverView:     Read "sepcific bits" from BB register
 404 *
 405 * Input:
 406 *                       PADAPTER                Adapter,
 407 *                       u32                     RegAddr,                //The target address to be readback
 408 *                       u32                     BitMask         //The target bit position in the target address
 409 *                                                                               //to be readback
 410 * Output:       None
 411 * Return:               u32                     Data                    //The readback register value
 412 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 413 */
 414 //use phy dm core 8225 8256 6052
 415 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 416 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 417 {
 418
 419         u32     ReturnValue = 0, OriginalValue, BitShift;
 420
 421
 422         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 423
 424         //
 425         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 426         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 427         // infinite cycle.
 428         // 2008.09.06.
 429         //
 430 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 431 #ifdef RTL8192SU
 432         if(IS_BB_REG_OFFSET_92S(RegAddr))
 433         {
 434                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 435
 436                 if((RegAddr & 0x03) != 0)
 437                 {
 438                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 439                         return 0;
 440                 }
 441
 442         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 443         }
 444         else
 445 #endif
 446         {
 447         OriginalValue = read_nic_dword(dev, RegAddr);
 448         }
 449
 450         BitShift = phy_CalculateBitShift(BitMask);
 451         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 452
 453         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 454         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 455         return (ReturnValue);
 456 }
 457
 458 /**
 459 * Function:     PHY_SetBBReg
 460 *
 461 * OverView:     Write "Specific bits" to BB register (page 8~)
 462 *
 463 * Input:
 464 *                       PADAPTER                Adapter,
 465 *                       u32                     RegAddr,                //The target address to be modified
 466 *                       u32                     BitMask         //The target bit position in the target address
 467 *                                                                               //to be modified
 468 *                       u32                     Data                    //The new register value in the target bit position
 469 *                                                                               //of the target address
 470 *
 471 * Output:       None
 472 * Return:               None
 473 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 474 */
 475 //use phy dm core 8225 8256
 476 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 477 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 478 {
 479         u32     OriginalValue, BitShift, NewValue;
 480
 481
 482         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 483
 484         //
 485         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 486         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 487         // infinite cycle.
 488         // 2008.09.06.
 489         //
 490 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 491 #ifdef RTL8192SU
 492         if(IS_BB_REG_OFFSET_92S(RegAddr))
 493         {
 494                 if((RegAddr & 0x03) != 0)
 495                 {
 496                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 497                         return;
 498                 }
 499
 500                 if(BitMask!= bMaskDWord)
 501                 {//if not "double word" write
 502                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 503                         BitShift = phy_CalculateBitShift(BitMask);
 504             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 505                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 506                 }else
 507                         phy_SetUsbBBReg(dev, RegAddr, Data);
 508         }
 509         else
 510 #endif
 511         {
 512                 if(BitMask!= bMaskDWord)
 513                 {//if not "double word" write
 514                         OriginalValue = read_nic_dword(dev, RegAddr);
 515                         BitShift = phy_CalculateBitShift(BitMask);
 516                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 517                         write_nic_dword(dev, RegAddr, NewValue);
 518                 }else
 519                         write_nic_dword(dev, RegAddr, Data);
 520         }
 521
 522         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 523
 524         return;
 525 }
 526
 527
 528 //
 529 // 2. RF register R/W API
 530 //
 531 /**
 532 * Function:     PHY_QueryRFReg
 533 *
 534 * OverView:     Query "Specific bits" to RF register (page 8~)
 535 *
 536 * Input:
 537 *                       PADAPTER                Adapter,
 538 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 539 *                       u32                     RegAddr,                //The target address to be read
 540 *                       u32                     BitMask         //The target bit position in the target address
 541 *                                                                               //to be read
 542 *
 543 * Output:       None
 544 * Return:               u32                     Readback value
 545 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 546 */
 547 //in dm 8256 and phy
 548 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 549 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 550 {
 551         u32 Original_Value, Readback_Value, BitShift;//, flags;
 552         struct r8192_priv *priv = ieee80211_priv(dev);
 553
 554
 555         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 556
 557         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 558         {
 559                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 560                 return 0;
 561         }
 562
 563         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 564         {
 565                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 566                 return 0;
 567         }
 568
 569         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 570         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 571         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 572         down(&priv->rf_sem);
 573         //
 574         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 575         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 576         // infinite cycle.
 577         // 2008.09.06.
 578         //
 579 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 580 #ifdef RTL8192SU
 581         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 582         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 583 #else
 584         if (priv->Rf_Mode == RF_OP_By_FW)
 585         {
 586                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 587         }
 588         else
 589         {
 590                 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 591         }
 592 #endif
 593
 594         BitShift =  phy_CalculateBitShift(BitMask);
 595         Readback_Value = (Original_Value & BitMask) >> BitShift;
 596         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 597         up(&priv->rf_sem);
 598         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 599
 600         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 601
 602         return (Readback_Value);
 603 }
 604
 605 /**
 606 * Function:     PHY_SetRFReg
 607 *
 608 * OverView:     Write "Specific bits" to RF register (page 8~)
 609 *
 610 * Input:
 611 *                       PADAPTER                Adapter,
 612 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 613 *                       u32                     RegAddr,                //The target address to be modified
 614 *                       u32                     BitMask         //The target bit position in the target address
 615 *                                                                               //to be modified
 616 *                       u32                     Data                    //The new register Data in the target bit position
 617 *                                                                               //of the target address
 618 *
 619 * Output:       None
 620 * Return:               None
 621 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 622 */
 623 //use phy  8225 8256
 624 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 625 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 626 {
 627
 628         struct r8192_priv *priv = ieee80211_priv(dev);
 629         u32 Original_Value, BitShift, New_Value;//, flags;
 630
 631         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 632                 RegAddr, BitMask, Data, eRFPath);
 633
 634         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 635         {
 636                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 637                 return ;
 638         }
 639         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 640         {
 641                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 642                 return;
 643         }
 644
 645         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 646         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 647         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 648         down(&priv->rf_sem);
 649         //
 650         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 651         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 652         // infinite cycle.
 653         // 2008.09.06.
 654         //
 655 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 656 #ifdef RTL8192SU
 657                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 658
 659                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 660                 {
 661                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 662                         BitShift =  phy_CalculateBitShift(BitMask);
 663                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 664                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 665                 }
 666                 else
 667                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 668 #else
 669         if (priv->Rf_Mode == RF_OP_By_FW)
 670         {
 671                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 672                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 673                 {
 674                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 675                         BitShift =  phy_CalculateBitShift(BitMask);
 676                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 677
 678                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 679                 }
 680                 else
 681                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 682         }
 683         else
 684         {
 685                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 686                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 687                 {
 688                         Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 689                         BitShift =  phy_CalculateBitShift(BitMask);
 690                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 691
 692                         phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 693                 }
 694                 else
 695                         phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 696
 697         }
 698 #endif
 699         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 700         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 701         up(&priv->rf_sem);
 702         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 703         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 704                         RegAddr, BitMask, Data, eRFPath);
 705
 706 }
 707
 708 #ifdef RTL8192SE
 709 /*-----------------------------------------------------------------------------
 710  * Function:    phy_FwRFSerialRead()
 711  *
 712  * Overview:    We support firmware to execute RF-R/W.
 713  *
 714  * Input:               NONE
 715  *
 716  * Output:              NONE
 717  *
 718  * Return:              NONE
 719  *
 720  * Revised History:
 721  *      When            Who             Remark
 722  *      01/21/2008      MHC             Create Version 0.
 723  *
 724  *---------------------------------------------------------------------------*/
 725 //use in phy only
 726 static  u32
 727 phy_FwRFSerialRead(
 728         struct net_device* dev,
 729         RF90_RADIO_PATH_E       eRFPath,
 730         u32                             Offset  )
 731 {
 732         u32             retValue = 0;
 733         //u32           Data = 0;
 734         //u8            time = 0;
 735 #if 0
 736         //DbgPrint("FW RF CTRL\n\r");
 737         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 738            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 739            much time. This is only for site survey. */
 740         // 1. Read operation need not insert data. bit 0-11
 741         //Data &= bMask12Bits;
 742         // 2. Write RF register address. Bit 12-19
 743         Data |= ((Offset&0xFF)<<12);
 744         // 3. Write RF path.  bit 20-21
 745         Data |= ((eRFPath&0x3)<<20);
 746         // 4. Set RF read indicator. bit 22=0
 747         //Data |= 0x00000;
 748         // 5. Trigger Fw to operate the command. bit 31
 749         Data |= 0x80000000;
 750         // 6. We can not execute read operation if bit 31 is 1.
 751         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 752         {
 753                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 754                 if (time++ < 100)
 755                 {
 756                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
 757                         delay_us(10);
 758                 }
 759                 else
 760                         break;
 761         }
 762         // 7. Execute read operation.
 763         PlatformIOWrite4Byte(dev, QPNR, Data);
 764         // 8. Check if firmawre send back RF content.
 765         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 766         {
 767                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 768                 if (time++ < 100)
 769                 {
 770                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 771                         delay_us(10);
 772                 }
 773                 else
 774                         return  (0);
 775         }
 776         retValue = PlatformIORead4Byte(dev, RF_DATA);
 777 #endif
 778         return  (retValue);
 779
 780 }       /* phy_FwRFSerialRead */
 781
 782 /*-----------------------------------------------------------------------------
 783  * Function:    phy_FwRFSerialWrite()
 784  *
 785  * Overview:    We support firmware to execute RF-R/W.
 786  *
 787  * Input:               NONE
 788  *
 789  * Output:              NONE
 790  *
 791  * Return:              NONE
 792  *
 793  * Revised History:
 794  *      When            Who             Remark
 795  *      01/21/2008      MHC             Create Version 0.
 796  *
 797  *---------------------------------------------------------------------------*/
 798 //use in phy only
 799 static  void
 800 phy_FwRFSerialWrite(
 801         struct net_device* dev,
 802         RF90_RADIO_PATH_E       eRFPath,
 803         u32                             Offset,
 804         u32                             Data    )
 805 {
 806 #if 0
 807         u8      time = 0;
 808         DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
 809         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 810            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 811            much time. This is only for site survey. */
 812
 813         // 1. Set driver write bit and 12 bit data. bit 0-11
 814         //Data &= bMask12Bits;  // Done by uper layer.
 815         // 2. Write RF register address. bit 12-19
 816         Data |= ((Offset&0xFF)<<12);
 817         // 3. Write RF path.  bit 20-21
 818         Data |= ((eRFPath&0x3)<<20);
 819         // 4. Set RF write indicator. bit 22=1
 820         Data |= 0x400000;
 821         // 5. Trigger Fw to operate the command. bit 31=1
 822         Data |= 0x80000000;
 823
 824         // 6. Write operation. We can not write if bit 31 is 1.
 825         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 826         {
 827                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 828                 if (time++ < 100)
 829                 {
 830                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 831                         delay_us(10);
 832                 }
 833                 else
 834                         break;
 835         }
 836         // 7. No matter check bit. We always force the write. Because FW will
 837         //    not accept the command.
 838         PlatformIOWrite4Byte(dev, QPNR, Data);
 839         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 840            to finish RF write operation. */
 841         /* 2008/01/17 MH We support delay in firmware side now. */
 842         //delay_us(20);
 843 #endif
 844 }       /* phy_FwRFSerialWrite */
 845
 846 /**
 847 * Function:     phy_RFSerialRead
 848 *
 849 * OverView:     Read regster from RF chips
 850 *
 851 * Input:
 852 *                       PADAPTER                Adapter,
 853 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 854 *                       u32                     Offset,         //The target address to be read
 855 *
 856 * Output:       None
 857 * Return:               u32                     reback value
 858 * Note:         Threre are three types of serial operations:
 859 *                       1. Software serial write
 860 *                       2. Hardware LSSI-Low Speed Serial Interface
 861 *                       3. Hardware HSSI-High speed
 862 *                       serial write. Driver need to implement (1) and (2).
 863 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 864 */
 865 //use in phy only
 866 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
 867 {
 868
 869         u32                                             retValue = 0;
 870         struct r8192_priv *priv = ieee80211_priv(dev);
 871         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 872         u32                                             NewOffset;
 873         u8                                              RfPiEnable=0;
 874
 875
 876         //
 877         // Make sure RF register offset is correct
 878         //
 879         Offset &= 0x3f;
 880
 881         //
 882         // Switch page for 8256 RF IC
 883         //
 884         if(     priv->rf_chip == RF_8256 ||
 885                 priv->rf_chip == RF_8225 ||
 886                 priv->rf_chip == RF_6052)
 887         {
 888                 //analog to digital off, for protection
 889                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
 890
 891                 if(Offset>=31)
 892                 {
 893                         priv->RFReadPageCnt[2]++;//cosa add for debug
 894                         priv->RfReg0Value[eRFPath] |= 0x140;
 895
 896                         // Switch to Reg_Mode2 for Reg31~45
 897                         rtl8192_setBBreg(dev,
 898                                 pPhyReg->rf3wireOffset,
 899                                 bMaskDWord,
 900                                 (priv->RfReg0Value[eRFPath] << 16)      );
 901
 902                         // Modified Offset
 903                         NewOffset = Offset - 30;
 904
 905                 }else if(Offset>=16)
 906                 {
 907                         priv->RFReadPageCnt[1]++;//cosa add for debug
 908                         priv->RfReg0Value[eRFPath] |= 0x100;
 909                         priv->RfReg0Value[eRFPath] &= (~0x40);
 910
 911                         // Switch to Reg_Mode1 for Reg16~30
 912                         rtl8192_setBBreg(dev,
 913                                 pPhyReg->rf3wireOffset,
 914                                 bMaskDWord,
 915                                 (priv->RfReg0Value[eRFPath] << 16)      );
 916
 917                         // Modified Offset
 918                         NewOffset = Offset - 15;
 919                 }
 920                 else
 921                 {
 922                         priv->RFReadPageCnt[0]++;//cosa add for debug
 923                         NewOffset = Offset;
 924         }
 925         }
 926         else
 927                 NewOffset = Offset;
 928
 929         //
 930         // Put desired read address to LSSI control register
 931         //
 932         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 933
 934         //
 935         // Issue a posedge trigger
 936         //
 937         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 938         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 939
 940         // TODO: we should not delay such a  long time. Ask help from SD3
 941         mdelay(1);
 942
 943         retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 944
 945         // Switch back to Reg_Mode0;
 946         if(     priv->rf_chip == RF_8256 ||
 947                 priv->rf_chip == RF_8225 ||
 948                 priv->rf_chip == RF_0222D)
 949         {
 950                 if (Offset >= 0x10)
 951                 {
 952                         priv->RfReg0Value[eRFPath] &= 0xebf;
 953
 954                         rtl8192_setBBreg(
 955                                 dev,
 956                                 pPhyReg->rf3wireOffset,
 957                                 bMaskDWord,
 958                                 (priv->RfReg0Value[eRFPath] << 16)      );
 959                 }
 960
 961                 //analog to digital on
 962                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
 963         }
 964
 965         return retValue;
 966 }
 967
 968
 969
 970 /**
 971 * Function:     phy_RFSerialWrite
 972 *
 973 * OverView:     Write data to RF register (page 8~)
 974 *
 975 * Input:
 976 *                       PADAPTER                Adapter,
 977 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 978 *                       u32                     Offset,         //The target address to be read
 979 *                       u32                     Data                    //The new register Data in the target bit position
 980 *                                                                               //of the target to be read
 981 *
 982 * Output:       None
 983 * Return:               None
 984 * Note:         Threre are three types of serial operations:
 985 *                       1. Software serial write
 986 *                       2. Hardware LSSI-Low Speed Serial Interface
 987 *                       3. Hardware HSSI-High speed
 988 *                       serial write. Driver need to implement (1) and (2).
 989 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 990  *
 991  * Note:                  For RF8256 only
 992  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 993  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 994  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 995  *                       programming guide" for more details.
 996  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 997  *                     ===========================================================
 998  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 999  *                                                              (Reg00[12])             (Reg00[10])
1000  *                     ===========================================================
1001  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1002  *                     ------------------------------------------------------------------
1003  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1004  *                     ------------------------------------------------------------------
1005  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1006  *                     ------------------------------------------------------------------
1007 */
1008 ////use in phy only
1009 static void
1010 phy_RFSerialWrite(
1011         struct net_device* dev,
1012         RF90_RADIO_PATH_E       eRFPath,
1013         u32                             Offset,
1014         u32                             Data
1015         )
1016 {
1017         u32                                     DataAndAddr = 0;
1018         struct r8192_priv                       *priv = ieee80211_priv(dev);
1019         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1020         u32                                     NewOffset;
1021
1022         Offset &= 0x3f;
1023
1024         // Shadow Update
1025         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1026
1027
1028         // Switch page for 8256 RF IC
1029         if(     priv->rf_chip == RF_8256 ||
1030                 priv->rf_chip == RF_8225 ||
1031                 priv->rf_chip == RF_0222D)
1032         {
1033                 //analog to digital off, for protection
1034                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1035
1036                 if(Offset>=31)
1037                 {
1038                         priv->RFWritePageCnt[2]++;//cosa add for debug
1039                         priv->RfReg0Value[eRFPath] |= 0x140;
1040
1041                         rtl8192_setBBreg(dev,
1042                                 pPhyReg->rf3wireOffset,
1043                                 bMaskDWord,
1044                                 (priv->RfReg0Value[eRFPath] << 16)      );
1045
1046                         NewOffset = Offset - 30;
1047
1048                 }else if(Offset>=16)
1049                 {
1050                         priv->RFWritePageCnt[1]++;//cosa add for debug
1051                         priv->RfReg0Value[eRFPath] |= 0x100;
1052                         priv->RfReg0Value[eRFPath] &= (~0x40);
1053
1054
1055                         rtl8192_setBBreg(dev,
1056                                 pPhyReg->rf3wireOffset,
1057                                 bMaskDWord,
1058                                 (priv->RfReg0Value[eRFPath] << 16)      );
1059
1060                         NewOffset = Offset - 15;
1061                 }
1062                 else
1063                 {
1064                         priv->RFWritePageCnt[0]++;//cosa add for debug
1065                         NewOffset = Offset;
1066         }
1067         }
1068         else
1069                 NewOffset = Offset;
1070
1071         //
1072         // Put write addr in [5:0]  and write data in [31:16]
1073         //
1074         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1075
1076         //
1077         // Write Operation
1078         //
1079         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1080
1081
1082         if(Offset==0x0)
1083                 priv->RfReg0Value[eRFPath] = Data;
1084
1085         // Switch back to Reg_Mode0;
1086         if(     priv->rf_chip == RF_8256 ||
1087                 priv->rf_chip == RF_8225 ||
1088                 priv->rf_chip == RF_0222D)
1089         {
1090                 if (Offset >= 0x10)
1091                 {
1092                         if(Offset != 0)
1093                         {
1094                                 priv->RfReg0Value[eRFPath] &= 0xebf;
1095                                 rtl8192_setBBreg(
1096                                 dev,
1097                                 pPhyReg->rf3wireOffset,
1098                                 bMaskDWord,
1099                                 (priv->RfReg0Value[eRFPath] << 16)      );
1100                         }
1101                 }
1102                 //analog to digital on
1103                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1104         }
1105
1106 }
1107 #else
1108 /**
1109 * Function:     phy_RFSerialRead
1110 *
1111 * OverView:     Read regster from RF chips
1112 *
1113 * Input:
1114 *                       PADAPTER                Adapter,
1115 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1116 *                       u4Byte                  Offset,         //The target address to be read
1117 *
1118 * Output:       None
1119 * Return:               u4Byte                  reback value
1120 * Note:         Threre are three types of serial operations:
1121 *                       1. Software serial write
1122 *                       2. Hardware LSSI-Low Speed Serial Interface
1123 *                       3. Hardware HSSI-High speed
1124 *                       serial write. Driver need to implement (1) and (2).
1125 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1126 */
1127 #if 0
1128 static  u32
1129 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
1130 {
1131
1132         u32                                             retValue = 0;
1133         struct r8192_priv *priv = ieee80211_priv(dev);
1134         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1135         u32                                             NewOffset;
1136         //u32                                           value  = 0;
1137         u32                                             tmplong,tmplong2;
1138         u32                                             RfPiEnable=0;
1139 #if 0
1140         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1141                 return  retValue;
1142         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1143                 return  retValue;
1144 #endif
1145         //
1146         // Make sure RF register offset is correct
1147         //
1148         Offset &= 0x3f;
1149
1150         //
1151         // Switch page for 8256 RF IC
1152         //
1153         NewOffset = Offset;
1154
1155         // For 92S LSSI Read RFLSSIRead
1156         // For RF A/B write 0x824/82c(does not work in the future)
1157         // We must use 0x824 for RF A and B to execute read trigger
1158         tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
1159         tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
1160         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF
1161
1162         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
1163         mdelay(1);
1164
1165         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
1166         mdelay(1);
1167
1168         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
1169         mdelay(1);
1170
1171         if(eRFPath == RF90_PATH_A)
1172                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
1173         else if(eRFPath == RF90_PATH_B)
1174                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
1175
1176         if(RfPiEnable)
1177         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
1178                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
1179                 //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
1180         }
1181         else
1182         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
1183                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1184                 //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
1185         }
1186         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
1187
1188         return retValue;
1189
1190 }
1191 4
1192
1193
1194 /**
1195 * Function:     phy_RFSerialWrite
1196 *
1197 * OverView:     Write data to RF register (page 8~)
1198 *
1199 * Input:
1200 *                       PADAPTER                Adapter,
1201 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1202 *                       u4Byte                  Offset,         //The target address to be read
1203 *                       u4Byte                  Data                    //The new register Data in the target bit position
1204 *                                                                               //of the target to be read
1205 *
1206 * Output:       None
1207 * Return:               None
1208 * Note:         Threre are three types of serial operations:
1209 *                       1. Software serial write
1210 *                       2. Hardware LSSI-Low Speed Serial Interface
1211 *                       3. Hardware HSSI-High speed
1212 *                       serial write. Driver need to implement (1) and (2).
1213 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1214  *
1215  * Note:                  For RF8256 only
1216  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1217  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1218  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1219  *                       programming guide" for more details.
1220  *                       Thus, we define a sub-finction for RTL8526 register address conversion
1221  *                     ===========================================================
1222  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
1223  *                                                              (Reg00[12])             (Reg00[10])
1224  *                     ===========================================================
1225  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1226  *                     ------------------------------------------------------------------
1227  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1228  *                     ------------------------------------------------------------------
1229  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1230  *                     ------------------------------------------------------------------
1231  *
1232  *      2008/09/02      MH      Add 92S RF definition
1233  *
1234  *
1235  *
1236 */
1237 static  void
1238 phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32       Data)
1239 {
1240         u32                                             DataAndAddr = 0;
1241         struct r8192_priv *priv = ieee80211_priv(dev);
1242         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1243         u32                                             NewOffset;
1244
1245 #if 0
1246         //<Roger_TODO> We should check valid regs for RF_6052 case.
1247         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1248                 return;
1249         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1250                 return;
1251 #endif
1252
1253         Offset &= 0x3f;
1254
1255         //
1256         // Shadow Update
1257         //
1258         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1259
1260         //
1261         // Switch page for 8256 RF IC
1262         //
1263                 NewOffset = Offset;
1264
1265         //
1266         // Put write addr in [5:0]  and write data in [31:16]
1267         //
1268         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1269         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF
1270
1271         //
1272         // Write Operation
1273         //
1274         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1275         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
1276
1277 }
1278 #endif
1279 #endif
1280
1281 /**
1282 * Function:     phy_CalculateBitShift
1283 *
1284 * OverView:     Get shifted position of the BitMask
1285 *
1286 * Input:
1287 *                       u32             BitMask,
1288 *
1289 * Output:       none
1290 * Return:               u32             Return the shift bit bit position of the mask
1291 */
1292 //use in phy only
1293 static u32 phy_CalculateBitShift(u32 BitMask)
1294 {
1295         u32 i;
1296
1297         for(i=0; i<=31; i++)
1298         {
1299                 if ( ((BitMask>>i) &  0x1 ) == 1)
1300                         break;
1301         }
1302
1303         return (i);
1304 }
1305
1306
1307 //
1308 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
1309 //
1310 /*-----------------------------------------------------------------------------
1311  * Function:    PHY_MACConfig8192S
1312  *
1313  * Overview:    Condig MAC by header file or parameter file.
1314  *
1315  * Input:       NONE
1316  *
1317  * Output:      NONE
1318  *
1319  * Return:      NONE
1320  *
1321  * Revised History:
1322  *  When                Who             Remark
1323  *  08/12/2008  MHC             Create Version 0.
1324  *
1325  *---------------------------------------------------------------------------*/
1326 //adapter_start
1327 extern bool PHY_MACConfig8192S(struct net_device* dev)
1328 {
1329         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1330
1331         //
1332         // Config MAC
1333         //
1334         rtStatus = phy_ConfigMACWithHeaderFile(dev);
1335         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
1336
1337 }
1338
1339 //adapter_start
1340 extern  bool
1341 PHY_BBConfig8192S(struct net_device* dev)
1342 {
1343         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1344
1345         u8 PathMap = 0, index = 0, rf_num = 0;
1346         struct r8192_priv       *priv = ieee80211_priv(dev);
1347         phy_InitBBRFRegisterDefinition(dev);
1348
1349         //
1350         // Config BB and AGC
1351         //
1352         //switch( Adapter->MgntInfo.bRegHwParaFile )
1353         //{
1354         //      case 0:
1355         //              phy_BB8190_Config_HardCode(dev);
1356         //              break;
1357
1358         //      case 1:
1359                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
1360         //              break;
1361
1362         //      case 2:
1363                         // Partial Modify.
1364         //              phy_BB8190_Config_HardCode(dev);
1365         //              phy_BB8192S_Config_ParaFile(dev);
1366         //              break;
1367
1368         //      default:
1369         //              phy_BB8190_Config_HardCode(dev);
1370         //              break;
1371         //}
1372         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
1373                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
1374         priv->rf_pathmap = PathMap;
1375         for(index = 0; index<4; index++)
1376         {
1377                 if((PathMap>>index)&0x1)
1378                         rf_num++;
1379         }
1380
1381         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
1382                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
1383                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
1384                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
1385                 (priv->rf_type==RF_2T4R && rf_num!=4))
1386         {
1387                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
1388         }
1389         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1390 }
1391
1392 //adapter_start
1393 extern  bool
1394 PHY_RFConfig8192S(struct net_device* dev)
1395 {
1396         struct r8192_priv       *priv = ieee80211_priv(dev);
1397         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1398
1399         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
1400
1401         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
1402         priv->rf_chip = RF_6052;
1403
1404         //
1405         // RF config
1406         //
1407         switch(priv->rf_chip)
1408         {
1409         case RF_8225:
1410         case RF_6052:
1411                 rtStatus = PHY_RF6052_Config(dev);
1412                 break;
1413
1414         case RF_8256:
1415                 //rtStatus = PHY_RF8256_Config(dev);
1416                 break;
1417
1418         case RF_8258:
1419                 break;
1420
1421         case RF_PSEUDO_11N:
1422                 //rtStatus = PHY_RF8225_Config(dev);
1423                 break;
1424         default:
1425             break;
1426         }
1427
1428         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1429 }
1430
1431
1432 // Joseph test: new initialize order!!
1433 // Test only!! This part need to be re-organized.
1434 // Now it is just for 8256.
1435 //use in phy only
1436 #ifdef TO_DO_LIST
1437 static RT_STATUS
1438 phy_BB8190_Config_HardCode(struct net_device* dev)
1439 {
1440         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1441         return RT_STATUS_SUCCESS;
1442 }
1443 #endif
1444
1445 /*-----------------------------------------------------------------------------
1446  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
1447  *
1448  * Overview:    This function
1449  *
1450  *
1451  * Input:       PADAPTER                Adapter
1452  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
1453  *
1454  * Output:      NONE
1455  *
1456  * Return:      RT_STATUS_SUCCESS: configuration file exist
1457  * When                 Who             Remark
1458  * 2008/11/10   tynli
1459  * use in phy only
1460  *---------------------------------------------------------------------------*/
1461 static RT_STATUS
1462 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
1463 {
1464         int i;
1465         struct r8192_priv       *priv = ieee80211_priv(dev);
1466         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
1467         u16                             PHY_REGArraytoXTXRLen;
1468
1469 //#if (HAL_CODE_BASE != RTL8192_S)
1470
1471         if(priv->rf_type == RF_1T1R)
1472         {
1473                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
1474                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
1475         }
1476         else if(priv->rf_type == RF_1T2R)
1477         {
1478                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
1479                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
1480         }
1481         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
1482         //{
1483         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
1484         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
1485         //}
1486         else
1487         {
1488                 return RT_STATUS_FAILURE;
1489         }
1490
1491         if(ConfigType == BaseBand_Config_PHY_REG)
1492         {
1493                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
1494                 {
1495                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
1496                                 mdelay(50);
1497                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
1498                                 mdelay(5);
1499                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
1500                                 mdelay(1);
1501                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
1502                                 udelay(50);
1503                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
1504                                 udelay(5);
1505                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
1506                                 udelay(1);
1507                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1508                         //RT_TRACE(COMP_SEND,
1509                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
1510                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1511                 }
1512         }
1513         else {
1514                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1515         }
1516 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1517         return RT_STATUS_SUCCESS;
1518 }
1519
1520
1521 //use in phy only
1522 static  RT_STATUS
1523 phy_BB8192S_Config_ParaFile(struct net_device* dev)
1524 {
1525         struct r8192_priv       *priv = ieee80211_priv(dev);
1526         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1527         //u8                            u2RegValue;
1528         //u16                           u4RegValue;
1529         //char                          szBBRegFile[] = RTL819X_PHY_REG;
1530         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
1531         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1532         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
1533         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
1534         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
1535
1536         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
1537
1538         //
1539         // 1. Read PHY_REG.TXT BB INIT!!
1540         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
1541         //
1542         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1543             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1544         {
1545                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1546                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1547                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1548                   //so we should reconfig BB reg with the right PHY parameters.
1549                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1550                 }
1551         }else
1552                 rtStatus = RT_STATUS_FAILURE;
1553
1554         if(rtStatus != RT_STATUS_SUCCESS){
1555                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
1556                 goto phy_BB8190_Config_ParaFile_Fail;
1557         }
1558
1559         //
1560         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1561         //
1562         if (priv->AutoloadFailFlag == false)
1563         {
1564                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
1565         }
1566         if(rtStatus != RT_STATUS_SUCCESS){
1567                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
1568                 goto phy_BB8190_Config_ParaFile_Fail;
1569         }
1570
1571         //
1572         // 3. BB AGC table Initialization
1573         //
1574         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
1575
1576         if(rtStatus != RT_STATUS_SUCCESS){
1577                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
1578                 goto phy_BB8190_Config_ParaFile_Fail;
1579         }
1580
1581
1582 #if 0   // 2008/08/18 MH Disable for 92SE
1583         if(pHalData->VersionID > VERSION_8190_BD)
1584         {
1585                 //if(pHalData->RF_Type == RF_2T4R)
1586                 //{
1587                 // Antenna gain offset from B/C/D to A
1588                 u4RegValue = (  pHalData->AntennaTxPwDiff[2]<<8 |
1589                                                 pHalData->AntennaTxPwDiff[1]<<4 |
1590                                                 pHalData->AntennaTxPwDiff[0]);
1591                 //}
1592                 //else
1593                 //u4RegValue = 0;
1594
1595                 PHY_SetBBReg(dev, rFPGA0_TxGainStage,
1596                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1597
1598                 // CrystalCap
1599                 // Simulate 8192???
1600                 u4RegValue = pHalData->CrystalCap;
1601                 PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
1602                 // Simulate 8190??
1603                 //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2);       // bit2~3 of crystal cap
1604                 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
1605
1606         }
1607 #endif
1608
1609         // Check if the CCK HighPower is turned ON.
1610         // This is used to calculate PWDB.
1611         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1612
1613
1614 phy_BB8190_Config_ParaFile_Fail:
1615         return rtStatus;
1616 }
1617
1618 /*-----------------------------------------------------------------------------
1619  * Function:    phy_ConfigMACWithHeaderFile()
1620  *
1621  * Overview:    This function read BB parameters from Header file we gen, and do register
1622  *                        Read/Write
1623  *
1624  * Input:       PADAPTER                Adapter
1625  *                      char*                   pFileName
1626  *
1627  * Output:      NONE
1628  *
1629  * Return:      RT_STATUS_SUCCESS: configuration file exist
1630  *
1631  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
1632  *                      [Register][Mask][Value]
1633  *---------------------------------------------------------------------------*/
1634 //use in phy only
1635 static  RT_STATUS
1636 phy_ConfigMACWithHeaderFile(struct net_device* dev)
1637 {
1638         u32                                     i = 0;
1639         u32                                     ArrayLength = 0;
1640         u32*                                    ptrArray;
1641         //struct r8192_priv     *priv = ieee80211_priv(dev);
1642
1643 //#if (HAL_CODE_BASE != RTL8192_S)
1644         /*if(Adapter->bInHctTest)
1645         {
1646                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
1647                 ArrayLength = MACPHY_ArrayLengthDTM;
1648                 ptrArray = Rtl819XMACPHY_ArrayDTM;
1649         }
1650         else if(pHalData->bTXPowerDataReadFromEEPORM)
1651         {
1652 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
1653 //              ArrayLength = MACPHY_Array_PGLength;
1654 //              ptrArray = Rtl819XMACPHY_Array_PG;
1655
1656         }else*/
1657         { //2008.11.06 Modified by tynli.
1658                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
1659                 ArrayLength = MAC_2T_ArrayLength;
1660                 ptrArray = Rtl819XMAC_Array;
1661         }
1662
1663         /*for(i = 0 ;i < ArrayLength;i=i+3){
1664                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
1665                 if(ptrArray[i] == 0x318)
1666                 {
1667                         ptrArray[i+2] = 0x00000800;
1668                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1669                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1670                 }
1671                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1672         }*/
1673         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
1674                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
1675         }
1676 //#endif
1677         return RT_STATUS_SUCCESS;
1678 }
1679
1680 /*-----------------------------------------------------------------------------
1681  * Function:    phy_ConfigBBWithHeaderFile()
1682  *
1683  * Overview:    This function read BB parameters from general file format, and do register
1684  *                        Read/Write
1685  *
1686  * Input:       PADAPTER                Adapter
1687  *                      u8                      ConfigType     0 => PHY_CONFIG
1688  *                                                                               1 =>AGC_TAB
1689  *
1690  * Output:      NONE
1691  *
1692  * Return:      RT_STATUS_SUCCESS: configuration file exist
1693  *
1694  *---------------------------------------------------------------------------*/
1695 //use in phy only
1696 static  RT_STATUS
1697 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1698 {
1699         int             i;
1700         //u8            ArrayLength;
1701         u32*    Rtl819XPHY_REGArray_Table;
1702         u32*    Rtl819XAGCTAB_Array_Table;
1703         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1704         //struct r8192_priv *priv = ieee80211_priv(dev);
1705 //#if (HAL_CODE_BASE != RTL8192_S)
1706         /*if(Adapter->bInHctTest)
1707         {
1708
1709                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1710                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1711
1712                 if(pHalData->RF_Type == RF_2T4R)
1713                 {
1714                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1715                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1716                 }
1717                 else if (pHalData->RF_Type == RF_1T2R)
1718                 {
1719                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1720                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1721                 }
1722
1723         }
1724         else
1725         */
1726         //{
1727         //
1728         // 2008.11.06 Modified by tynli.
1729         //
1730         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1731         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1732         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1733         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1734         //}
1735
1736         if(ConfigType == BaseBand_Config_PHY_REG)
1737         {
1738                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1739                 {
1740                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1741                                 mdelay(50);
1742                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1743                                 mdelay(5);
1744                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1745                                 mdelay(1);
1746                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1747                                 udelay(50);
1748                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1749                                 udelay(5);
1750                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1751                                 udelay(1);
1752                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1753                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1754
1755                 }
1756         }
1757         else if(ConfigType == BaseBand_Config_AGC_TAB){
1758                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1759                 {
1760                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1761                 }
1762         }
1763 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1764         return RT_STATUS_SUCCESS;
1765 }
1766
1767 /*-----------------------------------------------------------------------------
1768  * Function:    phy_ConfigBBWithPgHeaderFile
1769  *
1770  * Overview:    Config PHY_REG_PG array
1771  *
1772  * Input:       NONE
1773  *
1774  * Output:      NONE
1775  *
1776  * Return:      NONE
1777  *
1778  * Revised History:
1779  * When                 Who             Remark
1780  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1781  * 11/10/2008   tynli           Modify to mew files.
1782  //use in phy only
1783  *---------------------------------------------------------------------------*/
1784 static RT_STATUS
1785 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1786 {
1787         int i;
1788         //u8 ArrayLength;
1789         u32*    Rtl819XPHY_REGArray_Table_PG;
1790         u16     PHY_REGArrayPGLen;
1791         //struct r8192_priv *priv = ieee80211_priv(dev);
1792 //#if (HAL_CODE_BASE != RTL8192_S)
1793         // Default: pHalData->RF_Type = RF_2T2R.
1794
1795         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1796         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1797
1798         if(ConfigType == BaseBand_Config_PHY_REG)
1799         {
1800                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1801                 {
1802                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1803                                 mdelay(50);
1804                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1805                                 mdelay(5);
1806                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1807                                 mdelay(1);
1808                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1809                                 udelay(50);
1810                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1811                                 udelay(5);
1812                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1813                                 udelay(1);
1814                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1815                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1816                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1817                 }
1818         }else{
1819                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1820         }
1821         return RT_STATUS_SUCCESS;
1822
1823 }       /* phy_ConfigBBWithPgHeaderFile */
1824
1825 /*-----------------------------------------------------------------------------
1826  * Function:    PHY_ConfigRFWithHeaderFile()
1827  *
1828  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1829  *
1830  * Input:       PADAPTER                        Adapter
1831  *                      char*                           pFileName
1832  *                      RF90_RADIO_PATH_E       eRFPath
1833  *
1834  * Output:      NONE
1835  *
1836  * Return:      RT_STATUS_SUCCESS: configuration file exist
1837  *
1838  * Note:                Delay may be required for RF configuration
1839  *---------------------------------------------------------------------------*/
1840 //in 8256 phy_RF8256_Config_ParaFile only
1841 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1842 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1843 {
1844
1845         struct r8192_priv *priv = ieee80211_priv(dev);
1846         int                     i;
1847         //u32*  pRFArray;
1848         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1849         u32                     *Rtl819XRadioA_Array_Table;
1850         u32                     *Rtl819XRadioB_Array_Table;
1851         //u32*  Rtl819XRadioC_Array_Table;
1852         //u32*  Rtl819XRadioD_Array_Table;
1853         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1854
1855         {       //2008.11.06 Modified by tynli
1856                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1857                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1858                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1859                 RadioB_ArrayLen = RadioB_ArrayLength;
1860         }
1861
1862         if( priv->rf_type == RF_2T2R_GREEN )
1863         {
1864                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1865                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1866         }
1867         else
1868         {
1869                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1870                 RadioB_ArrayLen = RadioB_ArrayLength;
1871         }
1872
1873         rtStatus = RT_STATUS_SUCCESS;
1874
1875         // When initialization, we want the delay function(mdelay(), delay_us()
1876         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1877         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1878         // to run at Dispatch level to achive it.
1879         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1880
1881         switch(eRFPath){
1882                 case RF90_PATH_A:
1883                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1884                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1885                                         { // Deay specific ms. Only RF configuration require delay.
1886 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1887 #ifdef RTL8192SU
1888                                                 mdelay(1000);
1889 #else
1890                                                 mdelay(50);
1891 #endif
1892                                 }
1893                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1894                                                 mdelay(5);
1895                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1896                                                 mdelay(1);
1897                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1898                                                 udelay(50);
1899                                                 //PlatformStallExecution(50);
1900                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1901                                                 udelay(5);
1902                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1903                                                 udelay(1);
1904                                         else
1905                                         {
1906                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1907                                         }
1908                         }
1909                         break;
1910                 case RF90_PATH_B:
1911                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1912                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1913                                         { // Deay specific ms. Only RF configuration require delay.
1914 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1915 #ifdef RTL8192SU
1916                                                 mdelay(1000);
1917 #else
1918                                                 mdelay(50);
1919 #endif
1920                                 }
1921                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1922                                                 mdelay(5);
1923                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1924                                                 mdelay(1);
1925                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1926                                                 udelay(50);
1927                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1928                                                 udelay(5);
1929                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1930                                                 udelay(1);
1931                                         else
1932                                         {
1933                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1934                                         }
1935                         }
1936                         break;
1937                 case RF90_PATH_C:
1938                         break;
1939                 case RF90_PATH_D:
1940                         break;
1941                 default:
1942                         break;
1943         }
1944
1945         return rtStatus;
1946
1947 }
1948
1949 /*-----------------------------------------------------------------------------
1950  * Function:    PHY_CheckBBAndRFOK()
1951  *
1952  * Overview:    This function is write register and then readback to make sure whether
1953  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1954  *
1955  * Input:       PADAPTER                        Adapter
1956  *                      HW90_BLOCK_E            CheckBlock
1957  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
1958  *
1959  * Output:      NONE
1960  *
1961  * Return:      RT_STATUS_SUCCESS: PHY is OK
1962  *
1963  * Note:                This function may be removed in the ASIC
1964  *---------------------------------------------------------------------------*/
1965 //in 8256 phy_RF8256_Config_HardCode
1966 //but we don't use it temp
1967 RT_STATUS
1968 PHY_CheckBBAndRFOK(
1969         struct net_device* dev,
1970         HW90_BLOCK_E            CheckBlock,
1971         RF90_RADIO_PATH_E       eRFPath
1972         )
1973 {
1974         //struct r8192_priv *priv = ieee80211_priv(dev);
1975         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1976         u32                             i, CheckTimes = 4,ulRegRead = 0;
1977         u32                             WriteAddr[4];
1978         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1979
1980         // Initialize register address offset to be checked
1981         WriteAddr[HW90_BLOCK_MAC] = 0x100;
1982         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1983         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1984         WriteAddr[HW90_BLOCK_RF] = 0x3;
1985
1986         for(i=0 ; i < CheckTimes ; i++)
1987         {
1988
1989                 //
1990                 // Write Data to register and readback
1991                 //
1992                 switch(CheckBlock)
1993                 {
1994                 case HW90_BLOCK_MAC:
1995                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
1996                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1997                         break;
1998
1999                 case HW90_BLOCK_PHY0:
2000                 case HW90_BLOCK_PHY1:
2001                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2002                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2003                         break;
2004
2005                 case HW90_BLOCK_RF:
2006                         // When initialization, we want the delay function(mdelay(), delay_us()
2007                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
2008                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
2009                         // to run at Dispatch level to achive it.
2010                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
2011                         WriteData[i] &= 0xfff;
2012                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
2013                         // TODO: we should not delay for such a long time. Ask SD3
2014                         mdelay(10);
2015                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2016                         mdelay(10);
2017                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
2018                         break;
2019
2020                 default:
2021                         rtStatus = RT_STATUS_FAILURE;
2022                         break;
2023                 }
2024
2025
2026                 //
2027                 // Check whether readback data is correct
2028                 //
2029                 if(ulRegRead != WriteData[i])
2030                 {
2031                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
2032                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
2033                         rtStatus = RT_STATUS_FAILURE;
2034                         break;
2035                 }
2036         }
2037
2038         return rtStatus;
2039 }
2040
2041 //no use temp in windows driver
2042 #ifdef TO_DO_LIST
2043 void
2044 PHY_SetRFPowerState8192SUsb(
2045         struct net_device* dev,
2046         RF_POWER_STATE  RFPowerState
2047         )
2048 {
2049         struct r8192_priv *priv = ieee80211_priv(dev);
2050         bool                    WaitShutDown = FALSE;
2051         u32                     DWordContent;
2052         //RF90_RADIO_PATH_E     eRFPath;
2053         u8                              eRFPath;
2054         BB_REGISTER_DEFINITION_T        *pPhyReg;
2055
2056         if(priv->SetRFPowerStateInProgress == TRUE)
2057                 return;
2058
2059         priv->SetRFPowerStateInProgress = TRUE;
2060
2061         // TODO: Emily, 2006.11.21, we should rewrite this function
2062
2063         if(RFPowerState==RF_SHUT_DOWN)
2064         {
2065                 RFPowerState=RF_OFF;
2066                 WaitShutDown=TRUE;
2067         }
2068
2069
2070         priv->RFPowerState = RFPowerState;
2071         switch( priv->rf_chip )
2072         {
2073         case RF_8225:
2074         case RF_6052:
2075                 switch( RFPowerState )
2076                 {
2077                 case RF_ON:
2078                         break;
2079
2080                 case RF_SLEEP:
2081                         break;
2082
2083                 case RF_OFF:
2084                         break;
2085                 }
2086                 break;
2087
2088         case RF_8256:
2089                 switch( RFPowerState )
2090                 {
2091                 case RF_ON:
2092                         break;
2093
2094                 case RF_SLEEP:
2095                         break;
2096
2097                 case RF_OFF:
2098                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
2099                         {
2100                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2101                                         continue;
2102
2103                                 pPhyReg = &priv->PHYRegDef[eRFPath];
2104                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
2105                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
2106                         }
2107                         break;
2108                 }
2109                 break;
2110
2111         case RF_8258:
2112                 break;
2113         }// switch( priv->rf_chip )
2114
2115         priv->SetRFPowerStateInProgress = FALSE;
2116 }
2117 #endif
2118
2119 #ifdef RTL8192U
2120 //no use temp in windows driver
2121 void
2122 PHY_UpdateInitialGain(
2123         struct net_device* dev
2124         )
2125 {
2126         struct r8192_priv       *priv = ieee80211_priv(dev);
2127         //unsigned char                 *IGTable;
2128         //u8                    DIG_CurrentInitialGain = 4;
2129
2130         switch(priv->rf_chip)
2131         {
2132         case RF_8225:
2133                 break;
2134         case RF_8256:
2135                 break;
2136         case RF_8258:
2137                 break;
2138         case RF_PSEUDO_11N:
2139                 break;
2140         case RF_6052:
2141                 break;
2142         default:
2143                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
2144                 break;
2145         }
2146 }
2147 #endif
2148
2149 //YJ,modified,090107
2150 void PHY_GetHWRegOriginalValue(struct net_device* dev)
2151 {
2152         struct r8192_priv *priv = ieee80211_priv(dev);
2153
2154         // read tx power offset
2155         // Simulate 8192
2156         priv->MCSTxPowerLevelOriginalOffset[0] =
2157                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
2158         priv->MCSTxPowerLevelOriginalOffset[1] =
2159                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
2160         priv->MCSTxPowerLevelOriginalOffset[2] =
2161                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
2162         priv->MCSTxPowerLevelOriginalOffset[3] =
2163                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
2164         priv->MCSTxPowerLevelOriginalOffset[4] =
2165                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
2166         priv->MCSTxPowerLevelOriginalOffset[5] =
2167                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
2168
2169         // Read CCK offset
2170         priv->MCSTxPowerLevelOriginalOffset[6] =
2171                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
2172         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
2173         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
2174         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
2175         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
2176
2177         // read rx initial gain
2178         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
2179         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
2180         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
2181         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
2182         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2183                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2184                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2185
2186         // read framesync
2187         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
2188         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
2189         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2190                                 rOFDM0_RxDetector3, priv->framesync);
2191 }
2192 //YJ,modified,090107,end
2193
2194
2195
2196 /**
2197 * Function:     phy_InitBBRFRegisterDefinition
2198 *
2199 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
2200 *
2201 * Input:
2202 *                       PADAPTER                Adapter,
2203 *
2204 * Output:       None
2205 * Return:               None
2206 * Note:         The initialization value is constant and it should never be changes
2207 */
2208 //use in phy only
2209 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
2210 {
2211         struct r8192_priv *priv = ieee80211_priv(dev);
2212
2213         // RF Interface Sowrtware Control
2214         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2215         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2216         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2217         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2218
2219         // RF Interface Readback Value
2220         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2221         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2222         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2223         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2224
2225         // RF Interface Output (and Enable)
2226         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2227         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2228         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2229         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2230
2231         // RF Interface (Output and)  Enable
2232         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2233         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2234         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2235         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2236
2237         //Addr of LSSI. Wirte RF register by driver
2238         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2239         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2240         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2241         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2242
2243         // RF parameter
2244         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
2245         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2246         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2247         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2248
2249         // Tx AGC Gain Stage (same for all path. Should we remove this?)
2250         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2251         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2252         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2253         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2254
2255         // Tranceiver A~D HSSI Parameter-1
2256         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
2257         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
2258         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
2259         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
2260
2261         // Tranceiver A~D HSSI Parameter-2
2262         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
2263         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
2264         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
2265         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
2266
2267         // RF switch Control
2268         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2269         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2270         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2271         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2272
2273         // AGC control 1
2274         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2275         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2276         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2277         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2278
2279         // AGC control 2
2280         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2281         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2282         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2283         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2284
2285         // RX AFE control 1
2286         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2287         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2288         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2289         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2290
2291         // RX AFE control 1
2292         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2293         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2294         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2295         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2296
2297         // Tx AFE control 1
2298         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2299         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2300         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2301         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2302
2303         // Tx AFE control 2
2304         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2305         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2306         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2307         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2308
2309         // Tranceiver LSSI Readback  SI mode
2310         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2311         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2312         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2313         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2314
2315         // Tranceiver LSSI Readback PI mode
2316         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
2317         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
2318         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
2319         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
2320
2321 }
2322
2323
2324 //
2325 //      Description:  Change RF power state.
2326 //
2327 //      Assumption: This function must be executed in re-schdulable context,
2328 //              ie. PASSIVE_LEVEL.
2329 //
2330 //      050823, by rcnjko.
2331 //not understand it seem's use in init
2332 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
2333 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
2334 {
2335         struct r8192_priv *priv = ieee80211_priv(dev);
2336         bool                    bResult = FALSE;
2337
2338         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2339
2340         if(eRFPowerState == priv->ieee80211->eRFPowerState)
2341         {
2342                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2343                 return bResult;
2344         }
2345
2346         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
2347
2348         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
2349
2350         return bResult;
2351 }
2352
2353 //use in phy only
2354 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
2355 {
2356         struct r8192_priv *priv = ieee80211_priv(dev);
2357         bool                    bResult = TRUE;
2358         //u8            eRFPath;
2359         //u8            i, QueueID;
2360         u8              u1bTmp;
2361
2362         if(priv->SetRFPowerStateInProgress == TRUE)
2363                 return FALSE;
2364
2365         priv->SetRFPowerStateInProgress = TRUE;
2366
2367         switch(priv->rf_chip )
2368         {
2369                 default:
2370                 switch( eRFPowerState )
2371                 {
2372                         case eRfOn:
2373                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
2374                                 write_nic_word(dev, CMDR, 0x37FC);
2375                                 write_nic_byte(dev, PHY_CCA, 0x3);
2376                                 write_nic_byte(dev, TXPAUSE, 0x00);
2377                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
2378                                 break;
2379
2380                         //
2381                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
2382                         // By Bruce, 2008-01-16.
2383                         //
2384                         case eRfSleep:
2385                         case eRfOff:
2386                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
2387                                                 break;
2388 #ifdef NOT_YET
2389                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
2390                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
2391                                 {
2392                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
2393                                         {
2394                                                 QueueID++;
2395                                                 continue;
2396                                         }
2397                                         else
2398                                         {
2399                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
2400                                                 udelay(10);
2401                                                 i++;
2402                                         }
2403
2404                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
2405                                         {
2406                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
2407                                                 break;
2408                                         }
2409                                 }
2410 #endif
2411                                 //
2412                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
2413                                 // Added by Bruce, 2008-11-22.
2414                                 //
2415                                 //==================================================================
2416                                 // (0) Disable FW BB reset checking
2417                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
2418
2419                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
2420                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
2421                                 u1bTmp |= BIT0;
2422                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
2423
2424                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
2425                                 write_nic_byte(dev, TXPAUSE, 0xFF);
2426
2427                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
2428                                 write_nic_word(dev, CMDR, 0x77FC);
2429                                 write_nic_byte(dev, PHY_CCA, 0x0);
2430                                 udelay(100);
2431
2432                                 write_nic_word(dev, CMDR, 0x37FC);
2433                                 udelay(10);
2434
2435                                 write_nic_word(dev, CMDR, 0x77FC);
2436                                 udelay(10);
2437
2438                                 // (3) Reset BB TRX blocks
2439                                 write_nic_word(dev, CMDR, 0x57FC);
2440                                 break;
2441
2442                         default:
2443                                 bResult = FALSE;
2444                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
2445                                 break;
2446                 }
2447                 break;
2448
2449         }
2450         priv->ieee80211->eRFPowerState = eRFPowerState;
2451 #ifdef TO_DO_LIST
2452         if(bResult)
2453         {
2454                 // Update current RF state variable.
2455                 priv->ieee80211->eRFPowerState = eRFPowerState;
2456
2457                 switch(priv->rf_chip )
2458                 {
2459                         case RF_8256:
2460                         switch(priv->ieee80211->eRFPowerState)
2461                         {
2462                                 case eRfOff:
2463                                         //
2464                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
2465                                         //
2466                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
2467                                         {
2468                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
2469                                         }
2470                                         else
2471                                         {
2472                                                 // Turn off LED if RF is not ON.
2473                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
2474                                         }
2475                                         break;
2476
2477                                 case eRfOn:
2478                                         // Turn on RF we are still linked, which might happen when
2479                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
2480                                         if( pMgntInfo->bMediaConnect == TRUE )
2481                                         {
2482                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
2483                                         }
2484                                         else
2485                                         {
2486                                                 // Turn off LED if RF is not ON.
2487                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
2488                                         }
2489                                         break;
2490
2491                                 default:
2492                                         // do nothing.
2493                                         break;
2494                         }// Switch RF state
2495
2496                                 break;
2497
2498                         default:
2499                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
2500                                 break;
2501                 }// Switch rf_chip
2502         }
2503 #endif
2504         priv->SetRFPowerStateInProgress = FALSE;
2505
2506         return bResult;
2507 }
2508
2509 /*-----------------------------------------------------------------------------
2510  * Function:    GetTxPowerLevel8190()
2511  *
2512  * Overview:    This function is export to "common" moudule
2513  *
2514  * Input:       PADAPTER                Adapter
2515  *                      psByte                  Power Level
2516  *
2517  * Output:      NONE
2518  *
2519  * Return:      NONE
2520  *
2521  *---------------------------------------------------------------------------*/
2522  // no use temp
2523  void
2524 PHY_GetTxPowerLevel8192S(
2525         struct net_device* dev,
2526          long*                  powerlevel
2527         )
2528 {
2529         struct r8192_priv *priv = ieee80211_priv(dev);
2530         u8                      TxPwrLevel = 0;
2531         long                    TxPwrDbm;
2532         //
2533         // Because the Tx power indexes are different, we report the maximum of them to
2534         // meet the CCX TPC request. By Bruce, 2008-01-31.
2535         //
2536
2537         // CCK
2538         TxPwrLevel = priv->CurrentCckTxPwrIdx;
2539         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
2540
2541         // Legacy OFDM
2542         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
2543
2544         // Compare with Legacy OFDM Tx power.
2545         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2546                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
2547
2548         // HT OFDM
2549         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
2550
2551         // Compare with HT OFDM Tx power.
2552         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2553                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
2554
2555         *powerlevel = TxPwrDbm;
2556 }
2557
2558 /*-----------------------------------------------------------------------------
2559  * Function:    SetTxPowerLevel8190()
2560  *
2561  * Overview:    This function is export to "HalCommon" moudule
2562  *
2563  * Input:       PADAPTER                Adapter
2564  *                      u1Byte          channel
2565  *
2566  * Output:      NONE
2567  *
2568  * Return:      NONE
2569  *      2008/11/04      MHC             We remove EEPROM_93C56.
2570  *                                              We need to move CCX relative code to independet file.
2571 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
2572   *---------------------------------------------------------------------------*/
2573  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
2574 {
2575         struct r8192_priv *priv = ieee80211_priv(dev);
2576         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
2577         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
2578         s8      ant_pwr_diff = 0;
2579         u32     u4RegValue;
2580         u8      index = (channel -1);
2581         // 2009/01/22 MH Add for new EEPROM format from SD3
2582         u8      pwrdiff[2] = {0};
2583         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
2584         u8      rfpath = 0, rfpathnum = 2;
2585
2586         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
2587                 return;
2588
2589         //
2590         // Read predefined TX power index in EEPROM
2591         //
2592 //      if(priv->epromtype == EPROM_93c46)
2593         {
2594                 //
2595                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2596                 // Power must be calculated by the antenna diff.
2597                 // So we have to rewrite Antenna gain offset register here.
2598                 // Please refer to BB register 0x80c
2599                 // 1. For CCK.
2600                 // 2. For OFDM 1T or 2T
2601                 //
2602
2603                 // 1. CCK
2604                 powerlevel = priv->RfTxPwrLevelCck[0][index];
2605
2606                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
2607                 {
2608                 // Read HT 40 OFDM TX power
2609                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
2610                 // RF B HT OFDM pwr-RFA HT OFDM pwr
2611                 // Only one RF we need not to decide B <-> A pwr diff
2612
2613                 // Legacy<->HT pwr diff, we only care about path A.
2614
2615                 // We only assume 1T as RF path A
2616                 rfpathnum = 1;
2617                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
2618                 }
2619                 else if (priv->rf_type == RF_2T2R)
2620                 {
2621                 // Read HT 40 OFDM TX power
2622                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
2623                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2624                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
2625                                                 priv->RfTxPwrLevelOfdm2T[0][index];
2626                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
2627                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
2628
2629                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
2630                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
2631                 //priv->RfTxPwrLevelOfdm2T[1][index],
2632                 //priv->RfTxPwrLevelOfdm2T[0][index],
2633                 //priv->RfTxPwrLevelOfdm2T[1][index]));
2634
2635                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
2636                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
2637         }
2638
2639         //
2640         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
2641         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
2642         //
2643         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
2644         {
2645                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2646                 {
2647                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2648                         {
2649                                 // HT 20<->40 pwr diff
2650                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
2651
2652                                 // Calculate Antenna pwr diff
2653                                 if (pwrdiff[rfpath] < 8)        // 0~+7
2654                                 {
2655                                 #if 0//cosa, it doesn't need to add the offset here
2656                                         if (rfpath == 0)
2657                                                 powerlevelOFDM24G += pwrdiff[rfpath];
2658                                 #endif
2659                                         ht20pwr[rfpath] += pwrdiff[rfpath];
2660                                 }
2661                                 else                            // index8-15=-8~-1
2662                                 {
2663                                 #if 0//cosa, it doesn't need to add the offset here
2664                                         if (rfpath == 0)
2665                                                 powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
2666                                 #endif
2667                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
2668                                 }
2669                         }
2670
2671                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2672                         if (priv->rf_type == RF_2T2R)
2673                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2674
2675                         //RTPRINT(FPHY, PHY_TXPWR,
2676                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2677                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2678                 }
2679
2680                 // Band Edge scheme is enabled for FCC mode
2681                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
2682                 {
2683                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2684                         {
2685                                 pwrdiff[rfpath] = 0;
2686                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2687                                 {
2688                                         if (channel <= 3)
2689                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
2690                                         else if (channel >= 9)
2691                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
2692                                         else
2693                                                 pwrdiff[rfpath] = 0;
2694
2695                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
2696                                 }
2697                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2698                                 {
2699                                         if (channel == 1)
2700                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2701                                         else if (channel >= 11)
2702                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2703                                         else
2704                                                 pwrdiff[rfpath] = 0;
2705
2706                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2707                                 }
2708                         #if 0//cosa, it doesn't need to add the offset here
2709                                 if (rfpath == 0)
2710                                         powerlevelOFDM24G -= pwrdiff[rfpath];
2711                         #endif
2712                         }
2713
2714                         if (priv->rf_type == RF_2T2R)
2715                         {
2716                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2717                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2718                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2719                                 else
2720                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2721                         }
2722                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2723                         {
2724                                 if (channel <= 1 || channel >= 11)
2725                                 {
2726                                         //RTPRINT(FPHY, PHY_TXPWR,
2727                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2728                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2729                                 }
2730                         }
2731                         else
2732                         {
2733                                 if (channel <= 3 || channel >= 9)
2734                                 {
2735                                         //RTPRINT(FPHY, PHY_TXPWR,
2736                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2737                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2738                                 }
2739                         }
2740                 }
2741 #if 0//cosa, useless
2742                 // Read HT/Legacy OFDM diff
2743                 legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
2744 #endif
2745                 }
2746
2747         //Cosa added for protection, the reg rFPGA0_TxGainStage
2748         // range is from 7~-8, index = 0x0~0xf
2749         if(ant_pwr_diff > 7)
2750                 ant_pwr_diff = 7;
2751         if(ant_pwr_diff < -8)
2752                 ant_pwr_diff = -8;
2753
2754                 //RTPRINT(FPHY, PHY_TXPWR,
2755                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2756                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2757
2758                 ant_pwr_diff &= 0xf;
2759
2760                 // Antenna TX power difference
2761                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2762                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2763                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2764
2765                 // Antenna gain offset from B/C/D to A
2766                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2767                                                 priv->AntennaTxPwDiff[1]<<4 |
2768                                                 priv->AntennaTxPwDiff[0]        );
2769
2770                 // Notify Tx power difference for B/C/D to A!!!
2771                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2772         }
2773
2774         //
2775         // CCX 2 S31, AP control of client transmit power:
2776         // 1. We shall not exceed Cell Power Limit as possible as we can.
2777         // 2. Tolerance is +/- 5dB.
2778         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2779         //
2780         // TODO:
2781         // 1. 802.11h power contraint
2782         //
2783         // 071011, by rcnjko.
2784         //
2785 #ifdef TODO //WB, 11h has not implemented now.
2786         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2787                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2788         {
2789                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2790                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2791                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2792
2793                 RT_TRACE(COMP_TXAGC,
2794                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2795                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2796                 RT_TRACE(COMP_TXAGC,
2797                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2798                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2799
2800                 // CCK
2801                 if(powerlevel > CckCellPwrIdx)
2802                         powerlevel = CckCellPwrIdx;
2803                 // Legacy OFDM, HT OFDM
2804                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2805                 {
2806                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2807                         {
2808                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2809                         }
2810                         else
2811                         {
2812                                 powerlevelOFDM24G = 0;
2813                         }
2814                 }
2815
2816                 RT_TRACE(COMP_TXAGC,
2817                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2818                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2819         }
2820 #endif
2821
2822         priv->CurrentCckTxPwrIdx = powerlevel;
2823         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2824
2825         switch(priv->rf_chip)
2826         {
2827                 case RF_8225:
2828                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2829                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2830                 break;
2831
2832                 case RF_8256:
2833 #if 0
2834                         PHY_SetRF8256CCKTxPower(dev, powerlevel);
2835                         PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2836 #endif
2837                         break;
2838
2839                 case RF_6052:
2840                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2841                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2842                         break;
2843
2844                 case RF_8258:
2845                         break;
2846                 default:
2847                         break;
2848         }
2849
2850 }
2851
2852 //
2853 //      Description:
2854 //              Update transmit power level of all channel supported.
2855 //
2856 //      TODO:
2857 //              A mode.
2858 //      By Bruce, 2008-02-04.
2859 //    no use temp
2860 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2861 {
2862         struct r8192_priv       *priv = ieee80211_priv(dev);
2863         u8                              idx;
2864         u8                              rf_path;
2865
2866         // TODO: A mode Tx power.
2867         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2868         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2869
2870         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2871                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2872         else
2873                 OfdmTxPwrIdx = 0;
2874
2875         for(idx = 0; idx < 14; idx++)
2876         {
2877                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2878                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2879                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2880                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2881                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2882                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2883
2884                 for (rf_path = 0; rf_path < 2; rf_path++)
2885                 {
2886                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2887                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2888                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2889                 }
2890         }
2891
2892         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2893
2894         return TRUE;
2895 }
2896
2897 /*
2898         Description:
2899                 When beacon interval is changed, the values of the
2900                 hw registers should be modified.
2901         By tynli, 2008.10.24.
2902
2903 */
2904
2905 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2906 {
2907         u32 NewBeaconNum;
2908
2909         NewBeaconNum = BeaconInterval *32 - 64;
2910         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2911         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2912         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2913         write_nic_dword(dev, WFM3, 0xB026007C);
2914 }
2915
2916 //
2917 //      Description:
2918 //              Map dBm into Tx power index according to
2919 //              current HW model, for example, RF and PA, and
2920 //              current wireless mode.
2921 //      By Bruce, 2008-01-29.
2922 //    use in phy only
2923 static u8 phy_DbmToTxPwrIdx(
2924         struct net_device* dev,
2925         WIRELESS_MODE   WirelessMode,
2926         long                    PowerInDbm
2927         )
2928 {
2929         //struct r8192_priv *priv = ieee80211_priv(dev);
2930         u8                              TxPwrIdx = 0;
2931         long                            Offset = 0;
2932
2933
2934         //
2935         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2936         // 3dbm, and OFDM HT equals to 0dbm repectively.
2937         // Note:
2938         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2939         // By Bruce, 2008-01-29.
2940         //
2941         switch(WirelessMode)
2942         {
2943         case WIRELESS_MODE_B:
2944                 Offset = -7;
2945                 break;
2946
2947         case WIRELESS_MODE_G:
2948         case WIRELESS_MODE_N_24G:
2949                 Offset = -8;
2950                 break;
2951         default:
2952                 break;
2953         }
2954
2955         if((PowerInDbm - Offset) > 0)
2956         {
2957                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2958         }
2959         else
2960         {
2961                 TxPwrIdx = 0;
2962         }
2963
2964         // Tx Power Index is too large.
2965         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2966                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2967
2968         return TxPwrIdx;
2969 }
2970 //
2971 //      Description:
2972 //              Map Tx power index into dBm according to
2973 //              current HW model, for example, RF and PA, and
2974 //              current wireless mode.
2975 //      By Bruce, 2008-01-29.
2976 //    use in phy only
2977 static long phy_TxPwrIdxToDbm(
2978         struct net_device* dev,
2979         WIRELESS_MODE   WirelessMode,
2980         u8                      TxPwrIdx
2981         )
2982 {
2983         //struct r8192_priv *priv = ieee80211_priv(dev);
2984         long                            Offset = 0;
2985         long                            PwrOutDbm = 0;
2986
2987         //
2988         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2989         // 3dbm, and OFDM HT equals to 0dbm repectively.
2990         // Note:
2991         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2992         // By Bruce, 2008-01-29.
2993         //
2994         switch(WirelessMode)
2995         {
2996         case WIRELESS_MODE_B:
2997                 Offset = -7;
2998                 break;
2999
3000         case WIRELESS_MODE_G:
3001         case WIRELESS_MODE_N_24G:
3002                 Offset = -8;
3003                 break;
3004         default:
3005                 break;
3006         }
3007
3008         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
3009
3010         return PwrOutDbm;
3011 }
3012
3013 #ifdef TO_DO_LIST
3014 extern  VOID
3015 PHY_ScanOperationBackup8192S(
3016         IN      PADAPTER        Adapter,
3017         IN      u1Byte          Operation
3018         )
3019 {
3020
3021         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
3022         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
3023         u4Byte                          BitMask;
3024         u1Byte                          initial_gain;
3025
3026
3027
3028
3029
3030         if(!Adapter->bDriverStopped)
3031         {
3032                 switch(Operation)
3033                 {
3034                         case SCAN_OPT_BACKUP:
3035                                 //
3036                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
3037                                 // and resume both two DMs while scan complete.
3038                                 // 2008.11.27.
3039                                 //
3040                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
3041                                 break;
3042
3043                         case SCAN_OPT_RESTORE:
3044                                 //
3045                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
3046                                 // recover earlier DIG settings.
3047                                 // 2008.11.27.
3048                                 //
3049                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
3050                                 break;
3051
3052                         default:
3053                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
3054                                 break;
3055                 }
3056         }
3057 }
3058 #endif
3059
3060 //nouse temp
3061 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
3062 {
3063
3064         //struct r8192_priv *priv = ieee80211_priv(dev);
3065         //u32                                   BitMask;
3066         //u8                                    initial_gain;
3067
3068 #if 0   // For 8192s test disable
3069         if(!dev->bDriverStopped)
3070         {
3071                 switch(Operation)
3072                 {
3073                         case IG_Backup:
3074                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
3075                                 initial_gain = priv->DefaultInitialGain[0];
3076                                 BitMask = bMaskByte0;
3077                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3078                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3079                                 pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3080                                 pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3081                                 pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3082                                 pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3083                                 BitMask  = bMaskByte2;
3084                                 pMgntInfo->InitGain_Backup.CCA          = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3085
3086                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3087                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3088                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3089                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3090                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3091
3092                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
3093                                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3094                                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3095                                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3096                                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3097                                 break;
3098                         case IG_Restore:
3099                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
3100                                 BitMask = 0x7f; //Bit0~ Bit6
3101                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3102                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3103
3104                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
3105                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
3106                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
3107                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
3108                                 BitMask  = (BIT22|BIT23);
3109                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
3110
3111                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3112                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3113                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3114                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3115                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3116
3117                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3118                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1);      // FW DIG ON
3119                                 break;
3120                         default:
3121                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
3122                                 break;
3123                 }
3124         }
3125 #endif
3126 }
3127
3128 /*-----------------------------------------------------------------------------
3129  * Function:    SetBWModeCallback8190Pci()
3130  *
3131  * Overview:    Timer callback function for SetSetBWMode
3132  *
3133  * Input:               PRT_TIMER               pTimer
3134  *
3135  * Output:      NONE
3136  *
3137  * Return:      NONE
3138  *
3139  * Note:                (1) We do not take j mode into consideration now
3140  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3141  *                           concurrently?
3142  *---------------------------------------------------------------------------*/
3143 //    use in phy only (in win it's timer)
3144 void PHY_SetBWModeCallback8192S(struct net_device *dev)
3145 {
3146         struct r8192_priv *priv = ieee80211_priv(dev);
3147         u8                              regBwOpMode;
3148
3149         //return;
3150
3151         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3152         //u32                           NowL, NowH;
3153         //u8Byte                                BeginTime, EndTime;
3154         u8                              regRRSR_RSC;
3155
3156         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3157                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3158
3159         if(priv->rf_chip == RF_PSEUDO_11N)
3160         {
3161                 priv->SetBWModeInProgress= FALSE;
3162                 return;
3163         }
3164
3165         if(!priv->up)
3166                 return;
3167
3168         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3169         //NowL = read_nic_dword(dev, TSFR);
3170         //NowH = read_nic_dword(dev, TSFR+4);
3171         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3172
3173         //3//
3174         //3//<1>Set MAC register
3175         //3//
3176         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3177         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3178
3179         switch(priv->CurrentChannelBW)
3180         {
3181                 case HT_CHANNEL_WIDTH_20:
3182                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3183                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3184
3185                         regBwOpMode |= BW_OPMODE_20MHZ;
3186                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3187                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3188                         break;
3189
3190                 case HT_CHANNEL_WIDTH_20_40:
3191                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3192                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3193
3194                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3195                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3196                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3197                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3198                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3199                         break;
3200
3201                 default:
3202                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
3203                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3204                         break;
3205         }
3206
3207         //3//
3208         //3//<2>Set PHY related register
3209         //3//
3210         switch(priv->CurrentChannelBW)
3211         {
3212                 /* 20 MHz channel*/
3213                 case HT_CHANNEL_WIDTH_20:
3214                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3215                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3216
3217                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3218                         // It is set in Tx descriptor for 8192x series
3219                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3220                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3221                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3222                         #if 0 //LZM 090219
3223                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
3224                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
3225                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
3226                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3227                         #endif
3228
3229                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3230                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3231
3232
3233                         break;
3234
3235                 /* 40 MHz channel*/
3236                 case HT_CHANNEL_WIDTH_20_40:
3237                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3238                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3239
3240                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3241                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3242                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3243                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3244                         #if 0 //LZM 090219
3245                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3246                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3247                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3248                         #endif
3249
3250                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3251                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3252                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3253
3254                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3255                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3256                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3257
3258                         break;
3259
3260                 default:
3261                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
3262                                                 ,priv->CurrentChannelBW);
3263                         break;
3264
3265         }
3266         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3267
3268         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3269         //NowL = read_nic_dword(dev, TSFR);
3270         //NowH = read_nic_dword(dev, TSFR+4);
3271         //EndTime = ((u8Byte)NowH << 32) + NowL;
3272         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3273
3274         //3<3>Set RF related register
3275         switch( priv->rf_chip )
3276         {
3277                 case RF_8225:
3278                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3279                         break;
3280
3281                 case RF_8256:
3282                         // Please implement this function in Hal8190PciPhy8256.c
3283                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3284                         break;
3285
3286                 case RF_8258:
3287                         // Please implement this function in Hal8190PciPhy8258.c
3288                         // PHY_SetRF8258Bandwidth();
3289                         break;
3290
3291                 case RF_PSEUDO_11N:
3292                         // Do Nothing
3293                         break;
3294
3295                 case RF_6052:
3296                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3297                         break;
3298                 default:
3299                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
3300                         break;
3301         }
3302
3303         priv->SetBWModeInProgress= FALSE;
3304
3305         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
3306 }
3307
3308
3309  /*-----------------------------------------------------------------------------
3310  * Function:   SetBWMode8190Pci()
3311  *
3312  * Overview:  This function is export to "HalCommon" moudule
3313  *
3314  * Input:               PADAPTER                        Adapter
3315  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
3316  *
3317  * Output:      NONE
3318  *
3319  * Return:      NONE
3320  *
3321  * Note:                We do not take j mode into consideration now
3322  *---------------------------------------------------------------------------*/
3323 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
3324 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
3325 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
3326 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3327 {
3328         struct r8192_priv *priv = ieee80211_priv(dev);
3329         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
3330
3331
3332         // Modified it for 20/40 mhz switch by guangan 070531
3333
3334         //return;
3335
3336         //if(priv->SwChnlInProgress)
3337 //      if(pMgntInfo->bScanInProgress)
3338 //      {
3339 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
3340 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3341 //              return;
3342 //      }
3343
3344 //      if(priv->SetBWModeInProgress)
3345 //      {
3346 //              // Modified it for 20/40 mhz switch by guangan 070531
3347 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
3348 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3349 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
3350 //              //return;
3351 //      }
3352
3353         if(priv->SetBWModeInProgress)
3354                 return;
3355
3356         priv->SetBWModeInProgress= TRUE;
3357
3358         priv->CurrentChannelBW = Bandwidth;
3359
3360         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3361                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3362         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3363                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3364         else
3365                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3366
3367 #if 0
3368         if(!priv->bDriverStopped)
3369         {
3370 #ifdef USE_WORKITEM
3371                 PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
3372 #else
3373                 PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
3374 #endif
3375         }
3376 #endif
3377         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
3378         {
3379 #ifdef RTL8192SE
3380         PHY_SetBWModeCallback8192S(dev);
3381 #elif defined(RTL8192SU)
3382         SetBWModeCallback8192SUsbWorkItem(dev);
3383 #endif
3384         }
3385         else
3386         {
3387                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
3388                 priv->SetBWModeInProgress= FALSE;
3389                 priv->CurrentChannelBW = tmpBW;
3390         }
3391 }
3392
3393 //    use in phy only (in win it's timer)
3394 void PHY_SwChnlCallback8192S(struct net_device *dev)
3395 {
3396
3397         struct r8192_priv *priv = ieee80211_priv(dev);
3398         u32             delay;
3399         //bool                  ret;
3400
3401         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
3402
3403         if(!priv->up)
3404                 return;
3405
3406         if(priv->rf_chip == RF_PSEUDO_11N)
3407         {
3408                 priv->SwChnlInProgress=FALSE;
3409                 return;                                                                 //return immediately if it is peudo-phy
3410         }
3411
3412         do{
3413                 if(!priv->SwChnlInProgress)
3414                         break;
3415
3416                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3417                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3418                 {
3419                         if(delay>0)
3420                         {
3421                                 mdelay(delay);
3422                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3423                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
3424                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
3425                                 //==>SwChnlCallback8192SUsb(dev) for 92su
3426                         }
3427                         else
3428                         continue;
3429                 }
3430                 else
3431                 {
3432                         priv->SwChnlInProgress=FALSE;
3433                         break;
3434                 }
3435         }while(true);
3436 }
3437
3438 // Call after initialization
3439 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
3440 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
3441 {
3442         struct r8192_priv *priv = ieee80211_priv(dev);
3443         //u8                    tmpchannel =channel;
3444         //bool                  bResult = false;
3445
3446         if(!priv->up)
3447                 return false;
3448
3449         if(priv->SwChnlInProgress)
3450                 return false;
3451
3452         if(priv->SetBWModeInProgress)
3453                 return false;
3454
3455         //--------------------------------------------
3456         switch(priv->ieee80211->mode)
3457         {
3458         case WIRELESS_MODE_A:
3459         case WIRELESS_MODE_N_5G:
3460                 if (channel<=14){
3461                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
3462                         return false;
3463                 }
3464                 break;
3465
3466         case WIRELESS_MODE_B:
3467                 if (channel>14){
3468                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
3469                         return false;
3470                 }
3471                 break;
3472
3473         case WIRELESS_MODE_G:
3474         case WIRELESS_MODE_N_24G:
3475                 if (channel>14){
3476                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
3477                         return false;
3478                 }
3479                 break;
3480
3481         default:
3482                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
3483                 break;
3484         }
3485         //--------------------------------------------
3486
3487         priv->SwChnlInProgress = TRUE;
3488         if( channel == 0)
3489                 channel = 1;
3490
3491         priv->chan=channel;
3492
3493         priv->SwChnlStage=0;
3494         priv->SwChnlStep=0;
3495
3496         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
3497         {
3498 #ifdef RTL8192SE
3499         PHY_SwChnlCallback8192S(dev);
3500 #elif defined(RTL8192SU)
3501         SwChnlCallback8192SUsbWorkItem(dev);
3502 #endif
3503 #ifdef TO_DO_LIST
3504         if(bResult)
3505                 {
3506                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
3507                 }
3508                 else
3509                 {
3510                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
3511                         priv->SwChnlInProgress = false;
3512                         priv->CurrentChannel = tmpchannel;
3513                 }
3514 #endif
3515         }
3516         else
3517         {
3518                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
3519                 priv->SwChnlInProgress = false;
3520                 //priv->CurrentChannel = tmpchannel;
3521         }
3522         return true;
3523 }
3524
3525
3526 //
3527 // Description:
3528 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
3529 //
3530 // Implemented by Bruce, 2008-02-14.
3531 // The following procedure is operted according to SwChanlCallback8190Pci().
3532 // However, this procedure is performed synchronously  which should be running under
3533 // passive level.
3534 //
3535 //not understant it
3536 void PHY_SwChnlPhy8192S(        // Only called during initialize
3537         struct net_device* dev,
3538         u8              channel
3539         )
3540 {
3541         struct r8192_priv *priv = ieee80211_priv(dev);
3542
3543         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
3544
3545 #ifdef TO_DO_LIST
3546         // Cannot IO.
3547         if(RT_CANNOT_IO(dev))
3548                 return;
3549 #endif
3550
3551         // Channel Switching is in progress.
3552         if(priv->SwChnlInProgress)
3553                 return;
3554
3555         //return immediately if it is peudo-phy
3556         if(priv->rf_chip == RF_PSEUDO_11N)
3557         {
3558                 priv->SwChnlInProgress=FALSE;
3559                 return;
3560         }
3561
3562         priv->SwChnlInProgress = TRUE;
3563         if( channel == 0)
3564                 channel = 1;
3565
3566         priv->chan=channel;
3567
3568         priv->SwChnlStage = 0;
3569         priv->SwChnlStep = 0;
3570
3571         phy_FinishSwChnlNow(dev,channel);
3572
3573         priv->SwChnlInProgress = FALSE;
3574 }
3575
3576 //    use in phy only
3577 static bool
3578 phy_SetSwChnlCmdArray(
3579         SwChnlCmd*              CmdTable,
3580         u32                     CmdTableIdx,
3581         u32                     CmdTableSz,
3582         SwChnlCmdID             CmdID,
3583         u32                     Para1,
3584         u32                     Para2,
3585         u32                     msDelay
3586         )
3587 {
3588         SwChnlCmd* pCmd;
3589
3590         if(CmdTable == NULL)
3591         {
3592                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3593                 return FALSE;
3594         }
3595         if(CmdTableIdx >= CmdTableSz)
3596         {
3597                 //RT_ASSERT(FALSE,
3598                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
3599                                 //CmdTableIdx, CmdTableSz));
3600                 return FALSE;
3601         }
3602
3603         pCmd = CmdTable + CmdTableIdx;
3604         pCmd->CmdID = CmdID;
3605         pCmd->Para1 = Para1;
3606         pCmd->Para2 = Para2;
3607         pCmd->msDelay = msDelay;
3608
3609         return TRUE;
3610 }
3611
3612 //    use in phy only
3613 static bool
3614 phy_SwChnlStepByStep(
3615         struct net_device* dev,
3616         u8              channel,
3617         u8              *stage,
3618         u8              *step,
3619         u32             *delay
3620         )
3621 {
3622         struct r8192_priv *priv = ieee80211_priv(dev);
3623         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
3624         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
3625         u32                                     PreCommonCmdCnt;
3626         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
3627         u32                                     PostCommonCmdCnt;
3628         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
3629         u32                                     RfDependCmdCnt;
3630         SwChnlCmd                               *CurrentCmd = NULL;
3631         u8                                      eRFPath;
3632
3633         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
3634         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
3635         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3636         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3637         if (!IsLegalChannel(priv->ieee80211, channel))
3638         {
3639                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
3640                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
3641         }
3642
3643         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3644         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3645
3646         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
3647         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3648         //{
3649                 // <1> Fill up pre common command.
3650         PreCommonCmdCnt = 0;
3651         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3652                                 CmdID_SetTxPowerLevel, 0, 0, 0);
3653         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3654                                 CmdID_End, 0, 0, 0);
3655
3656                 // <2> Fill up post common command.
3657         PostCommonCmdCnt = 0;
3658
3659         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3660                                 CmdID_End, 0, 0, 0);
3661
3662                 // <3> Fill up RF dependent command.
3663         RfDependCmdCnt = 0;
3664         switch( priv->rf_chip )
3665         {
3666                 case RF_8225:
3667                 if (channel < 1 || channel > 14)
3668                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3669                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3670                 // 2008/09/04 MH Change channel.
3671                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3672                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3673                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3674                 CmdID_End, 0, 0, 0);
3675                 break;
3676
3677         case RF_8256:
3678                 if (channel < 1 || channel > 14)
3679                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3680                 // TEST!! This is not the table for 8256!!
3681                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3682                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3683                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3684                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3685                 CmdID_End, 0, 0, 0);
3686                 break;
3687
3688         case RF_6052:
3689                 if (channel < 1 || channel > 14)
3690                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3691                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3692                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3693                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3694                         CmdID_End, 0, 0, 0);
3695                 break;
3696
3697         case RF_8258:
3698                 break;
3699
3700         default:
3701                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3702                 return FALSE;
3703                 break;
3704         }
3705
3706
3707         do{
3708                 switch(*stage)
3709                 {
3710                 case 0:
3711                         CurrentCmd=&PreCommonCmd[*step];
3712                         break;
3713                 case 1:
3714                         CurrentCmd=&RfDependCmd[*step];
3715                         break;
3716                 case 2:
3717                         CurrentCmd=&PostCommonCmd[*step];
3718                         break;
3719                 }
3720
3721                 if(CurrentCmd->CmdID==CmdID_End)
3722                 {
3723                         if((*stage)==2)
3724                         {
3725                                 return TRUE;
3726                         }
3727                         else
3728                         {
3729                                 (*stage)++;
3730                                 (*step)=0;
3731                                 continue;
3732                         }
3733                 }
3734
3735                 switch(CurrentCmd->CmdID)
3736                 {
3737                 case CmdID_SetTxPowerLevel:
3738                         //if(priv->card_8192_version > VERSION_8190_BD)
3739                                 PHY_SetTxPowerLevel8192S(dev,channel);
3740                         break;
3741                 case CmdID_WritePortUlong:
3742                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
3743                         break;
3744                 case CmdID_WritePortUshort:
3745                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
3746                         break;
3747                 case CmdID_WritePortUchar:
3748                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
3749                         break;
3750                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3751                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3752                         {
3753 #if (defined RTL8192SE ||defined RTL8192SU )
3754                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
3755                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
3756                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
3757 #else
3758                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
3759 #endif
3760                         }
3761                         break;
3762                 default:
3763                         break;
3764                 }
3765
3766                 break;
3767         }while(TRUE);
3768         //cosa }/*for(Number of RF paths)*/
3769
3770         (*delay)=CurrentCmd->msDelay;
3771         (*step)++;
3772         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3773         return FALSE;
3774 }
3775
3776 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
3777 //    use in phy only
3778 static void
3779 phy_FinishSwChnlNow(    // We should not call this function directly
3780         struct net_device* dev,
3781         u8              channel
3782                 )
3783 {
3784         struct r8192_priv       *priv = ieee80211_priv(dev);
3785         u32                     delay;
3786
3787         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
3788         {
3789                 if(delay>0)
3790                         mdelay(delay);
3791                 if(!priv->up)
3792                         break;
3793         }
3794 }
3795
3796
3797 /*-----------------------------------------------------------------------------
3798  * Function:    PHYCheckIsLegalRfPath8190Pci()
3799  *
3800  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3801  *                      We will return false.
3802  *
3803  * Input:               NONE
3804  *
3805  * Output:              NONE
3806  *
3807  * Return:              NONE
3808  *
3809  * Revised History:
3810  *      When            Who             Remark
3811  *      11/15/2007      MHC             Create Version 0.
3812  *
3813  *---------------------------------------------------------------------------*/
3814  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3815 //extern        bool
3816 //PHY_CheckIsLegalRfPath8192S(
3817 //      struct net_device* dev,
3818 //      u32     eRFPath)
3819 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3820 {
3821 //      struct r8192_priv *priv = ieee80211_priv(dev);
3822         bool                            rtValue = TRUE;
3823
3824         // NOt check RF Path now.!
3825 #if 0
3826         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3827         {
3828                 rtValue = FALSE;
3829         }
3830         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3831         {
3832
3833         }
3834 #endif
3835         return  rtValue;
3836
3837 }       /* PHY_CheckIsLegalRfPath8192S */
3838
3839
3840
3841 /*-----------------------------------------------------------------------------
3842  * Function:    PHY_IQCalibrate8192S()
3843  *
3844  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3845  *                      to improve RF EVM!!?
3846  *
3847  * Input:               IN      PADAPTER        pAdapter
3848  *
3849  * Output:              NONE
3850  *
3851  * Return:              NONE
3852  *
3853  * Revised History:
3854  *      When            Who             Remark
3855  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3856  *
3857  *---------------------------------------------------------------------------*/
3858  //called by InitializeAdapter8192SE
3859 void
3860 PHY_IQCalibrate(        struct net_device* dev)
3861 {
3862         //struct r8192_priv     *priv = ieee80211_priv(dev);
3863         u32                             i, reg;
3864         u32                             old_value;
3865         long                            X, Y, TX0[4];
3866         u32                             TXA[4];
3867
3868         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3869
3870         //
3871         // 2. QFN 68
3872         //
3873         // For 1T2R IQK only now !!!
3874         for (i = 0; i < 10; i++)
3875         {
3876                 // IQK
3877                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3878                 //PlatformStallExecution(5);
3879                 udelay(5);
3880                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3881                 udelay(5);
3882                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3883                 udelay(5);
3884                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3885                 udelay(5);
3886                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3887                 udelay(5);
3888                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3889                 udelay(5);
3890                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3891                 udelay(5);
3892                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3893                 udelay(5);
3894                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3895                 udelay(5);
3896                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3897                 udelay(5);
3898                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3899                 udelay(2000);
3900                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3901                 udelay(5);
3902                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3903                 udelay(5);
3904                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3905
3906
3907                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3908
3909                 // Readback IQK value and rewrite
3910                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3911                 {
3912                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3913
3914                         // Calibrate init gain for A path for TX0
3915                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3916                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3917                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3918                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3919                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3920                         udelay(5);
3921
3922                         // Calibrate init gain for C path for TX0
3923                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3924                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3925                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3926                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3927                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3928                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3929                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3930                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3931                         udelay(5);
3932
3933                         // Calibrate RX A and B for RX0
3934                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3935                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3936                         reg = (reg & 0xFFFFFC00) |X;
3937                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3938                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3939                         reg = (reg & 0xFFFF03FF) |Y<<10;
3940                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3941                         udelay(5);
3942                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3943
3944                         // Calibrate init gain for A path for TX1 !!!!!!
3945                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3946                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3947                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3948                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3949                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3950                         udelay(5);
3951
3952                         // Calibrate init gain for C path for TX1
3953                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3954                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3955                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3956                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3957                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3958                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3959                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3960                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3961                         udelay(5);
3962
3963                         // Calibrate RX A and B for RX1
3964                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3965                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3966                         reg = (reg & 0xFFFFFC00) |X;
3967                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3968
3969                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3970                         reg = (reg & 0xFFFF03FF) |Y<<10;
3971                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3972                         udelay(5);
3973
3974                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3975                         break;
3976                 }
3977
3978         }
3979
3980
3981         //
3982         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3983         //
3984
3985
3986 }
3987
3988 /*-----------------------------------------------------------------------------
3989  * Function:    PHY_IQCalibrateBcut()
3990  *
3991  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3992  *                      to improve RF EVM!!?
3993  *
3994  * Input:               IN      PADAPTER        pAdapter
3995  *
3996  * Output:              NONE
3997  *
3998  * Return:              NONE
3999  *
4000  * Revised History:
4001  *      When            Who             Remark
4002  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
4003  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
4004  *
4005  *---------------------------------------------------------------------------*/
4006 extern void PHY_IQCalibrateBcut(struct net_device* dev)
4007 {
4008         //struct r8192_priv     *priv = ieee80211_priv(dev);
4009         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
4010         u32                             i, reg;
4011         u32                             old_value;
4012         long                            X, Y, TX0[4];
4013         u32                             TXA[4];
4014         u32                             calibrate_set[13] = {0};
4015         u32                             load_value[13];
4016         u8                              RfPiEnable=0;
4017
4018         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
4019
4020         //
4021         // 1. Save e70~ee0 register setting, and load calibration setting
4022         //
4023         /*
4024         0xee0[31:0]=0x3fed92fb;
4025         0xedc[31:0] =0x3fed92fb;
4026         0xe70[31:0] =0x3fed92fb;
4027         0xe74[31:0] =0x3fed92fb;
4028         0xe78[31:0] =0x3fed92fb;
4029         0xe7c[31:0]= 0x3fed92fb;
4030         0xe80[31:0]= 0x3fed92fb;
4031         0xe84[31:0]= 0x3fed92fb;
4032         0xe88[31:0]= 0x3fed92fb;
4033         0xe8c[31:0]= 0x3fed92fb;
4034         0xed0[31:0]= 0x3fed92fb;
4035         0xed4[31:0]= 0x3fed92fb;
4036         0xed8[31:0]= 0x3fed92fb;
4037         */
4038         calibrate_set [0] = 0xee0;
4039         calibrate_set [1] = 0xedc;
4040         calibrate_set [2] = 0xe70;
4041         calibrate_set [3] = 0xe74;
4042         calibrate_set [4] = 0xe78;
4043         calibrate_set [5] = 0xe7c;
4044         calibrate_set [6] = 0xe80;
4045         calibrate_set [7] = 0xe84;
4046         calibrate_set [8] = 0xe88;
4047         calibrate_set [9] = 0xe8c;
4048         calibrate_set [10] = 0xed0;
4049         calibrate_set [11] = 0xed4;
4050         calibrate_set [12] = 0xed8;
4051         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
4052         for (i = 0; i < 13; i++)
4053         {
4054                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
4055                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
4056
4057         }
4058
4059         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
4060
4061         //
4062         // 2. QFN 68
4063         //
4064         // For 1T2R IQK only now !!!
4065         for (i = 0; i < 10; i++)
4066         {
4067                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
4068                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
4069                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4070                 {
4071                         //DbgPrint("IQK Switch to PI mode\n");
4072                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
4073                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
4074                 }
4075
4076                 // IQK
4077                 // 2. IQ calibration & LO leakage calibration
4078                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
4079                 udelay(5);
4080                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
4081                 udelay(5);
4082                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
4083                 udelay(5);
4084                 //path-A IQ K and LO K gain setting
4085                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
4086                 udelay(5);
4087                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
4088                 udelay(5);
4089                 //set LO calibration
4090                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
4091                 udelay(5);
4092                 //path-B IQ K and LO K gain setting
4093                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
4094                 udelay(5);
4095                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
4096                 udelay(5);
4097                 //K idac_I & IQ
4098                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4099                 udelay(5);
4100                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4101                 udelay(5);
4102
4103                 // delay 2ms
4104                 udelay(2000);
4105
4106                 //idac_Q setting
4107                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
4108                 udelay(5);
4109                 //K idac_Q & IQ
4110                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4111                 udelay(5);
4112                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4113
4114                 // delay 2ms
4115                 udelay(2000);
4116
4117                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
4118                 udelay(5);
4119                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
4120                 udelay(5);
4121                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
4122
4123                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4124                 {
4125                         //DbgPrint("IQK Switch back to SI mode\n");
4126                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
4127                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
4128                 }
4129
4130
4131                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
4132
4133                 // 3.   check fail bit, and fill BB IQ matrix
4134                 // Readback IQK value and rewrite
4135                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
4136                 {
4137                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
4138
4139                         // Calibrate init gain for A path for TX0
4140                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
4141                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
4142                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4143                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
4144                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4145                         udelay(5);
4146
4147                         // Calibrate init gain for C path for TX0
4148                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
4149                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4150                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4151                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
4152                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4153                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
4154                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4155                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
4156                         udelay(5);
4157
4158                         // Calibrate RX A and B for RX0
4159                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
4160                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
4161                         reg = (reg & 0xFFFFFC00) |X;
4162                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4163                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
4164                         reg = (reg & 0xFFFF03FF) |Y<<10;
4165                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4166                         udelay(5);
4167                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4168
4169                         // Calibrate init gain for A path for TX1 !!!!!!
4170                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4171                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4172                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4173                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4174                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4175                         udelay(5);
4176
4177                         // Calibrate init gain for C path for TX1
4178                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4179                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4180                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4181                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4182                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4183                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4184                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4185                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4186                         udelay(5);
4187
4188                         // Calibrate RX A and B for RX1
4189                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4190                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4191                         reg = (reg & 0xFFFFFC00) |X;
4192                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4193
4194                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4195                         reg = (reg & 0xFFFF03FF) |Y<<10;
4196                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4197                         udelay(5);
4198
4199                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4200                         break;
4201                 }
4202
4203         }
4204
4205         //
4206         // 4. Reload e70~ee0 register setting.
4207         //
4208         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
4209         for (i = 0; i < 13; i++)
4210                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
4211
4212
4213         //
4214         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4215         //
4216
4217
4218
4219 }       // PHY_IQCalibrateBcut
4220
4221
4222 //
4223 // Move from phycfg.c to gen.c to be code independent later
4224 //
4225 //-------------------------Move to other DIR later----------------------------*/
4226 //#if (DEV_BUS_TYPE == USB_INTERFACE)
4227 #ifdef RTL8192SU
4228
4229 //    use in phy only (in win it's timer)
4230 void SwChnlCallback8192SUsb(struct net_device *dev)
4231 {
4232
4233         struct r8192_priv *priv = ieee80211_priv(dev);
4234         u32                     delay;
4235 //      bool                    ret;
4236
4237         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
4238                                 %d\n", priv->chan);
4239
4240
4241         if(!priv->up)
4242                 return;
4243
4244         if(priv->rf_chip == RF_PSEUDO_11N)
4245         {
4246                 priv->SwChnlInProgress=FALSE;
4247                 return;                                                                 //return immediately if it is peudo-phy
4248         }
4249
4250         do{
4251                 if(!priv->SwChnlInProgress)
4252                         break;
4253
4254                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
4255                 {
4256                         if(delay>0)
4257                         {
4258                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
4259
4260                         }
4261                         else
4262                         continue;
4263                 }
4264                 else
4265                 {
4266                         priv->SwChnlInProgress=FALSE;
4267                 }
4268                 break;
4269         }while(TRUE);
4270 }
4271
4272
4273 //
4274 // Callback routine of the work item for switch channel.
4275 //
4276 //    use in phy only (in win it's work)
4277 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
4278 {
4279         struct r8192_priv *priv = ieee80211_priv(dev);
4280
4281         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
4282 #ifdef TO_DO_LIST
4283         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
4284         {
4285                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
4286
4287                 pHalData->SwChnlInProgress = FALSE;
4288                 return;
4289         }
4290 #endif
4291         phy_FinishSwChnlNow(dev, priv->chan);
4292         priv->SwChnlInProgress = FALSE;
4293
4294         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
4295 }
4296
4297
4298 /*-----------------------------------------------------------------------------
4299  * Function:    SetBWModeCallback8192SUsb()
4300  *
4301  * Overview:    Timer callback function for SetSetBWMode
4302  *
4303  * Input:               PRT_TIMER               pTimer
4304  *
4305  * Output:      NONE
4306  *
4307  * Return:      NONE
4308  *
4309  * Note:                (1) We do not take j mode into consideration now
4310  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
4311  *                           concurrently?
4312  *---------------------------------------------------------------------------*/
4313 //====>//rtl8192_SetBWMode
4314 //    use in phy only (in win it's timer)
4315 void SetBWModeCallback8192SUsb(struct net_device *dev)
4316 {
4317         struct r8192_priv *priv = ieee80211_priv(dev);
4318         u8                              regBwOpMode;
4319
4320         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4321         //u32                           NowL, NowH;
4322         //u8Byte                                BeginTime, EndTime;
4323         u8                              regRRSR_RSC;
4324
4325         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
4326                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4327
4328         if(priv->rf_chip == RF_PSEUDO_11N)
4329         {
4330                 priv->SetBWModeInProgress= FALSE;
4331                 return;
4332         }
4333
4334         if(!priv->up)
4335                 return;
4336
4337         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4338         //NowL = read_nic_dword(dev, TSFR);
4339         //NowH = read_nic_dword(dev, TSFR+4);
4340         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4341
4342         //3<1>Set MAC register
4343         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4344         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4345
4346         switch(priv->CurrentChannelBW)
4347         {
4348                 case HT_CHANNEL_WIDTH_20:
4349                         regBwOpMode |= BW_OPMODE_20MHZ;
4350                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4351                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4352                         break;
4353
4354                 case HT_CHANNEL_WIDTH_20_40:
4355                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4356                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4357                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4358
4359                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4360                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4361                         break;
4362
4363                 default:
4364                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
4365                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4366                         break;
4367         }
4368
4369         //3 <2>Set PHY related register
4370         switch(priv->CurrentChannelBW)
4371         {
4372                 case HT_CHANNEL_WIDTH_20:
4373                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4374                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4375                         #if 0 //LZM090219
4376                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4377
4378                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4379                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
4380                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
4381                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
4382                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4383                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4384                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4385                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4386                         #endif
4387
4388                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4389                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4390
4391                         break;
4392                 case HT_CHANNEL_WIDTH_20_40:
4393                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4394                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4395                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4396                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4397
4398                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4399                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4400                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4401                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4402                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4403
4404                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4405                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4406
4407                         break;
4408                 default:
4409                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
4410                                                 ,priv->CurrentChannelBW);
4411                         break;
4412
4413         }
4414         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4415
4416         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4417         //NowL = read_nic_dword(dev, TSFR);
4418         //NowH = read_nic_dword(dev, TSFR+4);
4419         //EndTime = ((u8Byte)NowH << 32) + NowL;
4420         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
4421
4422 #if 1
4423         //3<3>Set RF related register
4424         switch( priv->rf_chip )
4425         {
4426                 case RF_8225:
4427                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4428                         break;
4429
4430                 case RF_8256:
4431                         // Please implement this function in Hal8190PciPhy8256.c
4432                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4433                         break;
4434
4435                 case RF_6052:
4436                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4437                         break;
4438
4439                 case RF_8258:
4440                         // Please implement this function in Hal8190PciPhy8258.c
4441                         // PHY_SetRF8258Bandwidth();
4442                         break;
4443
4444                 case RF_PSEUDO_11N:
4445                         // Do Nothing
4446                         break;
4447
4448                 default:
4449                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4450                         break;
4451         }
4452 #endif
4453         priv->SetBWModeInProgress= FALSE;
4454
4455         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
4456 }
4457
4458 //
4459 // Callback routine of the work item for set bandwidth mode.
4460 //
4461 //    use in phy only (in win it's work)
4462 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
4463 {
4464         struct r8192_priv               *priv = ieee80211_priv(dev);
4465         u8                              regBwOpMode;
4466
4467         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4468         //u32                           NowL, NowH;
4469         //u8Byte                                BeginTime, EndTime;
4470         u8                      regRRSR_RSC;
4471
4472         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
4473                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4474
4475         if(priv->rf_chip == RF_PSEUDO_11N)
4476         {
4477                 priv->SetBWModeInProgress= FALSE;
4478                 return;
4479         }
4480
4481         if(!priv->up)
4482                 return;
4483
4484         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4485         //NowL = read_nic_dword(dev, TSFR);
4486         //NowH = read_nic_dword(dev, TSFR+4);
4487         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4488
4489         //3<1>Set MAC register
4490         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4491         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4492
4493         switch(priv->CurrentChannelBW)
4494         {
4495                 case HT_CHANNEL_WIDTH_20:
4496                         regBwOpMode |= BW_OPMODE_20MHZ;
4497                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4498                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4499                         break;
4500
4501                 case HT_CHANNEL_WIDTH_20_40:
4502                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4503                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4504                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4505                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4506                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4507
4508                         break;
4509
4510                 default:
4511                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
4512                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4513                         break;
4514         }
4515
4516         //3 <2>Set PHY related register
4517         switch(priv->CurrentChannelBW)
4518         {
4519                 case HT_CHANNEL_WIDTH_20:
4520                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4521                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4522
4523                         #if 0 //LZM 090219
4524                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
4525
4526                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4527                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4528                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4529                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4530                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
4531                         #endif
4532
4533                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4534
4535                         break;
4536                 case HT_CHANNEL_WIDTH_20_40:
4537                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4538                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4539                         #if 0 //LZM 090219
4540                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4541
4542                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4543
4544                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4545                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4546                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4547                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4548                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4549                         #endif
4550
4551                         // Set Control channel to upper or lower. These settings are required only for 40MHz
4552                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4553                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4554
4555                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4556
4557                         break;
4558
4559
4560                 default:
4561                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
4562                                                 ,priv->CurrentChannelBW);
4563                         break;
4564
4565         }
4566         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4567
4568         //3<3>Set RF related register
4569         switch( priv->rf_chip )
4570         {
4571                 case RF_8225:
4572                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4573                         break;
4574
4575                 case RF_8256:
4576                         // Please implement this function in Hal8190PciPhy8256.c
4577                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4578                         break;
4579
4580                 case RF_6052:
4581                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4582                         break;
4583
4584                 case RF_8258:
4585                         // Please implement this function in Hal8190PciPhy8258.c
4586                         // PHY_SetRF8258Bandwidth();
4587                         break;
4588
4589                 case RF_PSEUDO_11N:
4590                         // Do Nothing
4591                         break;
4592
4593                 default:
4594                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4595                         break;
4596         }
4597
4598         priv->SetBWModeInProgress= FALSE;
4599
4600         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
4601 }
4602
4603 //--------------------------Move to oter DIR later-------------------------------*/
4604 #ifdef RTL8192SU
4605 void InitialGain8192S(struct net_device *dev,   u8 Operation)
4606 {
4607 #ifdef TO_DO_LIST
4608         struct r8192_priv *priv = ieee80211_priv(dev);
4609 #endif
4610
4611 }
4612 #endif
4613
4614 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
4615 {
4616         struct r8192_priv *priv = ieee80211_priv(dev);
4617
4618         priv->InitialGainOperateType = Operation;
4619
4620         if(priv->up)
4621         {
4622                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
4623         }
4624 }
4625
4626 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
4627 {
4628         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4629        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
4630        struct net_device *dev = priv->ieee80211->dev;
4631 #define SCAN_RX_INITIAL_GAIN    0x17
4632 #define POWER_DETECTION_TH      0x08
4633         u32     BitMask;
4634         u8      initial_gain;
4635         u8      Operation;
4636
4637         Operation = priv->InitialGainOperateType;
4638
4639         switch(Operation)
4640         {
4641                 case IG_Backup:
4642                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
4643                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
4644                         BitMask = bMaskByte0;
4645                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4646                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4647                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
4648                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
4649                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
4650                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
4651                         BitMask  = bMaskByte2;
4652                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
4653
4654                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4655                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4656                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4657                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4658                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
4659
4660                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
4661                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
4662                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
4663                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
4664                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
4665                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
4666                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
4667                         break;
4668                 case IG_Restore:
4669                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
4670                         BitMask = 0x7f; //Bit0~ Bit6
4671                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4672                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4673
4674                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
4675                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
4676                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
4677                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
4678                         BitMask  = bMaskByte2;
4679                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
4680
4681                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4682                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4683                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4684                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4685                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
4686
4687                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
4688
4689                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4690                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
4691                         break;
4692                 default:
4693                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
4694                         break;
4695         }
4696 }
4697
4698 #endif  // #if (DEV_BUS_TYPE == USB_INTERFACE)
4699
4700 //-----------------------------------------------------------------------------
4701 //      Description:
4702 //              Schedule workitem to send specific CMD IO to FW.
4703 //      Added by Roger, 2008.12.03.
4704 //
4705 //-----------------------------------------------------------------------------
4706 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
4707 {
4708         struct r8192_priv *priv = ieee80211_priv(dev);
4709         u16     FwCmdWaitCounter = 0;
4710
4711         u16     FwCmdWaitLimit = 1000;
4712
4713         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
4714         if(priv->bInHctTest)
4715                 return true;
4716
4717         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
4718
4719         // Will be done by high power respectively.
4720         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
4721         {
4722                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
4723                 return false;
4724         }
4725
4726 #if 1
4727         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
4728         {
4729                 //if(RT_USB_CANNOT_IO(Adapter))
4730                 //{
4731                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
4732                 //      return FALSE;
4733                 //}
4734
4735                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
4736                 return false;
4737                 FwCmdWaitCounter ++;
4738                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
4739                 udelay(100);
4740         }
4741
4742         if(FwCmdWaitCounter == FwCmdWaitLimit)
4743         {
4744                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
4745                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
4746                 //return false;
4747         }
4748 #endif
4749         if (priv->SetFwCmdInProgress)
4750         {
4751                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
4752                 return false;
4753         }
4754         priv->SetFwCmdInProgress = TRUE;
4755         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
4756
4757         phy_SetFwCmdIOCallback(dev);
4758         return true;
4759 }
4760 void ChkFwCmdIoDone(struct net_device* dev)
4761 {
4762         u16 PollingCnt = 1000;
4763         u32 tmpValue;
4764
4765         do
4766         {// Make sure that CMD IO has be accepted by FW.
4767 #ifdef TO_DO_LIST
4768                 if(RT_USB_CANNOT_IO(Adapter))
4769                 {
4770                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
4771                         return;
4772                 }
4773 #endif
4774                 udelay(10); // sleep 20us
4775                 tmpValue = read_nic_dword(dev, WFM5);
4776                 if(tmpValue == 0)
4777                 {
4778                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
4779                         break;
4780                 }
4781                 else
4782                 {
4783                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
4784                 }
4785         }while( --PollingCnt );
4786
4787         if(PollingCnt == 0)
4788         {
4789                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
4790         }
4791 }
4792 //      Callback routine of the timer callback for FW Cmd IO.
4793 //
4794 //      Description:
4795 //              This routine will send specific CMD IO to FW and check whether it is done.
4796 //
4797 void phy_SetFwCmdIOCallback(struct net_device* dev)
4798 {
4799         //struct net_device* dev = (struct net_device*) data;
4800         u32             input;
4801         static u32 ScanRegister;
4802         struct r8192_priv *priv = ieee80211_priv(dev);
4803         if(!priv->up)
4804         {
4805                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
4806                 return;
4807         }
4808
4809         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
4810
4811         switch(priv->CurrentFwCmdIO)
4812         {
4813                 case FW_CMD_HIGH_PWR_ENABLE:
4814                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4815                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
4816                         break;
4817
4818                 case FW_CMD_HIGH_PWR_DISABLE:
4819                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
4820                         break;
4821
4822                 case FW_CMD_DIG_RESUME:
4823                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4824                         break;
4825
4826                 case FW_CMD_DIG_HALT:
4827                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4828                         break;
4829
4830                 //
4831                 // <Roger_Notes> The following FW CMD IO was combined into single operation
4832                 // (i.e., to prevent number of system workitem out of resource!!).
4833                 // 2008.12.04.
4834                 //
4835                 case FW_CMD_RESUME_DM_BY_SCAN:
4836                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
4837                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4838                         {
4839                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
4840                                 ChkFwCmdIoDone(dev);
4841                         }
4842                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4843                         break;
4844
4845                 case FW_CMD_PAUSE_DM_BY_SCAN:
4846                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
4847                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4848                         ChkFwCmdIoDone(dev);
4849                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4850                         break;
4851
4852                 //
4853                 // <Roger_Notes> The following FW CMD IO should be checked
4854                 // (i.e., workitem schedule timing issue!!).
4855                 // 2008.12.04.
4856                 //
4857                 case FW_CMD_DIG_DISABLE:
4858                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4859                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4860                         break;
4861
4862                 case FW_CMD_DIG_ENABLE:
4863                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4864                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4865                         break;
4866
4867                 case FW_CMD_RA_RESET:
4868                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4869                         break;
4870
4871                 case FW_CMD_RA_ACTIVE:
4872                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4873                         break;
4874
4875                 case FW_CMD_RA_REFRESH_N:
4876                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4877                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4878                                 input = FW_RA_REFRESH;
4879                         else
4880                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4881                         write_nic_dword(dev, WFM5, input);
4882                         break;
4883                 case FW_CMD_RA_REFRESH_BG:
4884                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4885                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4886                         ChkFwCmdIoDone(dev);
4887                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4888                         break;
4889
4890                 case FW_CMD_IQK_ENABLE:
4891                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4892                         break;
4893
4894                 case FW_CMD_TXPWR_TRACK_ENABLE:
4895                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4896                         break;
4897
4898                 case FW_CMD_TXPWR_TRACK_DISABLE:
4899                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4900                         break;
4901
4902                 default:
4903                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4904                         break;
4905         }
4906
4907         ChkFwCmdIoDone(dev);
4908
4909         switch(priv->CurrentFwCmdIO)
4910         {
4911                 case FW_CMD_HIGH_PWR_DISABLE:
4912                         //if(pMgntInfo->bTurboScan)
4913                         {
4914                                 //Lower initial gain
4915                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4916                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4917                                 // CCA threshold
4918                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4919                                 // Disable OFDM Part
4920                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4921                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4922                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4923                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4924                         }
4925                         break;
4926
4927                 case FW_CMD_HIGH_PWR_ENABLE:
4928                         //if(pMgntInfo->bTurboScan)
4929                         {
4930                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4931                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4932
4933                                 // CCA threshold
4934                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4935                                 // Enable OFDM Part
4936                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4937
4938                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4939                                 if(ScanRegister != 0){
4940                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4941                                 }
4942
4943                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4944                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4945                                 else
4946                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4947                         }
4948                         break;
4949         }
4950
4951         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
4952         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
4953
4954 }
4955