SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_phy.c

   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #include "r8192S_hw.h"
  39 #include "r8192S_phy.h"
  40 #include "r8192S_phyreg.h"
  41 #include "r8192SU_HWImg.h"
  42 //#include "r8192S_FwImgDTM.h"
  43
  44 #include "ieee80211/dot11d.h"
  45
  46 /*---------------------------Define Local Constant---------------------------*/
  47 /* Channel switch:The size of command tables for switch channel*/
  48 #define MAX_PRECMD_CNT 16
  49 #define MAX_RFDEPENDCMD_CNT 16
  50 #define MAX_POSTCMD_CNT 16
  51 #define MAX_DOZE_WAITING_TIMES_9x 64
  52
  53 /*------------------------Define local variable------------------------------*/
  54 // 2004-05-11
  55
  56 static  u32
  57 phy_CalculateBitShift(u32 BitMask);
  58 static  RT_STATUS
  59 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  60 static void
  61 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  62 static  RT_STATUS
  63 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  64 static  RT_STATUS
  65 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  66 static bool
  67 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  68 void
  69 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  70 void
  71 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  72 void
  73 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
  74 static void
  75 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
  76 static bool
  77 phy_SwChnlStepByStep(
  78         struct net_device* dev,
  79         u8              channel,
  80         u8              *stage,
  81         u8              *step,
  82         u32             *delay
  83         );
  84 static RT_STATUS
  85 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
  86 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
  87 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
  88 void phy_SetFwCmdIOCallback(struct net_device* dev);
  89
  90 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
  91 //
  92 // Description:
  93 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
  94 //
  95 // Assumption:
  96 //              -       Only use on RTL8192S USB interface.
  97 //              -       PASSIVE LEVEL
  98 //
  99 // Created by Roger, 2008.09.06.
 100 //
 101 //use in phy only
 102 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 103 {
 104         struct r8192_priv *priv = ieee80211_priv(dev);
 105         u32     ReturnValue = 0xffffffff;
 106         u8      PollingCnt = 50;
 107         u8      BBWaitCounter = 0;
 108
 109
 110         //
 111         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 112         // We have to make sure that previous BB I/O has been done.
 113         // 2008.08.20.
 114         //
 115         while(priv->bChangeBBInProgress)
 116         {
 117                 BBWaitCounter ++;
 118                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 119                 msleep(1); // 1 ms
 120
 121                 // Wait too long, return FALSE to avoid to be stuck here.
 122                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 123                 {
 124                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 125                         return ReturnValue;
 126                 }
 127         }
 128
 129         priv->bChangeBBInProgress = true;
 130
 131         read_nic_dword(dev, RegAddr);
 132
 133         do
 134         {// Make sure that access could be done.
 135                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 136                         break;
 137         }while( --PollingCnt );
 138
 139         if(PollingCnt == 0)
 140         {
 141                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 142         }
 143         else
 144         {
 145                 // Data FW read back.
 146                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 147                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 148         }
 149
 150         priv->bChangeBBInProgress = false;
 151
 152         return ReturnValue;
 153 }
 154
 155
 156
 157 //
 158 // Description:
 159 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 160 //
 161 // Assumption:
 162 //              -       Only use on RTL8192S USB interface.
 163 //              -       PASSIVE LEVEL
 164 //
 165 // Created by Roger, 2008.09.06.
 166 //
 167 //use in phy only
 168 void
 169 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 170 {
 171         struct r8192_priv *priv = ieee80211_priv(dev);
 172         u8      BBWaitCounter = 0;
 173
 174         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 175
 176         //
 177         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 178         // We have to make sure that previous BB I/O has been done.
 179         // 2008.08.20.
 180         //
 181         while(priv->bChangeBBInProgress)
 182         {
 183                 BBWaitCounter ++;
 184                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 185                 msleep(1); // 1 ms
 186
 187                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 188                 {
 189                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 190                         return;
 191                 }
 192         }
 193
 194         priv->bChangeBBInProgress = true;
 195         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 196         write_nic_dword(dev, RegAddr, Data);
 197
 198         priv->bChangeBBInProgress = false;
 199 }
 200
 201
 202
 203 //
 204 // Description:
 205 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 206 //
 207 // Assumption:
 208 //              -       Only use on RTL8192S USB interface.
 209 //              -       PASSIVE LEVEL
 210 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 211 //
 212 // Created by Roger, 2008.09.06.
 213 //
 214 //use in phy only
 215 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 216 {
 217
 218         struct r8192_priv *priv = ieee80211_priv(dev);
 219         //u32   value  = 0, ReturnValue = 0;
 220         u32     ReturnValue = 0;
 221         //u32   tmplong,tmplong2;
 222         u8      PollingCnt = 50;
 223         u8      RFWaitCounter = 0;
 224
 225
 226         //
 227         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 228         // We have to make sure that previous RF I/O has been done.
 229         // 2008.08.20.
 230         //
 231         while(priv->bChangeRFInProgress)
 232         {
 233                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 234                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 235                 down(&priv->rf_sem);
 236
 237                 RFWaitCounter ++;
 238                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 239                 msleep(1); // 1 ms
 240
 241                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 242                 {
 243                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 244                         return 0xffffffff;
 245                 }
 246                 else
 247                 {
 248                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 249                 }
 250         }
 251
 252         priv->bChangeRFInProgress = true;
 253         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 254
 255
 256         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 257
 258         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 259                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 260                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 261
 262         do
 263         {// Make sure that access could be done.
 264                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 265                         break;
 266         }while( --PollingCnt );
 267
 268         // Data FW read back.
 269         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 270
 271         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 272         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 273         up(&priv->rf_sem);
 274         priv->bChangeRFInProgress = false;
 275
 276         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 277
 278         return ReturnValue;
 279
 280 }
 281
 282
 283 //
 284 // Description:
 285 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 286 //
 287 // Assumption:
 288 //              -       Only use on RTL8192S USB interface.
 289 //              -       PASSIVE LEVEL
 290 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 291 //
 292 // Created by Roger, 2008.09.06.
 293 //
 294 //use in phy only
 295 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 296 {
 297
 298         struct r8192_priv *priv = ieee80211_priv(dev);
 299         u8      PollingCnt = 50;
 300         u8      RFWaitCounter = 0;
 301
 302
 303         //
 304         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 305         // We have to make sure that previous BB I/O has been done.
 306         // 2008.08.20.
 307         //
 308         while(priv->bChangeRFInProgress)
 309         {
 310                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 311                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 312                 down(&priv->rf_sem);
 313
 314                 RFWaitCounter ++;
 315                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 316                 msleep(1); // 1 ms
 317
 318                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 319                 {
 320                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 321                         return;
 322                 }
 323                 else
 324                 {
 325                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 326                 }
 327         }
 328
 329         priv->bChangeRFInProgress = true;
 330         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 331
 332
 333         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 334
 335         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 336         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 337                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 338                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 339
 340         do
 341         {// Make sure that access could be done.
 342                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 343                                 break;
 344         }while( --PollingCnt );
 345
 346         if(PollingCnt == 0)
 347         {
 348                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 349         }
 350
 351         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 352         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 353         up(&priv->rf_sem);
 354         priv->bChangeRFInProgress = false;
 355
 356 }
 357
 358
 359 /*---------------------Define local function prototype-----------------------*/
 360
 361
 362 /*----------------------------Function Body----------------------------------*/
 363 //
 364 // 1. BB register R/W API
 365 //
 366 /**
 367 * Function:     PHY_QueryBBReg
 368 *
 369 * OverView:     Read "sepcific bits" from BB register
 370 *
 371 * Input:
 372 *                       PADAPTER                Adapter,
 373 *                       u32                     RegAddr,                //The target address to be readback
 374 *                       u32                     BitMask         //The target bit position in the target address
 375 *                                                                               //to be readback
 376 * Output:       None
 377 * Return:               u32                     Data                    //The readback register value
 378 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 379 */
 380 //use phy dm core 8225 8256 6052
 381 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 382 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 383 {
 384
 385         u32     ReturnValue = 0, OriginalValue, BitShift;
 386
 387
 388         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 389
 390         //
 391         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 392         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 393         // infinite cycle.
 394         // 2008.09.06.
 395         //
 396 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 397         if(IS_BB_REG_OFFSET_92S(RegAddr))
 398         {
 399                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 400
 401                 if((RegAddr & 0x03) != 0)
 402                 {
 403                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 404                         return 0;
 405                 }
 406
 407         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 408         }
 409         else
 410         {
 411         OriginalValue = read_nic_dword(dev, RegAddr);
 412         }
 413
 414         BitShift = phy_CalculateBitShift(BitMask);
 415         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 416
 417         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 418         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 419         return (ReturnValue);
 420 }
 421
 422 /**
 423 * Function:     PHY_SetBBReg
 424 *
 425 * OverView:     Write "Specific bits" to BB register (page 8~)
 426 *
 427 * Input:
 428 *                       PADAPTER                Adapter,
 429 *                       u32                     RegAddr,                //The target address to be modified
 430 *                       u32                     BitMask         //The target bit position in the target address
 431 *                                                                               //to be modified
 432 *                       u32                     Data                    //The new register value in the target bit position
 433 *                                                                               //of the target address
 434 *
 435 * Output:       None
 436 * Return:               None
 437 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 438 */
 439 //use phy dm core 8225 8256
 440 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 441 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 442 {
 443         u32     OriginalValue, BitShift, NewValue;
 444
 445
 446         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 447
 448         //
 449         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 450         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 451         // infinite cycle.
 452         // 2008.09.06.
 453         //
 454 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 455         if(IS_BB_REG_OFFSET_92S(RegAddr))
 456         {
 457                 if((RegAddr & 0x03) != 0)
 458                 {
 459                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 460                         return;
 461                 }
 462
 463                 if(BitMask!= bMaskDWord)
 464                 {//if not "double word" write
 465                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 466                         BitShift = phy_CalculateBitShift(BitMask);
 467             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 468                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 469                 }else
 470                         phy_SetUsbBBReg(dev, RegAddr, Data);
 471         }
 472         else
 473         {
 474                 if(BitMask!= bMaskDWord)
 475                 {//if not "double word" write
 476                         OriginalValue = read_nic_dword(dev, RegAddr);
 477                         BitShift = phy_CalculateBitShift(BitMask);
 478                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 479                         write_nic_dword(dev, RegAddr, NewValue);
 480                 }else
 481                         write_nic_dword(dev, RegAddr, Data);
 482         }
 483
 484         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 485
 486         return;
 487 }
 488
 489
 490 //
 491 // 2. RF register R/W API
 492 //
 493 /**
 494 * Function:     PHY_QueryRFReg
 495 *
 496 * OverView:     Query "Specific bits" to RF register (page 8~)
 497 *
 498 * Input:
 499 *                       PADAPTER                Adapter,
 500 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 501 *                       u32                     RegAddr,                //The target address to be read
 502 *                       u32                     BitMask         //The target bit position in the target address
 503 *                                                                               //to be read
 504 *
 505 * Output:       None
 506 * Return:               u32                     Readback value
 507 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 508 */
 509 //in dm 8256 and phy
 510 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 511 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 512 {
 513         u32 Original_Value, Readback_Value, BitShift;//, flags;
 514         struct r8192_priv *priv = ieee80211_priv(dev);
 515
 516
 517         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 518
 519         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 520         {
 521                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 522                 return 0;
 523         }
 524
 525         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 526         {
 527                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 528                 return 0;
 529         }
 530
 531         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 532         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 533         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 534         down(&priv->rf_sem);
 535         //
 536         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 537         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 538         // infinite cycle.
 539         // 2008.09.06.
 540         //
 541 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 542         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 543         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 544
 545         BitShift =  phy_CalculateBitShift(BitMask);
 546         Readback_Value = (Original_Value & BitMask) >> BitShift;
 547         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 548         up(&priv->rf_sem);
 549         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 550
 551         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 552
 553         return (Readback_Value);
 554 }
 555
 556 /**
 557 * Function:     PHY_SetRFReg
 558 *
 559 * OverView:     Write "Specific bits" to RF register (page 8~)
 560 *
 561 * Input:
 562 *                       PADAPTER                Adapter,
 563 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 564 *                       u32                     RegAddr,                //The target address to be modified
 565 *                       u32                     BitMask         //The target bit position in the target address
 566 *                                                                               //to be modified
 567 *                       u32                     Data                    //The new register Data in the target bit position
 568 *                                                                               //of the target address
 569 *
 570 * Output:       None
 571 * Return:               None
 572 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 573 */
 574 //use phy  8225 8256
 575 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 576 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 577 {
 578
 579         struct r8192_priv *priv = ieee80211_priv(dev);
 580         u32 Original_Value, BitShift, New_Value;//, flags;
 581
 582         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 583                 RegAddr, BitMask, Data, eRFPath);
 584
 585         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 586         {
 587                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 588                 return ;
 589         }
 590         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 591         {
 592                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 593                 return;
 594         }
 595
 596         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 597         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 598         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 599         down(&priv->rf_sem);
 600         //
 601         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 602         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 603         // infinite cycle.
 604         // 2008.09.06.
 605         //
 606 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 607                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 608
 609                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 610                 {
 611                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 612                         BitShift =  phy_CalculateBitShift(BitMask);
 613                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 614                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 615                 }
 616                 else
 617                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 618         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 619         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 620         up(&priv->rf_sem);
 621         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 622         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 623                         RegAddr, BitMask, Data, eRFPath);
 624
 625 }
 626
 627 /**
 628 * Function:     phy_CalculateBitShift
 629 *
 630 * OverView:     Get shifted position of the BitMask
 631 *
 632 * Input:
 633 *                       u32             BitMask,
 634 *
 635 * Output:       none
 636 * Return:               u32             Return the shift bit bit position of the mask
 637 */
 638 //use in phy only
 639 static u32 phy_CalculateBitShift(u32 BitMask)
 640 {
 641         u32 i;
 642
 643         for(i=0; i<=31; i++)
 644         {
 645                 if ( ((BitMask>>i) &  0x1 ) == 1)
 646                         break;
 647         }
 648
 649         return (i);
 650 }
 651
 652
 653 //
 654 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 655 //
 656 /*-----------------------------------------------------------------------------
 657  * Function:    PHY_MACConfig8192S
 658  *
 659  * Overview:    Condig MAC by header file or parameter file.
 660  *
 661  * Input:       NONE
 662  *
 663  * Output:      NONE
 664  *
 665  * Return:      NONE
 666  *
 667  * Revised History:
 668  *  When                Who             Remark
 669  *  08/12/2008  MHC             Create Version 0.
 670  *
 671  *---------------------------------------------------------------------------*/
 672 //adapter_start
 673 extern bool PHY_MACConfig8192S(struct net_device* dev)
 674 {
 675         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 676
 677         //
 678         // Config MAC
 679         //
 680         rtStatus = phy_ConfigMACWithHeaderFile(dev);
 681         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
 682
 683 }
 684
 685 //adapter_start
 686 extern  bool
 687 PHY_BBConfig8192S(struct net_device* dev)
 688 {
 689         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
 690
 691         u8 PathMap = 0, index = 0, rf_num = 0;
 692         struct r8192_priv       *priv = ieee80211_priv(dev);
 693         phy_InitBBRFRegisterDefinition(dev);
 694
 695         //
 696         // Config BB and AGC
 697         //
 698         //switch( Adapter->MgntInfo.bRegHwParaFile )
 699         //{
 700         //      case 0:
 701         //              phy_BB8190_Config_HardCode(dev);
 702         //              break;
 703
 704         //      case 1:
 705                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
 706         //              break;
 707
 708         //      case 2:
 709                         // Partial Modify.
 710         //              phy_BB8190_Config_HardCode(dev);
 711         //              phy_BB8192S_Config_ParaFile(dev);
 712         //              break;
 713
 714         //      default:
 715         //              phy_BB8190_Config_HardCode(dev);
 716         //              break;
 717         //}
 718         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
 719                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
 720         priv->rf_pathmap = PathMap;
 721         for(index = 0; index<4; index++)
 722         {
 723                 if((PathMap>>index)&0x1)
 724                         rf_num++;
 725         }
 726
 727         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
 728                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
 729                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
 730                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
 731                 (priv->rf_type==RF_2T4R && rf_num!=4))
 732         {
 733                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
 734         }
 735         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
 736 }
 737
 738 //adapter_start
 739 extern  bool
 740 PHY_RFConfig8192S(struct net_device* dev)
 741 {
 742         struct r8192_priv       *priv = ieee80211_priv(dev);
 743         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 744
 745         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
 746
 747         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
 748         priv->rf_chip = RF_6052;
 749
 750         //
 751         // RF config
 752         //
 753         switch(priv->rf_chip)
 754         {
 755         case RF_8225:
 756         case RF_6052:
 757                 rtStatus = PHY_RF6052_Config(dev);
 758                 break;
 759
 760         case RF_8256:
 761                 //rtStatus = PHY_RF8256_Config(dev);
 762                 break;
 763
 764         case RF_8258:
 765                 break;
 766
 767         case RF_PSEUDO_11N:
 768                 //rtStatus = PHY_RF8225_Config(dev);
 769                 break;
 770         default:
 771             break;
 772         }
 773
 774         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
 775 }
 776
 777
 778 // Joseph test: new initialize order!!
 779 // Test only!! This part need to be re-organized.
 780 // Now it is just for 8256.
 781 //use in phy only
 782 #ifdef TO_DO_LIST
 783 static RT_STATUS
 784 phy_BB8190_Config_HardCode(struct net_device* dev)
 785 {
 786         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
 787         return RT_STATUS_SUCCESS;
 788 }
 789 #endif
 790
 791 /*-----------------------------------------------------------------------------
 792  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
 793  *
 794  * Overview:    This function
 795  *
 796  *
 797  * Input:       PADAPTER                Adapter
 798  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
 799  *
 800  * Output:      NONE
 801  *
 802  * Return:      RT_STATUS_SUCCESS: configuration file exist
 803  * When                 Who             Remark
 804  * 2008/11/10   tynli
 805  * use in phy only
 806  *---------------------------------------------------------------------------*/
 807 static RT_STATUS
 808 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
 809 {
 810         int i;
 811         struct r8192_priv       *priv = ieee80211_priv(dev);
 812         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
 813         u16                             PHY_REGArraytoXTXRLen;
 814
 815 //#if (HAL_CODE_BASE != RTL8192_S)
 816
 817         if(priv->rf_type == RF_1T1R)
 818         {
 819                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
 820                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
 821         }
 822         else if(priv->rf_type == RF_1T2R)
 823         {
 824                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
 825                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
 826         }
 827         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
 828         //{
 829         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
 830         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
 831         //}
 832         else
 833         {
 834                 return RT_STATUS_FAILURE;
 835         }
 836
 837         if(ConfigType == BaseBand_Config_PHY_REG)
 838         {
 839                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
 840                 {
 841                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
 842                                 mdelay(50);
 843                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
 844                                 mdelay(5);
 845                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
 846                                 mdelay(1);
 847                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
 848                                 udelay(50);
 849                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
 850                                 udelay(5);
 851                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
 852                                 udelay(1);
 853                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
 854                         //RT_TRACE(COMP_SEND,
 855                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
 856                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
 857                 }
 858         }
 859         else {
 860                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
 861         }
 862 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
 863         return RT_STATUS_SUCCESS;
 864 }
 865
 866
 867 //use in phy only
 868 static  RT_STATUS
 869 phy_BB8192S_Config_ParaFile(struct net_device* dev)
 870 {
 871         struct r8192_priv       *priv = ieee80211_priv(dev);
 872         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
 873         //u8                            u2RegValue;
 874         //u16                           u4RegValue;
 875         //char                          szBBRegFile[] = RTL819X_PHY_REG;
 876         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
 877         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
 878         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
 879         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
 880         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
 881
 882         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
 883
 884         //
 885         // 1. Read PHY_REG.TXT BB INIT!!
 886         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
 887         //
 888         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
 889             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
 890         {
 891                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
 892                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
 893                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
 894                   //so we should reconfig BB reg with the right PHY parameters.
 895                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
 896                 }
 897         }else
 898                 rtStatus = RT_STATUS_FAILURE;
 899
 900         if(rtStatus != RT_STATUS_SUCCESS){
 901                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
 902                 goto phy_BB8190_Config_ParaFile_Fail;
 903         }
 904
 905         //
 906         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
 907         //
 908         if (priv->AutoloadFailFlag == false)
 909         {
 910                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
 911         }
 912         if(rtStatus != RT_STATUS_SUCCESS){
 913                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
 914                 goto phy_BB8190_Config_ParaFile_Fail;
 915         }
 916
 917         //
 918         // 3. BB AGC table Initialization
 919         //
 920         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
 921
 922         if(rtStatus != RT_STATUS_SUCCESS){
 923                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
 924                 goto phy_BB8190_Config_ParaFile_Fail;
 925         }
 926
 927
 928         // Check if the CCK HighPower is turned ON.
 929         // This is used to calculate PWDB.
 930         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
 931
 932
 933 phy_BB8190_Config_ParaFile_Fail:
 934         return rtStatus;
 935 }
 936
 937 /*-----------------------------------------------------------------------------
 938  * Function:    phy_ConfigMACWithHeaderFile()
 939  *
 940  * Overview:    This function read BB parameters from Header file we gen, and do register
 941  *                        Read/Write
 942  *
 943  * Input:       PADAPTER                Adapter
 944  *                      char*                   pFileName
 945  *
 946  * Output:      NONE
 947  *
 948  * Return:      RT_STATUS_SUCCESS: configuration file exist
 949  *
 950  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
 951  *                      [Register][Mask][Value]
 952  *---------------------------------------------------------------------------*/
 953 //use in phy only
 954 static  RT_STATUS
 955 phy_ConfigMACWithHeaderFile(struct net_device* dev)
 956 {
 957         u32                                     i = 0;
 958         u32                                     ArrayLength = 0;
 959         u32*                                    ptrArray;
 960         //struct r8192_priv     *priv = ieee80211_priv(dev);
 961
 962 //#if (HAL_CODE_BASE != RTL8192_S)
 963         /*if(Adapter->bInHctTest)
 964         {
 965                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
 966                 ArrayLength = MACPHY_ArrayLengthDTM;
 967                 ptrArray = Rtl819XMACPHY_ArrayDTM;
 968         }
 969         else if(pHalData->bTXPowerDataReadFromEEPORM)
 970         {
 971 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
 972 //              ArrayLength = MACPHY_Array_PGLength;
 973 //              ptrArray = Rtl819XMACPHY_Array_PG;
 974
 975         }else*/
 976         { //2008.11.06 Modified by tynli.
 977                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
 978                 ArrayLength = MAC_2T_ArrayLength;
 979                 ptrArray = Rtl819XMAC_Array;
 980         }
 981
 982         /*for(i = 0 ;i < ArrayLength;i=i+3){
 983                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
 984                 if(ptrArray[i] == 0x318)
 985                 {
 986                         ptrArray[i+2] = 0x00000800;
 987                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
 988                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
 989                 }
 990                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
 991         }*/
 992         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
 993                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
 994         }
 995 //#endif
 996         return RT_STATUS_SUCCESS;
 997 }
 998
 999 /*-----------------------------------------------------------------------------
1000  * Function:    phy_ConfigBBWithHeaderFile()
1001  *
1002  * Overview:    This function read BB parameters from general file format, and do register
1003  *                        Read/Write
1004  *
1005  * Input:       PADAPTER                Adapter
1006  *                      u8                      ConfigType     0 => PHY_CONFIG
1007  *                                                                               1 =>AGC_TAB
1008  *
1009  * Output:      NONE
1010  *
1011  * Return:      RT_STATUS_SUCCESS: configuration file exist
1012  *
1013  *---------------------------------------------------------------------------*/
1014 //use in phy only
1015 static  RT_STATUS
1016 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1017 {
1018         int             i;
1019         //u8            ArrayLength;
1020         u32*    Rtl819XPHY_REGArray_Table;
1021         u32*    Rtl819XAGCTAB_Array_Table;
1022         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1023         //struct r8192_priv *priv = ieee80211_priv(dev);
1024 //#if (HAL_CODE_BASE != RTL8192_S)
1025         /*if(Adapter->bInHctTest)
1026         {
1027
1028                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1029                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1030
1031                 if(pHalData->RF_Type == RF_2T4R)
1032                 {
1033                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1034                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1035                 }
1036                 else if (pHalData->RF_Type == RF_1T2R)
1037                 {
1038                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1039                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1040                 }
1041
1042         }
1043         else
1044         */
1045         //{
1046         //
1047         // 2008.11.06 Modified by tynli.
1048         //
1049         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1050         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1051         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1052         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1053         //}
1054
1055         if(ConfigType == BaseBand_Config_PHY_REG)
1056         {
1057                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1058                 {
1059                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1060                                 mdelay(50);
1061                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1062                                 mdelay(5);
1063                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1064                                 mdelay(1);
1065                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1066                                 udelay(50);
1067                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1068                                 udelay(5);
1069                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1070                                 udelay(1);
1071                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1072                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1073
1074                 }
1075         }
1076         else if(ConfigType == BaseBand_Config_AGC_TAB){
1077                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1078                 {
1079                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1080                 }
1081         }
1082 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1083         return RT_STATUS_SUCCESS;
1084 }
1085
1086 /*-----------------------------------------------------------------------------
1087  * Function:    phy_ConfigBBWithPgHeaderFile
1088  *
1089  * Overview:    Config PHY_REG_PG array
1090  *
1091  * Input:       NONE
1092  *
1093  * Output:      NONE
1094  *
1095  * Return:      NONE
1096  *
1097  * Revised History:
1098  * When                 Who             Remark
1099  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1100  * 11/10/2008   tynli           Modify to mew files.
1101  //use in phy only
1102  *---------------------------------------------------------------------------*/
1103 static RT_STATUS
1104 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1105 {
1106         int i;
1107         //u8 ArrayLength;
1108         u32*    Rtl819XPHY_REGArray_Table_PG;
1109         u16     PHY_REGArrayPGLen;
1110         //struct r8192_priv *priv = ieee80211_priv(dev);
1111 //#if (HAL_CODE_BASE != RTL8192_S)
1112         // Default: pHalData->RF_Type = RF_2T2R.
1113
1114         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1115         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1116
1117         if(ConfigType == BaseBand_Config_PHY_REG)
1118         {
1119                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1120                 {
1121                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1122                                 mdelay(50);
1123                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1124                                 mdelay(5);
1125                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1126                                 mdelay(1);
1127                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1128                                 udelay(50);
1129                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1130                                 udelay(5);
1131                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1132                                 udelay(1);
1133                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1134                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1135                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1136                 }
1137         }else{
1138                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1139         }
1140         return RT_STATUS_SUCCESS;
1141
1142 }       /* phy_ConfigBBWithPgHeaderFile */
1143
1144 /*-----------------------------------------------------------------------------
1145  * Function:    PHY_ConfigRFWithHeaderFile()
1146  *
1147  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1148  *
1149  * Input:       PADAPTER                        Adapter
1150  *                      char*                           pFileName
1151  *                      RF90_RADIO_PATH_E       eRFPath
1152  *
1153  * Output:      NONE
1154  *
1155  * Return:      RT_STATUS_SUCCESS: configuration file exist
1156  *
1157  * Note:                Delay may be required for RF configuration
1158  *---------------------------------------------------------------------------*/
1159 //in 8256 phy_RF8256_Config_ParaFile only
1160 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1161 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1162 {
1163
1164         struct r8192_priv *priv = ieee80211_priv(dev);
1165         int                     i;
1166         //u32*  pRFArray;
1167         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1168         u32                     *Rtl819XRadioA_Array_Table;
1169         u32                     *Rtl819XRadioB_Array_Table;
1170         //u32*  Rtl819XRadioC_Array_Table;
1171         //u32*  Rtl819XRadioD_Array_Table;
1172         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1173
1174         {       //2008.11.06 Modified by tynli
1175                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1176                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1177                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1178                 RadioB_ArrayLen = RadioB_ArrayLength;
1179         }
1180
1181         if( priv->rf_type == RF_2T2R_GREEN )
1182         {
1183                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1184                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1185         }
1186         else
1187         {
1188                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1189                 RadioB_ArrayLen = RadioB_ArrayLength;
1190         }
1191
1192         rtStatus = RT_STATUS_SUCCESS;
1193
1194         // When initialization, we want the delay function(mdelay(), delay_us()
1195         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1196         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1197         // to run at Dispatch level to achive it.
1198         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1199
1200         switch(eRFPath){
1201                 case RF90_PATH_A:
1202                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1203                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1204                                         { // Deay specific ms. Only RF configuration require delay.
1205 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1206                                                 mdelay(1000);
1207                                 }
1208                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1209                                                 mdelay(5);
1210                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1211                                                 mdelay(1);
1212                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1213                                                 udelay(50);
1214                                                 //PlatformStallExecution(50);
1215                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1216                                                 udelay(5);
1217                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1218                                                 udelay(1);
1219                                         else
1220                                         {
1221                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1222                                         }
1223                         }
1224                         break;
1225                 case RF90_PATH_B:
1226                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1227                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1228                                         { // Deay specific ms. Only RF configuration require delay.
1229 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1230                                                 mdelay(1000);
1231                                 }
1232                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1233                                                 mdelay(5);
1234                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1235                                                 mdelay(1);
1236                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1237                                                 udelay(50);
1238                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1239                                                 udelay(5);
1240                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1241                                                 udelay(1);
1242                                         else
1243                                         {
1244                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1245                                         }
1246                         }
1247                         break;
1248                 case RF90_PATH_C:
1249                         break;
1250                 case RF90_PATH_D:
1251                         break;
1252                 default:
1253                         break;
1254         }
1255
1256         return rtStatus;
1257
1258 }
1259
1260 /*-----------------------------------------------------------------------------
1261  * Function:    PHY_CheckBBAndRFOK()
1262  *
1263  * Overview:    This function is write register and then readback to make sure whether
1264  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
1265  *
1266  * Input:       PADAPTER                        Adapter
1267  *                      HW90_BLOCK_E            CheckBlock
1268  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
1269  *
1270  * Output:      NONE
1271  *
1272  * Return:      RT_STATUS_SUCCESS: PHY is OK
1273  *
1274  * Note:                This function may be removed in the ASIC
1275  *---------------------------------------------------------------------------*/
1276 //in 8256 phy_RF8256_Config_HardCode
1277 //but we don't use it temp
1278 RT_STATUS
1279 PHY_CheckBBAndRFOK(
1280         struct net_device* dev,
1281         HW90_BLOCK_E            CheckBlock,
1282         RF90_RADIO_PATH_E       eRFPath
1283         )
1284 {
1285         //struct r8192_priv *priv = ieee80211_priv(dev);
1286         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1287         u32                             i, CheckTimes = 4,ulRegRead = 0;
1288         u32                             WriteAddr[4];
1289         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1290
1291         // Initialize register address offset to be checked
1292         WriteAddr[HW90_BLOCK_MAC] = 0x100;
1293         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1294         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1295         WriteAddr[HW90_BLOCK_RF] = 0x3;
1296
1297         for(i=0 ; i < CheckTimes ; i++)
1298         {
1299
1300                 //
1301                 // Write Data to register and readback
1302                 //
1303                 switch(CheckBlock)
1304                 {
1305                 case HW90_BLOCK_MAC:
1306                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
1307                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
1308                         break;
1309
1310                 case HW90_BLOCK_PHY0:
1311                 case HW90_BLOCK_PHY1:
1312                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
1313                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
1314                         break;
1315
1316                 case HW90_BLOCK_RF:
1317                         // When initialization, we want the delay function(mdelay(), delay_us()
1318                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1319                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1320                         // to run at Dispatch level to achive it.
1321                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
1322                         WriteData[i] &= 0xfff;
1323                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
1324                         // TODO: we should not delay for such a long time. Ask SD3
1325                         mdelay(10);
1326                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1327                         mdelay(10);
1328                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
1329                         break;
1330
1331                 default:
1332                         rtStatus = RT_STATUS_FAILURE;
1333                         break;
1334                 }
1335
1336
1337                 //
1338                 // Check whether readback data is correct
1339                 //
1340                 if(ulRegRead != WriteData[i])
1341                 {
1342                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
1343                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
1344                         rtStatus = RT_STATUS_FAILURE;
1345                         break;
1346                 }
1347         }
1348
1349         return rtStatus;
1350 }
1351
1352 //no use temp in windows driver
1353 #ifdef TO_DO_LIST
1354 void
1355 PHY_SetRFPowerState8192SUsb(
1356         struct net_device* dev,
1357         RF_POWER_STATE  RFPowerState
1358         )
1359 {
1360         struct r8192_priv *priv = ieee80211_priv(dev);
1361         bool                    WaitShutDown = FALSE;
1362         u32                     DWordContent;
1363         //RF90_RADIO_PATH_E     eRFPath;
1364         u8                              eRFPath;
1365         BB_REGISTER_DEFINITION_T        *pPhyReg;
1366
1367         if(priv->SetRFPowerStateInProgress == TRUE)
1368                 return;
1369
1370         priv->SetRFPowerStateInProgress = TRUE;
1371
1372         // TODO: Emily, 2006.11.21, we should rewrite this function
1373
1374         if(RFPowerState==RF_SHUT_DOWN)
1375         {
1376                 RFPowerState=RF_OFF;
1377                 WaitShutDown=TRUE;
1378         }
1379
1380
1381         priv->RFPowerState = RFPowerState;
1382         switch( priv->rf_chip )
1383         {
1384         case RF_8225:
1385         case RF_6052:
1386                 switch( RFPowerState )
1387                 {
1388                 case RF_ON:
1389                         break;
1390
1391                 case RF_SLEEP:
1392                         break;
1393
1394                 case RF_OFF:
1395                         break;
1396                 }
1397                 break;
1398
1399         case RF_8256:
1400                 switch( RFPowerState )
1401                 {
1402                 case RF_ON:
1403                         break;
1404
1405                 case RF_SLEEP:
1406                         break;
1407
1408                 case RF_OFF:
1409                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
1410                         {
1411                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1412                                         continue;
1413
1414                                 pPhyReg = &priv->PHYRegDef[eRFPath];
1415                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
1416                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
1417                         }
1418                         break;
1419                 }
1420                 break;
1421
1422         case RF_8258:
1423                 break;
1424         }// switch( priv->rf_chip )
1425
1426         priv->SetRFPowerStateInProgress = FALSE;
1427 }
1428 #endif
1429
1430 #ifdef RTL8192U
1431 //no use temp in windows driver
1432 void
1433 PHY_UpdateInitialGain(
1434         struct net_device* dev
1435         )
1436 {
1437         struct r8192_priv       *priv = ieee80211_priv(dev);
1438         //unsigned char                 *IGTable;
1439         //u8                    DIG_CurrentInitialGain = 4;
1440
1441         switch(priv->rf_chip)
1442         {
1443         case RF_8225:
1444                 break;
1445         case RF_8256:
1446                 break;
1447         case RF_8258:
1448                 break;
1449         case RF_PSEUDO_11N:
1450                 break;
1451         case RF_6052:
1452                 break;
1453         default:
1454                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
1455                 break;
1456         }
1457 }
1458 #endif
1459
1460 //YJ,modified,090107
1461 void PHY_GetHWRegOriginalValue(struct net_device* dev)
1462 {
1463         struct r8192_priv *priv = ieee80211_priv(dev);
1464
1465         // read tx power offset
1466         // Simulate 8192
1467         priv->MCSTxPowerLevelOriginalOffset[0] =
1468                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
1469         priv->MCSTxPowerLevelOriginalOffset[1] =
1470                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
1471         priv->MCSTxPowerLevelOriginalOffset[2] =
1472                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
1473         priv->MCSTxPowerLevelOriginalOffset[3] =
1474                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
1475         priv->MCSTxPowerLevelOriginalOffset[4] =
1476                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
1477         priv->MCSTxPowerLevelOriginalOffset[5] =
1478                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
1479
1480         // Read CCK offset
1481         priv->MCSTxPowerLevelOriginalOffset[6] =
1482                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
1483         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
1484         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
1485         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
1486         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
1487
1488         // read rx initial gain
1489         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
1490         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
1491         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
1492         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
1493         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1494                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1495                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1496
1497         // read framesync
1498         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
1499         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
1500         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1501                                 rOFDM0_RxDetector3, priv->framesync);
1502 }
1503 //YJ,modified,090107,end
1504
1505
1506
1507 /**
1508 * Function:     phy_InitBBRFRegisterDefinition
1509 *
1510 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
1511 *
1512 * Input:
1513 *                       PADAPTER                Adapter,
1514 *
1515 * Output:       None
1516 * Return:               None
1517 * Note:         The initialization value is constant and it should never be changes
1518 */
1519 //use in phy only
1520 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
1521 {
1522         struct r8192_priv *priv = ieee80211_priv(dev);
1523
1524         // RF Interface Sowrtware Control
1525         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1526         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1527         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1528         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1529
1530         // RF Interface Readback Value
1531         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1532         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1533         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1534         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1535
1536         // RF Interface Output (and Enable)
1537         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1538         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1539         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1540         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1541
1542         // RF Interface (Output and)  Enable
1543         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1544         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1545         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1546         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1547
1548         //Addr of LSSI. Wirte RF register by driver
1549         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1550         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1551         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1552         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1553
1554         // RF parameter
1555         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
1556         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1557         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1558         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1559
1560         // Tx AGC Gain Stage (same for all path. Should we remove this?)
1561         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1562         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1563         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1564         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1565
1566         // Tranceiver A~D HSSI Parameter-1
1567         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
1568         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
1569         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
1570         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
1571
1572         // Tranceiver A~D HSSI Parameter-2
1573         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
1574         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
1575         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
1576         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
1577
1578         // RF switch Control
1579         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1580         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1581         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1582         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1583
1584         // AGC control 1
1585         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1586         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1587         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1588         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1589
1590         // AGC control 2
1591         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1592         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1593         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1594         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1595
1596         // RX AFE control 1
1597         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1598         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1599         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1600         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1601
1602         // RX AFE control 1
1603         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1604         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1605         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1606         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1607
1608         // Tx AFE control 1
1609         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1610         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1611         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1612         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1613
1614         // Tx AFE control 2
1615         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1616         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1617         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1618         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1619
1620         // Tranceiver LSSI Readback  SI mode
1621         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1622         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1623         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1624         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1625
1626         // Tranceiver LSSI Readback PI mode
1627         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
1628         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
1629         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
1630         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
1631
1632 }
1633
1634
1635 //
1636 //      Description:  Change RF power state.
1637 //
1638 //      Assumption: This function must be executed in re-schdulable context,
1639 //              ie. PASSIVE_LEVEL.
1640 //
1641 //      050823, by rcnjko.
1642 //not understand it seem's use in init
1643 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
1644 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
1645 {
1646         struct r8192_priv *priv = ieee80211_priv(dev);
1647         bool                    bResult = FALSE;
1648
1649         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
1650
1651         if(eRFPowerState == priv->ieee80211->eRFPowerState)
1652         {
1653                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
1654                 return bResult;
1655         }
1656
1657         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
1658
1659         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
1660
1661         return bResult;
1662 }
1663
1664 //use in phy only
1665 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
1666 {
1667         struct r8192_priv *priv = ieee80211_priv(dev);
1668         bool                    bResult = TRUE;
1669         //u8            eRFPath;
1670         //u8            i, QueueID;
1671         u8              u1bTmp;
1672
1673         if(priv->SetRFPowerStateInProgress == TRUE)
1674                 return FALSE;
1675
1676         priv->SetRFPowerStateInProgress = TRUE;
1677
1678         switch(priv->rf_chip )
1679         {
1680                 default:
1681                 switch( eRFPowerState )
1682                 {
1683                         case eRfOn:
1684                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
1685                                 write_nic_word(dev, CMDR, 0x37FC);
1686                                 write_nic_byte(dev, PHY_CCA, 0x3);
1687                                 write_nic_byte(dev, TXPAUSE, 0x00);
1688                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
1689                                 break;
1690
1691                         //
1692                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
1693                         // By Bruce, 2008-01-16.
1694                         //
1695                         case eRfSleep:
1696                         case eRfOff:
1697                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
1698                                                 break;
1699 #ifdef NOT_YET
1700                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
1701                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
1702                                 {
1703                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
1704                                         {
1705                                                 QueueID++;
1706                                                 continue;
1707                                         }
1708                                         else
1709                                         {
1710                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
1711                                                 udelay(10);
1712                                                 i++;
1713                                         }
1714
1715                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
1716                                         {
1717                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
1718                                                 break;
1719                                         }
1720                                 }
1721 #endif
1722                                 //
1723                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
1724                                 // Added by Bruce, 2008-11-22.
1725                                 //
1726                                 //==================================================================
1727                                 // (0) Disable FW BB reset checking
1728                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
1729
1730                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
1731                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
1732                                 u1bTmp |= BIT0;
1733                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
1734
1735                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
1736                                 write_nic_byte(dev, TXPAUSE, 0xFF);
1737
1738                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
1739                                 write_nic_word(dev, CMDR, 0x77FC);
1740                                 write_nic_byte(dev, PHY_CCA, 0x0);
1741                                 udelay(100);
1742
1743                                 write_nic_word(dev, CMDR, 0x37FC);
1744                                 udelay(10);
1745
1746                                 write_nic_word(dev, CMDR, 0x77FC);
1747                                 udelay(10);
1748
1749                                 // (3) Reset BB TRX blocks
1750                                 write_nic_word(dev, CMDR, 0x57FC);
1751                                 break;
1752
1753                         default:
1754                                 bResult = FALSE;
1755                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
1756                                 break;
1757                 }
1758                 break;
1759
1760         }
1761         priv->ieee80211->eRFPowerState = eRFPowerState;
1762 #ifdef TO_DO_LIST
1763         if(bResult)
1764         {
1765                 // Update current RF state variable.
1766                 priv->ieee80211->eRFPowerState = eRFPowerState;
1767
1768                 switch(priv->rf_chip )
1769                 {
1770                         case RF_8256:
1771                         switch(priv->ieee80211->eRFPowerState)
1772                         {
1773                                 case eRfOff:
1774                                         //
1775                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1776                                         //
1777                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
1778                                         {
1779                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
1780                                         }
1781                                         else
1782                                         {
1783                                                 // Turn off LED if RF is not ON.
1784                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
1785                                         }
1786                                         break;
1787
1788                                 case eRfOn:
1789                                         // Turn on RF we are still linked, which might happen when
1790                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1791                                         if( pMgntInfo->bMediaConnect == TRUE )
1792                                         {
1793                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
1794                                         }
1795                                         else
1796                                         {
1797                                                 // Turn off LED if RF is not ON.
1798                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
1799                                         }
1800                                         break;
1801
1802                                 default:
1803                                         // do nothing.
1804                                         break;
1805                         }// Switch RF state
1806
1807                                 break;
1808
1809                         default:
1810                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
1811                                 break;
1812                 }// Switch rf_chip
1813         }
1814 #endif
1815         priv->SetRFPowerStateInProgress = FALSE;
1816
1817         return bResult;
1818 }
1819
1820 /*-----------------------------------------------------------------------------
1821  * Function:    GetTxPowerLevel8190()
1822  *
1823  * Overview:    This function is export to "common" moudule
1824  *
1825  * Input:       PADAPTER                Adapter
1826  *                      psByte                  Power Level
1827  *
1828  * Output:      NONE
1829  *
1830  * Return:      NONE
1831  *
1832  *---------------------------------------------------------------------------*/
1833  // no use temp
1834  void
1835 PHY_GetTxPowerLevel8192S(
1836         struct net_device* dev,
1837          long*                  powerlevel
1838         )
1839 {
1840         struct r8192_priv *priv = ieee80211_priv(dev);
1841         u8                      TxPwrLevel = 0;
1842         long                    TxPwrDbm;
1843         //
1844         // Because the Tx power indexes are different, we report the maximum of them to
1845         // meet the CCX TPC request. By Bruce, 2008-01-31.
1846         //
1847
1848         // CCK
1849         TxPwrLevel = priv->CurrentCckTxPwrIdx;
1850         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
1851
1852         // Legacy OFDM
1853         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
1854
1855         // Compare with Legacy OFDM Tx power.
1856         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
1857                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
1858
1859         // HT OFDM
1860         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
1861
1862         // Compare with HT OFDM Tx power.
1863         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
1864                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
1865
1866         *powerlevel = TxPwrDbm;
1867 }
1868
1869 /*-----------------------------------------------------------------------------
1870  * Function:    SetTxPowerLevel8190()
1871  *
1872  * Overview:    This function is export to "HalCommon" moudule
1873  *
1874  * Input:       PADAPTER                Adapter
1875  *                      u1Byte          channel
1876  *
1877  * Output:      NONE
1878  *
1879  * Return:      NONE
1880  *      2008/11/04      MHC             We remove EEPROM_93C56.
1881  *                                              We need to move CCX relative code to independet file.
1882 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
1883   *---------------------------------------------------------------------------*/
1884  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
1885 {
1886         struct r8192_priv *priv = ieee80211_priv(dev);
1887         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
1888         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
1889         s8      ant_pwr_diff = 0;
1890         u32     u4RegValue;
1891         u8      index = (channel -1);
1892         // 2009/01/22 MH Add for new EEPROM format from SD3
1893         u8      pwrdiff[2] = {0};
1894         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
1895         u8      rfpath = 0, rfpathnum = 2;
1896
1897         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
1898                 return;
1899
1900         //
1901         // Read predefined TX power index in EEPROM
1902         //
1903 //      if(priv->epromtype == EPROM_93c46)
1904         {
1905                 //
1906                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
1907                 // Power must be calculated by the antenna diff.
1908                 // So we have to rewrite Antenna gain offset register here.
1909                 // Please refer to BB register 0x80c
1910                 // 1. For CCK.
1911                 // 2. For OFDM 1T or 2T
1912                 //
1913
1914                 // 1. CCK
1915                 powerlevel = priv->RfTxPwrLevelCck[0][index];
1916
1917                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
1918                 {
1919                 // Read HT 40 OFDM TX power
1920                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
1921                 // RF B HT OFDM pwr-RFA HT OFDM pwr
1922                 // Only one RF we need not to decide B <-> A pwr diff
1923
1924                 // Legacy<->HT pwr diff, we only care about path A.
1925
1926                 // We only assume 1T as RF path A
1927                 rfpathnum = 1;
1928                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
1929                 }
1930                 else if (priv->rf_type == RF_2T2R)
1931                 {
1932                 // Read HT 40 OFDM TX power
1933                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
1934                         // RF B HT OFDM pwr-RFA HT OFDM pwr
1935                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
1936                                                 priv->RfTxPwrLevelOfdm2T[0][index];
1937                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
1938                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
1939
1940                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
1941                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
1942                 //priv->RfTxPwrLevelOfdm2T[1][index],
1943                 //priv->RfTxPwrLevelOfdm2T[0][index],
1944                 //priv->RfTxPwrLevelOfdm2T[1][index]));
1945
1946                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
1947                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
1948         }
1949
1950         //
1951         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
1952         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
1953         //
1954         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
1955         {
1956                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
1957                 {
1958                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1959                         {
1960                                 // HT 20<->40 pwr diff
1961                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
1962
1963                                 // Calculate Antenna pwr diff
1964                                 if (pwrdiff[rfpath] < 8)        // 0~+7
1965                                 {
1966                                         ht20pwr[rfpath] += pwrdiff[rfpath];
1967                                 }
1968                                 else                            // index8-15=-8~-1
1969                                 {
1970                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
1971                                 }
1972                         }
1973
1974                         // RF B HT OFDM pwr-RFA HT OFDM pwr
1975                         if (priv->rf_type == RF_2T2R)
1976                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
1977
1978                         //RTPRINT(FPHY, PHY_TXPWR,
1979                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
1980                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
1981                 }
1982
1983                 // Band Edge scheme is enabled for FCC mode
1984                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
1985                 {
1986                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
1987                         {
1988                                 pwrdiff[rfpath] = 0;
1989                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
1990                                 {
1991                                         if (channel <= 3)
1992                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
1993                                         else if (channel >= 9)
1994                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
1995                                         else
1996                                                 pwrdiff[rfpath] = 0;
1997
1998                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
1999                                 }
2000                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2001                                 {
2002                                         if (channel == 1)
2003                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2004                                         else if (channel >= 11)
2005                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2006                                         else
2007                                                 pwrdiff[rfpath] = 0;
2008
2009                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2010                                 }
2011                         }
2012
2013                         if (priv->rf_type == RF_2T2R)
2014                         {
2015                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2016                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2017                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2018                                 else
2019                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2020                         }
2021                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2022                         {
2023                                 if (channel <= 1 || channel >= 11)
2024                                 {
2025                                         //RTPRINT(FPHY, PHY_TXPWR,
2026                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2027                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2028                                 }
2029                         }
2030                         else
2031                         {
2032                                 if (channel <= 3 || channel >= 9)
2033                                 {
2034                                         //RTPRINT(FPHY, PHY_TXPWR,
2035                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2036                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2037                                 }
2038                         }
2039                 }
2040                 }
2041
2042         //Cosa added for protection, the reg rFPGA0_TxGainStage
2043         // range is from 7~-8, index = 0x0~0xf
2044         if(ant_pwr_diff > 7)
2045                 ant_pwr_diff = 7;
2046         if(ant_pwr_diff < -8)
2047                 ant_pwr_diff = -8;
2048
2049                 //RTPRINT(FPHY, PHY_TXPWR,
2050                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2051                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2052
2053                 ant_pwr_diff &= 0xf;
2054
2055                 // Antenna TX power difference
2056                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2057                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2058                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2059
2060                 // Antenna gain offset from B/C/D to A
2061                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2062                                                 priv->AntennaTxPwDiff[1]<<4 |
2063                                                 priv->AntennaTxPwDiff[0]        );
2064
2065                 // Notify Tx power difference for B/C/D to A!!!
2066                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2067         }
2068
2069         //
2070         // CCX 2 S31, AP control of client transmit power:
2071         // 1. We shall not exceed Cell Power Limit as possible as we can.
2072         // 2. Tolerance is +/- 5dB.
2073         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2074         //
2075         // TODO:
2076         // 1. 802.11h power contraint
2077         //
2078         // 071011, by rcnjko.
2079         //
2080 #ifdef TODO //WB, 11h has not implemented now.
2081         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2082                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2083         {
2084                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2085                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2086                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2087
2088                 RT_TRACE(COMP_TXAGC,
2089                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2090                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2091                 RT_TRACE(COMP_TXAGC,
2092                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2093                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2094
2095                 // CCK
2096                 if(powerlevel > CckCellPwrIdx)
2097                         powerlevel = CckCellPwrIdx;
2098                 // Legacy OFDM, HT OFDM
2099                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2100                 {
2101                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2102                         {
2103                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2104                         }
2105                         else
2106                         {
2107                                 powerlevelOFDM24G = 0;
2108                         }
2109                 }
2110
2111                 RT_TRACE(COMP_TXAGC,
2112                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2113                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2114         }
2115 #endif
2116
2117         priv->CurrentCckTxPwrIdx = powerlevel;
2118         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2119
2120         switch(priv->rf_chip)
2121         {
2122                 case RF_8225:
2123                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2124                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2125                 break;
2126
2127                 case RF_8256:
2128                         break;
2129
2130                 case RF_6052:
2131                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2132                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2133                         break;
2134
2135                 case RF_8258:
2136                         break;
2137                 default:
2138                         break;
2139         }
2140
2141 }
2142
2143 //
2144 //      Description:
2145 //              Update transmit power level of all channel supported.
2146 //
2147 //      TODO:
2148 //              A mode.
2149 //      By Bruce, 2008-02-04.
2150 //    no use temp
2151 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2152 {
2153         struct r8192_priv       *priv = ieee80211_priv(dev);
2154         u8                              idx;
2155         u8                              rf_path;
2156
2157         // TODO: A mode Tx power.
2158         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2159         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2160
2161         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2162                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2163         else
2164                 OfdmTxPwrIdx = 0;
2165
2166         for(idx = 0; idx < 14; idx++)
2167         {
2168                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2169                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2170                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2171                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2172                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2173                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2174
2175                 for (rf_path = 0; rf_path < 2; rf_path++)
2176                 {
2177                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2178                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2179                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2180                 }
2181         }
2182
2183         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2184
2185         return TRUE;
2186 }
2187
2188 /*
2189         Description:
2190                 When beacon interval is changed, the values of the
2191                 hw registers should be modified.
2192         By tynli, 2008.10.24.
2193
2194 */
2195
2196 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2197 {
2198         u32 NewBeaconNum;
2199
2200         NewBeaconNum = BeaconInterval *32 - 64;
2201         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2202         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2203         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2204         write_nic_dword(dev, WFM3, 0xB026007C);
2205 }
2206
2207 //
2208 //      Description:
2209 //              Map dBm into Tx power index according to
2210 //              current HW model, for example, RF and PA, and
2211 //              current wireless mode.
2212 //      By Bruce, 2008-01-29.
2213 //    use in phy only
2214 static u8 phy_DbmToTxPwrIdx(
2215         struct net_device* dev,
2216         WIRELESS_MODE   WirelessMode,
2217         long                    PowerInDbm
2218         )
2219 {
2220         //struct r8192_priv *priv = ieee80211_priv(dev);
2221         u8                              TxPwrIdx = 0;
2222         long                            Offset = 0;
2223
2224
2225         //
2226         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2227         // 3dbm, and OFDM HT equals to 0dbm repectively.
2228         // Note:
2229         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2230         // By Bruce, 2008-01-29.
2231         //
2232         switch(WirelessMode)
2233         {
2234         case WIRELESS_MODE_B:
2235                 Offset = -7;
2236                 break;
2237
2238         case WIRELESS_MODE_G:
2239         case WIRELESS_MODE_N_24G:
2240                 Offset = -8;
2241                 break;
2242         default:
2243                 break;
2244         }
2245
2246         if((PowerInDbm - Offset) > 0)
2247         {
2248                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2249         }
2250         else
2251         {
2252                 TxPwrIdx = 0;
2253         }
2254
2255         // Tx Power Index is too large.
2256         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2257                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2258
2259         return TxPwrIdx;
2260 }
2261 //
2262 //      Description:
2263 //              Map Tx power index into dBm according to
2264 //              current HW model, for example, RF and PA, and
2265 //              current wireless mode.
2266 //      By Bruce, 2008-01-29.
2267 //    use in phy only
2268 static long phy_TxPwrIdxToDbm(
2269         struct net_device* dev,
2270         WIRELESS_MODE   WirelessMode,
2271         u8                      TxPwrIdx
2272         )
2273 {
2274         //struct r8192_priv *priv = ieee80211_priv(dev);
2275         long                            Offset = 0;
2276         long                            PwrOutDbm = 0;
2277
2278         //
2279         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2280         // 3dbm, and OFDM HT equals to 0dbm repectively.
2281         // Note:
2282         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2283         // By Bruce, 2008-01-29.
2284         //
2285         switch(WirelessMode)
2286         {
2287         case WIRELESS_MODE_B:
2288                 Offset = -7;
2289                 break;
2290
2291         case WIRELESS_MODE_G:
2292         case WIRELESS_MODE_N_24G:
2293                 Offset = -8;
2294                 break;
2295         default:
2296                 break;
2297         }
2298
2299         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2300
2301         return PwrOutDbm;
2302 }
2303
2304 #ifdef TO_DO_LIST
2305 extern  VOID
2306 PHY_ScanOperationBackup8192S(
2307         IN      PADAPTER        Adapter,
2308         IN      u1Byte          Operation
2309         )
2310 {
2311
2312         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
2313         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
2314         u4Byte                          BitMask;
2315         u1Byte                          initial_gain;
2316
2317
2318
2319
2320
2321         if(!Adapter->bDriverStopped)
2322         {
2323                 switch(Operation)
2324                 {
2325                         case SCAN_OPT_BACKUP:
2326                                 //
2327                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
2328                                 // and resume both two DMs while scan complete.
2329                                 // 2008.11.27.
2330                                 //
2331                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
2332                                 break;
2333
2334                         case SCAN_OPT_RESTORE:
2335                                 //
2336                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
2337                                 // recover earlier DIG settings.
2338                                 // 2008.11.27.
2339                                 //
2340                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
2341                                 break;
2342
2343                         default:
2344                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2345                                 break;
2346                 }
2347         }
2348 }
2349 #endif
2350
2351 //nouse temp
2352 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
2353 {
2354
2355         //struct r8192_priv *priv = ieee80211_priv(dev);
2356         //u32                                   BitMask;
2357         //u8                                    initial_gain;
2358 }
2359
2360 /*-----------------------------------------------------------------------------
2361  * Function:    SetBWModeCallback8190Pci()
2362  *
2363  * Overview:    Timer callback function for SetSetBWMode
2364  *
2365  * Input:               PRT_TIMER               pTimer
2366  *
2367  * Output:      NONE
2368  *
2369  * Return:      NONE
2370  *
2371  * Note:                (1) We do not take j mode into consideration now
2372  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2373  *                           concurrently?
2374  *---------------------------------------------------------------------------*/
2375 //    use in phy only (in win it's timer)
2376 void PHY_SetBWModeCallback8192S(struct net_device *dev)
2377 {
2378         struct r8192_priv *priv = ieee80211_priv(dev);
2379         u8                              regBwOpMode;
2380
2381         //return;
2382
2383         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2384         //u32                           NowL, NowH;
2385         //u8Byte                                BeginTime, EndTime;
2386         u8                              regRRSR_RSC;
2387
2388         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
2389                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
2390
2391         if(priv->rf_chip == RF_PSEUDO_11N)
2392         {
2393                 priv->SetBWModeInProgress= FALSE;
2394                 return;
2395         }
2396
2397         if(!priv->up)
2398                 return;
2399
2400         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2401         //NowL = read_nic_dword(dev, TSFR);
2402         //NowH = read_nic_dword(dev, TSFR+4);
2403         //BeginTime = ((u8Byte)NowH << 32) + NowL;
2404
2405         //3//
2406         //3//<1>Set MAC register
2407         //3//
2408         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
2409         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
2410
2411         switch(priv->CurrentChannelBW)
2412         {
2413                 case HT_CHANNEL_WIDTH_20:
2414                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2415                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2416
2417                         regBwOpMode |= BW_OPMODE_20MHZ;
2418                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2419                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2420                         break;
2421
2422                 case HT_CHANNEL_WIDTH_20_40:
2423                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
2424                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2425
2426                         regBwOpMode &= ~BW_OPMODE_20MHZ;
2427                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2428                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
2429                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
2430                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
2431                         break;
2432
2433                 default:
2434                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
2435                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2436                         break;
2437         }
2438
2439         //3//
2440         //3//<2>Set PHY related register
2441         //3//
2442         switch(priv->CurrentChannelBW)
2443         {
2444                 /* 20 MHz channel*/
2445                 case HT_CHANNEL_WIDTH_20:
2446                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2447                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2448
2449                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2450                         // It is set in Tx descriptor for 8192x series
2451                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2452                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2453                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2454
2455                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2456                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
2457
2458
2459                         break;
2460
2461                 /* 40 MHz channel*/
2462                 case HT_CHANNEL_WIDTH_20_40:
2463                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2464                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2465
2466                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2467                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2468                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2469                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2470
2471                         // Set Control channel to upper or lower. These settings are required only for 40MHz
2472                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2473                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2474
2475                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
2476                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
2477                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
2478
2479                         break;
2480
2481                 default:
2482                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
2483                                                 ,priv->CurrentChannelBW);
2484                         break;
2485
2486         }
2487         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2488
2489         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2490         //NowL = read_nic_dword(dev, TSFR);
2491         //NowH = read_nic_dword(dev, TSFR+4);
2492         //EndTime = ((u8Byte)NowH << 32) + NowL;
2493         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
2494
2495         //3<3>Set RF related register
2496         switch( priv->rf_chip )
2497         {
2498                 case RF_8225:
2499                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
2500                         break;
2501
2502                 case RF_8256:
2503                         // Please implement this function in Hal8190PciPhy8256.c
2504                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2505                         break;
2506
2507                 case RF_8258:
2508                         // Please implement this function in Hal8190PciPhy8258.c
2509                         // PHY_SetRF8258Bandwidth();
2510                         break;
2511
2512                 case RF_PSEUDO_11N:
2513                         // Do Nothing
2514                         break;
2515
2516                 case RF_6052:
2517                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
2518                         break;
2519                 default:
2520                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
2521                         break;
2522         }
2523
2524         priv->SetBWModeInProgress= FALSE;
2525
2526         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
2527 }
2528
2529
2530  /*-----------------------------------------------------------------------------
2531  * Function:   SetBWMode8190Pci()
2532  *
2533  * Overview:  This function is export to "HalCommon" moudule
2534  *
2535  * Input:               PADAPTER                        Adapter
2536  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
2537  *
2538  * Output:      NONE
2539  *
2540  * Return:      NONE
2541  *
2542  * Note:                We do not take j mode into consideration now
2543  *---------------------------------------------------------------------------*/
2544 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
2545 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
2546 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
2547 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2548 {
2549         struct r8192_priv *priv = ieee80211_priv(dev);
2550         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
2551
2552
2553         // Modified it for 20/40 mhz switch by guangan 070531
2554
2555         //return;
2556
2557         //if(priv->SwChnlInProgress)
2558 //      if(pMgntInfo->bScanInProgress)
2559 //      {
2560 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
2561 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2562 //              return;
2563 //      }
2564
2565 //      if(priv->SetBWModeInProgress)
2566 //      {
2567 //              // Modified it for 20/40 mhz switch by guangan 070531
2568 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
2569 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2570 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
2571 //              //return;
2572 //      }
2573
2574         if(priv->SetBWModeInProgress)
2575                 return;
2576
2577         priv->SetBWModeInProgress= TRUE;
2578
2579         priv->CurrentChannelBW = Bandwidth;
2580
2581         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2582                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2583         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2584                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2585         else
2586                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2587
2588         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
2589         {
2590         SetBWModeCallback8192SUsbWorkItem(dev);
2591         }
2592         else
2593         {
2594                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
2595                 priv->SetBWModeInProgress= FALSE;
2596                 priv->CurrentChannelBW = tmpBW;
2597         }
2598 }
2599
2600 //    use in phy only (in win it's timer)
2601 void PHY_SwChnlCallback8192S(struct net_device *dev)
2602 {
2603
2604         struct r8192_priv *priv = ieee80211_priv(dev);
2605         u32             delay;
2606         //bool                  ret;
2607
2608         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
2609
2610         if(!priv->up)
2611                 return;
2612
2613         if(priv->rf_chip == RF_PSEUDO_11N)
2614         {
2615                 priv->SwChnlInProgress=FALSE;
2616                 return;                                                                 //return immediately if it is peudo-phy
2617         }
2618
2619         do{
2620                 if(!priv->SwChnlInProgress)
2621                         break;
2622
2623                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2624                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
2625                 {
2626                         if(delay>0)
2627                         {
2628                                 mdelay(delay);
2629                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
2630                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
2631                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
2632                                 //==>SwChnlCallback8192SUsb(dev) for 92su
2633                         }
2634                         else
2635                         continue;
2636                 }
2637                 else
2638                 {
2639                         priv->SwChnlInProgress=FALSE;
2640                         break;
2641                 }
2642         }while(true);
2643 }
2644
2645 // Call after initialization
2646 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
2647 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2648 {
2649         struct r8192_priv *priv = ieee80211_priv(dev);
2650         //u8                    tmpchannel =channel;
2651         //bool                  bResult = false;
2652
2653         if(!priv->up)
2654                 return false;
2655
2656         if(priv->SwChnlInProgress)
2657                 return false;
2658
2659         if(priv->SetBWModeInProgress)
2660                 return false;
2661
2662         //--------------------------------------------
2663         switch(priv->ieee80211->mode)
2664         {
2665         case WIRELESS_MODE_A:
2666         case WIRELESS_MODE_N_5G:
2667                 if (channel<=14){
2668                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2669                         return false;
2670                 }
2671                 break;
2672
2673         case WIRELESS_MODE_B:
2674                 if (channel>14){
2675                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2676                         return false;
2677                 }
2678                 break;
2679
2680         case WIRELESS_MODE_G:
2681         case WIRELESS_MODE_N_24G:
2682                 if (channel>14){
2683                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2684                         return false;
2685                 }
2686                 break;
2687
2688         default:
2689                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
2690                 break;
2691         }
2692         //--------------------------------------------
2693
2694         priv->SwChnlInProgress = TRUE;
2695         if( channel == 0)
2696                 channel = 1;
2697
2698         priv->chan=channel;
2699
2700         priv->SwChnlStage=0;
2701         priv->SwChnlStep=0;
2702
2703         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
2704         {
2705         SwChnlCallback8192SUsbWorkItem(dev);
2706 #ifdef TO_DO_LIST
2707         if(bResult)
2708                 {
2709                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
2710                 }
2711                 else
2712                 {
2713                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
2714                         priv->SwChnlInProgress = false;
2715                         priv->CurrentChannel = tmpchannel;
2716                 }
2717 #endif
2718         }
2719         else
2720         {
2721                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
2722                 priv->SwChnlInProgress = false;
2723                 //priv->CurrentChannel = tmpchannel;
2724         }
2725         return true;
2726 }
2727
2728
2729 //
2730 // Description:
2731 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
2732 //
2733 // Implemented by Bruce, 2008-02-14.
2734 // The following procedure is operted according to SwChanlCallback8190Pci().
2735 // However, this procedure is performed synchronously  which should be running under
2736 // passive level.
2737 //
2738 //not understant it
2739 void PHY_SwChnlPhy8192S(        // Only called during initialize
2740         struct net_device* dev,
2741         u8              channel
2742         )
2743 {
2744         struct r8192_priv *priv = ieee80211_priv(dev);
2745
2746         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
2747
2748 #ifdef TO_DO_LIST
2749         // Cannot IO.
2750         if(RT_CANNOT_IO(dev))
2751                 return;
2752 #endif
2753
2754         // Channel Switching is in progress.
2755         if(priv->SwChnlInProgress)
2756                 return;
2757
2758         //return immediately if it is peudo-phy
2759         if(priv->rf_chip == RF_PSEUDO_11N)
2760         {
2761                 priv->SwChnlInProgress=FALSE;
2762                 return;
2763         }
2764
2765         priv->SwChnlInProgress = TRUE;
2766         if( channel == 0)
2767                 channel = 1;
2768
2769         priv->chan=channel;
2770
2771         priv->SwChnlStage = 0;
2772         priv->SwChnlStep = 0;
2773
2774         phy_FinishSwChnlNow(dev,channel);
2775
2776         priv->SwChnlInProgress = FALSE;
2777 }
2778
2779 //    use in phy only
2780 static bool
2781 phy_SetSwChnlCmdArray(
2782         SwChnlCmd*              CmdTable,
2783         u32                     CmdTableIdx,
2784         u32                     CmdTableSz,
2785         SwChnlCmdID             CmdID,
2786         u32                     Para1,
2787         u32                     Para2,
2788         u32                     msDelay
2789         )
2790 {
2791         SwChnlCmd* pCmd;
2792
2793         if(CmdTable == NULL)
2794         {
2795                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
2796                 return FALSE;
2797         }
2798         if(CmdTableIdx >= CmdTableSz)
2799         {
2800                 //RT_ASSERT(FALSE,
2801                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2802                                 //CmdTableIdx, CmdTableSz));
2803                 return FALSE;
2804         }
2805
2806         pCmd = CmdTable + CmdTableIdx;
2807         pCmd->CmdID = CmdID;
2808         pCmd->Para1 = Para1;
2809         pCmd->Para2 = Para2;
2810         pCmd->msDelay = msDelay;
2811
2812         return TRUE;
2813 }
2814
2815 //    use in phy only
2816 static bool
2817 phy_SwChnlStepByStep(
2818         struct net_device* dev,
2819         u8              channel,
2820         u8              *stage,
2821         u8              *step,
2822         u32             *delay
2823         )
2824 {
2825         struct r8192_priv *priv = ieee80211_priv(dev);
2826         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
2827         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
2828         u32                                     PreCommonCmdCnt;
2829         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
2830         u32                                     PostCommonCmdCnt;
2831         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
2832         u32                                     RfDependCmdCnt;
2833         SwChnlCmd                               *CurrentCmd = NULL;
2834         u8                                      eRFPath;
2835
2836         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
2837         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
2838         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2839         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
2840         if (!IsLegalChannel(priv->ieee80211, channel))
2841         {
2842                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2843                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2844         }
2845
2846         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
2847         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
2848
2849         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
2850         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2851         //{
2852                 // <1> Fill up pre common command.
2853         PreCommonCmdCnt = 0;
2854         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2855                                 CmdID_SetTxPowerLevel, 0, 0, 0);
2856         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2857                                 CmdID_End, 0, 0, 0);
2858
2859                 // <2> Fill up post common command.
2860         PostCommonCmdCnt = 0;
2861
2862         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2863                                 CmdID_End, 0, 0, 0);
2864
2865                 // <3> Fill up RF dependent command.
2866         RfDependCmdCnt = 0;
2867         switch( priv->rf_chip )
2868         {
2869                 case RF_8225:
2870                 if (channel < 1 || channel > 14)
2871                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2872                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2873                 // 2008/09/04 MH Change channel.
2874                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2875                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
2876                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2877                 CmdID_End, 0, 0, 0);
2878                 break;
2879
2880         case RF_8256:
2881                 if (channel < 1 || channel > 14)
2882                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2883                 // TEST!! This is not the table for 8256!!
2884                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
2885                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2886                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
2887                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2888                 CmdID_End, 0, 0, 0);
2889                 break;
2890
2891         case RF_6052:
2892                 if (channel < 1 || channel > 14)
2893                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
2894                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2895                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
2896                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2897                         CmdID_End, 0, 0, 0);
2898                 break;
2899
2900         case RF_8258:
2901                 break;
2902
2903         default:
2904                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
2905                 return FALSE;
2906                 break;
2907         }
2908
2909
2910         do{
2911                 switch(*stage)
2912                 {
2913                 case 0:
2914                         CurrentCmd=&PreCommonCmd[*step];
2915                         break;
2916                 case 1:
2917                         CurrentCmd=&RfDependCmd[*step];
2918                         break;
2919                 case 2:
2920                         CurrentCmd=&PostCommonCmd[*step];
2921                         break;
2922                 }
2923
2924                 if(CurrentCmd->CmdID==CmdID_End)
2925                 {
2926                         if((*stage)==2)
2927                         {
2928                                 return TRUE;
2929                         }
2930                         else
2931                         {
2932                                 (*stage)++;
2933                                 (*step)=0;
2934                                 continue;
2935                         }
2936                 }
2937
2938                 switch(CurrentCmd->CmdID)
2939                 {
2940                 case CmdID_SetTxPowerLevel:
2941                         //if(priv->card_8192_version > VERSION_8190_BD)
2942                                 PHY_SetTxPowerLevel8192S(dev,channel);
2943                         break;
2944                 case CmdID_WritePortUlong:
2945                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2946                         break;
2947                 case CmdID_WritePortUshort:
2948                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2949                         break;
2950                 case CmdID_WritePortUchar:
2951                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2952                         break;
2953                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
2954                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2955                         {
2956                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
2957                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
2958                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
2959                         }
2960                         break;
2961                 default:
2962                         break;
2963                 }
2964
2965                 break;
2966         }while(TRUE);
2967         //cosa }/*for(Number of RF paths)*/
2968
2969         (*delay)=CurrentCmd->msDelay;
2970         (*step)++;
2971         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
2972         return FALSE;
2973 }
2974
2975 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
2976 //    use in phy only
2977 static void
2978 phy_FinishSwChnlNow(    // We should not call this function directly
2979         struct net_device* dev,
2980         u8              channel
2981                 )
2982 {
2983         struct r8192_priv       *priv = ieee80211_priv(dev);
2984         u32                     delay;
2985
2986         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2987         {
2988                 if(delay>0)
2989                         mdelay(delay);
2990                 if(!priv->up)
2991                         break;
2992         }
2993 }
2994
2995
2996 /*-----------------------------------------------------------------------------
2997  * Function:    PHYCheckIsLegalRfPath8190Pci()
2998  *
2999  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3000  *                      We will return false.
3001  *
3002  * Input:               NONE
3003  *
3004  * Output:              NONE
3005  *
3006  * Return:              NONE
3007  *
3008  * Revised History:
3009  *      When            Who             Remark
3010  *      11/15/2007      MHC             Create Version 0.
3011  *
3012  *---------------------------------------------------------------------------*/
3013  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3014 //extern        bool
3015 //PHY_CheckIsLegalRfPath8192S(
3016 //      struct net_device* dev,
3017 //      u32     eRFPath)
3018 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3019 {
3020 //      struct r8192_priv *priv = ieee80211_priv(dev);
3021         bool                            rtValue = TRUE;
3022
3023         // NOt check RF Path now.!
3024         return  rtValue;
3025
3026 }       /* PHY_CheckIsLegalRfPath8192S */
3027
3028
3029
3030 /*-----------------------------------------------------------------------------
3031  * Function:    PHY_IQCalibrate8192S()
3032  *
3033  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3034  *                      to improve RF EVM!!?
3035  *
3036  * Input:               IN      PADAPTER        pAdapter
3037  *
3038  * Output:              NONE
3039  *
3040  * Return:              NONE
3041  *
3042  * Revised History:
3043  *      When            Who             Remark
3044  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3045  *
3046  *---------------------------------------------------------------------------*/
3047  //called by InitializeAdapter8192SE
3048 void
3049 PHY_IQCalibrate(        struct net_device* dev)
3050 {
3051         //struct r8192_priv     *priv = ieee80211_priv(dev);
3052         u32                             i, reg;
3053         u32                             old_value;
3054         long                            X, Y, TX0[4];
3055         u32                             TXA[4];
3056
3057         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3058
3059         //
3060         // 2. QFN 68
3061         //
3062         // For 1T2R IQK only now !!!
3063         for (i = 0; i < 10; i++)
3064         {
3065                 // IQK
3066                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3067                 //PlatformStallExecution(5);
3068                 udelay(5);
3069                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3070                 udelay(5);
3071                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3072                 udelay(5);
3073                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3074                 udelay(5);
3075                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3076                 udelay(5);
3077                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3078                 udelay(5);
3079                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3080                 udelay(5);
3081                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3082                 udelay(5);
3083                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3084                 udelay(5);
3085                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3086                 udelay(5);
3087                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3088                 udelay(2000);
3089                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3090                 udelay(5);
3091                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3092                 udelay(5);
3093                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3094
3095
3096                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3097
3098                 // Readback IQK value and rewrite
3099                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3100                 {
3101                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3102
3103                         // Calibrate init gain for A path for TX0
3104                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3105                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3106                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3107                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3108                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3109                         udelay(5);
3110
3111                         // Calibrate init gain for C path for TX0
3112                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3113                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3114                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3115                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3116                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3117                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3118                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3119                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3120                         udelay(5);
3121
3122                         // Calibrate RX A and B for RX0
3123                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3124                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3125                         reg = (reg & 0xFFFFFC00) |X;
3126                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3127                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3128                         reg = (reg & 0xFFFF03FF) |Y<<10;
3129                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3130                         udelay(5);
3131                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3132
3133                         // Calibrate init gain for A path for TX1 !!!!!!
3134                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3135                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3136                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3137                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3138                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3139                         udelay(5);
3140
3141                         // Calibrate init gain for C path for TX1
3142                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3143                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3144                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3145                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3146                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3147                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3148                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3149                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3150                         udelay(5);
3151
3152                         // Calibrate RX A and B for RX1
3153                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3154                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3155                         reg = (reg & 0xFFFFFC00) |X;
3156                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3157
3158                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3159                         reg = (reg & 0xFFFF03FF) |Y<<10;
3160                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3161                         udelay(5);
3162
3163                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3164                         break;
3165                 }
3166
3167         }
3168
3169
3170         //
3171         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3172         //
3173
3174
3175 }
3176
3177 /*-----------------------------------------------------------------------------
3178  * Function:    PHY_IQCalibrateBcut()
3179  *
3180  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3181  *                      to improve RF EVM!!?
3182  *
3183  * Input:               IN      PADAPTER        pAdapter
3184  *
3185  * Output:              NONE
3186  *
3187  * Return:              NONE
3188  *
3189  * Revised History:
3190  *      When            Who             Remark
3191  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3192  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
3193  *
3194  *---------------------------------------------------------------------------*/
3195 extern void PHY_IQCalibrateBcut(struct net_device* dev)
3196 {
3197         //struct r8192_priv     *priv = ieee80211_priv(dev);
3198         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
3199         u32                             i, reg;
3200         u32                             old_value;
3201         long                            X, Y, TX0[4];
3202         u32                             TXA[4];
3203         u32                             calibrate_set[13] = {0};
3204         u32                             load_value[13];
3205         u8                              RfPiEnable=0;
3206
3207         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
3208
3209         //
3210         // 1. Save e70~ee0 register setting, and load calibration setting
3211         //
3212         /*
3213         0xee0[31:0]=0x3fed92fb;
3214         0xedc[31:0] =0x3fed92fb;
3215         0xe70[31:0] =0x3fed92fb;
3216         0xe74[31:0] =0x3fed92fb;
3217         0xe78[31:0] =0x3fed92fb;
3218         0xe7c[31:0]= 0x3fed92fb;
3219         0xe80[31:0]= 0x3fed92fb;
3220         0xe84[31:0]= 0x3fed92fb;
3221         0xe88[31:0]= 0x3fed92fb;
3222         0xe8c[31:0]= 0x3fed92fb;
3223         0xed0[31:0]= 0x3fed92fb;
3224         0xed4[31:0]= 0x3fed92fb;
3225         0xed8[31:0]= 0x3fed92fb;
3226         */
3227         calibrate_set [0] = 0xee0;
3228         calibrate_set [1] = 0xedc;
3229         calibrate_set [2] = 0xe70;
3230         calibrate_set [3] = 0xe74;
3231         calibrate_set [4] = 0xe78;
3232         calibrate_set [5] = 0xe7c;
3233         calibrate_set [6] = 0xe80;
3234         calibrate_set [7] = 0xe84;
3235         calibrate_set [8] = 0xe88;
3236         calibrate_set [9] = 0xe8c;
3237         calibrate_set [10] = 0xed0;
3238         calibrate_set [11] = 0xed4;
3239         calibrate_set [12] = 0xed8;
3240         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
3241         for (i = 0; i < 13; i++)
3242         {
3243                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
3244                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
3245
3246         }
3247
3248         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
3249
3250         //
3251         // 2. QFN 68
3252         //
3253         // For 1T2R IQK only now !!!
3254         for (i = 0; i < 10; i++)
3255         {
3256                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
3257                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
3258                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3259                 {
3260                         //DbgPrint("IQK Switch to PI mode\n");
3261                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
3262                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
3263                 }
3264
3265                 // IQK
3266                 // 2. IQ calibration & LO leakage calibration
3267                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3268                 udelay(5);
3269                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3270                 udelay(5);
3271                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3272                 udelay(5);
3273                 //path-A IQ K and LO K gain setting
3274                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
3275                 udelay(5);
3276                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
3277                 udelay(5);
3278                 //set LO calibration
3279                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3280                 udelay(5);
3281                 //path-B IQ K and LO K gain setting
3282                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
3283                 udelay(5);
3284                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
3285                 udelay(5);
3286                 //K idac_I & IQ
3287                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3288                 udelay(5);
3289                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3290                 udelay(5);
3291
3292                 // delay 2ms
3293                 udelay(2000);
3294
3295                 //idac_Q setting
3296                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
3297                 udelay(5);
3298                 //K idac_Q & IQ
3299                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
3300                 udelay(5);
3301                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
3302
3303                 // delay 2ms
3304                 udelay(2000);
3305
3306                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3307                 udelay(5);
3308                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3309                 udelay(5);
3310                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3311
3312                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
3313                 {
3314                         //DbgPrint("IQK Switch back to SI mode\n");
3315                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
3316                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
3317                 }
3318
3319
3320                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3321
3322                 // 3.   check fail bit, and fill BB IQ matrix
3323                 // Readback IQK value and rewrite
3324                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3325                 {
3326                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3327
3328                         // Calibrate init gain for A path for TX0
3329                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3330                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3331                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3332                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3333                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3334                         udelay(5);
3335
3336                         // Calibrate init gain for C path for TX0
3337                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3338                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3339                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3340                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3341                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3342                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3343                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3344                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3345                         udelay(5);
3346
3347                         // Calibrate RX A and B for RX0
3348                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3349                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3350                         reg = (reg & 0xFFFFFC00) |X;
3351                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3352                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3353                         reg = (reg & 0xFFFF03FF) |Y<<10;
3354                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3355                         udelay(5);
3356                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
3357
3358                         // Calibrate init gain for A path for TX1 !!!!!!
3359                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
3360                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3361                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
3362                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
3363                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3364                         udelay(5);
3365
3366                         // Calibrate init gain for C path for TX1
3367                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
3368                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3369                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
3370                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
3371                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
3372                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
3373                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3374                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
3375                         udelay(5);
3376
3377                         // Calibrate RX A and B for RX1
3378                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
3379                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
3380                         reg = (reg & 0xFFFFFC00) |X;
3381                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3382
3383                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
3384                         reg = (reg & 0xFFFF03FF) |Y<<10;
3385                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
3386                         udelay(5);
3387
3388                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
3389                         break;
3390                 }
3391
3392         }
3393
3394         //
3395         // 4. Reload e70~ee0 register setting.
3396         //
3397         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
3398         for (i = 0; i < 13; i++)
3399                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
3400
3401
3402         //
3403         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
3404         //
3405
3406
3407
3408 }       // PHY_IQCalibrateBcut
3409
3410
3411 //
3412 // Move from phycfg.c to gen.c to be code independent later
3413 //
3414 //-------------------------Move to other DIR later----------------------------*/
3415 //#if (DEV_BUS_TYPE == USB_INTERFACE)
3416
3417 //    use in phy only (in win it's timer)
3418 void SwChnlCallback8192SUsb(struct net_device *dev)
3419 {
3420
3421         struct r8192_priv *priv = ieee80211_priv(dev);
3422         u32                     delay;
3423 //      bool                    ret;
3424
3425         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
3426                                 %d\n", priv->chan);
3427
3428
3429         if(!priv->up)
3430                 return;
3431
3432         if(priv->rf_chip == RF_PSEUDO_11N)
3433         {
3434                 priv->SwChnlInProgress=FALSE;
3435                 return;                                                                 //return immediately if it is peudo-phy
3436         }
3437
3438         do{
3439                 if(!priv->SwChnlInProgress)
3440                         break;
3441
3442                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3443                 {
3444                         if(delay>0)
3445                         {
3446                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3447
3448                         }
3449                         else
3450                         continue;
3451                 }
3452                 else
3453                 {
3454                         priv->SwChnlInProgress=FALSE;
3455                 }
3456                 break;
3457         }while(TRUE);
3458 }
3459
3460
3461 //
3462 // Callback routine of the work item for switch channel.
3463 //
3464 //    use in phy only (in win it's work)
3465 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
3466 {
3467         struct r8192_priv *priv = ieee80211_priv(dev);
3468
3469         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
3470 #ifdef TO_DO_LIST
3471         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
3472         {
3473                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
3474
3475                 pHalData->SwChnlInProgress = FALSE;
3476                 return;
3477         }
3478 #endif
3479         phy_FinishSwChnlNow(dev, priv->chan);
3480         priv->SwChnlInProgress = FALSE;
3481
3482         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
3483 }
3484
3485
3486 /*-----------------------------------------------------------------------------
3487  * Function:    SetBWModeCallback8192SUsb()
3488  *
3489  * Overview:    Timer callback function for SetSetBWMode
3490  *
3491  * Input:               PRT_TIMER               pTimer
3492  *
3493  * Output:      NONE
3494  *
3495  * Return:      NONE
3496  *
3497  * Note:                (1) We do not take j mode into consideration now
3498  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3499  *                           concurrently?
3500  *---------------------------------------------------------------------------*/
3501 //====>//rtl8192_SetBWMode
3502 //    use in phy only (in win it's timer)
3503 void SetBWModeCallback8192SUsb(struct net_device *dev)
3504 {
3505         struct r8192_priv *priv = ieee80211_priv(dev);
3506         u8                              regBwOpMode;
3507
3508         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3509         //u32                           NowL, NowH;
3510         //u8Byte                                BeginTime, EndTime;
3511         u8                              regRRSR_RSC;
3512
3513         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3514                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3515
3516         if(priv->rf_chip == RF_PSEUDO_11N)
3517         {
3518                 priv->SetBWModeInProgress= FALSE;
3519                 return;
3520         }
3521
3522         if(!priv->up)
3523                 return;
3524
3525         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3526         //NowL = read_nic_dword(dev, TSFR);
3527         //NowH = read_nic_dword(dev, TSFR+4);
3528         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3529
3530         //3<1>Set MAC register
3531         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3532         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3533
3534         switch(priv->CurrentChannelBW)
3535         {
3536                 case HT_CHANNEL_WIDTH_20:
3537                         regBwOpMode |= BW_OPMODE_20MHZ;
3538                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3539                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3540                         break;
3541
3542                 case HT_CHANNEL_WIDTH_20_40:
3543                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3544                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3545                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3546
3547                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3548                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3549                         break;
3550
3551                 default:
3552                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
3553                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3554                         break;
3555         }
3556
3557         //3 <2>Set PHY related register
3558         switch(priv->CurrentChannelBW)
3559         {
3560                 case HT_CHANNEL_WIDTH_20:
3561                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3562                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3563
3564                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3565                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3566
3567                         break;
3568                 case HT_CHANNEL_WIDTH_20_40:
3569                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3570                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3571                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3572                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3573
3574                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3575                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3576                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3577                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3578                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3579
3580                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3581                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3582
3583                         break;
3584                 default:
3585                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
3586                                                 ,priv->CurrentChannelBW);
3587                         break;
3588
3589         }
3590         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3591
3592         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3593         //NowL = read_nic_dword(dev, TSFR);
3594         //NowH = read_nic_dword(dev, TSFR+4);
3595         //EndTime = ((u8Byte)NowH << 32) + NowL;
3596         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3597
3598 #if 1
3599         //3<3>Set RF related register
3600         switch( priv->rf_chip )
3601         {
3602                 case RF_8225:
3603                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3604                         break;
3605
3606                 case RF_8256:
3607                         // Please implement this function in Hal8190PciPhy8256.c
3608                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3609                         break;
3610
3611                 case RF_6052:
3612                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3613                         break;
3614
3615                 case RF_8258:
3616                         // Please implement this function in Hal8190PciPhy8258.c
3617                         // PHY_SetRF8258Bandwidth();
3618                         break;
3619
3620                 case RF_PSEUDO_11N:
3621                         // Do Nothing
3622                         break;
3623
3624                 default:
3625                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3626                         break;
3627         }
3628 #endif
3629         priv->SetBWModeInProgress= FALSE;
3630
3631         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
3632 }
3633
3634 //
3635 // Callback routine of the work item for set bandwidth mode.
3636 //
3637 //    use in phy only (in win it's work)
3638 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
3639 {
3640         struct r8192_priv               *priv = ieee80211_priv(dev);
3641         u8                              regBwOpMode;
3642
3643         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3644         //u32                           NowL, NowH;
3645         //u8Byte                                BeginTime, EndTime;
3646         u8                      regRRSR_RSC;
3647
3648         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
3649                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3650
3651         if(priv->rf_chip == RF_PSEUDO_11N)
3652         {
3653                 priv->SetBWModeInProgress= FALSE;
3654                 return;
3655         }
3656
3657         if(!priv->up)
3658                 return;
3659
3660         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3661         //NowL = read_nic_dword(dev, TSFR);
3662         //NowH = read_nic_dword(dev, TSFR+4);
3663         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3664
3665         //3<1>Set MAC register
3666         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3667         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3668
3669         switch(priv->CurrentChannelBW)
3670         {
3671                 case HT_CHANNEL_WIDTH_20:
3672                         regBwOpMode |= BW_OPMODE_20MHZ;
3673                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3674                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3675                         break;
3676
3677                 case HT_CHANNEL_WIDTH_20_40:
3678                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3679                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3680                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3681                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3682                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3683
3684                         break;
3685
3686                 default:
3687                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
3688                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3689                         break;
3690         }
3691
3692         //3 <2>Set PHY related register
3693         switch(priv->CurrentChannelBW)
3694         {
3695                 case HT_CHANNEL_WIDTH_20:
3696                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3697                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3698
3699                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
3700
3701                         break;
3702                 case HT_CHANNEL_WIDTH_20_40:
3703                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3704                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3705
3706                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3707                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3708                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3709
3710                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
3711
3712                         break;
3713
3714
3715                 default:
3716                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
3717                                                 ,priv->CurrentChannelBW);
3718                         break;
3719
3720         }
3721         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3722
3723         //3<3>Set RF related register
3724         switch( priv->rf_chip )
3725         {
3726                 case RF_8225:
3727                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3728                         break;
3729
3730                 case RF_8256:
3731                         // Please implement this function in Hal8190PciPhy8256.c
3732                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3733                         break;
3734
3735                 case RF_6052:
3736                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3737                         break;
3738
3739                 case RF_8258:
3740                         // Please implement this function in Hal8190PciPhy8258.c
3741                         // PHY_SetRF8258Bandwidth();
3742                         break;
3743
3744                 case RF_PSEUDO_11N:
3745                         // Do Nothing
3746                         break;
3747
3748                 default:
3749                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3750                         break;
3751         }
3752
3753         priv->SetBWModeInProgress= FALSE;
3754
3755         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
3756 }
3757
3758 //--------------------------Move to oter DIR later-------------------------------*/
3759 void InitialGain8192S(struct net_device *dev,   u8 Operation)
3760 {
3761 #ifdef TO_DO_LIST
3762         struct r8192_priv *priv = ieee80211_priv(dev);
3763 #endif
3764
3765 }
3766
3767 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
3768 {
3769         struct r8192_priv *priv = ieee80211_priv(dev);
3770
3771         priv->InitialGainOperateType = Operation;
3772
3773         if(priv->up)
3774         {
3775                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
3776         }
3777 }
3778
3779 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
3780 {
3781         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
3782        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
3783        struct net_device *dev = priv->ieee80211->dev;
3784 #define SCAN_RX_INITIAL_GAIN    0x17
3785 #define POWER_DETECTION_TH      0x08
3786         u32     BitMask;
3787         u8      initial_gain;
3788         u8      Operation;
3789
3790         Operation = priv->InitialGainOperateType;
3791
3792         switch(Operation)
3793         {
3794                 case IG_Backup:
3795                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3796                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
3797                         BitMask = bMaskByte0;
3798                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3799                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3800                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3801                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3802                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3803                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3804                         BitMask  = bMaskByte2;
3805                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3806
3807                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3808                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3809                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3810                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3811                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3812
3813                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3814                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3815                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3816                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3817                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3818                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3819                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3820                         break;
3821                 case IG_Restore:
3822                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3823                         BitMask = 0x7f; //Bit0~ Bit6
3824                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3825                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3826
3827                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3828                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3829                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3830                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3831                         BitMask  = bMaskByte2;
3832                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3833
3834                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3835                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3836                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3837                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3838                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3839
3840                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
3841
3842                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3843                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
3844                         break;
3845                 default:
3846                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3847                         break;
3848         }
3849 }
3850
3851
3852 //-----------------------------------------------------------------------------
3853 //      Description:
3854 //              Schedule workitem to send specific CMD IO to FW.
3855 //      Added by Roger, 2008.12.03.
3856 //
3857 //-----------------------------------------------------------------------------
3858 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
3859 {
3860         struct r8192_priv *priv = ieee80211_priv(dev);
3861         u16     FwCmdWaitCounter = 0;
3862
3863         u16     FwCmdWaitLimit = 1000;
3864
3865         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
3866         if(priv->bInHctTest)
3867                 return true;
3868
3869         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
3870
3871         // Will be done by high power respectively.
3872         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
3873         {
3874                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
3875                 return false;
3876         }
3877
3878 #if 1
3879         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
3880         {
3881                 //if(RT_USB_CANNOT_IO(Adapter))
3882                 //{
3883                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
3884                 //      return FALSE;
3885                 //}
3886
3887                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
3888                 return false;
3889                 FwCmdWaitCounter ++;
3890                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
3891                 udelay(100);
3892         }
3893
3894         if(FwCmdWaitCounter == FwCmdWaitLimit)
3895         {
3896                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
3897                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
3898                 //return false;
3899         }
3900 #endif
3901         if (priv->SetFwCmdInProgress)
3902         {
3903                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
3904                 return false;
3905         }
3906         priv->SetFwCmdInProgress = TRUE;
3907         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
3908
3909         phy_SetFwCmdIOCallback(dev);
3910         return true;
3911 }
3912 void ChkFwCmdIoDone(struct net_device* dev)
3913 {
3914         u16 PollingCnt = 1000;
3915         u32 tmpValue;
3916
3917         do
3918         {// Make sure that CMD IO has be accepted by FW.
3919 #ifdef TO_DO_LIST
3920                 if(RT_USB_CANNOT_IO(Adapter))
3921                 {
3922                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
3923                         return;
3924                 }
3925 #endif
3926                 udelay(10); // sleep 20us
3927                 tmpValue = read_nic_dword(dev, WFM5);
3928                 if(tmpValue == 0)
3929                 {
3930                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
3931                         break;
3932                 }
3933                 else
3934                 {
3935                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
3936                 }
3937         }while( --PollingCnt );
3938
3939         if(PollingCnt == 0)
3940         {
3941                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
3942         }
3943 }
3944 //      Callback routine of the timer callback for FW Cmd IO.
3945 //
3946 //      Description:
3947 //              This routine will send specific CMD IO to FW and check whether it is done.
3948 //
3949 void phy_SetFwCmdIOCallback(struct net_device* dev)
3950 {
3951         //struct net_device* dev = (struct net_device*) data;
3952         u32             input;
3953         static u32 ScanRegister;
3954         struct r8192_priv *priv = ieee80211_priv(dev);
3955         if(!priv->up)
3956         {
3957                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
3958                 return;
3959         }
3960
3961         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
3962
3963         switch(priv->CurrentFwCmdIO)
3964         {
3965                 case FW_CMD_HIGH_PWR_ENABLE:
3966                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3967                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
3968                         break;
3969
3970                 case FW_CMD_HIGH_PWR_DISABLE:
3971                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
3972                         break;
3973
3974                 case FW_CMD_DIG_RESUME:
3975                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3976                         break;
3977
3978                 case FW_CMD_DIG_HALT:
3979                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
3980                         break;
3981
3982                 //
3983                 // <Roger_Notes> The following FW CMD IO was combined into single operation
3984                 // (i.e., to prevent number of system workitem out of resource!!).
3985                 // 2008.12.04.
3986                 //
3987                 case FW_CMD_RESUME_DM_BY_SCAN:
3988                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
3989                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
3990                         {
3991                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
3992                                 ChkFwCmdIoDone(dev);
3993                         }
3994                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
3995                         break;
3996
3997                 case FW_CMD_PAUSE_DM_BY_SCAN:
3998                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
3999                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4000                         ChkFwCmdIoDone(dev);
4001                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4002                         break;
4003
4004                 //
4005                 // <Roger_Notes> The following FW CMD IO should be checked
4006                 // (i.e., workitem schedule timing issue!!).
4007                 // 2008.12.04.
4008                 //
4009                 case FW_CMD_DIG_DISABLE:
4010                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4011                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4012                         break;
4013
4014                 case FW_CMD_DIG_ENABLE:
4015                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4016                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4017                         break;
4018
4019                 case FW_CMD_RA_RESET:
4020                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4021                         break;
4022
4023                 case FW_CMD_RA_ACTIVE:
4024                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4025                         break;
4026
4027                 case FW_CMD_RA_REFRESH_N:
4028                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4029                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4030                                 input = FW_RA_REFRESH;
4031                         else
4032                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4033                         write_nic_dword(dev, WFM5, input);
4034                         break;
4035                 case FW_CMD_RA_REFRESH_BG:
4036                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4037                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4038                         ChkFwCmdIoDone(dev);
4039                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4040                         break;
4041
4042                 case FW_CMD_IQK_ENABLE:
4043                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4044                         break;
4045
4046                 case FW_CMD_TXPWR_TRACK_ENABLE:
4047                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4048                         break;
4049
4050                 case FW_CMD_TXPWR_TRACK_DISABLE:
4051                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4052                         break;
4053
4054                 default:
4055                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4056                         break;
4057         }
4058
4059         ChkFwCmdIoDone(dev);
4060
4061         switch(priv->CurrentFwCmdIO)
4062         {
4063                 case FW_CMD_HIGH_PWR_DISABLE:
4064                         //if(pMgntInfo->bTurboScan)
4065                         {
4066                                 //Lower initial gain
4067                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4068                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4069                                 // CCA threshold
4070                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4071                                 // Disable OFDM Part
4072                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4073                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4074                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4075                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4076                         }
4077                         break;
4078
4079                 case FW_CMD_HIGH_PWR_ENABLE:
4080                         //if(pMgntInfo->bTurboScan)
4081                         {
4082                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4083                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4084
4085                                 // CCA threshold
4086                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4087                                 // Enable OFDM Part
4088                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4089
4090                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4091                                 if(ScanRegister != 0){
4092                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
4093                                 }
4094
4095                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
4096                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
4097                                 else
4098                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
4099                         }
4100                         break;
4101         }
4102
4103         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
4104         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
4105
4106 }
4107