SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_phy.c

   1 /******************************************************************************
   2
   3      (c) Copyright 2008, RealTEK Technologies Inc. All Rights Reserved.
   4
   5  Module:        hal8192sphy.c
   6
   7  Note:          Merge 92SE/SU PHY config as below
   8                         1. BB register R/W API
   9                         2. RF register R/W API
  10                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  11                         3. Power setting API
  12                         4. Channel switch API
  13                         5. Initial gain switch API.
  14                         6. Other BB/MAC/RF API.
  15
  16  Function:      PHY: Extern function, phy: local function
  17
  18  Export:        PHY_FunctionName
  19
  20  Abbrev:        NONE
  21
  22  History:
  23         Data            Who             Remark
  24         08/08/2008  MHC         1. Port from 9x series phycfg.c
  25                                                 2. Reorganize code arch and ad description.
  26                                                 3. Collect similar function.
  27                                                 4. Seperate extern/local API.
  28         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  29         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  30         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  31                                                 area to map with EEPROM/EFUSE tx pwr index.
  32
  33 ******************************************************************************/
  34 #include "r8192U.h"
  35 #include "r8192U_dm.h"
  36 #include "r8192S_rtl6052.h"
  37
  38 #ifdef RTL8192SU
  39 #include "r8192S_hw.h"
  40 #include "r8192S_phy.h"
  41 #include "r8192S_phyreg.h"
  42 #include "r8192SU_HWImg.h"
  43 //#include "r8192S_FwImgDTM.h"
  44 #else
  45 #include "r8192U_hw.h"
  46 #include "r819xU_phy.h"
  47 #include "r819xU_phyreg.h"
  48 #endif
  49
  50 #ifdef ENABLE_DOT11D
  51 #include "ieee80211/dot11d.h"
  52 #endif
  53
  54 /*---------------------------Define Local Constant---------------------------*/
  55 /* Channel switch:The size of command tables for switch channel*/
  56 #define MAX_PRECMD_CNT 16
  57 #define MAX_RFDEPENDCMD_CNT 16
  58 #define MAX_POSTCMD_CNT 16
  59 #define MAX_DOZE_WAITING_TIMES_9x 64
  60
  61 /*------------------------Define local variable------------------------------*/
  62 // 2004-05-11
  63 #ifndef RTL8192SU
  64 static u32      RF_CHANNEL_TABLE_ZEBRA[]={
  65                 0,
  66                 0x085c,//2412 1
  67                 0x08dc,//2417 2
  68                 0x095c,//2422 3
  69                 0x09dc,//2427 4
  70                 0x0a5c,//2432 5
  71                 0x0adc,//2437 6
  72                 0x0b5c,//2442 7
  73                 0x0bdc,//2447 8
  74                 0x0c5c,//2452 9
  75                 0x0cdc,//2457 10
  76                 0x0d5c,//2462 11
  77                 0x0ddc,//2467 12
  78                 0x0e5c,//2472 13
  79                 //0x0f5c,//2484
  80                 0x0f72,//2484  //20040810
  81 };
  82 #endif
  83
  84 static  u32
  85 phy_CalculateBitShift(u32 BitMask);
  86 static  RT_STATUS
  87 phy_ConfigMACWithHeaderFile(struct net_device* dev);
  88 static void
  89 phy_InitBBRFRegisterDefinition(struct net_device* dev);
  90 static  RT_STATUS
  91 phy_BB8192S_Config_ParaFile(struct net_device* dev);
  92 static  RT_STATUS
  93 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType);
  94 static bool
  95 phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState);
  96 void
  97 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
  98 void
  99 SetBWModeCallback8192SUsbWorkItem(struct net_device *dev);
 100 void
 101 SwChnlCallback8192SUsbWorkItem(struct net_device *dev );
 102 static void
 103 phy_FinishSwChnlNow(struct net_device* dev,u8 channel);
 104 static bool
 105 phy_SwChnlStepByStep(
 106         struct net_device* dev,
 107         u8              channel,
 108         u8              *stage,
 109         u8              *step,
 110         u32             *delay
 111         );
 112 static RT_STATUS
 113 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
 114 #ifdef RTL8192SE
 115 static  u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
 116 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
 117 static  void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 118 static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
 119 #endif
 120 static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE   WirelessMode, u8 TxPwrIdx);
 121 static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
 122 void phy_SetFwCmdIOCallback(struct net_device* dev);
 123
 124 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 125 #ifdef RTL8192SU
 126 //
 127 // Description:
 128 //      Base Band read by 4181 to make sure that operation could be done in unlimited cycle.
 129 //
 130 // Assumption:
 131 //              -       Only use on RTL8192S USB interface.
 132 //              -       PASSIVE LEVEL
 133 //
 134 // Created by Roger, 2008.09.06.
 135 //
 136 //use in phy only
 137 u32 phy_QueryUsbBBReg(struct net_device* dev, u32       RegAddr)
 138 {
 139         struct r8192_priv *priv = ieee80211_priv(dev);
 140         u32     ReturnValue = 0xffffffff;
 141         u8      PollingCnt = 50;
 142         u8      BBWaitCounter = 0;
 143
 144
 145         //
 146         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 147         // We have to make sure that previous BB I/O has been done.
 148         // 2008.08.20.
 149         //
 150         while(priv->bChangeBBInProgress)
 151         {
 152                 BBWaitCounter ++;
 153                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 154                 msleep(1); // 1 ms
 155
 156                 // Wait too long, return FALSE to avoid to be stuck here.
 157                 if((BBWaitCounter > 100) )//||RT_USB_CANNOT_IO(Adapter))
 158                 {
 159                         RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 160                         return ReturnValue;
 161                 }
 162         }
 163
 164         priv->bChangeBBInProgress = true;
 165
 166         read_nic_dword(dev, RegAddr);
 167
 168         do
 169         {// Make sure that access could be done.
 170                 if((read_nic_byte(dev, PHY_REG)&HST_RDBUSY) == 0)
 171                         break;
 172         }while( --PollingCnt );
 173
 174         if(PollingCnt == 0)
 175         {
 176                 RT_TRACE(COMP_RF, "Fail!!!phy_QueryUsbBBReg(): RegAddr(%#x) = %#x\n", RegAddr, ReturnValue);
 177         }
 178         else
 179         {
 180                 // Data FW read back.
 181                 ReturnValue = read_nic_dword(dev, PHY_REG_DATA);
 182                 RT_TRACE(COMP_RF, "phy_QueryUsbBBReg(): RegAddr(%#x) = %#x, PollingCnt(%d)\n", RegAddr, ReturnValue, PollingCnt);
 183         }
 184
 185         priv->bChangeBBInProgress = false;
 186
 187         return ReturnValue;
 188 }
 189
 190
 191
 192 //
 193 // Description:
 194 //      Base Band wrote by 4181 to make sure that operation could be done in unlimited cycle.
 195 //
 196 // Assumption:
 197 //              -       Only use on RTL8192S USB interface.
 198 //              -       PASSIVE LEVEL
 199 //
 200 // Created by Roger, 2008.09.06.
 201 //
 202 //use in phy only
 203 void
 204 phy_SetUsbBBReg(struct net_device* dev,u32      RegAddr,u32 Data)
 205 {
 206         struct r8192_priv *priv = ieee80211_priv(dev);
 207         u8      BBWaitCounter = 0;
 208
 209         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): RegAddr(%#x) <= %#x\n", RegAddr, Data);
 210
 211         //
 212         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 213         // We have to make sure that previous BB I/O has been done.
 214         // 2008.08.20.
 215         //
 216         while(priv->bChangeBBInProgress)
 217         {
 218                 BBWaitCounter ++;
 219                 RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): Wait 1 ms (%d times)...\n", BBWaitCounter);
 220                 msleep(1); // 1 ms
 221
 222                 if((BBWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 223                 {
 224                         RT_TRACE(COMP_RF, "phy_SetUsbBBReg(): (%d) Wait too logn to query BB!!\n", BBWaitCounter);
 225                         return;
 226                 }
 227         }
 228
 229         priv->bChangeBBInProgress = true;
 230         //printk("**************%s: RegAddr:%x Data:%x\n", __FUNCTION__,RegAddr, Data);
 231         write_nic_dword(dev, RegAddr, Data);
 232
 233         priv->bChangeBBInProgress = false;
 234 }
 235
 236
 237
 238 //
 239 // Description:
 240 //      RF read by 4181 to make sure that operation could be done in unlimited cycle.
 241 //
 242 // Assumption:
 243 //              -       Only use on RTL8192S USB interface.
 244 //              -       PASSIVE LEVEL
 245 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 246 //
 247 // Created by Roger, 2008.09.06.
 248 //
 249 //use in phy only
 250 u32 phy_QueryUsbRFReg(  struct net_device* dev, RF90_RADIO_PATH_E eRFPath,      u32     Offset)
 251 {
 252
 253         struct r8192_priv *priv = ieee80211_priv(dev);
 254         //u32   value  = 0, ReturnValue = 0;
 255         u32     ReturnValue = 0;
 256         //u32   tmplong,tmplong2;
 257         u8      PollingCnt = 50;
 258         u8      RFWaitCounter = 0;
 259
 260
 261         //
 262         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 263         // We have to make sure that previous RF I/O has been done.
 264         // 2008.08.20.
 265         //
 266         while(priv->bChangeRFInProgress)
 267         {
 268                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 269                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 270                 down(&priv->rf_sem);
 271
 272                 RFWaitCounter ++;
 273                 RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 274                 msleep(1); // 1 ms
 275
 276                 if((RFWaitCounter > 100)) //|| RT_USB_CANNOT_IO(Adapter))
 277                 {
 278                         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 279                         return 0xffffffff;
 280                 }
 281                 else
 282                 {
 283                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 284                 }
 285         }
 286
 287         priv->bChangeRFInProgress = true;
 288         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 289
 290
 291         Offset &= 0x3f; //RF_Offset= 0x00~0x3F
 292
 293         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000002|
 294                                                 (Offset<<8)|    //RF_Offset= 0x00~0x3F
 295                                                 (eRFPath<<16));         //RF_Path = 0(A) or 1(B)
 296
 297         do
 298         {// Make sure that access could be done.
 299                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 300                         break;
 301         }while( --PollingCnt );
 302
 303         // Data FW read back.
 304         ReturnValue = read_nic_dword(dev, RF_BB_CMD_DATA);
 305
 306         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 307         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 308         up(&priv->rf_sem);
 309         priv->bChangeRFInProgress = false;
 310
 311         RT_TRACE(COMP_RF, "phy_QueryUsbRFReg(): eRFPath(%d), Offset(%#x) = %#x\n", eRFPath, Offset, ReturnValue);
 312
 313         return ReturnValue;
 314
 315 }
 316
 317
 318 //
 319 // Description:
 320 //      RF wrote by 4181 to make sure that operation could be done in unlimited cycle.
 321 //
 322 // Assumption:
 323 //              -       Only use on RTL8192S USB interface.
 324 //              -       PASSIVE LEVEL
 325 //              -       RT_RF_OPERATE_SPINLOCK is acquired and keep on holding to the end.FIXLZM
 326 //
 327 // Created by Roger, 2008.09.06.
 328 //
 329 //use in phy only
 330 void phy_SetUsbRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32       RegAddr,u32 Data)
 331 {
 332
 333         struct r8192_priv *priv = ieee80211_priv(dev);
 334         u8      PollingCnt = 50;
 335         u8      RFWaitCounter = 0;
 336
 337
 338         //
 339         // <Roger_Notes> Due to PASSIVE_LEVEL, so we ONLY simply busy waiting for a while here.
 340         // We have to make sure that previous BB I/O has been done.
 341         // 2008.08.20.
 342         //
 343         while(priv->bChangeRFInProgress)
 344         {
 345                 //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 346                 //spin_lock_irqsave(&priv->rf_lock, flags);     //LZM,090318
 347                 down(&priv->rf_sem);
 348
 349                 RFWaitCounter ++;
 350                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Wait 1 ms (%d times)...\n", RFWaitCounter);
 351                 msleep(1); // 1 ms
 352
 353                 if((RFWaitCounter > 100))// || RT_USB_CANNOT_IO(Adapter))
 354                 {
 355                         RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): (%d) Wait too logn to query BB!!\n", RFWaitCounter);
 356                         return;
 357                 }
 358                 else
 359                 {
 360                         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 361                 }
 362         }
 363
 364         priv->bChangeRFInProgress = true;
 365         //PlatformReleaseSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 366
 367
 368         RegAddr &= 0x3f; //RF_Offset= 0x00~0x3F
 369
 370         write_nic_dword(dev, RF_BB_CMD_DATA, Data);
 371         write_nic_dword(dev, RF_BB_CMD_ADDR, 0xF0000003|
 372                                         (RegAddr<<8)| //RF_Offset= 0x00~0x3F
 373                                         (eRFPath<<16));  //RF_Path = 0(A) or 1(B)
 374
 375         do
 376         {// Make sure that access could be done.
 377                 if(read_nic_dword(dev, RF_BB_CMD_ADDR) == 0)
 378                                 break;
 379         }while( --PollingCnt );
 380
 381         if(PollingCnt == 0)
 382         {
 383                 RT_TRACE(COMP_RF, "phy_SetUsbRFReg(): Set RegAddr(%#x) = %#x Fail!!!\n", RegAddr, Data);
 384         }
 385
 386         //PlatformAcquireSpinLock(Adapter, RT_RF_OPERATE_SPINLOCK);
 387         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //LZM,090318
 388         up(&priv->rf_sem);
 389         priv->bChangeRFInProgress = false;
 390
 391 }
 392
 393 #endif
 394
 395 /*---------------------Define local function prototype-----------------------*/
 396
 397
 398 /*----------------------------Function Body----------------------------------*/
 399 //
 400 // 1. BB register R/W API
 401 //
 402 /**
 403 * Function:     PHY_QueryBBReg
 404 *
 405 * OverView:     Read "sepcific bits" from BB register
 406 *
 407 * Input:
 408 *                       PADAPTER                Adapter,
 409 *                       u32                     RegAddr,                //The target address to be readback
 410 *                       u32                     BitMask         //The target bit position in the target address
 411 *                                                                               //to be readback
 412 * Output:       None
 413 * Return:               u32                     Data                    //The readback register value
 414 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 415 */
 416 //use phy dm core 8225 8256 6052
 417 //u32 PHY_QueryBBReg(struct net_device* dev,u32         RegAddr,        u32             BitMask)
 418 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 RegAddr, u32 BitMask)
 419 {
 420
 421         u32     ReturnValue = 0, OriginalValue, BitShift;
 422
 423 #if (DISABLE_BB_RF == 1)
 424         return 0;
 425 #endif
 426
 427         RT_TRACE(COMP_RF, "--->PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x)\n", RegAddr, BitMask);
 428
 429         //
 430         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 431         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 432         // infinite cycle.
 433         // 2008.09.06.
 434         //
 435 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 436 #ifdef RTL8192SU
 437         if(IS_BB_REG_OFFSET_92S(RegAddr))
 438         {
 439                 //if(RT_USB_CANNOT_IO(Adapter)) return  FALSE;
 440
 441                 if((RegAddr & 0x03) != 0)
 442                 {
 443                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 444                         return 0;
 445                 }
 446
 447         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 448         }
 449         else
 450 #endif
 451         {
 452         OriginalValue = read_nic_dword(dev, RegAddr);
 453         }
 454
 455         BitShift = phy_CalculateBitShift(BitMask);
 456         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 457
 458         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%x Addr[0x%x]=0x%x\n", BitMask, RegAddr, OriginalValue));
 459         RT_TRACE(COMP_RF, "<---PHY_QueryBBReg(): RegAddr(%#x), BitMask(%#x), OriginalValue(%#x)\n", RegAddr, BitMask, OriginalValue);
 460         return (ReturnValue);
 461 }
 462
 463 /**
 464 * Function:     PHY_SetBBReg
 465 *
 466 * OverView:     Write "Specific bits" to BB register (page 8~)
 467 *
 468 * Input:
 469 *                       PADAPTER                Adapter,
 470 *                       u32                     RegAddr,                //The target address to be modified
 471 *                       u32                     BitMask         //The target bit position in the target address
 472 *                                                                               //to be modified
 473 *                       u32                     Data                    //The new register value in the target bit position
 474 *                                                                               //of the target address
 475 *
 476 * Output:       None
 477 * Return:               None
 478 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 479 */
 480 //use phy dm core 8225 8256
 481 //void PHY_SetBBReg(struct net_device* dev,u32          RegAddr,        u32             BitMask,        u32             Data    )
 482 void rtl8192_setBBreg(struct net_device* dev, u32 RegAddr, u32 BitMask, u32 Data)
 483 {
 484         u32     OriginalValue, BitShift, NewValue;
 485
 486 #if (DISABLE_BB_RF == 1)
 487         return;
 488 #endif
 489
 490         RT_TRACE(COMP_RF, "--->PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 491
 492         //
 493         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 494         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 495         // infinite cycle.
 496         // 2008.09.06.
 497         //
 498 //#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
 499 #ifdef RTL8192SU
 500         if(IS_BB_REG_OFFSET_92S(RegAddr))
 501         {
 502                 if((RegAddr & 0x03) != 0)
 503                 {
 504                         printk("%s: Not DWORD alignment!!\n", __FUNCTION__);
 505                         return;
 506                 }
 507
 508                 if(BitMask!= bMaskDWord)
 509                 {//if not "double word" write
 510                         OriginalValue = phy_QueryUsbBBReg(dev, RegAddr);
 511                         BitShift = phy_CalculateBitShift(BitMask);
 512             NewValue = (((OriginalValue) & (~BitMask))|(Data << BitShift));
 513                         phy_SetUsbBBReg(dev, RegAddr, NewValue);
 514                 }else
 515                         phy_SetUsbBBReg(dev, RegAddr, Data);
 516         }
 517         else
 518 #endif
 519         {
 520                 if(BitMask!= bMaskDWord)
 521                 {//if not "double word" write
 522                         OriginalValue = read_nic_dword(dev, RegAddr);
 523                         BitShift = phy_CalculateBitShift(BitMask);
 524                         NewValue = (((OriginalValue) & (~BitMask)) | (Data << BitShift));
 525                         write_nic_dword(dev, RegAddr, NewValue);
 526                 }else
 527                         write_nic_dword(dev, RegAddr, Data);
 528         }
 529
 530         //RT_TRACE(COMP_RF, "<---PHY_SetBBReg(): RegAddr(%#x), BitMask(%#x), Data(%#x)\n", RegAddr, BitMask, Data);
 531
 532         return;
 533 }
 534
 535
 536 //
 537 // 2. RF register R/W API
 538 //
 539 /**
 540 * Function:     PHY_QueryRFReg
 541 *
 542 * OverView:     Query "Specific bits" to RF register (page 8~)
 543 *
 544 * Input:
 545 *                       PADAPTER                Adapter,
 546 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 547 *                       u32                     RegAddr,                //The target address to be read
 548 *                       u32                     BitMask         //The target bit position in the target address
 549 *                                                                               //to be read
 550 *
 551 * Output:       None
 552 * Return:               u32                     Readback value
 553 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 554 */
 555 //in dm 8256 and phy
 556 //u32 PHY_QueryRFReg(struct net_device* dev,    RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 557 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
 558 {
 559         u32 Original_Value, Readback_Value, BitShift;//, flags;
 560         struct r8192_priv *priv = ieee80211_priv(dev);
 561
 562 #if (DISABLE_BB_RF == 1)
 563         return 0;
 564 #endif
 565
 566         RT_TRACE(COMP_RF, "--->PHY_QueryRFReg(): RegAddr(%#x), eRFPath(%#x), BitMask(%#x)\n", RegAddr, eRFPath,BitMask);
 567
 568         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 569         {
 570                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 571                 return 0;
 572         }
 573
 574         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 575         {
 576                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 577                 return 0;
 578         }
 579
 580         /* 2008/01/17 MH We get and release spin lock when reading RF register. */
 581         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);FIXLZM
 582         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 583         down(&priv->rf_sem);
 584         //
 585         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 586         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 587         // infinite cycle.
 588         // 2008.09.06.
 589         //
 590 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 591 #ifdef RTL8192SU
 592         //if(RT_USB_CANNOT_IO(Adapter)) return FALSE;
 593         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 594 #else
 595         if (priv->Rf_Mode == RF_OP_By_FW)
 596         {
 597                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 598         }
 599         else
 600         {
 601                 Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 602         }
 603 #endif
 604
 605         BitShift =  phy_CalculateBitShift(BitMask);
 606         Readback_Value = (Original_Value & BitMask) >> BitShift;
 607         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 608         up(&priv->rf_sem);
 609         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 610
 611         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Original_Value));
 612
 613         return (Readback_Value);
 614 }
 615
 616 /**
 617 * Function:     PHY_SetRFReg
 618 *
 619 * OverView:     Write "Specific bits" to RF register (page 8~)
 620 *
 621 * Input:
 622 *                       PADAPTER                Adapter,
 623 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 624 *                       u32                     RegAddr,                //The target address to be modified
 625 *                       u32                     BitMask         //The target bit position in the target address
 626 *                                                                               //to be modified
 627 *                       u32                     Data                    //The new register Data in the target bit position
 628 *                                                                               //of the target address
 629 *
 630 * Output:       None
 631 * Return:               None
 632 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 633 */
 634 //use phy  8225 8256
 635 //void PHY_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32       RegAddr,        u32 BitMask,u32 Data    )
 636 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
 637 {
 638
 639         struct r8192_priv *priv = ieee80211_priv(dev);
 640         u32 Original_Value, BitShift, New_Value;//, flags;
 641 #if (DISABLE_BB_RF == 1)
 642         return;
 643 #endif
 644
 645         RT_TRACE(COMP_RF, "--->PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 646                 RegAddr, BitMask, Data, eRFPath);
 647
 648         if (!((priv->rf_pathmap >> eRFPath) & 0x1))
 649         {
 650                 printk("EEEEEError: rfpath off! rf_pathmap=%x eRFPath=%x\n", priv->rf_pathmap, eRFPath);
 651                 return ;
 652         }
 653         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 654         {
 655                 printk("EEEEEError: not legal rfpath! eRFPath=%x\n", eRFPath);
 656                 return;
 657         }
 658
 659         /* 2008/01/17 MH We get and release spin lock when writing RF register. */
 660         //PlatformAcquireSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 661         //spin_lock_irqsave(&priv->rf_lock, flags);     //YJ,test,090113
 662         down(&priv->rf_sem);
 663         //
 664         // <Roger_Notes> Due to 8051 operation cycle (limitation cycle: 6us) and 1-Byte access issue, we should use
 665         // 4181 to access Base Band instead of 8051 on USB interface to make sure that access could be done in
 666         // infinite cycle.
 667         // 2008.09.06.
 668         //
 669 //#if (HAL_CODE_BASE == RTL8192_S && DEV_BUS_TYPE==USB_INTERFACE)
 670 #ifdef RTL8192SU
 671                 //if(RT_USB_CANNOT_IO(Adapter)) return;
 672
 673                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 674                 {
 675                         Original_Value = phy_QueryUsbRFReg(dev, eRFPath, RegAddr);
 676                         BitShift =  phy_CalculateBitShift(BitMask);
 677                         New_Value = (((Original_Value)&(~BitMask))|(Data<< BitShift));
 678                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, New_Value);
 679                 }
 680                 else
 681                         phy_SetUsbRFReg(dev, eRFPath, RegAddr, Data);
 682 #else
 683         if (priv->Rf_Mode == RF_OP_By_FW)
 684         {
 685                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 686                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 687                 {
 688                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
 689                         BitShift =  phy_CalculateBitShift(BitMask);
 690                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 691
 692                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 693                 }
 694                 else
 695                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
 696         }
 697         else
 698         {
 699                 //DbgPrint("eRFPath-%d Addr[%02x] = %08x\n", eRFPath, RegAddr, Data);
 700                 if (BitMask != bRFRegOffsetMask) // RF data is 12 bits only
 701                 {
 702                         Original_Value = phy_RFSerialRead(dev, eRFPath, RegAddr);
 703                         BitShift =  phy_CalculateBitShift(BitMask);
 704                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
 705
 706                         phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
 707                 }
 708                 else
 709                         phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
 710
 711         }
 712 #endif
 713         //PlatformReleaseSpinLock(dev, RT_RF_OPERATE_SPINLOCK);
 714         //spin_unlock_irqrestore(&priv->rf_lock, flags);   //YJ,test,090113
 715         up(&priv->rf_sem);
 716         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d MASK=0x%x Addr[0x%x]=0x%x\n", eRFPath, BitMask, RegAddr, Data));
 717         RT_TRACE(COMP_RF, "<---PHY_SetRFReg(): RegAddr(%#x), BitMask(%#x), Data(%#x), eRFPath(%#x)\n",
 718                         RegAddr, BitMask, Data, eRFPath);
 719
 720 }
 721
 722 #ifdef RTL8192SE
 723 /*-----------------------------------------------------------------------------
 724  * Function:    phy_FwRFSerialRead()
 725  *
 726  * Overview:    We support firmware to execute RF-R/W.
 727  *
 728  * Input:               NONE
 729  *
 730  * Output:              NONE
 731  *
 732  * Return:              NONE
 733  *
 734  * Revised History:
 735  *      When            Who             Remark
 736  *      01/21/2008      MHC             Create Version 0.
 737  *
 738  *---------------------------------------------------------------------------*/
 739 //use in phy only
 740 static  u32
 741 phy_FwRFSerialRead(
 742         struct net_device* dev,
 743         RF90_RADIO_PATH_E       eRFPath,
 744         u32                             Offset  )
 745 {
 746         u32             retValue = 0;
 747         //u32           Data = 0;
 748         //u8            time = 0;
 749 #if 0
 750         //DbgPrint("FW RF CTRL\n\r");
 751         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 752            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 753            much time. This is only for site survey. */
 754         // 1. Read operation need not insert data. bit 0-11
 755         //Data &= bMask12Bits;
 756         // 2. Write RF register address. Bit 12-19
 757         Data |= ((Offset&0xFF)<<12);
 758         // 3. Write RF path.  bit 20-21
 759         Data |= ((eRFPath&0x3)<<20);
 760         // 4. Set RF read indicator. bit 22=0
 761         //Data |= 0x00000;
 762         // 5. Trigger Fw to operate the command. bit 31
 763         Data |= 0x80000000;
 764         // 6. We can not execute read operation if bit 31 is 1.
 765         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 766         {
 767                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 768                 if (time++ < 100)
 769                 {
 770                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
 771                         delay_us(10);
 772                 }
 773                 else
 774                         break;
 775         }
 776         // 7. Execute read operation.
 777         PlatformIOWrite4Byte(dev, QPNR, Data);
 778         // 8. Check if firmawre send back RF content.
 779         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 780         {
 781                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 782                 if (time++ < 100)
 783                 {
 784                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 785                         delay_us(10);
 786                 }
 787                 else
 788                         return  (0);
 789         }
 790         retValue = PlatformIORead4Byte(dev, RF_DATA);
 791 #endif
 792         return  (retValue);
 793
 794 }       /* phy_FwRFSerialRead */
 795
 796 /*-----------------------------------------------------------------------------
 797  * Function:    phy_FwRFSerialWrite()
 798  *
 799  * Overview:    We support firmware to execute RF-R/W.
 800  *
 801  * Input:               NONE
 802  *
 803  * Output:              NONE
 804  *
 805  * Return:              NONE
 806  *
 807  * Revised History:
 808  *      When            Who             Remark
 809  *      01/21/2008      MHC             Create Version 0.
 810  *
 811  *---------------------------------------------------------------------------*/
 812 //use in phy only
 813 static  void
 814 phy_FwRFSerialWrite(
 815         struct net_device* dev,
 816         RF90_RADIO_PATH_E       eRFPath,
 817         u32                             Offset,
 818         u32                             Data    )
 819 {
 820 #if 0
 821         u8      time = 0;
 822         DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
 823         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
 824            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
 825            much time. This is only for site survey. */
 826
 827         // 1. Set driver write bit and 12 bit data. bit 0-11
 828         //Data &= bMask12Bits;  // Done by uper layer.
 829         // 2. Write RF register address. bit 12-19
 830         Data |= ((Offset&0xFF)<<12);
 831         // 3. Write RF path.  bit 20-21
 832         Data |= ((eRFPath&0x3)<<20);
 833         // 4. Set RF write indicator. bit 22=1
 834         Data |= 0x400000;
 835         // 5. Trigger Fw to operate the command. bit 31=1
 836         Data |= 0x80000000;
 837
 838         // 6. Write operation. We can not write if bit 31 is 1.
 839         while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
 840         {
 841                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
 842                 if (time++ < 100)
 843                 {
 844                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
 845                         delay_us(10);
 846                 }
 847                 else
 848                         break;
 849         }
 850         // 7. No matter check bit. We always force the write. Because FW will
 851         //    not accept the command.
 852         PlatformIOWrite4Byte(dev, QPNR, Data);
 853         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
 854            to finish RF write operation. */
 855         /* 2008/01/17 MH We support delay in firmware side now. */
 856         //delay_us(20);
 857 #endif
 858 }       /* phy_FwRFSerialWrite */
 859
 860 /**
 861 * Function:     phy_RFSerialRead
 862 *
 863 * OverView:     Read regster from RF chips
 864 *
 865 * Input:
 866 *                       PADAPTER                Adapter,
 867 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 868 *                       u32                     Offset,         //The target address to be read
 869 *
 870 * Output:       None
 871 * Return:               u32                     reback value
 872 * Note:         Threre are three types of serial operations:
 873 *                       1. Software serial write
 874 *                       2. Hardware LSSI-Low Speed Serial Interface
 875 *                       3. Hardware HSSI-High speed
 876 *                       serial write. Driver need to implement (1) and (2).
 877 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 878 */
 879 //use in phy only
 880 static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
 881 {
 882
 883         u32                                             retValue = 0;
 884         struct r8192_priv *priv = ieee80211_priv(dev);
 885         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
 886         u32                                             NewOffset;
 887         u8                                              RfPiEnable=0;
 888
 889
 890         //
 891         // Make sure RF register offset is correct
 892         //
 893         Offset &= 0x3f;
 894
 895         //
 896         // Switch page for 8256 RF IC
 897         //
 898         if(     priv->rf_chip == RF_8256 ||
 899                 priv->rf_chip == RF_8225 ||
 900                 priv->rf_chip == RF_6052)
 901         {
 902                 //analog to digital off, for protection
 903                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
 904
 905                 if(Offset>=31)
 906                 {
 907                         priv->RFReadPageCnt[2]++;//cosa add for debug
 908                         priv->RfReg0Value[eRFPath] |= 0x140;
 909
 910                         // Switch to Reg_Mode2 for Reg31~45
 911                         rtl8192_setBBreg(dev,
 912                                 pPhyReg->rf3wireOffset,
 913                                 bMaskDWord,
 914                                 (priv->RfReg0Value[eRFPath] << 16)      );
 915
 916                         // Modified Offset
 917                         NewOffset = Offset - 30;
 918
 919                 }else if(Offset>=16)
 920                 {
 921                         priv->RFReadPageCnt[1]++;//cosa add for debug
 922                         priv->RfReg0Value[eRFPath] |= 0x100;
 923                         priv->RfReg0Value[eRFPath] &= (~0x40);
 924
 925                         // Switch to Reg_Mode1 for Reg16~30
 926                         rtl8192_setBBreg(dev,
 927                                 pPhyReg->rf3wireOffset,
 928                                 bMaskDWord,
 929                                 (priv->RfReg0Value[eRFPath] << 16)      );
 930
 931                         // Modified Offset
 932                         NewOffset = Offset - 15;
 933                 }
 934                 else
 935                 {
 936                         priv->RFReadPageCnt[0]++;//cosa add for debug
 937                         NewOffset = Offset;
 938         }
 939         }
 940         else
 941                 NewOffset = Offset;
 942
 943         //
 944         // Put desired read address to LSSI control register
 945         //
 946         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
 947
 948         //
 949         // Issue a posedge trigger
 950         //
 951         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
 952         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 953
 954         // TODO: we should not delay such a  long time. Ask help from SD3
 955         mdelay(1);
 956
 957         retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 958
 959         // Switch back to Reg_Mode0;
 960         if(     priv->rf_chip == RF_8256 ||
 961                 priv->rf_chip == RF_8225 ||
 962                 priv->rf_chip == RF_0222D)
 963         {
 964                 if (Offset >= 0x10)
 965                 {
 966                         priv->RfReg0Value[eRFPath] &= 0xebf;
 967
 968                         rtl8192_setBBreg(
 969                                 dev,
 970                                 pPhyReg->rf3wireOffset,
 971                                 bMaskDWord,
 972                                 (priv->RfReg0Value[eRFPath] << 16)      );
 973                 }
 974
 975                 //analog to digital on
 976                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
 977         }
 978
 979         return retValue;
 980 }
 981
 982
 983
 984 /**
 985 * Function:     phy_RFSerialWrite
 986 *
 987 * OverView:     Write data to RF register (page 8~)
 988 *
 989 * Input:
 990 *                       PADAPTER                Adapter,
 991 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
 992 *                       u32                     Offset,         //The target address to be read
 993 *                       u32                     Data                    //The new register Data in the target bit position
 994 *                                                                               //of the target to be read
 995 *
 996 * Output:       None
 997 * Return:               None
 998 * Note:         Threre are three types of serial operations:
 999 *                       1. Software serial write
1000 *                       2. Hardware LSSI-Low Speed Serial Interface
1001 *                       3. Hardware HSSI-High speed
1002 *                       serial write. Driver need to implement (1) and (2).
1003 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1004  *
1005  * Note:                  For RF8256 only
1006  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1007  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1008  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1009  *                       programming guide" for more details.
1010  *                       Thus, we define a sub-finction for RTL8526 register address conversion
1011  *                     ===========================================================
1012  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
1013  *                                                              (Reg00[12])             (Reg00[10])
1014  *                     ===========================================================
1015  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1016  *                     ------------------------------------------------------------------
1017  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1018  *                     ------------------------------------------------------------------
1019  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1020  *                     ------------------------------------------------------------------
1021 */
1022 ////use in phy only
1023 static void
1024 phy_RFSerialWrite(
1025         struct net_device* dev,
1026         RF90_RADIO_PATH_E       eRFPath,
1027         u32                             Offset,
1028         u32                             Data
1029         )
1030 {
1031         u32                                     DataAndAddr = 0;
1032         struct r8192_priv                       *priv = ieee80211_priv(dev);
1033         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1034         u32                                     NewOffset;
1035
1036         Offset &= 0x3f;
1037
1038         // Shadow Update
1039         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1040
1041
1042         // Switch page for 8256 RF IC
1043         if(     priv->rf_chip == RF_8256 ||
1044                 priv->rf_chip == RF_8225 ||
1045                 priv->rf_chip == RF_0222D)
1046         {
1047                 //analog to digital off, for protection
1048                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1049
1050                 if(Offset>=31)
1051                 {
1052                         priv->RFWritePageCnt[2]++;//cosa add for debug
1053                         priv->RfReg0Value[eRFPath] |= 0x140;
1054
1055                         rtl8192_setBBreg(dev,
1056                                 pPhyReg->rf3wireOffset,
1057                                 bMaskDWord,
1058                                 (priv->RfReg0Value[eRFPath] << 16)      );
1059
1060                         NewOffset = Offset - 30;
1061
1062                 }else if(Offset>=16)
1063                 {
1064                         priv->RFWritePageCnt[1]++;//cosa add for debug
1065                         priv->RfReg0Value[eRFPath] |= 0x100;
1066                         priv->RfReg0Value[eRFPath] &= (~0x40);
1067
1068
1069                         rtl8192_setBBreg(dev,
1070                                 pPhyReg->rf3wireOffset,
1071                                 bMaskDWord,
1072                                 (priv->RfReg0Value[eRFPath] << 16)      );
1073
1074                         NewOffset = Offset - 15;
1075                 }
1076                 else
1077                 {
1078                         priv->RFWritePageCnt[0]++;//cosa add for debug
1079                         NewOffset = Offset;
1080         }
1081         }
1082         else
1083                 NewOffset = Offset;
1084
1085         //
1086         // Put write addr in [5:0]  and write data in [31:16]
1087         //
1088         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1089
1090         //
1091         // Write Operation
1092         //
1093         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1094
1095
1096         if(Offset==0x0)
1097                 priv->RfReg0Value[eRFPath] = Data;
1098
1099         // Switch back to Reg_Mode0;
1100         if(     priv->rf_chip == RF_8256 ||
1101                 priv->rf_chip == RF_8225 ||
1102                 priv->rf_chip == RF_0222D)
1103         {
1104                 if (Offset >= 0x10)
1105                 {
1106                         if(Offset != 0)
1107                         {
1108                                 priv->RfReg0Value[eRFPath] &= 0xebf;
1109                                 rtl8192_setBBreg(
1110                                 dev,
1111                                 pPhyReg->rf3wireOffset,
1112                                 bMaskDWord,
1113                                 (priv->RfReg0Value[eRFPath] << 16)      );
1114                         }
1115                 }
1116                 //analog to digital on
1117                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1118         }
1119
1120 }
1121 #else
1122 /**
1123 * Function:     phy_RFSerialRead
1124 *
1125 * OverView:     Read regster from RF chips
1126 *
1127 * Input:
1128 *                       PADAPTER                Adapter,
1129 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1130 *                       u4Byte                  Offset,         //The target address to be read
1131 *
1132 * Output:       None
1133 * Return:               u4Byte                  reback value
1134 * Note:         Threre are three types of serial operations:
1135 *                       1. Software serial write
1136 *                       2. Hardware LSSI-Low Speed Serial Interface
1137 *                       3. Hardware HSSI-High speed
1138 *                       serial write. Driver need to implement (1) and (2).
1139 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1140 */
1141 #if 0
1142 static  u32
1143 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
1144 {
1145
1146         u32                                             retValue = 0;
1147         struct r8192_priv *priv = ieee80211_priv(dev);
1148         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1149         u32                                             NewOffset;
1150         //u32                                           value  = 0;
1151         u32                                             tmplong,tmplong2;
1152         u32                                             RfPiEnable=0;
1153 #if 0
1154         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1155                 return  retValue;
1156         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1157                 return  retValue;
1158 #endif
1159         //
1160         // Make sure RF register offset is correct
1161         //
1162         Offset &= 0x3f;
1163
1164         //
1165         // Switch page for 8256 RF IC
1166         //
1167         NewOffset = Offset;
1168
1169         // For 92S LSSI Read RFLSSIRead
1170         // For RF A/B write 0x824/82c(does not work in the future)
1171         // We must use 0x824 for RF A and B to execute read trigger
1172         tmplong = rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord);
1173         tmplong2 = rtl8192_QueryBBReg(dev, pPhyReg->rfHSSIPara2, bMaskDWord);
1174         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF
1175
1176         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
1177         mdelay(1);
1178
1179         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
1180         mdelay(1);
1181
1182         rtl8192_setBBreg(dev, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
1183         mdelay(1);
1184
1185         if(eRFPath == RF90_PATH_A)
1186                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
1187         else if(eRFPath == RF90_PATH_B)
1188                 RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XB_HSSIParameter1, BIT8);
1189
1190         if(RfPiEnable)
1191         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
1192                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
1193                 //DbgPrint("Readback from RF-PI : 0x%x\n", retValue);
1194         }
1195         else
1196         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
1197                 retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1198                 //DbgPrint("Readback from RF-SI : 0x%x\n", retValue);
1199         }
1200         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue));
1201
1202         return retValue;
1203
1204 }
1205 4
1206
1207
1208 /**
1209 * Function:     phy_RFSerialWrite
1210 *
1211 * OverView:     Write data to RF register (page 8~)
1212 *
1213 * Input:
1214 *                       PADAPTER                Adapter,
1215 *                       RF90_RADIO_PATH_E       eRFPath,        //Radio path of A/B/C/D
1216 *                       u4Byte                  Offset,         //The target address to be read
1217 *                       u4Byte                  Data                    //The new register Data in the target bit position
1218 *                                                                               //of the target to be read
1219 *
1220 * Output:       None
1221 * Return:               None
1222 * Note:         Threre are three types of serial operations:
1223 *                       1. Software serial write
1224 *                       2. Hardware LSSI-Low Speed Serial Interface
1225 *                       3. Hardware HSSI-High speed
1226 *                       serial write. Driver need to implement (1) and (2).
1227 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
1228  *
1229  * Note:                  For RF8256 only
1230  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
1231  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
1232  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
1233  *                       programming guide" for more details.
1234  *                       Thus, we define a sub-finction for RTL8526 register address conversion
1235  *                     ===========================================================
1236  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
1237  *                                                              (Reg00[12])             (Reg00[10])
1238  *                     ===========================================================
1239  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
1240  *                     ------------------------------------------------------------------
1241  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
1242  *                     ------------------------------------------------------------------
1243  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1244  *                     ------------------------------------------------------------------
1245  *
1246  *      2008/09/02      MH      Add 92S RF definition
1247  *
1248  *
1249  *
1250 */
1251 static  void
1252 phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32       Data)
1253 {
1254         u32                                             DataAndAddr = 0;
1255         struct r8192_priv *priv = ieee80211_priv(dev);
1256         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1257         u32                                             NewOffset;
1258
1259 #if 0
1260         //<Roger_TODO> We should check valid regs for RF_6052 case.
1261         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
1262                 return;
1263         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
1264                 return;
1265 #endif
1266
1267         Offset &= 0x3f;
1268
1269         //
1270         // Shadow Update
1271         //
1272         PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
1273
1274         //
1275         // Switch page for 8256 RF IC
1276         //
1277                 NewOffset = Offset;
1278
1279         //
1280         // Put write addr in [5:0]  and write data in [31:16]
1281         //
1282         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1283         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF
1284
1285         //
1286         // Write Operation
1287         //
1288         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1289         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
1290
1291 }
1292 #endif
1293 #endif
1294
1295 /**
1296 * Function:     phy_CalculateBitShift
1297 *
1298 * OverView:     Get shifted position of the BitMask
1299 *
1300 * Input:
1301 *                       u32             BitMask,
1302 *
1303 * Output:       none
1304 * Return:               u32             Return the shift bit bit position of the mask
1305 */
1306 //use in phy only
1307 static u32 phy_CalculateBitShift(u32 BitMask)
1308 {
1309         u32 i;
1310
1311         for(i=0; i<=31; i++)
1312         {
1313                 if ( ((BitMask>>i) &  0x1 ) == 1)
1314                         break;
1315         }
1316
1317         return (i);
1318 }
1319
1320
1321 //
1322 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
1323 //
1324 /*-----------------------------------------------------------------------------
1325  * Function:    PHY_MACConfig8192S
1326  *
1327  * Overview:    Condig MAC by header file or parameter file.
1328  *
1329  * Input:       NONE
1330  *
1331  * Output:      NONE
1332  *
1333  * Return:      NONE
1334  *
1335  * Revised History:
1336  *  When                Who             Remark
1337  *  08/12/2008  MHC             Create Version 0.
1338  *
1339  *---------------------------------------------------------------------------*/
1340 //adapter_start
1341 extern bool PHY_MACConfig8192S(struct net_device* dev)
1342 {
1343         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1344
1345         //
1346         // Config MAC
1347         //
1348 #if RTL8190_Download_Firmware_From_Header
1349         rtStatus = phy_ConfigMACWithHeaderFile(dev);
1350 #else
1351         // Not make sure EEPROM, add later
1352         RT_TRACE(COMP_INIT, "Read MACREG.txt\n");
1353         //rtStatus = phy_ConfigMACWithParaFile(dev, RTL819X_PHY_MACREG);// lzm del it temp
1354 #endif
1355         return (rtStatus == RT_STATUS_SUCCESS) ? true:false;
1356
1357 }
1358
1359 //adapter_start
1360 extern  bool
1361 PHY_BBConfig8192S(struct net_device* dev)
1362 {
1363         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1364
1365         u8 PathMap = 0, index = 0, rf_num = 0;
1366         struct r8192_priv       *priv = ieee80211_priv(dev);
1367         phy_InitBBRFRegisterDefinition(dev);
1368
1369         //
1370         // Config BB and AGC
1371         //
1372         //switch( Adapter->MgntInfo.bRegHwParaFile )
1373         //{
1374         //      case 0:
1375         //              phy_BB8190_Config_HardCode(dev);
1376         //              break;
1377
1378         //      case 1:
1379                         rtStatus = phy_BB8192S_Config_ParaFile(dev);
1380         //              break;
1381
1382         //      case 2:
1383                         // Partial Modify.
1384         //              phy_BB8190_Config_HardCode(dev);
1385         //              phy_BB8192S_Config_ParaFile(dev);
1386         //              break;
1387
1388         //      default:
1389         //              phy_BB8190_Config_HardCode(dev);
1390         //              break;
1391         //}
1392         PathMap = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_TxInfo, 0xf) |
1393                                 rtl8192_QueryBBReg(dev, rOFDM0_TRxPathEnable, 0xf));
1394         priv->rf_pathmap = PathMap;
1395         for(index = 0; index<4; index++)
1396         {
1397                 if((PathMap>>index)&0x1)
1398                         rf_num++;
1399         }
1400
1401         if((priv->rf_type==RF_1T1R && rf_num!=1) ||
1402                 (priv->rf_type==RF_1T2R && rf_num!=2) ||
1403                 (priv->rf_type==RF_2T2R && rf_num!=2) ||
1404                 (priv->rf_type==RF_2T2R_GREEN && rf_num!=2) ||
1405                 (priv->rf_type==RF_2T4R && rf_num!=4))
1406         {
1407                 RT_TRACE( COMP_INIT, "PHY_BBConfig8192S: RF_Type(%x) does not match RF_Num(%x)!!\n", priv->rf_type, rf_num);
1408         }
1409         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1410 }
1411
1412 //adapter_start
1413 extern  bool
1414 PHY_RFConfig8192S(struct net_device* dev)
1415 {
1416         struct r8192_priv       *priv = ieee80211_priv(dev);
1417         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1418
1419         //Set priv->rf_chip = RF_8225 to do real PHY FPGA initilization
1420
1421         //<Roger_EXP> We assign RF type here temporally. 2008.09.12.
1422         priv->rf_chip = RF_6052;
1423
1424         //
1425         // RF config
1426         //
1427         switch(priv->rf_chip)
1428         {
1429         case RF_8225:
1430         case RF_6052:
1431                 rtStatus = PHY_RF6052_Config(dev);
1432                 break;
1433
1434         case RF_8256:
1435                 //rtStatus = PHY_RF8256_Config(dev);
1436                 break;
1437
1438         case RF_8258:
1439                 break;
1440
1441         case RF_PSEUDO_11N:
1442                 //rtStatus = PHY_RF8225_Config(dev);
1443                 break;
1444         default:
1445             break;
1446         }
1447
1448         return (rtStatus == RT_STATUS_SUCCESS) ? 1:0;
1449 }
1450
1451
1452 // Joseph test: new initialize order!!
1453 // Test only!! This part need to be re-organized.
1454 // Now it is just for 8256.
1455 //use in phy only
1456 #ifdef TO_DO_LIST
1457 static RT_STATUS
1458 phy_BB8190_Config_HardCode(struct net_device* dev)
1459 {
1460         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1461         return RT_STATUS_SUCCESS;
1462 }
1463 #endif
1464
1465 /*-----------------------------------------------------------------------------
1466  * Function:    phy_SetBBtoDiffRFWithHeaderFile()
1467  *
1468  * Overview:    This function
1469  *
1470  *
1471  * Input:       PADAPTER                Adapter
1472  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
1473  *
1474  * Output:      NONE
1475  *
1476  * Return:      RT_STATUS_SUCCESS: configuration file exist
1477  * When                 Who             Remark
1478  * 2008/11/10   tynli
1479  * use in phy only
1480  *---------------------------------------------------------------------------*/
1481 static RT_STATUS
1482 phy_SetBBtoDiffRFWithHeaderFile(struct net_device* dev, u8 ConfigType)
1483 {
1484         int i;
1485         struct r8192_priv       *priv = ieee80211_priv(dev);
1486         u32*                    Rtl819XPHY_REGArraytoXTXR_Table;
1487         u16                             PHY_REGArraytoXTXRLen;
1488
1489 //#if (HAL_CODE_BASE != RTL8192_S)
1490
1491         if(priv->rf_type == RF_1T1R)
1492         {
1493                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T1R_Array;
1494                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T1RArrayLength;
1495         }
1496         else if(priv->rf_type == RF_1T2R)
1497         {
1498                 Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to1T2R_Array;
1499                 PHY_REGArraytoXTXRLen = PHY_ChangeTo_1T2RArrayLength;
1500         }
1501         //else if(priv->rf_type == RF_2T2R || priv->rf_type == RF_2T2R_GREEN)
1502         //{
1503         //      Rtl819XPHY_REGArraytoXTXR_Table = Rtl819XPHY_REG_to2T2R_Array;
1504         //      PHY_REGArraytoXTXRLen = PHY_ChangeTo_2T2RArrayLength;
1505         //}
1506         else
1507         {
1508                 return RT_STATUS_FAILURE;
1509         }
1510
1511         if(ConfigType == BaseBand_Config_PHY_REG)
1512         {
1513                 for(i=0;i<PHY_REGArraytoXTXRLen;i=i+3)
1514                 {
1515                         if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfe)
1516                                 mdelay(50);
1517                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfd)
1518                                 mdelay(5);
1519                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfc)
1520                                 mdelay(1);
1521                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfb)
1522                                 udelay(50);
1523                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xfa)
1524                                 udelay(5);
1525                         else if (Rtl819XPHY_REGArraytoXTXR_Table[i] == 0xf9)
1526                                 udelay(1);
1527                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArraytoXTXR_Table[i], Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1528                         //RT_TRACE(COMP_SEND,
1529                         //"The Rtl819XPHY_REGArraytoXTXR_Table[0] is %lx Rtl819XPHY_REGArraytoXTXR_Table[1] is %lx Rtl819XPHY_REGArraytoXTXR_Table[2] is %lx \n",
1530                         //Rtl819XPHY_REGArraytoXTXR_Table[i],Rtl819XPHY_REGArraytoXTXR_Table[i+1], Rtl819XPHY_REGArraytoXTXR_Table[i+2]);
1531                 }
1532         }
1533         else {
1534                 RT_TRACE(COMP_SEND, "phy_SetBBtoDiffRFWithHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1535         }
1536 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1537         return RT_STATUS_SUCCESS;
1538 }
1539
1540
1541 //use in phy only
1542 static  RT_STATUS
1543 phy_BB8192S_Config_ParaFile(struct net_device* dev)
1544 {
1545         struct r8192_priv       *priv = ieee80211_priv(dev);
1546         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
1547         //u8                            u2RegValue;
1548         //u16                           u4RegValue;
1549         //char                          szBBRegFile[] = RTL819X_PHY_REG;
1550         //char                          szBBRegFile1T2R[] = RTL819X_PHY_REG_1T2R;
1551         //char                          szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1552         //char                          szAGCTableFile[] = RTL819X_AGC_TAB;
1553         //char                          szBBRegto1T1RFile[] = RTL819X_PHY_REG_to1T1R;
1554         //char                          szBBRegto1T2RFile[] = RTL819X_PHY_REG_to1T2R;
1555
1556         RT_TRACE(COMP_INIT, "==>phy_BB8192S_Config_ParaFile\n");
1557
1558         //
1559         // 1. Read PHY_REG.TXT BB INIT!!
1560         // We will seperate as 1T1R/1T2R/1T2R_GREEN/2T2R
1561         //
1562 #if RTL8190_Download_Firmware_From_Header
1563         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1564             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1565         {
1566                 rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1567                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1568                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1569                   //so we should reconfig BB reg with the right PHY parameters.
1570                         rtStatus = phy_SetBBtoDiffRFWithHeaderFile(dev,BaseBand_Config_PHY_REG);
1571                 }
1572         }else
1573                 rtStatus = RT_STATUS_FAILURE;
1574 #else
1575         RT_TRACE(COMP_INIT, "RF_Type == %d\n", priv->rf_type);
1576         // No matter what kind of RF we always read PHY_REG.txt. We must copy different
1577         // type of parameter files to phy_reg.txt at first.
1578         if (priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R ||
1579             priv->rf_type == RF_1T1R ||priv->rf_type == RF_2T2R_GREEN)
1580         {
1581                 rtStatus = phy_ConfigBBWithParaFile(dev, (char* )&szBBRegFile);
1582                 if(priv->rf_type != RF_2T2R && priv->rf_type != RF_2T2R_GREEN)
1583                 {//2008.11.10 Added by tynli. The default PHY_REG.txt we read is for 2T2R,
1584                   //so we should reconfig BB reg with the right PHY parameters.
1585                         if(priv->rf_type == RF_1T1R)
1586                                 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T1RFile);
1587                         else if(priv->rf_type == RF_1T2R)
1588                                 rtStatus = phy_SetBBtoDiffRFWithParaFile(dev, (char* )&szBBRegto1T2RFile);
1589                 }
1590
1591         }else
1592                 rtStatus = RT_STATUS_FAILURE;
1593 #endif
1594
1595         if(rtStatus != RT_STATUS_SUCCESS){
1596                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!");
1597                 goto phy_BB8190_Config_ParaFile_Fail;
1598         }
1599
1600         //
1601         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1602         //
1603         if (priv->AutoloadFailFlag == false)
1604         {
1605 #if     RTL8190_Download_Firmware_From_Header
1606                 rtStatus = phy_ConfigBBWithPgHeaderFile(dev,BaseBand_Config_PHY_REG);
1607 #else
1608                 rtStatus = phy_ConfigBBWithPgParaFile(dev, (char* )&szBBRegPgFile);
1609 #endif
1610         }
1611         if(rtStatus != RT_STATUS_SUCCESS){
1612                 RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!");
1613                 goto phy_BB8190_Config_ParaFile_Fail;
1614         }
1615
1616         //
1617         // 3. BB AGC table Initialization
1618         //
1619 #if RTL8190_Download_Firmware_From_Header
1620         rtStatus = phy_ConfigBBWithHeaderFile(dev,BaseBand_Config_AGC_TAB);
1621 #else
1622         RT_TRACE(COMP_INIT, "phy_BB8192S_Config_ParaFile AGC_TAB.txt\n");
1623         rtStatus = phy_ConfigBBWithParaFile(Adapter, (char* )&szAGCTableFile);
1624 #endif
1625
1626         if(rtStatus != RT_STATUS_SUCCESS){
1627                 printk( "phy_BB8192S_Config_ParaFile():AGC Table Fail\n");
1628                 goto phy_BB8190_Config_ParaFile_Fail;
1629         }
1630
1631
1632 #if 0   // 2008/08/18 MH Disable for 92SE
1633         if(pHalData->VersionID > VERSION_8190_BD)
1634         {
1635                 //if(pHalData->RF_Type == RF_2T4R)
1636                 //{
1637                 // Antenna gain offset from B/C/D to A
1638                 u4RegValue = (  pHalData->AntennaTxPwDiff[2]<<8 |
1639                                                 pHalData->AntennaTxPwDiff[1]<<4 |
1640                                                 pHalData->AntennaTxPwDiff[0]);
1641                 //}
1642                 //else
1643                 //u4RegValue = 0;
1644
1645                 PHY_SetBBReg(dev, rFPGA0_TxGainStage,
1646                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1647
1648                 // CrystalCap
1649                 // Simulate 8192???
1650                 u4RegValue = pHalData->CrystalCap;
1651                 PHY_SetBBReg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, u4RegValue);
1652                 // Simulate 8190??
1653                 //u4RegValue = ((pHalData->CrystalCap & 0xc)>>2);       // bit2~3 of crystal cap
1654                 //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, bXtalCap23, u4RegValue);
1655
1656         }
1657 #endif
1658
1659         // Check if the CCK HighPower is turned ON.
1660         // This is used to calculate PWDB.
1661         priv->bCckHighPower = (bool)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1662
1663
1664 phy_BB8190_Config_ParaFile_Fail:
1665         return rtStatus;
1666 }
1667
1668 /*-----------------------------------------------------------------------------
1669  * Function:    phy_ConfigMACWithHeaderFile()
1670  *
1671  * Overview:    This function read BB parameters from Header file we gen, and do register
1672  *                        Read/Write
1673  *
1674  * Input:       PADAPTER                Adapter
1675  *                      char*                   pFileName
1676  *
1677  * Output:      NONE
1678  *
1679  * Return:      RT_STATUS_SUCCESS: configuration file exist
1680  *
1681  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
1682  *                      [Register][Mask][Value]
1683  *---------------------------------------------------------------------------*/
1684 //use in phy only
1685 static  RT_STATUS
1686 phy_ConfigMACWithHeaderFile(struct net_device* dev)
1687 {
1688         u32                                     i = 0;
1689         u32                                     ArrayLength = 0;
1690         u32*                                    ptrArray;
1691         //struct r8192_priv     *priv = ieee80211_priv(dev);
1692
1693 //#if (HAL_CODE_BASE != RTL8192_S)
1694         /*if(Adapter->bInHctTest)
1695         {
1696                 RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_ArrayDTM\n"));
1697                 ArrayLength = MACPHY_ArrayLengthDTM;
1698                 ptrArray = Rtl819XMACPHY_ArrayDTM;
1699         }
1700         else if(pHalData->bTXPowerDataReadFromEEPORM)
1701         {
1702 //              RT_TRACE(COMP_INIT, DBG_LOUD, ("Rtl819XMACPHY_Array_PG\n"));
1703 //              ArrayLength = MACPHY_Array_PGLength;
1704 //              ptrArray = Rtl819XMACPHY_Array_PG;
1705
1706         }else*/
1707         { //2008.11.06 Modified by tynli.
1708                 RT_TRACE(COMP_INIT, "Read Rtl819XMACPHY_Array\n");
1709                 ArrayLength = MAC_2T_ArrayLength;
1710                 ptrArray = Rtl819XMAC_Array;
1711         }
1712
1713         /*for(i = 0 ;i < ArrayLength;i=i+3){
1714                 RT_TRACE(COMP_SEND, DBG_LOUD, ("The Rtl819XMACPHY_Array[0] is %lx Rtl819XMACPHY_Array[1] is %lx Rtl819XMACPHY_Array[2] is %lx\n",ptrArray[i], ptrArray[i+1], ptrArray[i+2]));
1715                 if(ptrArray[i] == 0x318)
1716                 {
1717                         ptrArray[i+2] = 0x00000800;
1718                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1719                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1720                 }
1721                 PHY_SetBBReg(Adapter, ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1722         }*/
1723         for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
1724                 write_nic_byte(dev, ptrArray[i], (u8)ptrArray[i+1]);
1725         }
1726 //#endif
1727         return RT_STATUS_SUCCESS;
1728 }
1729
1730 /*-----------------------------------------------------------------------------
1731  * Function:    phy_ConfigBBWithHeaderFile()
1732  *
1733  * Overview:    This function read BB parameters from general file format, and do register
1734  *                        Read/Write
1735  *
1736  * Input:       PADAPTER                Adapter
1737  *                      u8                      ConfigType     0 => PHY_CONFIG
1738  *                                                                               1 =>AGC_TAB
1739  *
1740  * Output:      NONE
1741  *
1742  * Return:      RT_STATUS_SUCCESS: configuration file exist
1743  *
1744  *---------------------------------------------------------------------------*/
1745 //use in phy only
1746 static  RT_STATUS
1747 phy_ConfigBBWithHeaderFile(struct net_device* dev,u8 ConfigType)
1748 {
1749         int             i;
1750         //u8            ArrayLength;
1751         u32*    Rtl819XPHY_REGArray_Table;
1752         u32*    Rtl819XAGCTAB_Array_Table;
1753         u16             PHY_REGArrayLen, AGCTAB_ArrayLen;
1754         //struct r8192_priv *priv = ieee80211_priv(dev);
1755 //#if (HAL_CODE_BASE != RTL8192_S)
1756         /*if(Adapter->bInHctTest)
1757         {
1758
1759                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1760                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1761
1762                 if(pHalData->RF_Type == RF_2T4R)
1763                 {
1764                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1765                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1766                 }
1767                 else if (pHalData->RF_Type == RF_1T2R)
1768                 {
1769                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1770                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1771                 }
1772
1773         }
1774         else
1775         */
1776         //{
1777         //
1778         // 2008.11.06 Modified by tynli.
1779         //
1780         AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1781         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1782         PHY_REGArrayLen = PHY_REG_2T2RArrayLength; // Default RF_type: 2T2R
1783         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_Array;
1784         //}
1785
1786         if(ConfigType == BaseBand_Config_PHY_REG)
1787         {
1788                 for(i=0;i<PHY_REGArrayLen;i=i+2)
1789                 {
1790                         if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1791                                 mdelay(50);
1792                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1793                                 mdelay(5);
1794                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1795                                 mdelay(1);
1796                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1797                                 udelay(50);
1798                         else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1799                                 udelay(5);
1800                         else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1801                                 udelay(1);
1802                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1803                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1804
1805                 }
1806         }
1807         else if(ConfigType == BaseBand_Config_AGC_TAB){
1808                 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1809                 {
1810                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1811                 }
1812         }
1813 //#endif        // #if (HAL_CODE_BASE != RTL8192_S)
1814         return RT_STATUS_SUCCESS;
1815 }
1816
1817 /*-----------------------------------------------------------------------------
1818  * Function:    phy_ConfigBBWithPgHeaderFile
1819  *
1820  * Overview:    Config PHY_REG_PG array
1821  *
1822  * Input:       NONE
1823  *
1824  * Output:      NONE
1825  *
1826  * Return:      NONE
1827  *
1828  * Revised History:
1829  * When                 Who             Remark
1830  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1831  * 11/10/2008   tynli           Modify to mew files.
1832  //use in phy only
1833  *---------------------------------------------------------------------------*/
1834 static RT_STATUS
1835 phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType)
1836 {
1837         int i;
1838         //u8 ArrayLength;
1839         u32*    Rtl819XPHY_REGArray_Table_PG;
1840         u16     PHY_REGArrayPGLen;
1841         //struct r8192_priv *priv = ieee80211_priv(dev);
1842 //#if (HAL_CODE_BASE != RTL8192_S)
1843         // Default: pHalData->RF_Type = RF_2T2R.
1844
1845         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1846         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1847
1848         if(ConfigType == BaseBand_Config_PHY_REG)
1849         {
1850                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1851                 {
1852                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe)
1853                                 mdelay(50);
1854                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1855                                 mdelay(5);
1856                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1857                                 mdelay(1);
1858                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1859                                 udelay(50);
1860                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1861                                 udelay(5);
1862                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1863                                 udelay(1);
1864                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1865                         //RT_TRACE(COMP_SEND, "The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",
1866                         //              Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]);
1867                 }
1868         }else{
1869                 RT_TRACE(COMP_SEND, "phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n");
1870         }
1871         return RT_STATUS_SUCCESS;
1872
1873 }       /* phy_ConfigBBWithPgHeaderFile */
1874
1875 /*-----------------------------------------------------------------------------
1876  * Function:    PHY_ConfigRFWithHeaderFile()
1877  *
1878  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1879  *
1880  * Input:       PADAPTER                        Adapter
1881  *                      char*                           pFileName
1882  *                      RF90_RADIO_PATH_E       eRFPath
1883  *
1884  * Output:      NONE
1885  *
1886  * Return:      RT_STATUS_SUCCESS: configuration file exist
1887  *
1888  * Note:                Delay may be required for RF configuration
1889  *---------------------------------------------------------------------------*/
1890 //in 8256 phy_RF8256_Config_ParaFile only
1891 //RT_STATUS PHY_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath)
1892 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1893 {
1894
1895         struct r8192_priv *priv = ieee80211_priv(dev);
1896         int                     i;
1897         //u32*  pRFArray;
1898         RT_STATUS       rtStatus = RT_STATUS_SUCCESS;
1899         u32                     *Rtl819XRadioA_Array_Table;
1900         u32                     *Rtl819XRadioB_Array_Table;
1901         //u32*  Rtl819XRadioC_Array_Table;
1902         //u32*  Rtl819XRadioD_Array_Table;
1903         u16                     RadioA_ArrayLen,RadioB_ArrayLen;
1904
1905         {       //2008.11.06 Modified by tynli
1906                 RadioA_ArrayLen = RadioA_1T_ArrayLength;
1907                 Rtl819XRadioA_Array_Table=Rtl819XRadioA_Array;
1908                 Rtl819XRadioB_Array_Table=Rtl819XRadioB_Array;
1909                 RadioB_ArrayLen = RadioB_ArrayLength;
1910         }
1911
1912         if( priv->rf_type == RF_2T2R_GREEN )
1913         {
1914                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_GM_Array;
1915                 RadioB_ArrayLen = RadioB_GM_ArrayLength;
1916         }
1917         else
1918         {
1919                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_Array;
1920                 RadioB_ArrayLen = RadioB_ArrayLength;
1921         }
1922
1923         rtStatus = RT_STATUS_SUCCESS;
1924
1925         // When initialization, we want the delay function(mdelay(), delay_us()
1926         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
1927         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
1928         // to run at Dispatch level to achive it.
1929         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
1930
1931         switch(eRFPath){
1932                 case RF90_PATH_A:
1933                         for(i = 0;i<RadioA_ArrayLen; i=i+2){
1934                                 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
1935                                         { // Deay specific ms. Only RF configuration require delay.
1936 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1937 #ifdef RTL8192SU
1938                                                 mdelay(1000);
1939 #else
1940                                                 mdelay(50);
1941 #endif
1942                                 }
1943                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
1944                                                 mdelay(5);
1945                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
1946                                                 mdelay(1);
1947                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
1948                                                 udelay(50);
1949                                                 //PlatformStallExecution(50);
1950                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
1951                                                 udelay(5);
1952                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
1953                                                 udelay(1);
1954                                         else
1955                                         {
1956                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
1957                                         }
1958                         }
1959                         break;
1960                 case RF90_PATH_B:
1961                         for(i = 0;i<RadioB_ArrayLen; i=i+2){
1962                                 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
1963                                         { // Deay specific ms. Only RF configuration require delay.
1964 //#if (DEV_BUS_TYPE == USB_INTERFACE)
1965 #ifdef RTL8192SU
1966                                                 mdelay(1000);
1967 #else
1968                                                 mdelay(50);
1969 #endif
1970                                 }
1971                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
1972                                                 mdelay(5);
1973                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
1974                                                 mdelay(1);
1975                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
1976                                                 udelay(50);
1977                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
1978                                                 udelay(5);
1979                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
1980                                                 udelay(1);
1981                                         else
1982                                         {
1983                                         rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
1984                                         }
1985                         }
1986                         break;
1987                 case RF90_PATH_C:
1988                         break;
1989                 case RF90_PATH_D:
1990                         break;
1991                 default:
1992                         break;
1993         }
1994
1995         return rtStatus;
1996
1997 }
1998
1999 /*-----------------------------------------------------------------------------
2000  * Function:    PHY_CheckBBAndRFOK()
2001  *
2002  * Overview:    This function is write register and then readback to make sure whether
2003  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
2004  *
2005  * Input:       PADAPTER                        Adapter
2006  *                      HW90_BLOCK_E            CheckBlock
2007  *                      RF90_RADIO_PATH_E       eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
2008  *
2009  * Output:      NONE
2010  *
2011  * Return:      RT_STATUS_SUCCESS: PHY is OK
2012  *
2013  * Note:                This function may be removed in the ASIC
2014  *---------------------------------------------------------------------------*/
2015 //in 8256 phy_RF8256_Config_HardCode
2016 //but we don't use it temp
2017 RT_STATUS
2018 PHY_CheckBBAndRFOK(
2019         struct net_device* dev,
2020         HW90_BLOCK_E            CheckBlock,
2021         RF90_RADIO_PATH_E       eRFPath
2022         )
2023 {
2024         //struct r8192_priv *priv = ieee80211_priv(dev);
2025         RT_STATUS                       rtStatus = RT_STATUS_SUCCESS;
2026         u32                             i, CheckTimes = 4,ulRegRead = 0;
2027         u32                             WriteAddr[4];
2028         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2029
2030         // Initialize register address offset to be checked
2031         WriteAddr[HW90_BLOCK_MAC] = 0x100;
2032         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2033         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2034         WriteAddr[HW90_BLOCK_RF] = 0x3;
2035
2036         for(i=0 ; i < CheckTimes ; i++)
2037         {
2038
2039                 //
2040                 // Write Data to register and readback
2041                 //
2042                 switch(CheckBlock)
2043                 {
2044                 case HW90_BLOCK_MAC:
2045                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
2046                         RT_TRACE(COMP_INIT, "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
2047                         break;
2048
2049                 case HW90_BLOCK_PHY0:
2050                 case HW90_BLOCK_PHY1:
2051                         write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2052                         ulRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2053                         break;
2054
2055                 case HW90_BLOCK_RF:
2056                         // When initialization, we want the delay function(mdelay(), delay_us()
2057                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
2058                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
2059                         // to run at Dispatch level to achive it.
2060                         //cosa PlatformAcquireSpinLock(dev, RT_INITIAL_SPINLOCK);
2061                         WriteData[i] &= 0xfff;
2062                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
2063                         // TODO: we should not delay for such a long time. Ask SD3
2064                         mdelay(10);
2065                         ulRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2066                         mdelay(10);
2067                         //cosa PlatformReleaseSpinLock(dev, RT_INITIAL_SPINLOCK);
2068                         break;
2069
2070                 default:
2071                         rtStatus = RT_STATUS_FAILURE;
2072                         break;
2073                 }
2074
2075
2076                 //
2077                 // Check whether readback data is correct
2078                 //
2079                 if(ulRegRead != WriteData[i])
2080                 {
2081                         //RT_TRACE(COMP_FPGA,  ("ulRegRead: %x, WriteData: %x \n", ulRegRead, WriteData[i]));
2082                         RT_TRACE(COMP_ERR, "read back error(read:%x, write:%x)\n", ulRegRead, WriteData[i]);
2083                         rtStatus = RT_STATUS_FAILURE;
2084                         break;
2085                 }
2086         }
2087
2088         return rtStatus;
2089 }
2090
2091 //no use temp in windows driver
2092 #ifdef TO_DO_LIST
2093 void
2094 PHY_SetRFPowerState8192SUsb(
2095         struct net_device* dev,
2096         RF_POWER_STATE  RFPowerState
2097         )
2098 {
2099         struct r8192_priv *priv = ieee80211_priv(dev);
2100         bool                    WaitShutDown = FALSE;
2101         u32                     DWordContent;
2102         //RF90_RADIO_PATH_E     eRFPath;
2103         u8                              eRFPath;
2104         BB_REGISTER_DEFINITION_T        *pPhyReg;
2105
2106         if(priv->SetRFPowerStateInProgress == TRUE)
2107                 return;
2108
2109         priv->SetRFPowerStateInProgress = TRUE;
2110
2111         // TODO: Emily, 2006.11.21, we should rewrite this function
2112
2113         if(RFPowerState==RF_SHUT_DOWN)
2114         {
2115                 RFPowerState=RF_OFF;
2116                 WaitShutDown=TRUE;
2117         }
2118
2119
2120         priv->RFPowerState = RFPowerState;
2121         switch( priv->rf_chip )
2122         {
2123         case RF_8225:
2124         case RF_6052:
2125                 switch( RFPowerState )
2126                 {
2127                 case RF_ON:
2128                         break;
2129
2130                 case RF_SLEEP:
2131                         break;
2132
2133                 case RF_OFF:
2134                         break;
2135                 }
2136                 break;
2137
2138         case RF_8256:
2139                 switch( RFPowerState )
2140                 {
2141                 case RF_ON:
2142                         break;
2143
2144                 case RF_SLEEP:
2145                         break;
2146
2147                 case RF_OFF:
2148                         for(eRFPath=(RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < RF90_PATH_MAX; eRFPath++)
2149                         {
2150                                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2151                                         continue;
2152
2153                                 pPhyReg = &priv->PHYRegDef[eRFPath];
2154                                 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, bRFSI_RFENV);
2155                                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0);
2156                         }
2157                         break;
2158                 }
2159                 break;
2160
2161         case RF_8258:
2162                 break;
2163         }// switch( priv->rf_chip )
2164
2165         priv->SetRFPowerStateInProgress = FALSE;
2166 }
2167 #endif
2168
2169 #ifdef RTL8192U
2170 //no use temp in windows driver
2171 void
2172 PHY_UpdateInitialGain(
2173         struct net_device* dev
2174         )
2175 {
2176         struct r8192_priv       *priv = ieee80211_priv(dev);
2177         //unsigned char                 *IGTable;
2178         //u8                    DIG_CurrentInitialGain = 4;
2179
2180         switch(priv->rf_chip)
2181         {
2182         case RF_8225:
2183                 break;
2184         case RF_8256:
2185                 break;
2186         case RF_8258:
2187                 break;
2188         case RF_PSEUDO_11N:
2189                 break;
2190         case RF_6052:
2191                 break;
2192         default:
2193                 RT_TRACE(COMP_DBG, "PHY_UpdateInitialGain(): unknown rf_chip: %#X\n", priv->rf_chip);
2194                 break;
2195         }
2196 }
2197 #endif
2198
2199 //YJ,modified,090107
2200 void PHY_GetHWRegOriginalValue(struct net_device* dev)
2201 {
2202         struct r8192_priv *priv = ieee80211_priv(dev);
2203
2204         // read tx power offset
2205         // Simulate 8192
2206         priv->MCSTxPowerLevelOriginalOffset[0] =
2207                 rtl8192_QueryBBReg(dev, rTxAGC_Rate18_06, bMaskDWord);
2208         priv->MCSTxPowerLevelOriginalOffset[1] =
2209                 rtl8192_QueryBBReg(dev, rTxAGC_Rate54_24, bMaskDWord);
2210         priv->MCSTxPowerLevelOriginalOffset[2] =
2211                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs03_Mcs00, bMaskDWord);
2212         priv->MCSTxPowerLevelOriginalOffset[3] =
2213                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs07_Mcs04, bMaskDWord);
2214         priv->MCSTxPowerLevelOriginalOffset[4] =
2215                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs11_Mcs08, bMaskDWord);
2216         priv->MCSTxPowerLevelOriginalOffset[5] =
2217                 rtl8192_QueryBBReg(dev, rTxAGC_Mcs15_Mcs12, bMaskDWord);
2218
2219         // Read CCK offset
2220         priv->MCSTxPowerLevelOriginalOffset[6] =
2221                 rtl8192_QueryBBReg(dev, rTxAGC_CCK_Mcs32, bMaskDWord);
2222         RT_TRACE(COMP_INIT, "Legacy OFDM =%08x/%08x HT_OFDM=%08x/%08x/%08x/%08x\n",
2223         priv->MCSTxPowerLevelOriginalOffset[0], priv->MCSTxPowerLevelOriginalOffset[1] ,
2224         priv->MCSTxPowerLevelOriginalOffset[2], priv->MCSTxPowerLevelOriginalOffset[3] ,
2225         priv->MCSTxPowerLevelOriginalOffset[4], priv->MCSTxPowerLevelOriginalOffset[5] );
2226
2227         // read rx initial gain
2228         priv->DefaultInitialGain[0] = rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bMaskByte0);
2229         priv->DefaultInitialGain[1] = rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bMaskByte0);
2230         priv->DefaultInitialGain[2] = rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bMaskByte0);
2231         priv->DefaultInitialGain[3] = rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bMaskByte0);
2232         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2233                         priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2234                         priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2235
2236         // read framesync
2237         priv->framesync = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector3, bMaskByte0);
2238         priv->framesyncC34 = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector2, bMaskDWord);
2239         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2240                                 rOFDM0_RxDetector3, priv->framesync);
2241 }
2242 //YJ,modified,090107,end
2243
2244
2245
2246 /**
2247 * Function:     phy_InitBBRFRegisterDefinition
2248 *
2249 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
2250 *
2251 * Input:
2252 *                       PADAPTER                Adapter,
2253 *
2254 * Output:       None
2255 * Return:               None
2256 * Note:         The initialization value is constant and it should never be changes
2257 */
2258 //use in phy only
2259 static void phy_InitBBRFRegisterDefinition(     struct net_device* dev)
2260 {
2261         struct r8192_priv *priv = ieee80211_priv(dev);
2262
2263         // RF Interface Sowrtware Control
2264         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2265         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2266         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2267         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2268
2269         // RF Interface Readback Value
2270         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2271         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2272         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2273         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2274
2275         // RF Interface Output (and Enable)
2276         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2277         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2278         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2279         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2280
2281         // RF Interface (Output and)  Enable
2282         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2283         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2284         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2285         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2286
2287         //Addr of LSSI. Wirte RF register by driver
2288         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2289         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2290         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2291         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2292
2293         // RF parameter
2294         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
2295         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2296         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2297         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2298
2299         // Tx AGC Gain Stage (same for all path. Should we remove this?)
2300         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2301         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2302         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2303         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2304
2305         // Tranceiver A~D HSSI Parameter-1
2306         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
2307         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
2308         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
2309         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
2310
2311         // Tranceiver A~D HSSI Parameter-2
2312         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
2313         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
2314         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
2315         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
2316
2317         // RF switch Control
2318         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2319         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2320         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2321         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2322
2323         // AGC control 1
2324         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2325         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2326         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2327         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2328
2329         // AGC control 2
2330         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2331         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2332         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2333         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2334
2335         // RX AFE control 1
2336         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2337         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2338         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2339         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2340
2341         // RX AFE control 1
2342         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2343         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2344         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2345         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2346
2347         // Tx AFE control 1
2348         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2349         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2350         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2351         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2352
2353         // Tx AFE control 2
2354         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2355         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2356         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2357         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2358
2359         // Tranceiver LSSI Readback  SI mode
2360         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2361         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2362         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2363         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2364
2365         // Tranceiver LSSI Readback PI mode
2366         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
2367         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
2368         //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
2369         //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
2370
2371 }
2372
2373
2374 //
2375 //      Description:  Change RF power state.
2376 //
2377 //      Assumption: This function must be executed in re-schdulable context,
2378 //              ie. PASSIVE_LEVEL.
2379 //
2380 //      050823, by rcnjko.
2381 //not understand it seem's use in init
2382 //SetHwReg8192SUsb--->HalFunc.SetHwRegHandler
2383 bool PHY_SetRFPowerState(struct net_device* dev, RT_RF_POWER_STATE eRFPowerState)
2384 {
2385         struct r8192_priv *priv = ieee80211_priv(dev);
2386         bool                    bResult = FALSE;
2387
2388         RT_TRACE(COMP_RF, "---------> PHY_SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2389
2390         if(eRFPowerState == priv->ieee80211->eRFPowerState)
2391         {
2392                 RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2393                 return bResult;
2394         }
2395
2396         bResult = phy_SetRFPowerState8192SU(dev, eRFPowerState);
2397
2398         RT_TRACE(COMP_RF, "<--------- PHY_SetRFPowerState(): bResult(%d)\n", bResult);
2399
2400         return bResult;
2401 }
2402
2403 //use in phy only
2404 static bool phy_SetRFPowerState8192SU(struct net_device* dev,RT_RF_POWER_STATE eRFPowerState)
2405 {
2406         struct r8192_priv *priv = ieee80211_priv(dev);
2407         bool                    bResult = TRUE;
2408         //u8            eRFPath;
2409         //u8            i, QueueID;
2410         u8              u1bTmp;
2411
2412         if(priv->SetRFPowerStateInProgress == TRUE)
2413                 return FALSE;
2414
2415         priv->SetRFPowerStateInProgress = TRUE;
2416
2417         switch(priv->rf_chip )
2418         {
2419                 default:
2420                 switch( eRFPowerState )
2421                 {
2422                         case eRfOn:
2423                                 write_nic_dword(dev, WFM5, FW_BB_RESET_ENABLE);
2424                                 write_nic_word(dev, CMDR, 0x37FC);
2425                                 write_nic_byte(dev, PHY_CCA, 0x3);
2426                                 write_nic_byte(dev, TXPAUSE, 0x00);
2427                                 write_nic_byte(dev, SPS1_CTRL, 0x64);
2428                                 break;
2429
2430                         //
2431                         // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
2432                         // By Bruce, 2008-01-16.
2433                         //
2434                         case eRfSleep:
2435                         case eRfOff:
2436                                 if (priv->ieee80211->eRFPowerState == eRfSleep || priv->ieee80211->eRFPowerState == eRfOff)
2437                                                 break;
2438 #ifdef NOT_YET
2439                                 // Make sure BusyQueue is empty befor turn off RFE pwoer.
2440                                 for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
2441                                 {
2442                                         if(RTIsListEmpty(&Adapter->TcbBusyQueue[QueueID]))
2443                                         {
2444                                                 QueueID++;
2445                                                 continue;
2446                                         }
2447                                         else
2448                                         {
2449                                                 RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
2450                                                 udelay(10);
2451                                                 i++;
2452                                         }
2453
2454                                         if(i >= MAX_DOZE_WAITING_TIMES_9x)
2455                                         {
2456                                                 RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
2457                                                 break;
2458                                         }
2459                                 }
2460 #endif
2461                                 //
2462                                 //RF Off/Sleep sequence. Designed/tested from SD4 Scott, SD1 Grent and Jonbon.
2463                                 // Added by Bruce, 2008-11-22.
2464                                 //
2465                                 //==================================================================
2466                                 // (0) Disable FW BB reset checking
2467                                 write_nic_dword(dev, WFM5, FW_BB_RESET_DISABLE);
2468
2469                                 // (1) Switching Power Supply Register : Disable LD12 & SW12 (for IT)
2470                                 u1bTmp = read_nic_byte(dev, LDOV12D_CTRL);
2471                                 u1bTmp |= BIT0;
2472                                 write_nic_byte(dev, LDOV12D_CTRL, u1bTmp);
2473
2474                                 write_nic_byte(dev, SPS1_CTRL, 0x0);
2475                                 write_nic_byte(dev, TXPAUSE, 0xFF);
2476
2477                                 // (2) MAC Tx/Rx enable, BB enable, CCK/OFDM enable
2478                                 write_nic_word(dev, CMDR, 0x77FC);
2479                                 write_nic_byte(dev, PHY_CCA, 0x0);
2480                                 udelay(100);
2481
2482                                 write_nic_word(dev, CMDR, 0x37FC);
2483                                 udelay(10);
2484
2485                                 write_nic_word(dev, CMDR, 0x77FC);
2486                                 udelay(10);
2487
2488                                 // (3) Reset BB TRX blocks
2489                                 write_nic_word(dev, CMDR, 0x57FC);
2490                                 break;
2491
2492                         default:
2493                                 bResult = FALSE;
2494                                 //RT_ASSERT(FALSE, ("phy_SetRFPowerState8192SU(): unknow state to set: 0x%X!!!\n", eRFPowerState));
2495                                 break;
2496                 }
2497                 break;
2498
2499         }
2500         priv->ieee80211->eRFPowerState = eRFPowerState;
2501 #ifdef TO_DO_LIST
2502         if(bResult)
2503         {
2504                 // Update current RF state variable.
2505                 priv->ieee80211->eRFPowerState = eRFPowerState;
2506
2507                 switch(priv->rf_chip )
2508                 {
2509                         case RF_8256:
2510                         switch(priv->ieee80211->eRFPowerState)
2511                         {
2512                                 case eRfOff:
2513                                         //
2514                                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
2515                                         //
2516                                         if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS )
2517                                         {
2518                                                 dev->HalFunc.LedControlHandler(dev,LED_CTL_NO_LINK);
2519                                         }
2520                                         else
2521                                         {
2522                                                 // Turn off LED if RF is not ON.
2523                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_POWER_OFF);
2524                                         }
2525                                         break;
2526
2527                                 case eRfOn:
2528                                         // Turn on RF we are still linked, which might happen when
2529                                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
2530                                         if( pMgntInfo->bMediaConnect == TRUE )
2531                                         {
2532                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_LINK);
2533                                         }
2534                                         else
2535                                         {
2536                                                 // Turn off LED if RF is not ON.
2537                                                 dev->HalFunc.LedControlHandler(dev, LED_CTL_NO_LINK);
2538                                         }
2539                                         break;
2540
2541                                 default:
2542                                         // do nothing.
2543                                         break;
2544                         }// Switch RF state
2545
2546                                 break;
2547
2548                         default:
2549                                 RT_TRACE(COMP_RF, "phy_SetRFPowerState8192SU(): Unknown RF type\n");
2550                                 break;
2551                 }// Switch rf_chip
2552         }
2553 #endif
2554         priv->SetRFPowerStateInProgress = FALSE;
2555
2556         return bResult;
2557 }
2558
2559 /*-----------------------------------------------------------------------------
2560  * Function:    GetTxPowerLevel8190()
2561  *
2562  * Overview:    This function is export to "common" moudule
2563  *
2564  * Input:       PADAPTER                Adapter
2565  *                      psByte                  Power Level
2566  *
2567  * Output:      NONE
2568  *
2569  * Return:      NONE
2570  *
2571  *---------------------------------------------------------------------------*/
2572  // no use temp
2573  void
2574 PHY_GetTxPowerLevel8192S(
2575         struct net_device* dev,
2576          long*                  powerlevel
2577         )
2578 {
2579         struct r8192_priv *priv = ieee80211_priv(dev);
2580         u8                      TxPwrLevel = 0;
2581         long                    TxPwrDbm;
2582         //
2583         // Because the Tx power indexes are different, we report the maximum of them to
2584         // meet the CCX TPC request. By Bruce, 2008-01-31.
2585         //
2586
2587         // CCK
2588         TxPwrLevel = priv->CurrentCckTxPwrIdx;
2589         TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_B, TxPwrLevel);
2590
2591         // Legacy OFDM
2592         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx + priv->LegacyHTTxPowerDiff;
2593
2594         // Compare with Legacy OFDM Tx power.
2595         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2596                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_G, TxPwrLevel);
2597
2598         // HT OFDM
2599         TxPwrLevel = priv->CurrentOfdm24GTxPwrIdx;
2600
2601         // Compare with HT OFDM Tx power.
2602         if(phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2603                 TxPwrDbm = phy_TxPwrIdxToDbm(dev, WIRELESS_MODE_N_24G, TxPwrLevel);
2604
2605         *powerlevel = TxPwrDbm;
2606 }
2607
2608 /*-----------------------------------------------------------------------------
2609  * Function:    SetTxPowerLevel8190()
2610  *
2611  * Overview:    This function is export to "HalCommon" moudule
2612  *
2613  * Input:       PADAPTER                Adapter
2614  *                      u1Byte          channel
2615  *
2616  * Output:      NONE
2617  *
2618  * Return:      NONE
2619  *      2008/11/04      MHC             We remove EEPROM_93C56.
2620  *                                              We need to move CCX relative code to independet file.
2621 *       2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
2622   *---------------------------------------------------------------------------*/
2623  void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8       channel)
2624 {
2625         struct r8192_priv *priv = ieee80211_priv(dev);
2626         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(dev);
2627         u8      powerlevel = (u8)EEPROM_Default_TxPower, powerlevelOFDM24G = 0x10;
2628         s8      ant_pwr_diff = 0;
2629         u32     u4RegValue;
2630         u8      index = (channel -1);
2631         // 2009/01/22 MH Add for new EEPROM format from SD3
2632         u8      pwrdiff[2] = {0};
2633         u8      ht20pwr[2] = {0}, ht40pwr[2] = {0};
2634         u8      rfpath = 0, rfpathnum = 2;
2635
2636         if(priv->bTXPowerDataReadFromEEPORM == FALSE)
2637                 return;
2638
2639         //
2640         // Read predefined TX power index in EEPROM
2641         //
2642 //      if(priv->epromtype == EPROM_93c46)
2643         {
2644 #ifdef EEPROM_OLD_FORMAT_SUPPORT
2645                 powerlevel = priv->TxPowerLevelCCK[index];
2646                 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[index];
2647 #else
2648                 //
2649                 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-B Tx
2650                 // Power must be calculated by the antenna diff.
2651                 // So we have to rewrite Antenna gain offset register here.
2652                 // Please refer to BB register 0x80c
2653                 // 1. For CCK.
2654                 // 2. For OFDM 1T or 2T
2655                 //
2656
2657                 // 1. CCK
2658                 powerlevel = priv->RfTxPwrLevelCck[0][index];
2659
2660                 if (priv->rf_type == RF_1T2R || priv->rf_type == RF_1T1R)
2661                 {
2662                 // Read HT 40 OFDM TX power
2663                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm1T[0][index];
2664                 // RF B HT OFDM pwr-RFA HT OFDM pwr
2665                 // Only one RF we need not to decide B <-> A pwr diff
2666
2667                 // Legacy<->HT pwr diff, we only care about path A.
2668
2669                 // We only assume 1T as RF path A
2670                 rfpathnum = 1;
2671                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm1T[0][index];
2672                 }
2673                 else if (priv->rf_type == RF_2T2R)
2674                 {
2675                 // Read HT 40 OFDM TX power
2676                 powerlevelOFDM24G = priv->RfTxPwrLevelOfdm2T[0][index];
2677                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2678                 ant_pwr_diff =  priv->RfTxPwrLevelOfdm2T[1][index] -
2679                                                 priv->RfTxPwrLevelOfdm2T[0][index];
2680                         // RF B (HT OFDM pwr+legacy-ht-diff) -(RFA HT OFDM pwr+legacy-ht-diff)
2681                 // We can not handle Path B&A HT/Legacy pwr diff for 92S now.
2682
2683                 //RTPRINT(FPHY, PHY_TXPWR, ("CH-%d HT40 A/B Pwr index = %x/%x(%d/%d)\n",
2684                 //channel, priv->RfTxPwrLevelOfdm2T[0][index],
2685                 //priv->RfTxPwrLevelOfdm2T[1][index],
2686                 //priv->RfTxPwrLevelOfdm2T[0][index],
2687                 //priv->RfTxPwrLevelOfdm2T[1][index]));
2688
2689                 ht20pwr[0] = ht40pwr[0] = priv->RfTxPwrLevelOfdm2T[0][index];
2690                 ht20pwr[1] = ht40pwr[1] = priv->RfTxPwrLevelOfdm2T[1][index];
2691         }
2692
2693         //
2694         // 2009/01/21 MH Support new EEPROM format from SD3 requirement
2695         // 2009/02/10 Cosa, Here is only for reg B/C/D to A gain diff.
2696         //
2697         if (priv->EEPROMVersion == 2)   // Defined by SD1 Jong
2698         {
2699                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2700                 {
2701                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2702                         {
2703                                 // HT 20<->40 pwr diff
2704                                 pwrdiff[rfpath] = priv->TxPwrHt20Diff[rfpath][index];
2705
2706                                 // Calculate Antenna pwr diff
2707                                 if (pwrdiff[rfpath] < 8)        // 0~+7
2708                                 {
2709                                 #if 0//cosa, it doesn't need to add the offset here
2710                                         if (rfpath == 0)
2711                                                 powerlevelOFDM24G += pwrdiff[rfpath];
2712                                 #endif
2713                                         ht20pwr[rfpath] += pwrdiff[rfpath];
2714                                 }
2715                                 else                            // index8-15=-8~-1
2716                                 {
2717                                 #if 0//cosa, it doesn't need to add the offset here
2718                                         if (rfpath == 0)
2719                                                 powerlevelOFDM24G -= (15-pwrdiff[rfpath]);
2720                                 #endif
2721                                         ht20pwr[rfpath] -= (15-pwrdiff[rfpath]);
2722                                 }
2723                         }
2724
2725                         // RF B HT OFDM pwr-RFA HT OFDM pwr
2726                         if (priv->rf_type == RF_2T2R)
2727                                 ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2728
2729                         //RTPRINT(FPHY, PHY_TXPWR,
2730                         //("HT20 to HT40 pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2731                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2732                 }
2733
2734                 // Band Edge scheme is enabled for FCC mode
2735                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
2736                 {
2737                         for (rfpath = 0; rfpath < rfpathnum; rfpath++)
2738                         {
2739                                 pwrdiff[rfpath] = 0;
2740                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2741                                 {
2742                                         if (channel <= 3)
2743                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][0];
2744                                         else if (channel >= 9)
2745                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt40[rfpath][1];
2746                                         else
2747                                                 pwrdiff[rfpath] = 0;
2748
2749                                         ht40pwr[rfpath] -= pwrdiff[rfpath];
2750                                 }
2751                                 else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2752                                 {
2753                                         if (channel == 1)
2754                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][0];
2755                                         else if (channel >= 11)
2756                                                 pwrdiff[rfpath] = priv->TxPwrbandEdgeHt20[rfpath][1];
2757                                         else
2758                                                 pwrdiff[rfpath] = 0;
2759
2760                                         ht20pwr[rfpath] -= pwrdiff[rfpath];
2761                                 }
2762                         #if 0//cosa, it doesn't need to add the offset here
2763                                 if (rfpath == 0)
2764                                         powerlevelOFDM24G -= pwrdiff[rfpath];
2765                         #endif
2766                         }
2767
2768                         if (priv->rf_type == RF_2T2R)
2769                         {
2770                                 // HT 20/40 must decide if they need to minus  BD pwr offset
2771                                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
2772                                         ant_pwr_diff = ht40pwr[1] - ht40pwr[0];
2773                                 else
2774                                         ant_pwr_diff = ht20pwr[1] - ht20pwr[0];
2775                         }
2776                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
2777                         {
2778                                 if (channel <= 1 || channel >= 11)
2779                                 {
2780                                         //RTPRINT(FPHY, PHY_TXPWR,
2781                                         //("HT20 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2782                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht20pwr[1], ht20pwr[0]));
2783                                 }
2784                         }
2785                         else
2786                         {
2787                                 if (channel <= 3 || channel >= 9)
2788                                 {
2789                                         //RTPRINT(FPHY, PHY_TXPWR,
2790                                         //("HT40 Band-edge pwrdiff[A/B]=%d/%d, ant_pwr_diff=%d(B-A=%d-%d)\n",
2791                                         //pwrdiff[0], pwrdiff[1], ant_pwr_diff, ht40pwr[1], ht40pwr[0]));
2792                                 }
2793                         }
2794                 }
2795 #if 0//cosa, useless
2796                 // Read HT/Legacy OFDM diff
2797                 legacy_ant_pwr_diff= pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][index];
2798 #endif
2799                 }
2800
2801         //Cosa added for protection, the reg rFPGA0_TxGainStage
2802         // range is from 7~-8, index = 0x0~0xf
2803         if(ant_pwr_diff > 7)
2804                 ant_pwr_diff = 7;
2805         if(ant_pwr_diff < -8)
2806                 ant_pwr_diff = -8;
2807
2808                 //RTPRINT(FPHY, PHY_TXPWR,
2809                 //("CCK/HT Power index = %x/%x(%d/%d), ant_pwr_diff=%d\n",
2810                 //powerlevel, powerlevelOFDM24G, powerlevel, powerlevelOFDM24G, ant_pwr_diff));
2811
2812                 ant_pwr_diff &= 0xf;
2813
2814                 // Antenna TX power difference
2815                 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2816                 priv->AntennaTxPwDiff[1] = 0;// RF-C, don't care
2817                 priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          // RF-B
2818
2819                 // Antenna gain offset from B/C/D to A
2820                 u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2821                                                 priv->AntennaTxPwDiff[1]<<4 |
2822                                                 priv->AntennaTxPwDiff[0]        );
2823
2824                 // Notify Tx power difference for B/C/D to A!!!
2825                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2826 #endif
2827         }
2828
2829         //
2830         // CCX 2 S31, AP control of client transmit power:
2831         // 1. We shall not exceed Cell Power Limit as possible as we can.
2832         // 2. Tolerance is +/- 5dB.
2833         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2834         //
2835         // TODO:
2836         // 1. 802.11h power contraint
2837         //
2838         // 071011, by rcnjko.
2839         //
2840 #ifdef TODO //WB, 11h has not implemented now.
2841         if(     priv->ieee80211->iw_mode != IW_MODE_INFRA && priv->bWithCcxCellPwr &&
2842                 channel == priv->ieee80211->current_network.channel)// & priv->ieee80211->mAssoc )
2843         {
2844                 u8      CckCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, priv->CcxCellPwr);
2845                 u8      LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_G, priv->CcxCellPwr);
2846                 u8      OfdmCellPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, priv->CcxCellPwr);
2847
2848                 RT_TRACE(COMP_TXAGC,
2849                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2850                 priv->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2851                 RT_TRACE(COMP_TXAGC,
2852                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2853                 channel, powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2854
2855                 // CCK
2856                 if(powerlevel > CckCellPwrIdx)
2857                         powerlevel = CckCellPwrIdx;
2858                 // Legacy OFDM, HT OFDM
2859                 if(powerlevelOFDM24G + priv->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2860                 {
2861                         if((OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff) > 0)
2862                         {
2863                                 powerlevelOFDM24G = OfdmCellPwrIdx - priv->LegacyHTTxPowerDiff;
2864                         }
2865                         else
2866                         {
2867                                 powerlevelOFDM24G = 0;
2868                         }
2869                 }
2870
2871                 RT_TRACE(COMP_TXAGC,
2872                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2873                 powerlevel, powerlevelOFDM24G + priv->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2874         }
2875 #endif
2876
2877         priv->CurrentCckTxPwrIdx = powerlevel;
2878         priv->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2879
2880         switch(priv->rf_chip)
2881         {
2882                 case RF_8225:
2883                         //PHY_SetRF8225CckTxPower(dev, powerlevel);
2884                         //PHY_SetRF8225OfdmTxPower(dev, powerlevelOFDM24G);
2885                 break;
2886
2887                 case RF_8256:
2888 #if 0
2889                         PHY_SetRF8256CCKTxPower(dev, powerlevel);
2890                         PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2891 #endif
2892                         break;
2893
2894                 case RF_6052:
2895                         PHY_RF6052SetCckTxPower(dev, powerlevel);
2896                         PHY_RF6052SetOFDMTxPower(dev, powerlevelOFDM24G);
2897                         break;
2898
2899                 case RF_8258:
2900                         break;
2901                 default:
2902                         break;
2903         }
2904
2905 }
2906
2907 //
2908 //      Description:
2909 //              Update transmit power level of all channel supported.
2910 //
2911 //      TODO:
2912 //              A mode.
2913 //      By Bruce, 2008-02-04.
2914 //    no use temp
2915 bool PHY_UpdateTxPowerDbm8192S(struct net_device* dev, long powerInDbm)
2916 {
2917         struct r8192_priv       *priv = ieee80211_priv(dev);
2918         u8                              idx;
2919         u8                              rf_path;
2920
2921         // TODO: A mode Tx power.
2922         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_B, powerInDbm);
2923         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(dev, WIRELESS_MODE_N_24G, powerInDbm);
2924
2925         if(OfdmTxPwrIdx - priv->LegacyHTTxPowerDiff > 0)
2926                 OfdmTxPwrIdx -= priv->LegacyHTTxPowerDiff;
2927         else
2928                 OfdmTxPwrIdx = 0;
2929
2930         for(idx = 0; idx < 14; idx++)
2931         {
2932                 priv->TxPowerLevelCCK[idx] = CckTxPwrIdx;
2933                 priv->TxPowerLevelCCK_A[idx] = CckTxPwrIdx;
2934                 priv->TxPowerLevelCCK_C[idx] = CckTxPwrIdx;
2935                 priv->TxPowerLevelOFDM24G[idx] = OfdmTxPwrIdx;
2936                 priv->TxPowerLevelOFDM24G_A[idx] = OfdmTxPwrIdx;
2937                 priv->TxPowerLevelOFDM24G_C[idx] = OfdmTxPwrIdx;
2938
2939                 for (rf_path = 0; rf_path < 2; rf_path++)
2940                 {
2941                         priv->RfTxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2942                         priv->RfTxPwrLevelOfdm1T[rf_path][idx] =  \
2943                         priv->RfTxPwrLevelOfdm2T[rf_path][idx] = OfdmTxPwrIdx;
2944                 }
2945         }
2946
2947         PHY_SetTxPowerLevel8192S(dev, priv->chan);
2948
2949         return TRUE;
2950 }
2951
2952 /*
2953         Description:
2954                 When beacon interval is changed, the values of the
2955                 hw registers should be modified.
2956         By tynli, 2008.10.24.
2957
2958 */
2959
2960 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval)
2961 {
2962         u32 NewBeaconNum;
2963
2964         NewBeaconNum = BeaconInterval *32 - 64;
2965         //PlatformEFIOWrite4Byte(Adapter, WFM3+4, NewBeaconNum);
2966         //PlatformEFIOWrite4Byte(Adapter, WFM3, 0xB026007C);
2967         write_nic_dword(dev, WFM3+4, NewBeaconNum);
2968         write_nic_dword(dev, WFM3, 0xB026007C);
2969 }
2970
2971 //
2972 //      Description:
2973 //              Map dBm into Tx power index according to
2974 //              current HW model, for example, RF and PA, and
2975 //              current wireless mode.
2976 //      By Bruce, 2008-01-29.
2977 //    use in phy only
2978 static u8 phy_DbmToTxPwrIdx(
2979         struct net_device* dev,
2980         WIRELESS_MODE   WirelessMode,
2981         long                    PowerInDbm
2982         )
2983 {
2984         //struct r8192_priv *priv = ieee80211_priv(dev);
2985         u8                              TxPwrIdx = 0;
2986         long                            Offset = 0;
2987
2988
2989         //
2990         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
2991         // 3dbm, and OFDM HT equals to 0dbm repectively.
2992         // Note:
2993         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2994         // By Bruce, 2008-01-29.
2995         //
2996         switch(WirelessMode)
2997         {
2998         case WIRELESS_MODE_B:
2999                 Offset = -7;
3000                 break;
3001
3002         case WIRELESS_MODE_G:
3003         case WIRELESS_MODE_N_24G:
3004                 Offset = -8;
3005                 break;
3006         default:
3007                 break;
3008         }
3009
3010         if((PowerInDbm - Offset) > 0)
3011         {
3012                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
3013         }
3014         else
3015         {
3016                 TxPwrIdx = 0;
3017         }
3018
3019         // Tx Power Index is too large.
3020         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
3021                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
3022
3023         return TxPwrIdx;
3024 }
3025 //
3026 //      Description:
3027 //              Map Tx power index into dBm according to
3028 //              current HW model, for example, RF and PA, and
3029 //              current wireless mode.
3030 //      By Bruce, 2008-01-29.
3031 //    use in phy only
3032 static long phy_TxPwrIdxToDbm(
3033         struct net_device* dev,
3034         WIRELESS_MODE   WirelessMode,
3035         u8                      TxPwrIdx
3036         )
3037 {
3038         //struct r8192_priv *priv = ieee80211_priv(dev);
3039         long                            Offset = 0;
3040         long                            PwrOutDbm = 0;
3041
3042         //
3043         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to
3044         // 3dbm, and OFDM HT equals to 0dbm repectively.
3045         // Note:
3046         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
3047         // By Bruce, 2008-01-29.
3048         //
3049         switch(WirelessMode)
3050         {
3051         case WIRELESS_MODE_B:
3052                 Offset = -7;
3053                 break;
3054
3055         case WIRELESS_MODE_G:
3056         case WIRELESS_MODE_N_24G:
3057                 Offset = -8;
3058                 break;
3059         default:
3060                 break;
3061         }
3062
3063         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
3064
3065         return PwrOutDbm;
3066 }
3067
3068 #ifdef TO_DO_LIST
3069 extern  VOID
3070 PHY_ScanOperationBackup8192S(
3071         IN      PADAPTER        Adapter,
3072         IN      u1Byte          Operation
3073         )
3074 {
3075
3076         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
3077         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
3078         u4Byte                          BitMask;
3079         u1Byte                          initial_gain;
3080
3081
3082
3083
3084 #if(RTL8192S_DISABLE_FW_DM == 0)
3085
3086         if(!Adapter->bDriverStopped)
3087         {
3088                 switch(Operation)
3089                 {
3090                         case SCAN_OPT_BACKUP:
3091                                 //
3092                                 // <Roger_Notes> We halt FW DIG and disable high ppower both two DMs here
3093                                 // and resume both two DMs while scan complete.
3094                                 // 2008.11.27.
3095                                 //
3096                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_PAUSE_DM_BY_SCAN);
3097                                 break;
3098
3099                         case SCAN_OPT_RESTORE:
3100                                 //
3101                                 // <Roger_Notes> We resume DIG and enable high power both two DMs here and
3102                                 // recover earlier DIG settings.
3103                                 // 2008.11.27.
3104                                 //
3105                                 Adapter->HalFunc.SetFwCmdHandler(Adapter, FW_CMD_RESUME_DM_BY_SCAN);
3106                                 break;
3107
3108                         default:
3109                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
3110                                 break;
3111                 }
3112         }
3113 #endif
3114 }
3115 #endif
3116
3117 //nouse temp
3118 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   )
3119 {
3120
3121         //struct r8192_priv *priv = ieee80211_priv(dev);
3122         //u32                                   BitMask;
3123         //u8                                    initial_gain;
3124
3125 #if 0   // For 8192s test disable
3126         if(!dev->bDriverStopped)
3127         {
3128                 switch(Operation)
3129                 {
3130                         case IG_Backup:
3131                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Backup, backup the initial gain.\n"));
3132                                 initial_gain = priv->DefaultInitialGain[0];
3133                                 BitMask = bMaskByte0;
3134                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3135                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3136                                 pMgntInfo->InitGain_Backup.XAAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3137                                 pMgntInfo->InitGain_Backup.XBAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3138                                 pMgntInfo->InitGain_Backup.XCAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3139                                 pMgntInfo->InitGain_Backup.XDAGCCore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3140                                 BitMask  = bMaskByte2;
3141                                 pMgntInfo->InitGain_Backup.CCA          = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3142
3143                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3144                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3145                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3146                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3147                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan InitialGainBackup 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3148
3149                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Write scan initial gain = 0x%x \n", initial_gain));
3150                                 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3151                                 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3152                                 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3153                                 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3154                                 break;
3155                         case IG_Restore:
3156                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("IG_Restore, restore the initial gain.\n"));
3157                                 BitMask = 0x7f; //Bit0~ Bit6
3158                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3159                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x8);      // FW DIG OFF
3160
3161                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XAAGCCore1);
3162                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XBAGCCore1);
3163                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XCAGCCore1);
3164                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)pMgntInfo->InitGain_Backup.XDAGCCore1);
3165                                 BitMask  = (BIT22|BIT23);
3166                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)pMgntInfo->InitGain_Backup.CCA);
3167
3168                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc50 is %x\n",pMgntInfo->InitGain_Backup.XAAGCCore1));
3169                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc58 is %x\n",pMgntInfo->InitGain_Backup.XBAGCCore1));
3170                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc60 is %x\n",pMgntInfo->InitGain_Backup.XCAGCCore1));
3171                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xc68 is %x\n",pMgntInfo->InitGain_Backup.XDAGCCore1));
3172                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Scan BBInitialGainRestore 0xa0a is %x\n",pMgntInfo->InitGain_Backup.CCA));
3173
3174                                 if(DM_DigTable.Dig_Algorithm == DIG_ALGO_BY_FALSE_ALARM)
3175                                         PHY_SetMacReg(dev, UFWP, bMaskByte1, 0x1);      // FW DIG ON
3176                                 break;
3177                         default:
3178                         RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown IG Operation. \n"));
3179                                 break;
3180                 }
3181         }
3182 #endif
3183 }
3184
3185 /*-----------------------------------------------------------------------------
3186  * Function:    SetBWModeCallback8190Pci()
3187  *
3188  * Overview:    Timer callback function for SetSetBWMode
3189  *
3190  * Input:               PRT_TIMER               pTimer
3191  *
3192  * Output:      NONE
3193  *
3194  * Return:      NONE
3195  *
3196  * Note:                (1) We do not take j mode into consideration now
3197  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
3198  *                           concurrently?
3199  *---------------------------------------------------------------------------*/
3200 //    use in phy only (in win it's timer)
3201 void PHY_SetBWModeCallback8192S(struct net_device *dev)
3202 {
3203         struct r8192_priv *priv = ieee80211_priv(dev);
3204         u8                              regBwOpMode;
3205
3206         //return;
3207
3208         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3209         //u32                           NowL, NowH;
3210         //u8Byte                                BeginTime, EndTime;
3211         u8                              regRRSR_RSC;
3212
3213         RT_TRACE(COMP_SWBW, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
3214                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
3215
3216         if(priv->rf_chip == RF_PSEUDO_11N)
3217         {
3218                 priv->SetBWModeInProgress= FALSE;
3219                 return;
3220         }
3221
3222         if(!priv->up)
3223                 return;
3224
3225         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3226         //NowL = read_nic_dword(dev, TSFR);
3227         //NowH = read_nic_dword(dev, TSFR+4);
3228         //BeginTime = ((u8Byte)NowH << 32) + NowL;
3229
3230         //3//
3231         //3//<1>Set MAC register
3232         //3//
3233         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3234         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
3235
3236         switch(priv->CurrentChannelBW)
3237         {
3238                 case HT_CHANNEL_WIDTH_20:
3239                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3240                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3241
3242                         regBwOpMode |= BW_OPMODE_20MHZ;
3243                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3244                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3245                         break;
3246
3247                 case HT_CHANNEL_WIDTH_20_40:
3248                         //if(priv->card_8192_version >= VERSION_8192S_BCUT)
3249                         //      write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3250
3251                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3252                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3253                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3254                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
3255                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
3256                         break;
3257
3258                 default:
3259                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci():\
3260                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3261                         break;
3262         }
3263
3264         //3//
3265         //3//<2>Set PHY related register
3266         //3//
3267         switch(priv->CurrentChannelBW)
3268         {
3269                 /* 20 MHz channel*/
3270                 case HT_CHANNEL_WIDTH_20:
3271                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3272                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3273
3274                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3275                         // It is set in Tx descriptor for 8192x series
3276                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3277                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3278                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3279                         #if 0 //LZM 090219
3280                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
3281                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
3282                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
3283                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3284                         #endif
3285
3286                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3287                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x58);
3288
3289
3290                         break;
3291
3292                 /* 40 MHz channel*/
3293                 case HT_CHANNEL_WIDTH_20_40:
3294                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3295                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3296
3297                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3298                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3299                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3300                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3301                         #if 0 //LZM 090219
3302                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
3303                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
3304                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
3305                         #endif
3306
3307                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3308                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3309                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3310
3311                         //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
3312                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
3313                                 write_nic_byte(dev, rFPGA0_AnalogParameter2, 0x18);
3314
3315                         break;
3316
3317                 default:
3318                         RT_TRACE(COMP_DBG, "SetBWModeCallback8190Pci(): unknown Bandwidth: %#X\n"\
3319                                                 ,priv->CurrentChannelBW);
3320                         break;
3321
3322         }
3323         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3324
3325         // Added it for 20/40 mhz switch time evaluation by guangan 070531
3326         //NowL = read_nic_dword(dev, TSFR);
3327         //NowH = read_nic_dword(dev, TSFR+4);
3328         //EndTime = ((u8Byte)NowH << 32) + NowL;
3329         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
3330
3331         //3<3>Set RF related register
3332         switch( priv->rf_chip )
3333         {
3334                 case RF_8225:
3335                         //PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
3336                         break;
3337
3338                 case RF_8256:
3339                         // Please implement this function in Hal8190PciPhy8256.c
3340                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3341                         break;
3342
3343                 case RF_8258:
3344                         // Please implement this function in Hal8190PciPhy8258.c
3345                         // PHY_SetRF8258Bandwidth();
3346                         break;
3347
3348                 case RF_PSEUDO_11N:
3349                         // Do Nothing
3350                         break;
3351
3352                 case RF_6052:
3353                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
3354                         break;
3355                 default:
3356                         printk("Unknown rf_chip: %d\n", priv->rf_chip);
3357                         break;
3358         }
3359
3360         priv->SetBWModeInProgress= FALSE;
3361
3362         RT_TRACE(COMP_SWBW, "<==SetBWModeCallback8190Pci() \n" );
3363 }
3364
3365
3366  /*-----------------------------------------------------------------------------
3367  * Function:   SetBWMode8190Pci()
3368  *
3369  * Overview:  This function is export to "HalCommon" moudule
3370  *
3371  * Input:               PADAPTER                        Adapter
3372  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
3373  *
3374  * Output:      NONE
3375  *
3376  * Return:      NONE
3377  *
3378  * Note:                We do not take j mode into consideration now
3379  *---------------------------------------------------------------------------*/
3380 //extern void PHY_SetBWMode8192S(       struct net_device* dev,
3381 //      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
3382 //      HT_EXTCHNL_OFFSET       Offset          // Upper, Lower, or Don't care
3383 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3384 {
3385         struct r8192_priv *priv = ieee80211_priv(dev);
3386         HT_CHANNEL_WIDTH tmpBW = priv->CurrentChannelBW;
3387
3388
3389         // Modified it for 20/40 mhz switch by guangan 070531
3390
3391         //return;
3392
3393         //if(priv->SwChnlInProgress)
3394 //      if(pMgntInfo->bScanInProgress)
3395 //      {
3396 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s Exit because bScanInProgress!\n",
3397 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3398 //              return;
3399 //      }
3400
3401 //      if(priv->SetBWModeInProgress)
3402 //      {
3403 //              // Modified it for 20/40 mhz switch by guangan 070531
3404 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWMode8190Pci() %s cancel last timer because SetBWModeInProgress!\n",
3405 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
3406 //              PlatformCancelTimer(dev, &priv->SetBWModeTimer);
3407 //              //return;
3408 //      }
3409
3410         if(priv->SetBWModeInProgress)
3411                 return;
3412
3413         priv->SetBWModeInProgress= TRUE;
3414
3415         priv->CurrentChannelBW = Bandwidth;
3416
3417         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3418                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3419         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3420                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3421         else
3422                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3423
3424 #if 0
3425         if(!priv->bDriverStopped)
3426         {
3427 #ifdef USE_WORKITEM
3428                 PlatformScheduleWorkItem(&(priv->SetBWModeWorkItem));//SetBWModeCallback8192SUsbWorkItem
3429 #else
3430                 PlatformSetTimer(dev, &(priv->SetBWModeTimer), 0);//PHY_SetBWModeCallback8192S
3431 #endif
3432         }
3433 #endif
3434         if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
3435         {
3436 #ifdef RTL8192SE
3437         PHY_SetBWModeCallback8192S(dev);
3438 #elif defined(RTL8192SU)
3439         SetBWModeCallback8192SUsbWorkItem(dev);
3440 #endif
3441         }
3442         else
3443         {
3444                 RT_TRACE(COMP_SCAN, "PHY_SetBWMode8192S() SetBWModeInProgress FALSE driver sleep or unload\n");
3445                 priv->SetBWModeInProgress= FALSE;
3446                 priv->CurrentChannelBW = tmpBW;
3447         }
3448 }
3449
3450 //    use in phy only (in win it's timer)
3451 void PHY_SwChnlCallback8192S(struct net_device *dev)
3452 {
3453
3454         struct r8192_priv *priv = ieee80211_priv(dev);
3455         u32             delay;
3456         //bool                  ret;
3457
3458         RT_TRACE(COMP_CH, "==>SwChnlCallback8190Pci(), switch to channel %d\n", priv->chan);
3459
3460         if(!priv->up)
3461                 return;
3462
3463         if(priv->rf_chip == RF_PSEUDO_11N)
3464         {
3465                 priv->SwChnlInProgress=FALSE;
3466                 return;                                                                 //return immediately if it is peudo-phy
3467         }
3468
3469         do{
3470                 if(!priv->SwChnlInProgress)
3471                         break;
3472
3473                 //if(!phy_SwChnlStepByStep(dev, priv->CurrentChannel, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3474                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
3475                 {
3476                         if(delay>0)
3477                         {
3478                                 mdelay(delay);
3479                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
3480                                 //mod_timer(&priv->SwChnlTimer,  jiffies + MSECS(delay));
3481                                 //==>PHY_SwChnlCallback8192S(dev); for 92se
3482                                 //==>SwChnlCallback8192SUsb(dev) for 92su
3483                         }
3484                         else
3485                         continue;
3486                 }
3487                 else
3488                 {
3489                         priv->SwChnlInProgress=FALSE;
3490                         break;
3491                 }
3492         }while(true);
3493 }
3494
3495 // Call after initialization
3496 //extern void PHY_SwChnl8192S(struct net_device* dev,   u8 channel)
3497 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
3498 {
3499         struct r8192_priv *priv = ieee80211_priv(dev);
3500         //u8                    tmpchannel =channel;
3501         //bool                  bResult = false;
3502
3503         if(!priv->up)
3504                 return false;
3505
3506         if(priv->SwChnlInProgress)
3507                 return false;
3508
3509         if(priv->SetBWModeInProgress)
3510                 return false;
3511
3512         //--------------------------------------------
3513         switch(priv->ieee80211->mode)
3514         {
3515         case WIRELESS_MODE_A:
3516         case WIRELESS_MODE_N_5G:
3517                 if (channel<=14){
3518                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
3519                         return false;
3520                 }
3521                 break;
3522
3523         case WIRELESS_MODE_B:
3524                 if (channel>14){
3525                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
3526                         return false;
3527                 }
3528                 break;
3529
3530         case WIRELESS_MODE_G:
3531         case WIRELESS_MODE_N_24G:
3532                 if (channel>14){
3533                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
3534                         return false;
3535                 }
3536                 break;
3537
3538         default:
3539                         ;//RT_TRACE(COMP_ERR, "Invalid WirelessMode(%#x)!!\n", priv->ieee80211->mode);
3540                 break;
3541         }
3542         //--------------------------------------------
3543
3544         priv->SwChnlInProgress = TRUE;
3545         if( channel == 0)
3546                 channel = 1;
3547
3548         priv->chan=channel;
3549
3550         priv->SwChnlStage=0;
3551         priv->SwChnlStep=0;
3552
3553         if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
3554         {
3555 #ifdef RTL8192SE
3556         PHY_SwChnlCallback8192S(dev);
3557 #elif defined(RTL8192SU)
3558         SwChnlCallback8192SUsbWorkItem(dev);
3559 #endif
3560 #ifdef TO_DO_LIST
3561         if(bResult)
3562                 {
3563                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress TRUE schdule workitem done\n");
3564                 }
3565                 else
3566                 {
3567                         RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE schdule workitem error\n");
3568                         priv->SwChnlInProgress = false;
3569                         priv->CurrentChannel = tmpchannel;
3570                 }
3571 #endif
3572         }
3573         else
3574         {
3575                 RT_TRACE(COMP_SCAN, "PHY_SwChnl8192S SwChnlInProgress FALSE driver sleep or unload\n");
3576                 priv->SwChnlInProgress = false;
3577                 //priv->CurrentChannel = tmpchannel;
3578         }
3579         return true;
3580 }
3581
3582
3583 //
3584 // Description:
3585 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
3586 //
3587 // Implemented by Bruce, 2008-02-14.
3588 // The following procedure is operted according to SwChanlCallback8190Pci().
3589 // However, this procedure is performed synchronously  which should be running under
3590 // passive level.
3591 //
3592 //not understant it
3593 void PHY_SwChnlPhy8192S(        // Only called during initialize
3594         struct net_device* dev,
3595         u8              channel
3596         )
3597 {
3598         struct r8192_priv *priv = ieee80211_priv(dev);
3599
3600         RT_TRACE(COMP_SCAN, "==>PHY_SwChnlPhy8192S(), switch to channel %d.\n", priv->chan);
3601
3602 #ifdef TO_DO_LIST
3603         // Cannot IO.
3604         if(RT_CANNOT_IO(dev))
3605                 return;
3606 #endif
3607
3608         // Channel Switching is in progress.
3609         if(priv->SwChnlInProgress)
3610                 return;
3611
3612         //return immediately if it is peudo-phy
3613         if(priv->rf_chip == RF_PSEUDO_11N)
3614         {
3615                 priv->SwChnlInProgress=FALSE;
3616                 return;
3617         }
3618
3619         priv->SwChnlInProgress = TRUE;
3620         if( channel == 0)
3621                 channel = 1;
3622
3623         priv->chan=channel;
3624
3625         priv->SwChnlStage = 0;
3626         priv->SwChnlStep = 0;
3627
3628         phy_FinishSwChnlNow(dev,channel);
3629
3630         priv->SwChnlInProgress = FALSE;
3631 }
3632
3633 //    use in phy only
3634 static bool
3635 phy_SetSwChnlCmdArray(
3636         SwChnlCmd*              CmdTable,
3637         u32                     CmdTableIdx,
3638         u32                     CmdTableSz,
3639         SwChnlCmdID             CmdID,
3640         u32                     Para1,
3641         u32                     Para2,
3642         u32                     msDelay
3643         )
3644 {
3645         SwChnlCmd* pCmd;
3646
3647         if(CmdTable == NULL)
3648         {
3649                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3650                 return FALSE;
3651         }
3652         if(CmdTableIdx >= CmdTableSz)
3653         {
3654                 //RT_ASSERT(FALSE,
3655                         //      ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
3656                                 //CmdTableIdx, CmdTableSz));
3657                 return FALSE;
3658         }
3659
3660         pCmd = CmdTable + CmdTableIdx;
3661         pCmd->CmdID = CmdID;
3662         pCmd->Para1 = Para1;
3663         pCmd->Para2 = Para2;
3664         pCmd->msDelay = msDelay;
3665
3666         return TRUE;
3667 }
3668
3669 //    use in phy only
3670 static bool
3671 phy_SwChnlStepByStep(
3672         struct net_device* dev,
3673         u8              channel,
3674         u8              *stage,
3675         u8              *step,
3676         u32             *delay
3677         )
3678 {
3679         struct r8192_priv *priv = ieee80211_priv(dev);
3680         //PCHANNEL_ACCESS_SETTING       pChnlAccessSetting;
3681         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
3682         u32                                     PreCommonCmdCnt;
3683         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
3684         u32                                     PostCommonCmdCnt;
3685         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
3686         u32                                     RfDependCmdCnt;
3687         SwChnlCmd                               *CurrentCmd = NULL;
3688         u8                                      eRFPath;
3689
3690         //RT_ASSERT((dev != NULL), ("Adapter should not be NULL\n"));
3691         //RT_ASSERT(IsLegalChannel(dev, channel), ("illegal channel: %d\n", channel));
3692         RT_TRACE(COMP_CH, "===========>%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3693         //RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3694 #ifdef ENABLE_DOT11D
3695         if (!IsLegalChannel(priv->ieee80211, channel))
3696         {
3697                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
3698                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
3699         }
3700 #endif
3701
3702         //pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3703         //RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3704
3705         //for(eRFPath = RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
3706         //for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3707         //{
3708                 // <1> Fill up pre common command.
3709         PreCommonCmdCnt = 0;
3710         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3711                                 CmdID_SetTxPowerLevel, 0, 0, 0);
3712         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3713                                 CmdID_End, 0, 0, 0);
3714
3715                 // <2> Fill up post common command.
3716         PostCommonCmdCnt = 0;
3717
3718         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3719                                 CmdID_End, 0, 0, 0);
3720
3721                 // <3> Fill up RF dependent command.
3722         RfDependCmdCnt = 0;
3723         switch( priv->rf_chip )
3724         {
3725                 case RF_8225:
3726                 if (channel < 1 || channel > 14)
3727                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3728                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3729                 // 2008/09/04 MH Change channel.
3730                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3731                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3732                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3733                 CmdID_End, 0, 0, 0);
3734                 break;
3735
3736         case RF_8256:
3737                 if (channel < 1 || channel > 14)
3738                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3739                 // TEST!! This is not the table for 8256!!
3740                 //RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3741                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3742                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3743                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3744                 CmdID_End, 0, 0, 0);
3745                 break;
3746
3747         case RF_6052:
3748                 if (channel < 1 || channel > 14)
3749                         RT_TRACE(COMP_ERR, "illegal channel for zebra:%d\n", channel);
3750                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3751                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3752                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3753                         CmdID_End, 0, 0, 0);
3754                 break;
3755
3756         case RF_8258:
3757                 break;
3758
3759         default:
3760                 //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
3761                 return FALSE;
3762                 break;
3763         }
3764
3765
3766         do{
3767                 switch(*stage)
3768                 {
3769                 case 0:
3770                         CurrentCmd=&PreCommonCmd[*step];
3771                         break;
3772                 case 1:
3773                         CurrentCmd=&RfDependCmd[*step];
3774                         break;
3775                 case 2:
3776                         CurrentCmd=&PostCommonCmd[*step];
3777                         break;
3778                 }
3779
3780                 if(CurrentCmd->CmdID==CmdID_End)
3781                 {
3782                         if((*stage)==2)
3783                         {
3784                                 return TRUE;
3785                         }
3786                         else
3787                         {
3788                                 (*stage)++;
3789                                 (*step)=0;
3790                                 continue;
3791                         }
3792                 }
3793
3794                 switch(CurrentCmd->CmdID)
3795                 {
3796                 case CmdID_SetTxPowerLevel:
3797                         //if(priv->card_8192_version > VERSION_8190_BD)
3798                                 PHY_SetTxPowerLevel8192S(dev,channel);
3799                         break;
3800                 case CmdID_WritePortUlong:
3801                         write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
3802                         break;
3803                 case CmdID_WritePortUshort:
3804                         write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
3805                         break;
3806                 case CmdID_WritePortUchar:
3807                         write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
3808                         break;
3809                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3810                         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
3811                         {
3812 #if (defined RTL8192SE ||defined RTL8192SU )
3813                         // For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
3814                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
3815                                 //printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
3816 #else
3817                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, ((CurrentCmd->Para2)<<7));
3818 #endif
3819                         }
3820                         break;
3821                 default:
3822                         break;
3823                 }
3824
3825                 break;
3826         }while(TRUE);
3827         //cosa }/*for(Number of RF paths)*/
3828
3829         (*delay)=CurrentCmd->msDelay;
3830         (*step)++;
3831         RT_TRACE(COMP_CH, "<===========%s(), channel:%d, stage:%d, step:%d\n", __FUNCTION__, channel, *stage, *step);
3832         return FALSE;
3833 }
3834
3835 //called PHY_SwChnlPhy8192S, SwChnlCallback8192SUsbWorkItem
3836 //    use in phy only
3837 static void
3838 phy_FinishSwChnlNow(    // We should not call this function directly
3839         struct net_device* dev,
3840         u8              channel
3841                 )
3842 {
3843         struct r8192_priv       *priv = ieee80211_priv(dev);
3844         u32                     delay;
3845
3846         while(!phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
3847         {
3848                 if(delay>0)
3849                         mdelay(delay);
3850                 if(!priv->up)
3851                         break;
3852         }
3853 }
3854
3855
3856 /*-----------------------------------------------------------------------------
3857  * Function:    PHYCheckIsLegalRfPath8190Pci()
3858  *
3859  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3860  *                      We will return false.
3861  *
3862  * Input:               NONE
3863  *
3864  * Output:              NONE
3865  *
3866  * Return:              NONE
3867  *
3868  * Revised History:
3869  *      When            Who             Remark
3870  *      11/15/2007      MHC             Create Version 0.
3871  *
3872  *---------------------------------------------------------------------------*/
3873  //called by rtl8192_phy_QueryRFReg, rtl8192_phy_SetRFReg, PHY_SetRFPowerState8192SUsb
3874 //extern        bool
3875 //PHY_CheckIsLegalRfPath8192S(
3876 //      struct net_device* dev,
3877 //      u32     eRFPath)
3878 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
3879 {
3880 //      struct r8192_priv *priv = ieee80211_priv(dev);
3881         bool                            rtValue = TRUE;
3882
3883         // NOt check RF Path now.!
3884 #if 0
3885         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3886         {
3887                 rtValue = FALSE;
3888         }
3889         if (priv->rf_type == RF_1T2R && eRFPath != RF90_PATH_A)
3890         {
3891
3892         }
3893 #endif
3894         return  rtValue;
3895
3896 }       /* PHY_CheckIsLegalRfPath8192S */
3897
3898
3899
3900 /*-----------------------------------------------------------------------------
3901  * Function:    PHY_IQCalibrate8192S()
3902  *
3903  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
3904  *                      to improve RF EVM!!?
3905  *
3906  * Input:               IN      PADAPTER        pAdapter
3907  *
3908  * Output:              NONE
3909  *
3910  * Return:              NONE
3911  *
3912  * Revised History:
3913  *      When            Who             Remark
3914  *      10/07/2008      MHC             Create. Document from SD3 RFSI Jenyu.
3915  *
3916  *---------------------------------------------------------------------------*/
3917  //called by InitializeAdapter8192SE
3918 void
3919 PHY_IQCalibrate(        struct net_device* dev)
3920 {
3921         //struct r8192_priv     *priv = ieee80211_priv(dev);
3922         u32                             i, reg;
3923         u32                             old_value;
3924         long                            X, Y, TX0[4];
3925         u32                             TXA[4];
3926
3927         // 1. Check QFN68 or 64 92S (Read from EEPROM)
3928
3929         //
3930         // 2. QFN 68
3931         //
3932         // For 1T2R IQK only now !!!
3933         for (i = 0; i < 10; i++)
3934         {
3935                 // IQK
3936                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
3937                 //PlatformStallExecution(5);
3938                 udelay(5);
3939                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
3940                 udelay(5);
3941                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
3942                 udelay(5);
3943                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140148);
3944                 udelay(5);
3945                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604a2);
3946                 udelay(5);
3947                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
3948                 udelay(5);
3949                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x0214014d);
3950                 udelay(5);
3951                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x281608ba);
3952                 udelay(5);
3953                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x000028d1);
3954                 udelay(5);
3955                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000001);
3956                 udelay(5);
3957                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000001);
3958                 udelay(2000);
3959                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
3960                 udelay(5);
3961                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
3962                 udelay(5);
3963                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
3964
3965
3966                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
3967
3968                 // Readback IQK value and rewrite
3969                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
3970                 {
3971                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
3972
3973                         // Calibrate init gain for A path for TX0
3974                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
3975                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
3976                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3977                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
3978                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3979                         udelay(5);
3980
3981                         // Calibrate init gain for C path for TX0
3982                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
3983                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
3984                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
3985                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
3986                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
3987                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
3988                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
3989                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
3990                         udelay(5);
3991
3992                         // Calibrate RX A and B for RX0
3993                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
3994                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
3995                         reg = (reg & 0xFFFFFC00) |X;
3996                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
3997                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
3998                         reg = (reg & 0xFFFF03FF) |Y<<10;
3999                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4000                         udelay(5);
4001                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4002
4003                         // Calibrate init gain for A path for TX1 !!!!!!
4004                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4005                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4006                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4007                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4008                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4009                         udelay(5);
4010
4011                         // Calibrate init gain for C path for TX1
4012                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4013                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4014                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4015                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4016                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4017                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4018                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4019                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4020                         udelay(5);
4021
4022                         // Calibrate RX A and B for RX1
4023                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4024                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4025                         reg = (reg & 0xFFFFFC00) |X;
4026                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4027
4028                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4029                         reg = (reg & 0xFFFF03FF) |Y<<10;
4030                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4031                         udelay(5);
4032
4033                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4034                         break;
4035                 }
4036
4037         }
4038
4039
4040         //
4041         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4042         //
4043
4044
4045 }
4046
4047 /*-----------------------------------------------------------------------------
4048  * Function:    PHY_IQCalibrateBcut()
4049  *
4050  * Overview:    After all MAC/PHY/RF is configued. We must execute IQ calibration
4051  *                      to improve RF EVM!!?
4052  *
4053  * Input:               IN      PADAPTER        pAdapter
4054  *
4055  * Output:              NONE
4056  *
4057  * Return:              NONE
4058  *
4059  * Revised History:
4060  *      When            Who             Remark
4061  *      11/18/2008      MHC             Create. Document from SD3 RFSI Jenyu.
4062  *                                              92S B-cut QFN 68 pin IQ calibration procedure.doc
4063  *
4064  *---------------------------------------------------------------------------*/
4065 extern void PHY_IQCalibrateBcut(struct net_device* dev)
4066 {
4067         //struct r8192_priv     *priv = ieee80211_priv(dev);
4068         //PMGNT_INFO            pMgntInfo = &pAdapter->MgntInfo;
4069         u32                             i, reg;
4070         u32                             old_value;
4071         long                            X, Y, TX0[4];
4072         u32                             TXA[4];
4073         u32                             calibrate_set[13] = {0};
4074         u32                             load_value[13];
4075         u8                              RfPiEnable=0;
4076
4077         // 0. Check QFN68 or 64 92S (Read from EEPROM/EFUSE)
4078
4079         //
4080         // 1. Save e70~ee0 register setting, and load calibration setting
4081         //
4082         /*
4083         0xee0[31:0]=0x3fed92fb;
4084         0xedc[31:0] =0x3fed92fb;
4085         0xe70[31:0] =0x3fed92fb;
4086         0xe74[31:0] =0x3fed92fb;
4087         0xe78[31:0] =0x3fed92fb;
4088         0xe7c[31:0]= 0x3fed92fb;
4089         0xe80[31:0]= 0x3fed92fb;
4090         0xe84[31:0]= 0x3fed92fb;
4091         0xe88[31:0]= 0x3fed92fb;
4092         0xe8c[31:0]= 0x3fed92fb;
4093         0xed0[31:0]= 0x3fed92fb;
4094         0xed4[31:0]= 0x3fed92fb;
4095         0xed8[31:0]= 0x3fed92fb;
4096         */
4097         calibrate_set [0] = 0xee0;
4098         calibrate_set [1] = 0xedc;
4099         calibrate_set [2] = 0xe70;
4100         calibrate_set [3] = 0xe74;
4101         calibrate_set [4] = 0xe78;
4102         calibrate_set [5] = 0xe7c;
4103         calibrate_set [6] = 0xe80;
4104         calibrate_set [7] = 0xe84;
4105         calibrate_set [8] = 0xe88;
4106         calibrate_set [9] = 0xe8c;
4107         calibrate_set [10] = 0xed0;
4108         calibrate_set [11] = 0xed4;
4109         calibrate_set [12] = 0xed8;
4110         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Save e70~ee0 register setting\n"));
4111         for (i = 0; i < 13; i++)
4112         {
4113                 load_value[i] = rtl8192_QueryBBReg(dev, calibrate_set[i], bMaskDWord);
4114                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, 0x3fed92fb);
4115
4116         }
4117
4118         RfPiEnable = (u8)rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter1, BIT8);
4119
4120         //
4121         // 2. QFN 68
4122         //
4123         // For 1T2R IQK only now !!!
4124         for (i = 0; i < 10; i++)
4125         {
4126                 RT_TRACE(COMP_INIT, "IQK -%d\n", i);
4127                 //BB switch to PI mode. If default is PI mode, ignoring 2 commands below.
4128                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4129                 {
4130                         //DbgPrint("IQK Switch to PI mode\n");
4131                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000100);
4132                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000100);
4133                 }
4134
4135                 // IQK
4136                 // 2. IQ calibration & LO leakage calibration
4137                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05430);
4138                 udelay(5);
4139                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000800e4);
4140                 udelay(5);
4141                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x80800000);
4142                 udelay(5);
4143                 //path-A IQ K and LO K gain setting
4144                 rtl8192_setBBreg(dev, 0xe40, bMaskDWord, 0x02140102);
4145                 udelay(5);
4146                 rtl8192_setBBreg(dev, 0xe44, bMaskDWord, 0x681604c2);
4147                 udelay(5);
4148                 //set LO calibration
4149                 rtl8192_setBBreg(dev, 0xe4c, bMaskDWord, 0x000028d1);
4150                 udelay(5);
4151                 //path-B IQ K and LO K gain setting
4152                 rtl8192_setBBreg(dev, 0xe60, bMaskDWord, 0x02140102);
4153                 udelay(5);
4154                 rtl8192_setBBreg(dev, 0xe64, bMaskDWord, 0x28160d05);
4155                 udelay(5);
4156                 //K idac_I & IQ
4157                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4158                 udelay(5);
4159                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4160                 udelay(5);
4161
4162                 // delay 2ms
4163                 udelay(2000);
4164
4165                 //idac_Q setting
4166                 rtl8192_setBBreg(dev, 0xe6c, bMaskDWord, 0x020028d1);
4167                 udelay(5);
4168                 //K idac_Q & IQ
4169                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xfb000000);
4170                 udelay(5);
4171                 rtl8192_setBBreg(dev, 0xe48, bMaskDWord, 0xf8000000);
4172
4173                 // delay 2ms
4174                 udelay(2000);
4175
4176                 rtl8192_setBBreg(dev, 0xc04, bMaskDWord, 0x00a05433);
4177                 udelay(5);
4178                 rtl8192_setBBreg(dev, 0xc08, bMaskDWord, 0x000000e4);
4179                 udelay(5);
4180                 rtl8192_setBBreg(dev, 0xe28, bMaskDWord, 0x0);
4181
4182                 if (!RfPiEnable)        //if original is SI mode, then switch to PI mode.
4183                 {
4184                         //DbgPrint("IQK Switch back to SI mode\n");
4185                         rtl8192_setBBreg(dev, 0x820, bMaskDWord, 0x01000000);
4186                         rtl8192_setBBreg(dev, 0x828, bMaskDWord, 0x01000000);
4187                 }
4188
4189
4190                 reg = rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord);
4191
4192                 // 3.   check fail bit, and fill BB IQ matrix
4193                 // Readback IQK value and rewrite
4194                 if (!(reg&(BIT27|BIT28|BIT30|BIT31)))
4195                 {
4196                         old_value = (rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord) & 0x3FF);
4197
4198                         // Calibrate init gain for A path for TX0
4199                         X = (rtl8192_QueryBBReg(dev, 0xe94, bMaskDWord) & 0x03FF0000)>>16;
4200                         TXA[RF90_PATH_A] = (X * old_value)/0x100;
4201                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4202                         reg = (reg & 0xFFFFFC00) | (u32)TXA[RF90_PATH_A];
4203                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4204                         udelay(5);
4205
4206                         // Calibrate init gain for C path for TX0
4207                         Y = ( rtl8192_QueryBBReg(dev, 0xe9C, bMaskDWord) & 0x03FF0000)>>16;
4208                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4209                         reg = rtl8192_QueryBBReg(dev, 0xc80, bMaskDWord);
4210                         reg = (reg & 0xffc0ffff) |((u32) (TX0[RF90_PATH_C]&0x3F)<<16);
4211                         rtl8192_setBBreg(dev, 0xc80, bMaskDWord, reg);
4212                         reg = rtl8192_QueryBBReg(dev, 0xc94, bMaskDWord);
4213                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4214                         rtl8192_setBBreg(dev, 0xc94, bMaskDWord, reg);
4215                         udelay(5);
4216
4217                         // Calibrate RX A and B for RX0
4218                         reg = rtl8192_QueryBBReg(dev, 0xc14, bMaskDWord);
4219                         X = (rtl8192_QueryBBReg(dev, 0xea4, bMaskDWord) & 0x03FF0000)>>16;
4220                         reg = (reg & 0xFFFFFC00) |X;
4221                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4222                         Y = (rtl8192_QueryBBReg(dev, 0xeac, bMaskDWord) & 0x003F0000)>>16;
4223                         reg = (reg & 0xFFFF03FF) |Y<<10;
4224                         rtl8192_setBBreg(dev, 0xc14, bMaskDWord, reg);
4225                         udelay(5);
4226                         old_value = (rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord) & 0x3FF);
4227
4228                         // Calibrate init gain for A path for TX1 !!!!!!
4229                         X = (rtl8192_QueryBBReg(dev, 0xeb4, bMaskDWord) & 0x03FF0000)>>16;
4230                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4231                         TXA[RF90_PATH_A] = (X * old_value) / 0x100;
4232                         reg = (reg & 0xFFFFFC00) | TXA[RF90_PATH_A];
4233                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4234                         udelay(5);
4235
4236                         // Calibrate init gain for C path for TX1
4237                         Y = (rtl8192_QueryBBReg(dev, 0xebc, bMaskDWord)& 0x03FF0000)>>16;
4238                         TX0[RF90_PATH_C] = ((Y * old_value)/0x100);
4239                         reg = rtl8192_QueryBBReg(dev, 0xc88, bMaskDWord);
4240                         reg = (reg & 0xffc0ffff) |( (TX0[RF90_PATH_C]&0x3F)<<16);
4241                         rtl8192_setBBreg(dev, 0xc88, bMaskDWord, reg);
4242                         reg = rtl8192_QueryBBReg(dev, 0xc9c, bMaskDWord);
4243                         reg = (reg & 0x0fffffff) |(((Y&0x3c0)>>6)<<28);
4244                         rtl8192_setBBreg(dev, 0xc9c, bMaskDWord, reg);
4245                         udelay(5);
4246
4247                         // Calibrate RX A and B for RX1
4248                         reg = rtl8192_QueryBBReg(dev, 0xc1c, bMaskDWord);
4249                         X = (rtl8192_QueryBBReg(dev, 0xec4, bMaskDWord) & 0x03FF0000)>>16;
4250                         reg = (reg & 0xFFFFFC00) |X;
4251                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4252
4253                         Y = (rtl8192_QueryBBReg(dev, 0xecc, bMaskDWord) & 0x003F0000)>>16;
4254                         reg = (reg & 0xFFFF03FF) |Y<<10;
4255                         rtl8192_setBBreg(dev, 0xc1c, bMaskDWord, reg);
4256                         udelay(5);
4257
4258                         RT_TRACE(COMP_INIT, "PHY_IQCalibrate OK\n");
4259                         break;
4260                 }
4261
4262         }
4263
4264         //
4265         // 4. Reload e70~ee0 register setting.
4266         //
4267         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reload e70~ee0 register setting.\n"));
4268         for (i = 0; i < 13; i++)
4269                 rtl8192_setBBreg(dev, calibrate_set[i], bMaskDWord, load_value[i]);
4270
4271
4272         //
4273         // 3. QFN64. Not enabled now !!! We must use different gain table for 1T2R.
4274         //
4275
4276
4277
4278 }       // PHY_IQCalibrateBcut
4279
4280
4281 //
4282 // Move from phycfg.c to gen.c to be code independent later
4283 //
4284 //-------------------------Move to other DIR later----------------------------*/
4285 //#if (DEV_BUS_TYPE == USB_INTERFACE)
4286 #ifdef RTL8192SU
4287
4288 //    use in phy only (in win it's timer)
4289 void SwChnlCallback8192SUsb(struct net_device *dev)
4290 {
4291
4292         struct r8192_priv *priv = ieee80211_priv(dev);
4293         u32                     delay;
4294 //      bool                    ret;
4295
4296         RT_TRACE(COMP_SCAN, "==>SwChnlCallback8190Pci(), switch to channel\
4297                                 %d\n", priv->chan);
4298
4299
4300         if(!priv->up)
4301                 return;
4302
4303         if(priv->rf_chip == RF_PSEUDO_11N)
4304         {
4305                 priv->SwChnlInProgress=FALSE;
4306                 return;                                                                 //return immediately if it is peudo-phy
4307         }
4308
4309         do{
4310                 if(!priv->SwChnlInProgress)
4311                         break;
4312
4313                 if(!phy_SwChnlStepByStep(dev, priv->chan, &priv->SwChnlStage, &priv->SwChnlStep, &delay))
4314                 {
4315                         if(delay>0)
4316                         {
4317                                 //PlatformSetTimer(dev, &priv->SwChnlTimer, delay);
4318
4319                         }
4320                         else
4321                         continue;
4322                 }
4323                 else
4324                 {
4325                         priv->SwChnlInProgress=FALSE;
4326                 }
4327                 break;
4328         }while(TRUE);
4329 }
4330
4331
4332 //
4333 // Callback routine of the work item for switch channel.
4334 //
4335 //    use in phy only (in win it's work)
4336 void SwChnlCallback8192SUsbWorkItem(struct net_device *dev )
4337 {
4338         struct r8192_priv *priv = ieee80211_priv(dev);
4339
4340         RT_TRACE(COMP_TRACE, "==> SwChnlCallback8192SUsbWorkItem()\n");
4341 #ifdef TO_DO_LIST
4342         if(pAdapter->bInSetPower && RT_USB_CANNOT_IO(pAdapter))
4343         {
4344                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("<== SwChnlCallback8192SUsbWorkItem() SwChnlInProgress FALSE driver sleep or unload\n"));
4345
4346                 pHalData->SwChnlInProgress = FALSE;
4347                 return;
4348         }
4349 #endif
4350         phy_FinishSwChnlNow(dev, priv->chan);
4351         priv->SwChnlInProgress = FALSE;
4352
4353         RT_TRACE(COMP_TRACE, "<== SwChnlCallback8192SUsbWorkItem()\n");
4354 }
4355
4356
4357 /*-----------------------------------------------------------------------------
4358  * Function:    SetBWModeCallback8192SUsb()
4359  *
4360  * Overview:    Timer callback function for SetSetBWMode
4361  *
4362  * Input:               PRT_TIMER               pTimer
4363  *
4364  * Output:      NONE
4365  *
4366  * Return:      NONE
4367  *
4368  * Note:                (1) We do not take j mode into consideration now
4369  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
4370  *                           concurrently?
4371  *---------------------------------------------------------------------------*/
4372 //====>//rtl8192_SetBWMode
4373 //    use in phy only (in win it's timer)
4374 void SetBWModeCallback8192SUsb(struct net_device *dev)
4375 {
4376         struct r8192_priv *priv = ieee80211_priv(dev);
4377         u8                              regBwOpMode;
4378
4379         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4380         //u32                           NowL, NowH;
4381         //u8Byte                                BeginTime, EndTime;
4382         u8                              regRRSR_RSC;
4383
4384         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8190Pci()  Switch to %s bandwidth\n", \
4385                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4386
4387         if(priv->rf_chip == RF_PSEUDO_11N)
4388         {
4389                 priv->SetBWModeInProgress= FALSE;
4390                 return;
4391         }
4392
4393         if(!priv->up)
4394                 return;
4395
4396         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4397         //NowL = read_nic_dword(dev, TSFR);
4398         //NowH = read_nic_dword(dev, TSFR+4);
4399         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4400
4401         //3<1>Set MAC register
4402         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4403         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4404
4405         switch(priv->CurrentChannelBW)
4406         {
4407                 case HT_CHANNEL_WIDTH_20:
4408                         regBwOpMode |= BW_OPMODE_20MHZ;
4409                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4410                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4411                         break;
4412
4413                 case HT_CHANNEL_WIDTH_20_40:
4414                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4415                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4416                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4417
4418                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4419                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4420                         break;
4421
4422                 default:
4423                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci():\
4424                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4425                         break;
4426         }
4427
4428         //3 <2>Set PHY related register
4429         switch(priv->CurrentChannelBW)
4430         {
4431                 case HT_CHANNEL_WIDTH_20:
4432                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4433                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4434                         #if 0 //LZM090219
4435                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4436
4437                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4438                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
4439                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
4440                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
4441                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4442                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4443                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4444                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00300000, 3);
4445                         #endif
4446
4447                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4448                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4449
4450                         break;
4451                 case HT_CHANNEL_WIDTH_20_40:
4452                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4453                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4454                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4455                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4456
4457                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4458                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4459                         //PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4460                         //PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4461                         //PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4462
4463                         if (priv->card_8192_version >= VERSION_8192S_BCUT)
4464                                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4465
4466                         break;
4467                 default:
4468                         RT_TRACE(COMP_DBG, "SetChannelBandwidth8190Pci(): unknown Bandwidth: %#X\n"\
4469                                                 ,priv->CurrentChannelBW);
4470                         break;
4471
4472         }
4473         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4474
4475         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4476         //NowL = read_nic_dword(dev, TSFR);
4477         //NowH = read_nic_dword(dev, TSFR+4);
4478         //EndTime = ((u8Byte)NowH << 32) + NowL;
4479         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
4480
4481 #if 1
4482         //3<3>Set RF related register
4483         switch( priv->rf_chip )
4484         {
4485                 case RF_8225:
4486                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4487                         break;
4488
4489                 case RF_8256:
4490                         // Please implement this function in Hal8190PciPhy8256.c
4491                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4492                         break;
4493
4494                 case RF_6052:
4495                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4496                         break;
4497
4498                 case RF_8258:
4499                         // Please implement this function in Hal8190PciPhy8258.c
4500                         // PHY_SetRF8258Bandwidth();
4501                         break;
4502
4503                 case RF_PSEUDO_11N:
4504                         // Do Nothing
4505                         break;
4506
4507                 default:
4508                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4509                         break;
4510         }
4511 #endif
4512         priv->SetBWModeInProgress= FALSE;
4513
4514         RT_TRACE(COMP_SCAN, "<==SetBWMode8190Pci()" );
4515 }
4516
4517 //
4518 // Callback routine of the work item for set bandwidth mode.
4519 //
4520 //    use in phy only (in win it's work)
4521 void SetBWModeCallback8192SUsbWorkItem(struct net_device *dev)
4522 {
4523         struct r8192_priv               *priv = ieee80211_priv(dev);
4524         u8                              regBwOpMode;
4525
4526         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4527         //u32                           NowL, NowH;
4528         //u8Byte                                BeginTime, EndTime;
4529         u8                      regRRSR_RSC;
4530
4531         RT_TRACE(COMP_SCAN, "==>SetBWModeCallback8192SUsbWorkItem()  Switch to %s bandwidth\n", \
4532                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
4533
4534         if(priv->rf_chip == RF_PSEUDO_11N)
4535         {
4536                 priv->SetBWModeInProgress= FALSE;
4537                 return;
4538         }
4539
4540         if(!priv->up)
4541                 return;
4542
4543         // Added it for 20/40 mhz switch time evaluation by guangan 070531
4544         //NowL = read_nic_dword(dev, TSFR);
4545         //NowH = read_nic_dword(dev, TSFR+4);
4546         //BeginTime = ((u8Byte)NowH << 32) + NowL;
4547
4548         //3<1>Set MAC register
4549         regBwOpMode = read_nic_byte(dev, BW_OPMODE);
4550         regRRSR_RSC = read_nic_byte(dev, RRSR+2);
4551
4552         switch(priv->CurrentChannelBW)
4553         {
4554                 case HT_CHANNEL_WIDTH_20:
4555                         regBwOpMode |= BW_OPMODE_20MHZ;
4556                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4557                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4558                         break;
4559
4560                 case HT_CHANNEL_WIDTH_20_40:
4561                         regBwOpMode &= ~BW_OPMODE_20MHZ;
4562                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
4563                         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
4564                         regRRSR_RSC = (regRRSR_RSC&0x90) |(priv->nCur40MhzPrimeSC<<5);
4565                         write_nic_byte(dev, RRSR+2, regRRSR_RSC);
4566
4567                         break;
4568
4569                 default:
4570                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem():\
4571                                                 unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
4572                         break;
4573         }
4574
4575         //3 <2>Set PHY related register
4576         switch(priv->CurrentChannelBW)
4577         {
4578                 case HT_CHANNEL_WIDTH_20:
4579                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
4580                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
4581
4582                         #if 0 //LZM 090219
4583                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
4584
4585                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
4586                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x1a1b0000);
4587                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x090e1317);
4588                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000204);
4589                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
4590                         #endif
4591
4592                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
4593
4594                         break;
4595                 case HT_CHANNEL_WIDTH_20_40:
4596                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
4597                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
4598                         #if 0 //LZM 090219
4599                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4600
4601                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
4602
4603                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4604                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
4605                         rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskDWord, 0x35360000);
4606                         rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, 0x121c252e);
4607                         rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskDWord, 0x00000409);
4608                         #endif
4609
4610                         // Set Control channel to upper or lower. These settings are required only for 40MHz
4611                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
4612                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
4613
4614                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
4615
4616                         break;
4617
4618
4619                 default:
4620                         RT_TRACE(COMP_DBG, "SetBWModeCallback8192SUsbWorkItem(): unknown Bandwidth: %#X\n"\
4621                                                 ,priv->CurrentChannelBW);
4622                         break;
4623
4624         }
4625         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
4626
4627         //3<3>Set RF related register
4628         switch( priv->rf_chip )
4629         {
4630                 case RF_8225:
4631                         PHY_SetRF8225Bandwidth(dev, priv->CurrentChannelBW);
4632                         break;
4633
4634                 case RF_8256:
4635                         // Please implement this function in Hal8190PciPhy8256.c
4636                         //PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
4637                         break;
4638
4639                 case RF_6052:
4640                         PHY_RF6052SetBandwidth(dev, priv->CurrentChannelBW);
4641                         break;
4642
4643                 case RF_8258:
4644                         // Please implement this function in Hal8190PciPhy8258.c
4645                         // PHY_SetRF8258Bandwidth();
4646                         break;
4647
4648                 case RF_PSEUDO_11N:
4649                         // Do Nothing
4650                         break;
4651
4652                 default:
4653                         //RT_ASSERT(FALSE, ("Unknown rf_chip: %d\n", priv->rf_chip));
4654                         break;
4655         }
4656
4657         priv->SetBWModeInProgress= FALSE;
4658
4659         RT_TRACE(COMP_SCAN, "<==SetBWModeCallback8192SUsbWorkItem()" );
4660 }
4661
4662 //--------------------------Move to oter DIR later-------------------------------*/
4663 #ifdef RTL8192SU
4664 void InitialGain8192S(struct net_device *dev,   u8 Operation)
4665 {
4666 #ifdef TO_DO_LIST
4667         struct r8192_priv *priv = ieee80211_priv(dev);
4668 #endif
4669
4670 }
4671 #endif
4672
4673 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
4674 {
4675         struct r8192_priv *priv = ieee80211_priv(dev);
4676
4677         priv->InitialGainOperateType = Operation;
4678
4679         if(priv->up)
4680         {
4681                 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0);
4682         }
4683 }
4684
4685 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
4686 {
4687         struct delayed_work *dwork = container_of(work,struct delayed_work,work);
4688        struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq);
4689        struct net_device *dev = priv->ieee80211->dev;
4690 #define SCAN_RX_INITIAL_GAIN    0x17
4691 #define POWER_DETECTION_TH      0x08
4692         u32     BitMask;
4693         u8      initial_gain;
4694         u8      Operation;
4695
4696         Operation = priv->InitialGainOperateType;
4697
4698         switch(Operation)
4699         {
4700                 case IG_Backup:
4701                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
4702                         initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];//
4703                         BitMask = bMaskByte0;
4704                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4705                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4706                         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
4707                         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
4708                         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
4709                         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
4710                         BitMask  = bMaskByte2;
4711                         priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
4712
4713                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4714                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4715                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4716                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4717                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
4718
4719                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
4720                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
4721                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
4722                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
4723                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
4724                         RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
4725                         write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
4726                         break;
4727                 case IG_Restore:
4728                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
4729                         BitMask = 0x7f; //Bit0~ Bit6
4730                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4731                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
4732
4733                         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
4734                         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
4735                         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
4736                         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
4737                         BitMask  = bMaskByte2;
4738                         rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
4739
4740                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
4741                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
4742                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
4743                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
4744                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
4745
4746                         PHY_SetTxPowerLevel8192S(dev,priv->ieee80211->current_network.channel);
4747
4748                         if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
4749                                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
4750                         break;
4751                 default:
4752                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
4753                         break;
4754         }
4755 }
4756
4757 #endif  // #if (DEV_BUS_TYPE == USB_INTERFACE)
4758
4759 //-----------------------------------------------------------------------------
4760 //      Description:
4761 //              Schedule workitem to send specific CMD IO to FW.
4762 //      Added by Roger, 2008.12.03.
4763 //
4764 //-----------------------------------------------------------------------------
4765 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE    FwCmdIO)
4766 {
4767         struct r8192_priv *priv = ieee80211_priv(dev);
4768         u16     FwCmdWaitCounter = 0;
4769
4770         u16     FwCmdWaitLimit = 1000;
4771
4772         //if(IS_HARDWARE_TYPE_8192SU(Adapter) && Adapter->bInHctTest)
4773         if(priv->bInHctTest)
4774                 return true;
4775
4776         RT_TRACE(COMP_CMD, "-->HalSetFwCmd8192S(): Set FW Cmd(%x), SetFwCmdInProgress(%d)\n", (u32)FwCmdIO, priv->SetFwCmdInProgress);
4777
4778         // Will be done by high power respectively.
4779         if(FwCmdIO==FW_CMD_DIG_HALT || FwCmdIO==FW_CMD_DIG_RESUME)
4780         {
4781                 RT_TRACE(COMP_CMD, "<--HalSetFwCmd8192S(): Set FW Cmd(%x)\n", (u32)FwCmdIO);
4782                 return false;
4783         }
4784
4785 #if 1
4786         while(priv->SetFwCmdInProgress && FwCmdWaitCounter<FwCmdWaitLimit)
4787         {
4788                 //if(RT_USB_CANNOT_IO(Adapter))
4789                 //{
4790                 //      RT_TRACE(COMP_CMD, DBG_WARNING, ("HalSetFwCmd8192S(): USB can NOT IO!!\n"));
4791                 //      return FALSE;
4792                 //}
4793
4794                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): previous workitem not finish!!\n");
4795                 return false;
4796                 FwCmdWaitCounter ++;
4797                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait 10 ms (%d times)...\n", FwCmdWaitCounter);
4798                 udelay(100);
4799         }
4800
4801         if(FwCmdWaitCounter == FwCmdWaitLimit)
4802         {
4803                 //RT_ASSERT(FALSE, ("SetFwCmdIOWorkItemCallback(): Wait too logn to set FW CMD\n"));
4804                 RT_TRACE(COMP_CMD, "HalSetFwCmd8192S(): Wait too logn to set FW CMD\n");
4805                 //return false;
4806         }
4807 #endif
4808         if (priv->SetFwCmdInProgress)
4809         {
4810                 RT_TRACE(COMP_ERR, "<--HalSetFwCmd8192S(): Set FW Cmd(%#x)\n", FwCmdIO);
4811                 return false;
4812         }
4813         priv->SetFwCmdInProgress = TRUE;
4814         priv->CurrentFwCmdIO = FwCmdIO; // Update current FW Cmd for callback use.
4815
4816         phy_SetFwCmdIOCallback(dev);
4817         return true;
4818 }
4819 void ChkFwCmdIoDone(struct net_device* dev)
4820 {
4821         u16 PollingCnt = 1000;
4822         u32 tmpValue;
4823
4824         do
4825         {// Make sure that CMD IO has be accepted by FW.
4826 #ifdef TO_DO_LIST
4827                 if(RT_USB_CANNOT_IO(Adapter))
4828                 {
4829                         RT_TRACE(COMP_CMD, "ChkFwCmdIoDone(): USB can NOT IO!!\n");
4830                         return;
4831                 }
4832 #endif
4833                 udelay(10); // sleep 20us
4834                 tmpValue = read_nic_dword(dev, WFM5);
4835                 if(tmpValue == 0)
4836                 {
4837                         RT_TRACE(COMP_CMD, "[FW CMD] Set FW Cmd success!!\n");
4838                         break;
4839                 }
4840                 else
4841                 {
4842                         RT_TRACE(COMP_CMD, "[FW CMD] Polling FW Cmd PollingCnt(%d)!!\n", PollingCnt);
4843                 }
4844         }while( --PollingCnt );
4845
4846         if(PollingCnt == 0)
4847         {
4848                 RT_TRACE(COMP_ERR, "[FW CMD] Set FW Cmd fail!!\n");
4849         }
4850 }
4851 //      Callback routine of the timer callback for FW Cmd IO.
4852 //
4853 //      Description:
4854 //              This routine will send specific CMD IO to FW and check whether it is done.
4855 //
4856 void phy_SetFwCmdIOCallback(struct net_device* dev)
4857 {
4858         //struct net_device* dev = (struct net_device*) data;
4859         u32             input;
4860         static u32 ScanRegister;
4861         struct r8192_priv *priv = ieee80211_priv(dev);
4862         if(!priv->up)
4863         {
4864                 RT_TRACE(COMP_CMD, "SetFwCmdIOTimerCallback(): driver is going to unload\n");
4865                 return;
4866         }
4867
4868         RT_TRACE(COMP_CMD, "--->SetFwCmdIOTimerCallback(): Cmd(%#x), SetFwCmdInProgress(%d)\n", priv->CurrentFwCmdIO, priv->SetFwCmdInProgress);
4869
4870         switch(priv->CurrentFwCmdIO)
4871         {
4872                 case FW_CMD_HIGH_PWR_ENABLE:
4873                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4874                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE);
4875                         break;
4876
4877                 case FW_CMD_HIGH_PWR_DISABLE:
4878                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE);
4879                         break;
4880
4881                 case FW_CMD_DIG_RESUME:
4882                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4883                         break;
4884
4885                 case FW_CMD_DIG_HALT:
4886                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4887                         break;
4888
4889                 //
4890                 // <Roger_Notes> The following FW CMD IO was combined into single operation
4891                 // (i.e., to prevent number of system workitem out of resource!!).
4892                 // 2008.12.04.
4893                 //
4894                 case FW_CMD_RESUME_DM_BY_SCAN:
4895                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR enable and DIG resume!!\n");
4896                         if((priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)==0)
4897                         {
4898                                 write_nic_dword(dev, WFM5, FW_HIGH_PWR_ENABLE); //break;
4899                                 ChkFwCmdIoDone(dev);
4900                         }
4901                         write_nic_dword(dev, WFM5, FW_DIG_RESUME);
4902                         break;
4903
4904                 case FW_CMD_PAUSE_DM_BY_SCAN:
4905                         RT_TRACE(COMP_CMD, "[FW CMD] Set HIGHPWR disable and DIG halt!!\n");
4906                         write_nic_dword(dev, WFM5, FW_HIGH_PWR_DISABLE); //break;
4907                         ChkFwCmdIoDone(dev);
4908                         write_nic_dword(dev, WFM5, FW_DIG_HALT);
4909                         break;
4910
4911                 //
4912                 // <Roger_Notes> The following FW CMD IO should be checked
4913                 // (i.e., workitem schedule timing issue!!).
4914                 // 2008.12.04.
4915                 //
4916                 case FW_CMD_DIG_DISABLE:
4917                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG disable!!\n");
4918                         write_nic_dword(dev, WFM5, FW_DIG_DISABLE);
4919                         break;
4920
4921                 case FW_CMD_DIG_ENABLE:
4922                         RT_TRACE(COMP_CMD, "[FW CMD] Set DIG enable!!\n");
4923                         write_nic_dword(dev, WFM5, FW_DIG_ENABLE);
4924                         break;
4925
4926                 case FW_CMD_RA_RESET:
4927                         write_nic_dword(dev, WFM5, FW_RA_RESET);
4928                         break;
4929
4930                 case FW_CMD_RA_ACTIVE:
4931                         write_nic_dword(dev, WFM5, FW_RA_ACTIVE);
4932                         break;
4933
4934                 case FW_CMD_RA_REFRESH_N:
4935                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! N\n");
4936                         if(priv->ieee80211->pHTInfo->IOTRaFunc & HT_IOT_RAFUNC_DISABLE_ALL)
4937                                 input = FW_RA_REFRESH;
4938                         else
4939                                 input = FW_RA_REFRESH | (priv->ieee80211->pHTInfo->IOTRaFunc << 8);
4940                         write_nic_dword(dev, WFM5, input);
4941                         break;
4942                 case FW_CMD_RA_REFRESH_BG:
4943                         RT_TRACE(COMP_CMD, "[FW CMD] Set RA refresh!! B/G\n");
4944                         write_nic_dword(dev, WFM5, FW_RA_REFRESH);
4945                         ChkFwCmdIoDone(dev);
4946                         write_nic_dword(dev, WFM5, FW_RA_ENABLE_BG);
4947                         break;
4948
4949                 case FW_CMD_IQK_ENABLE:
4950                         write_nic_dword(dev, WFM5, FW_IQK_ENABLE);
4951                         break;
4952
4953                 case FW_CMD_TXPWR_TRACK_ENABLE:
4954                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_ENABLE);
4955                         break;
4956
4957                 case FW_CMD_TXPWR_TRACK_DISABLE:
4958                         write_nic_dword(dev, WFM5, FW_TXPWR_TRACK_DISABLE);
4959                         break;
4960
4961                 default:
4962                         RT_TRACE(COMP_CMD,"Unknown FW Cmd IO(%#x)\n", priv->CurrentFwCmdIO);
4963                         break;
4964         }
4965
4966         ChkFwCmdIoDone(dev);
4967
4968         switch(priv->CurrentFwCmdIO)
4969         {
4970                 case FW_CMD_HIGH_PWR_DISABLE:
4971                         //if(pMgntInfo->bTurboScan)
4972                         {
4973                                 //Lower initial gain
4974                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x17);
4975                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x17);
4976                                 // CCA threshold
4977                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x40);
4978                                 // Disable OFDM Part
4979                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x1);
4980                                 ScanRegister = rtl8192_QueryBBReg(dev, rOFDM0_RxDetector1,bMaskDWord);
4981                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, 0xf, 0xf);
4982                                 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
4983                         }
4984                         break;
4985
4986                 case FW_CMD_HIGH_PWR_ENABLE:
4987                         //if(pMgntInfo->bTurboScan)
4988                         {
4989                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bMaskByte0, 0x36);
4990                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bMaskByte0, 0x36);
4991
4992                                 // CCA threshold
4993                                 rtl8192_setBBreg(dev, rCCK0_CCA, bMaskByte2, 0x83);
4994                                 // Enable OFDM Part
4995                                 rtl8192_setBBreg(dev, rOFDM0_TRMuxPar, bMaskByte2, 0x0);
4996
4997                                 //LZM ADD because sometimes there is no FW_CMD_HIGH_PWR_DISABLE, this value will be 0.
4998                                 if(ScanRegister != 0){
4999                                 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskDWord, ScanRegister);
5000                                 }
5001
5002                                 if(priv->rf_type == RF_1T2R || priv->rf_type == RF_2T2R)
5003                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x3);
5004                                 else
5005                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x1);
5006                         }
5007                         break;
5008         }
5009
5010         priv->SetFwCmdInProgress = false;// Clear FW CMD operation flag.
5011         RT_TRACE(COMP_CMD, "<---SetFwCmdIOWorkItemCallback()\n");
5012
5013 }
5014